Struct DMA

pub struct DMA { /* private fields */ }

Implementations

impl DMA

pub const PTR: *const <DMA as Deref>::Target = {0x60080000 as *const <esp32c6::DMA as core::ops::Deref>::Target}

Pointer to the register block

pub unsafe fn steal() -> DMA

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const fn ptr() -> *const <DMA as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn in_int_raw_ch(&self, n: usize) -> &Reg<IN_INT_RAW_CH_SPEC>

0x00..0x0c - Raw status interrupt of channel 0

pub fn in_int_raw_ch_iter( &self, ) -> impl Iterator<Item = &Reg<IN_INT_RAW_CH_SPEC>>

Iterator for array of: 0x00..0x0c - Raw status interrupt of channel 0

pub fn in_int_st_ch(&self, n: usize) -> &Reg<IN_INT_ST_CH_SPEC>

0x04..0x10 - Masked interrupt of channel 0

pub fn in_int_st_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_INT_ST_CH_SPEC>>

Iterator for array of: 0x04..0x10 - Masked interrupt of channel 0

pub fn in_int_ena_ch(&self, n: usize) -> &Reg<IN_INT_ENA_CH_SPEC>

0x08..0x14 - Interrupt enable bits of channel 0

pub fn in_int_ena_ch_iter( &self, ) -> impl Iterator<Item = &Reg<IN_INT_ENA_CH_SPEC>>

Iterator for array of: 0x08..0x14 - Interrupt enable bits of channel 0

pub fn in_int_clr_ch(&self, n: usize) -> &Reg<IN_INT_CLR_CH_SPEC>

0x0c..0x18 - Interrupt clear bits of channel 0

pub fn in_int_clr_ch_iter( &self, ) -> impl Iterator<Item = &Reg<IN_INT_CLR_CH_SPEC>>

Iterator for array of: 0x0c..0x18 - Interrupt clear bits of channel 0

pub fn out_int_raw_ch(&self, n: usize) -> &Reg<OUT_INT_RAW_CH_SPEC>

0x30..0x3c - Raw status interrupt of channel 0

pub fn out_int_raw_ch_iter( &self, ) -> impl Iterator<Item = &Reg<OUT_INT_RAW_CH_SPEC>>

Iterator for array of: 0x30..0x3c - Raw status interrupt of channel 0

pub fn out_int_st_ch(&self, n: usize) -> &Reg<OUT_INT_ST_CH_SPEC>

0x34..0x40 - Masked interrupt of channel 0

pub fn out_int_st_ch_iter( &self, ) -> impl Iterator<Item = &Reg<OUT_INT_ST_CH_SPEC>>

Iterator for array of: 0x34..0x40 - Masked interrupt of channel 0

pub fn out_int_ena_ch(&self, n: usize) -> &Reg<OUT_INT_ENA_CH_SPEC>

0x38..0x44 - Interrupt enable bits of channel 0

pub fn out_int_ena_ch_iter( &self, ) -> impl Iterator<Item = &Reg<OUT_INT_ENA_CH_SPEC>>

Iterator for array of: 0x38..0x44 - Interrupt enable bits of channel 0

pub fn out_int_clr_ch(&self, n: usize) -> &Reg<OUT_INT_CLR_CH_SPEC>

0x3c..0x48 - Interrupt clear bits of channel 0

pub fn out_int_clr_ch_iter( &self, ) -> impl Iterator<Item = &Reg<OUT_INT_CLR_CH_SPEC>>

Iterator for array of: 0x3c..0x48 - Interrupt clear bits of channel 0

pub fn ahb_test(&self) -> &Reg<AHB_TEST_SPEC>

0x60 - reserved

pub fn misc_conf(&self) -> &Reg<MISC_CONF_SPEC>

0x64 - MISC register

pub fn date(&self) -> &Reg<DATE_SPEC>

0x68 - Version control register

pub fn in_conf0_ch(&self, n: usize) -> &Reg<IN_CONF0_CH_SPEC>

0x70..0x7c - Configure 0 register of Rx channel 0

pub fn in_conf0_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_CONF0_CH_SPEC>>

Iterator for array of: 0x70..0x7c - Configure 0 register of Rx channel 0

pub fn in_conf1_ch(&self, n: usize) -> &Reg<IN_CONF1_CH_SPEC>

0x74..0x80 - Configure 1 register of Rx channel 0

pub fn in_conf1_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_CONF1_CH_SPEC>>

Iterator for array of: 0x74..0x80 - Configure 1 register of Rx channel 0

pub fn infifo_status_ch(&self, n: usize) -> &Reg<INFIFO_STATUS_CH_SPEC>

0x78..0x84 - Receive FIFO status of Rx channel 0

pub fn infifo_status_ch_iter( &self, ) -> impl Iterator<Item = &Reg<INFIFO_STATUS_CH_SPEC>>

Iterator for array of: 0x78..0x84 - Receive FIFO status of Rx channel 0

pub fn in_pop_ch(&self, n: usize) -> &Reg<IN_POP_CH_SPEC>

0x7c..0x88 - Pop control register of Rx channel 0

pub fn in_pop_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_POP_CH_SPEC>>

Iterator for array of: 0x7c..0x88 - Pop control register of Rx channel 0

pub fn in_link_ch(&self, n: usize) -> &Reg<IN_LINK_CH_SPEC>

0x80..0x8c - Link descriptor configure and control register of Rx channel 0

pub fn in_link_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_LINK_CH_SPEC>>

Iterator for array of: 0x80..0x8c - Link descriptor configure and control register of Rx channel 0

pub fn in_state_ch(&self, n: usize) -> &Reg<IN_STATE_CH_SPEC>

0x84..0x90 - Receive status of Rx channel 0

pub fn in_state_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_STATE_CH_SPEC>>

Iterator for array of: 0x84..0x90 - Receive status of Rx channel 0

pub fn in_suc_eof_des_addr_ch( &self, n: usize, ) -> &Reg<IN_SUC_EOF_DES_ADDR_CH_SPEC>

0x88..0x94 - Inlink descriptor address when EOF occurs of Rx channel 0

pub fn in_suc_eof_des_addr_ch_iter( &self, ) -> impl Iterator<Item = &Reg<IN_SUC_EOF_DES_ADDR_CH_SPEC>>

Iterator for array of: 0x88..0x94 - Inlink descriptor address when EOF occurs of Rx channel 0

pub fn in_err_eof_des_addr_ch( &self, n: usize, ) -> &Reg<IN_ERR_EOF_DES_ADDR_CH_SPEC>

0x8c..0x98 - Inlink descriptor address when errors occur of Rx channel 0

pub fn in_err_eof_des_addr_ch_iter( &self, ) -> impl Iterator<Item = &Reg<IN_ERR_EOF_DES_ADDR_CH_SPEC>>

Iterator for array of: 0x8c..0x98 - Inlink descriptor address when errors occur of Rx channel 0

pub fn in_dscr_ch(&self, n: usize) -> &Reg<IN_DSCR_CH_SPEC>

0x90..0x9c - Current inlink descriptor address of Rx channel 0

pub fn in_dscr_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_DSCR_CH_SPEC>>

Iterator for array of: 0x90..0x9c - Current inlink descriptor address of Rx channel 0

pub fn in_dscr_bf0_ch(&self, n: usize) -> &Reg<IN_DSCR_BF0_CH_SPEC>

0x94..0xa0 - The last inlink descriptor address of Rx channel 0

pub fn in_dscr_bf0_ch_iter( &self, ) -> impl Iterator<Item = &Reg<IN_DSCR_BF0_CH_SPEC>>

Iterator for array of: 0x94..0xa0 - The last inlink descriptor address of Rx channel 0

pub fn in_dscr_bf1_ch(&self, n: usize) -> &Reg<IN_DSCR_BF1_CH_SPEC>

0x98..0xa4 - The second-to-last inlink descriptor address of Rx channel 0

pub fn in_dscr_bf1_ch_iter( &self, ) -> impl Iterator<Item = &Reg<IN_DSCR_BF1_CH_SPEC>>

Iterator for array of: 0x98..0xa4 - The second-to-last inlink descriptor address of Rx channel 0

pub fn in_pri_ch(&self, n: usize) -> &Reg<IN_PRI_CH_SPEC>

0x9c..0xa8 - Priority register of Rx channel 0

pub fn in_pri_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_PRI_CH_SPEC>>

Iterator for array of: 0x9c..0xa8 - Priority register of Rx channel 0

pub fn in_peri_sel_ch(&self, n: usize) -> &Reg<IN_PERI_SEL_CH_SPEC>

0xa0..0xac - Peripheral selection of Rx channel 0

pub fn in_peri_sel_ch_iter( &self, ) -> impl Iterator<Item = &Reg<IN_PERI_SEL_CH_SPEC>>

Iterator for array of: 0xa0..0xac - Peripheral selection of Rx channel 0

pub fn out_conf1_ch(&self, n: usize) -> &Reg<OUT_CONF1_CH_SPEC>

0xd4..0xe0 - Configure 1 register of Tx channel 0

pub fn out_conf1_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_CONF1_CH_SPEC>>

Iterator for array of: 0xd4..0xe0 - Configure 1 register of Tx channel 0

pub fn outfifo_status_ch(&self, n: usize) -> &Reg<OUTFIFO_STATUS_CH_SPEC>

0xd8..0xe4 - Transmit FIFO status of Tx channel 0

pub fn outfifo_status_ch_iter( &self, ) -> impl Iterator<Item = &Reg<OUTFIFO_STATUS_CH_SPEC>>

Iterator for array of: 0xd8..0xe4 - Transmit FIFO status of Tx channel 0

pub fn out_push_ch(&self, n: usize) -> &Reg<OUT_PUSH_CH_SPEC>

0xdc..0xe8 - Push control register of Rx channel 0

pub fn out_push_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_PUSH_CH_SPEC>>

Iterator for array of: 0xdc..0xe8 - Push control register of Rx channel 0

pub fn out_link_ch(&self, n: usize) -> &Reg<OUT_LINK_CH_SPEC>

0xe0..0xec - Link descriptor configure and control register of Tx channel 0

pub fn out_link_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_LINK_CH_SPEC>>

Iterator for array of: 0xe0..0xec - Link descriptor configure and control register of Tx channel 0

pub fn out_state_ch(&self, n: usize) -> &Reg<OUT_STATE_CH_SPEC>

0xe4..0xf0 - Transmit status of Tx channel 0

pub fn out_state_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_STATE_CH_SPEC>>

Iterator for array of: 0xe4..0xf0 - Transmit status of Tx channel 0

pub fn out_eof_des_addr_ch(&self, n: usize) -> &Reg<OUT_EOF_DES_ADDR_CH_SPEC>

0xe8..0xf4 - Outlink descriptor address when EOF occurs of Tx channel 0

pub fn out_eof_des_addr_ch_iter( &self, ) -> impl Iterator<Item = &Reg<OUT_EOF_DES_ADDR_CH_SPEC>>

Iterator for array of: 0xe8..0xf4 - Outlink descriptor address when EOF occurs of Tx channel 0

pub fn out_eof_bfr_des_addr_ch( &self, n: usize, ) -> &Reg<OUT_EOF_BFR_DES_ADDR_CH_SPEC>

0xec..0xf8 - The last outlink descriptor address when EOF occurs of Tx channel 0

pub fn out_eof_bfr_des_addr_ch_iter( &self, ) -> impl Iterator<Item = &Reg<OUT_EOF_BFR_DES_ADDR_CH_SPEC>>

Iterator for array of: 0xec..0xf8 - The last outlink descriptor address when EOF occurs of Tx channel 0

pub fn out_dscr_ch(&self, n: usize) -> &Reg<OUT_DSCR_CH_SPEC>

0xf0..0xfc - Current inlink descriptor address of Tx channel 0

pub fn out_dscr_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_DSCR_CH_SPEC>>

Iterator for array of: 0xf0..0xfc - Current inlink descriptor address of Tx channel 0

pub fn out_dscr_bf0_ch(&self, n: usize) -> &Reg<OUT_DSCR_BF0_CH_SPEC>

0xf4..0x100 - The last inlink descriptor address of Tx channel 0

pub fn out_dscr_bf0_ch_iter( &self, ) -> impl Iterator<Item = &Reg<OUT_DSCR_BF0_CH_SPEC>>

Iterator for array of: 0xf4..0x100 - The last inlink descriptor address of Tx channel 0

pub fn out_dscr_bf1_ch(&self, n: usize) -> &Reg<OUT_DSCR_BF1_CH_SPEC>

0xf8..0x104 - The second-to-last inlink descriptor address of Tx channel 0

pub fn out_dscr_bf1_ch_iter( &self, ) -> impl Iterator<Item = &Reg<OUT_DSCR_BF1_CH_SPEC>>

Iterator for array of: 0xf8..0x104 - The second-to-last inlink descriptor address of Tx channel 0

pub fn out_pri_ch(&self, n: usize) -> &Reg<OUT_PRI_CH_SPEC>

0xfc..0x108 - Priority register of Tx channel 0.

pub fn out_pri_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_PRI_CH_SPEC>>

Iterator for array of: 0xfc..0x108 - Priority register of Tx channel 0.

pub fn out_peri_sel_ch(&self, n: usize) -> &Reg<OUT_PERI_SEL_CH_SPEC>

0x100..0x10c - Peripheral selection of Tx channel 0

pub fn out_peri_sel_ch_iter( &self, ) -> impl Iterator<Item = &Reg<OUT_PERI_SEL_CH_SPEC>>

Iterator for array of: 0x100..0x10c - Peripheral selection of Tx channel 0

pub fn out_conf0_ch(&self, n: usize) -> &Reg<OUT_CONF0_CH_SPEC>

0x190..0x19c - Configure 0 register of Tx channel 1

pub fn out_conf0_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_CONF0_CH_SPEC>>

Iterator for array of: 0x190..0x19c - Configure 0 register of Tx channel 1

Trait Implementations

impl Debug for DMA

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for DMA

type Target = <DMA as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<DMA as Deref>::Target

Dereferences the value.

impl DerefMut for DMA

fn deref_mut(&mut self) -> &mut <DMA as Deref>::Target

Mutably dereferences the value.

impl Peripheral for DMA

type P = DMA

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <DMA as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.