Struct MCPWM0

pub struct MCPWM0 { /* private fields */ }

Implementations

impl MCPWM0

pub const PTR: *const <MCPWM0 as Deref>::Target = {0x60014000 as *const <esp32c6::MCPWM0 as core::ops::Deref>::Target}

Pointer to the register block

pub unsafe fn steal() -> MCPWM0

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const fn ptr() -> *const <MCPWM0 as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn clk_cfg(&self) -> &Reg<CLK_CFG_SPEC>

0x00 - PWM clock prescaler register.

pub fn timer0_cfg0(&self) -> &Reg<TIMER0_CFG0_SPEC>

0x04 - PWM timer0 period and update method configuration register.

pub fn timer0_cfg1(&self) -> &Reg<TIMER0_CFG1_SPEC>

0x08 - PWM timer0 working mode and start/stop control configuration register.

pub fn timer0_sync(&self) -> &Reg<TIMER0_SYNC_SPEC>

0x0c - PWM timer0 sync function configuration register.

pub fn timer0_status(&self) -> &Reg<TIMER0_STATUS_SPEC>

0x10 - PWM timer0 status register.

pub fn timer1_cfg0(&self) -> &Reg<TIMER1_CFG0_SPEC>

0x14 - PWM timer1 period and update method configuration register.

pub fn timer1_cfg1(&self) -> &Reg<TIMER1_CFG1_SPEC>

0x18 - PWM timer1 working mode and start/stop control configuration register.

pub fn timer1_sync(&self) -> &Reg<TIMER1_SYNC_SPEC>

0x1c - PWM timer1 sync function configuration register.

pub fn timer1_status(&self) -> &Reg<TIMER1_STATUS_SPEC>

0x20 - PWM timer1 status register.

pub fn timer2_cfg0(&self) -> &Reg<TIMER2_CFG0_SPEC>

0x24 - PWM timer2 period and update method configuration register.

pub fn timer2_cfg1(&self) -> &Reg<TIMER2_CFG1_SPEC>

0x28 - PWM timer2 working mode and start/stop control configuration register.

pub fn timer2_sync(&self) -> &Reg<TIMER2_SYNC_SPEC>

0x2c - PWM timer2 sync function configuration register.

pub fn timer2_status(&self) -> &Reg<TIMER2_STATUS_SPEC>

0x30 - PWM timer2 status register.

pub fn timer_synci_cfg(&self) -> &Reg<TIMER_SYNCI_CFG_SPEC>

0x34 - Synchronization input selection for three PWM timers.

pub fn operator_timersel(&self) -> &Reg<OPERATOR_TIMERSEL_SPEC>

0x38 - Select specific timer for PWM operators.

pub fn gen0_stmp_cfg(&self) -> &Reg<GEN0_STMP_CFG_SPEC>

0x3c - Transfer status and update method for time stamp registers A and B

pub fn gen0_tstmp_a(&self) -> &Reg<GEN0_TSTMP_A_SPEC>

0x40 - Shadow register for register A.

pub fn gen0_tstmp_b(&self) -> &Reg<GEN0_TSTMP_B_SPEC>

0x44 - Shadow register for register B.

pub fn gen0_cfg0(&self) -> &Reg<GEN0_CFG0_SPEC>

0x48 - Fault event T0 and T1 handling

pub fn gen0_force(&self) -> &Reg<GEN0_FORCE_SPEC>

0x4c - Permissives to force PWM0A and PWM0B outputs by software

pub fn gen0_a(&self) -> &Reg<GEN0_A_SPEC>

0x50 - Actions triggered by events on PWM0A

pub fn gen0_b(&self) -> &Reg<GEN0_B_SPEC>

0x54 - Actions triggered by events on PWM0B

pub fn dt0_cfg(&self) -> &Reg<DT0_CFG_SPEC>

0x58 - dead time type selection and configuration

pub fn dt0_fed_cfg(&self) -> &Reg<DT0_FED_CFG_SPEC>

0x5c - Shadow register for falling edge delay (FED).

pub fn dt0_red_cfg(&self) -> &Reg<DT0_RED_CFG_SPEC>

0x60 - Shadow register for rising edge delay (RED).

pub fn carrier0_cfg(&self) -> &Reg<CARRIER0_CFG_SPEC>

0x64 - Carrier enable and configuratoin

pub fn fh0_cfg0(&self) -> &Reg<FH0_CFG0_SPEC>

0x68 - Actions on PWM0A and PWM0B trip events

pub fn fh0_cfg1(&self) -> &Reg<FH0_CFG1_SPEC>

0x6c - Software triggers for fault handler actions

pub fn fh0_status(&self) -> &Reg<FH0_STATUS_SPEC>

0x70 - Status of fault events.

pub fn gen1_stmp_cfg(&self) -> &Reg<GEN1_STMP_CFG_SPEC>

0x74 - Transfer status and update method for time stamp registers A and B

pub fn gen1_tstmp_a(&self) -> &Reg<GEN1_TSTMP_A_SPEC>

0x78 - Shadow register for register A.

pub fn gen1_tstmp_b(&self) -> &Reg<GEN1_TSTMP_B_SPEC>

0x7c - Shadow register for register B.

pub fn gen1_cfg0(&self) -> &Reg<GEN1_CFG0_SPEC>

0x80 - Fault event T0 and T1 handling

pub fn gen1_force(&self) -> &Reg<GEN1_FORCE_SPEC>

0x84 - Permissives to force PWM1A and PWM1B outputs by software

pub fn gen1_a(&self) -> &Reg<GEN1_A_SPEC>

0x88 - Actions triggered by events on PWM1A

pub fn gen1_b(&self) -> &Reg<GEN1_B_SPEC>

0x8c - Actions triggered by events on PWM1B

pub fn dt1_cfg(&self) -> &Reg<DT1_CFG_SPEC>

0x90 - dead time type selection and configuration

pub fn dt1_fed_cfg(&self) -> &Reg<DT1_FED_CFG_SPEC>

0x94 - Shadow register for falling edge delay (FED).

pub fn dt1_red_cfg(&self) -> &Reg<DT1_RED_CFG_SPEC>

0x98 - Shadow register for rising edge delay (RED).

pub fn carrier1_cfg(&self) -> &Reg<CARRIER1_CFG_SPEC>

0x9c - Carrier enable and configuratoin

pub fn fh1_cfg0(&self) -> &Reg<FH1_CFG0_SPEC>

0xa0 - Actions on PWM1A and PWM1B trip events

pub fn fh1_cfg1(&self) -> &Reg<FH1_CFG1_SPEC>

0xa4 - Software triggers for fault handler actions

pub fn fh1_status(&self) -> &Reg<FH1_STATUS_SPEC>

0xa8 - Status of fault events.

pub fn gen2_stmp_cfg(&self) -> &Reg<GEN2_STMP_CFG_SPEC>

0xac - Transfer status and update method for time stamp registers A and B

pub fn gen2_tstmp_a(&self) -> &Reg<GEN2_TSTMP_A_SPEC>

0xb0 - Shadow register for register A.

pub fn gen2_tstmp_b(&self) -> &Reg<GEN2_TSTMP_B_SPEC>

0xb4 - Shadow register for register B.

pub fn gen2_cfg0(&self) -> &Reg<GEN2_CFG0_SPEC>

0xb8 - Fault event T0 and T1 handling

pub fn gen2_force(&self) -> &Reg<GEN2_FORCE_SPEC>

0xbc - Permissives to force PWM2A and PWM2B outputs by software

pub fn gen2_a(&self) -> &Reg<GEN2_A_SPEC>

0xc0 - Actions triggered by events on PWM2A

pub fn gen2_b(&self) -> &Reg<GEN2_B_SPEC>

0xc4 - Actions triggered by events on PWM2B

pub fn dt2_cfg(&self) -> &Reg<DT2_CFG_SPEC>

0xc8 - dead time type selection and configuration

pub fn dt2_fed_cfg(&self) -> &Reg<DT2_FED_CFG_SPEC>

0xcc - Shadow register for falling edge delay (FED).

pub fn dt2_red_cfg(&self) -> &Reg<DT2_RED_CFG_SPEC>

0xd0 - Shadow register for rising edge delay (RED).

pub fn carrier2_cfg(&self) -> &Reg<CARRIER2_CFG_SPEC>

0xd4 - Carrier enable and configuratoin

pub fn fh2_cfg0(&self) -> &Reg<FH2_CFG0_SPEC>

0xd8 - Actions on PWM2A and PWM2B trip events

pub fn fh2_cfg1(&self) -> &Reg<FH2_CFG1_SPEC>

0xdc - Software triggers for fault handler actions

pub fn fh2_status(&self) -> &Reg<FH2_STATUS_SPEC>

0xe0 - Status of fault events.

pub fn fault_detect(&self) -> &Reg<FAULT_DETECT_SPEC>

0xe4 - Fault detection configuration and status

pub fn cap_timer_cfg(&self) -> &Reg<CAP_TIMER_CFG_SPEC>

0xe8 - Configure capture timer

pub fn cap_timer_phase(&self) -> &Reg<CAP_TIMER_PHASE_SPEC>

0xec - Phase for capture timer sync

pub fn cap_ch0_cfg(&self) -> &Reg<CAP_CH0_CFG_SPEC>

0xf0 - Capture channel 0 configuration and enable

pub fn cap_ch1_cfg(&self) -> &Reg<CAP_CH1_CFG_SPEC>

0xf4 - Capture channel 1 configuration and enable

pub fn cap_ch2_cfg(&self) -> &Reg<CAP_CH2_CFG_SPEC>

0xf8 - Capture channel 2 configuration and enable

pub fn cap_ch0(&self) -> &Reg<CAP_CH0_SPEC>

0xfc - ch0 capture value status register

pub fn cap_ch1(&self) -> &Reg<CAP_CH1_SPEC>

0x100 - ch1 capture value status register

pub fn cap_ch2(&self) -> &Reg<CAP_CH2_SPEC>

0x104 - ch2 capture value status register

pub fn cap_status(&self) -> &Reg<CAP_STATUS_SPEC>

0x108 - Edge of last capture trigger

pub fn update_cfg(&self) -> &Reg<UPDATE_CFG_SPEC>

0x10c - Enable update.

pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>

0x110 - Interrupt enable bits

pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>

0x114 - Raw interrupt status

pub fn int_st(&self) -> &Reg<INT_ST_SPEC>

0x118 - Masked interrupt status

pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>

0x11c - Interrupt clear bits

pub fn evt_en(&self) -> &Reg<EVT_EN_SPEC>

0x120 - MCPWM event enable register

pub fn task_en(&self) -> &Reg<TASK_EN_SPEC>

0x124 - MCPWM task enable register

pub fn clk(&self) -> &Reg<CLK_SPEC>

0x128 - MCPWM APB configuration register

pub fn version(&self) -> &Reg<VERSION_SPEC>

0x12c - Version register.

Trait Implementations

impl Debug for MCPWM0

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for MCPWM0

type Target = <MCPWM0 as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<MCPWM0 as Deref>::Target

Dereferences the value.

impl DerefMut for MCPWM0

fn deref_mut(&mut self) -> &mut <MCPWM0 as Deref>::Target

Mutably dereferences the value.

impl Peripheral for MCPWM0

type P = MCPWM0

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <MCPWM0 as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.

impl PwmPeripheral for MCPWM0

fn enable()

Enable peripheral

fn block() -> *const RegisterBlock

Get a pointer to the peripheral RegisterBlock

fn output_signal<const OP: u8, const IS_A: bool>() -> OutputSignal

Get operator GPIO mux output signal