Struct EXTMEM

pub struct EXTMEM { /* private fields */ }

Implementations

impl EXTMEM

pub const PTR: *const <EXTMEM as Deref>::Target = {0x600c8000 as *const <esp32c6::EXTMEM as core::ops::Deref>::Target}

Pointer to the register block

pub unsafe fn steal() -> EXTMEM

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const fn ptr() -> *const <EXTMEM as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn l1_icache_ctrl(&self) -> &Reg<L1_ICACHE_CTRL_SPEC>

0x00 - L1 instruction Cache(L1-ICache) control register

pub fn l1_cache_ctrl(&self) -> &Reg<L1_CACHE_CTRL_SPEC>

0x04 - L1 data Cache(L1-Cache) control register

pub fn l1_bypass_cache_conf(&self) -> &Reg<L1_BYPASS_CACHE_CONF_SPEC>

0x08 - Bypass Cache configure register

pub fn l1_cache_atomic_conf(&self) -> &Reg<L1_CACHE_ATOMIC_CONF_SPEC>

0x0c - L1 Cache atomic feature configure register

pub fn l1_icache_cachesize_conf(&self) -> &Reg<L1_ICACHE_CACHESIZE_CONF_SPEC>

0x10 - L1 instruction Cache CacheSize mode configure register

pub fn l1_icache_blocksize_conf(&self) -> &Reg<L1_ICACHE_BLOCKSIZE_CONF_SPEC>

0x14 - L1 instruction Cache BlockSize mode configure register

pub fn l1_cache_cachesize_conf(&self) -> &Reg<L1_CACHE_CACHESIZE_CONF_SPEC>

0x18 - L1 data Cache CacheSize mode configure register

pub fn l1_cache_blocksize_conf(&self) -> &Reg<L1_CACHE_BLOCKSIZE_CONF_SPEC>

0x1c - L1 data Cache BlockSize mode configure register

pub fn l1_cache_wrap_around_ctrl(&self) -> &Reg<L1_CACHE_WRAP_AROUND_CTRL_SPEC>

0x20 - Cache wrap around control register

pub fn l1_cache_tag_mem_power_ctrl( &self, ) -> &Reg<L1_CACHE_TAG_MEM_POWER_CTRL_SPEC>

0x24 - Cache tag memory power control register

pub fn l1_cache_data_mem_power_ctrl( &self, ) -> &Reg<L1_CACHE_DATA_MEM_POWER_CTRL_SPEC>

0x28 - Cache data memory power control register

pub fn l1_cache_freeze_ctrl(&self) -> &Reg<L1_CACHE_FREEZE_CTRL_SPEC>

0x2c - Cache Freeze control register

pub fn l1_cache_data_mem_acs_conf( &self, ) -> &Reg<L1_CACHE_DATA_MEM_ACS_CONF_SPEC>

0x30 - Cache data memory access configure register

pub fn l1_cache_tag_mem_acs_conf(&self) -> &Reg<L1_CACHE_TAG_MEM_ACS_CONF_SPEC>

0x34 - Cache tag memory access configure register

pub fn l1_icache0_prelock_conf(&self) -> &Reg<L1_ICACHE0_PRELOCK_CONF_SPEC>

0x38 - L1 instruction Cache 0 prelock configure register

pub fn l1_icache0_prelock_sct0_addr( &self, ) -> &Reg<L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC>

0x3c - L1 instruction Cache 0 prelock section0 address configure register

pub fn l1_icache0_prelock_sct1_addr( &self, ) -> &Reg<L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC>

0x40 - L1 instruction Cache 0 prelock section1 address configure register

pub fn l1_icache0_prelock_sct_size( &self, ) -> &Reg<L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC>

0x44 - L1 instruction Cache 0 prelock section size configure register

pub fn l1_icache1_prelock_conf(&self) -> &Reg<L1_ICACHE1_PRELOCK_CONF_SPEC>

0x48 - L1 instruction Cache 1 prelock configure register

pub fn l1_icache1_prelock_sct0_addr( &self, ) -> &Reg<L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC>

0x4c - L1 instruction Cache 1 prelock section0 address configure register

pub fn l1_icache1_prelock_sct1_addr( &self, ) -> &Reg<L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC>

0x50 - L1 instruction Cache 1 prelock section1 address configure register

pub fn l1_icache1_prelock_sct_size( &self, ) -> &Reg<L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC>

0x54 - L1 instruction Cache 1 prelock section size configure register

pub fn l1_icache2_prelock_conf(&self) -> &Reg<L1_ICACHE2_PRELOCK_CONF_SPEC>

0x58 - L1 instruction Cache 2 prelock configure register

pub fn l1_icache2_prelock_sct0_addr( &self, ) -> &Reg<L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC>

0x5c - L1 instruction Cache 2 prelock section0 address configure register

pub fn l1_icache2_prelock_sct1_addr( &self, ) -> &Reg<L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC>

0x60 - L1 instruction Cache 2 prelock section1 address configure register

pub fn l1_icache2_prelock_sct_size( &self, ) -> &Reg<L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC>

0x64 - L1 instruction Cache 2 prelock section size configure register

pub fn l1_icache3_prelock_conf(&self) -> &Reg<L1_ICACHE3_PRELOCK_CONF_SPEC>

0x68 - L1 instruction Cache 3 prelock configure register

pub fn l1_icache3_prelock_sct0_addr( &self, ) -> &Reg<L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC>

0x6c - L1 instruction Cache 3 prelock section0 address configure register

pub fn l1_icache3_prelock_sct1_addr( &self, ) -> &Reg<L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC>

0x70 - L1 instruction Cache 3 prelock section1 address configure register

pub fn l1_icache3_prelock_sct_size( &self, ) -> &Reg<L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC>

0x74 - L1 instruction Cache 3 prelock section size configure register

pub fn l1_cache_prelock_conf(&self) -> &Reg<L1_CACHE_PRELOCK_CONF_SPEC>

0x78 - L1 Cache prelock configure register

pub fn l1_cache_prelock_sct0_addr( &self, ) -> &Reg<L1_CACHE_PRELOCK_SCT0_ADDR_SPEC>

0x7c - L1 Cache prelock section0 address configure register

pub fn l1_dcache_prelock_sct1_addr( &self, ) -> &Reg<L1_DCACHE_PRELOCK_SCT1_ADDR_SPEC>

0x80 - L1 Cache prelock section1 address configure register

pub fn l1_dcache_prelock_sct_size( &self, ) -> &Reg<L1_DCACHE_PRELOCK_SCT_SIZE_SPEC>

0x84 - L1 Cache prelock section size configure register

pub fn cache_lock_ctrl(&self) -> &Reg<CACHE_LOCK_CTRL_SPEC>

0x88 - Lock-class (manual lock) operation control register

pub fn cache_lock_map(&self) -> &Reg<CACHE_LOCK_MAP_SPEC>

0x8c - Lock (manual lock) map configure register

pub fn cache_lock_addr(&self) -> &Reg<CACHE_LOCK_ADDR_SPEC>

0x90 - Lock (manual lock) address configure register

pub fn cache_lock_size(&self) -> &Reg<CACHE_LOCK_SIZE_SPEC>

0x94 - Lock (manual lock) size configure register

pub fn cache_sync_ctrl(&self) -> &Reg<CACHE_SYNC_CTRL_SPEC>

0x98 - Sync-class operation control register

pub fn cache_sync_map(&self) -> &Reg<CACHE_SYNC_MAP_SPEC>

0x9c - Sync map configure register

pub fn cache_sync_addr(&self) -> &Reg<CACHE_SYNC_ADDR_SPEC>

0xa0 - Sync address configure register

pub fn cache_sync_size(&self) -> &Reg<CACHE_SYNC_SIZE_SPEC>

0xa4 - Sync size configure register

pub fn l1_icache0_preload_ctrl(&self) -> &Reg<L1_ICACHE0_PRELOAD_CTRL_SPEC>

0xa8 - L1 instruction Cache 0 preload-operation control register

pub fn l1_icache0_preload_addr(&self) -> &Reg<L1_ICACHE0_PRELOAD_ADDR_SPEC>

0xac - L1 instruction Cache 0 preload address configure register

pub fn l1_icache0_preload_size(&self) -> &Reg<L1_ICACHE0_PRELOAD_SIZE_SPEC>

0xb0 - L1 instruction Cache 0 preload size configure register

pub fn l1_icache1_preload_ctrl(&self) -> &Reg<L1_ICACHE1_PRELOAD_CTRL_SPEC>

0xb4 - L1 instruction Cache 1 preload-operation control register

pub fn l1_icache1_preload_addr(&self) -> &Reg<L1_ICACHE1_PRELOAD_ADDR_SPEC>

0xb8 - L1 instruction Cache 1 preload address configure register

pub fn l1_icache1_preload_size(&self) -> &Reg<L1_ICACHE1_PRELOAD_SIZE_SPEC>

0xbc - L1 instruction Cache 1 preload size configure register

pub fn l1_icache2_preload_ctrl(&self) -> &Reg<L1_ICACHE2_PRELOAD_CTRL_SPEC>

0xc0 - L1 instruction Cache 2 preload-operation control register

pub fn l1_icache2_preload_addr(&self) -> &Reg<L1_ICACHE2_PRELOAD_ADDR_SPEC>

0xc4 - L1 instruction Cache 2 preload address configure register

pub fn l1_icache2_preload_size(&self) -> &Reg<L1_ICACHE2_PRELOAD_SIZE_SPEC>

0xc8 - L1 instruction Cache 2 preload size configure register

pub fn l1_icache3_preload_ctrl(&self) -> &Reg<L1_ICACHE3_PRELOAD_CTRL_SPEC>

0xcc - L1 instruction Cache 3 preload-operation control register

pub fn l1_icache3_preload_addr(&self) -> &Reg<L1_ICACHE3_PRELOAD_ADDR_SPEC>

0xd0 - L1 instruction Cache 3 preload address configure register

pub fn l1_icache3_preload_size(&self) -> &Reg<L1_ICACHE3_PRELOAD_SIZE_SPEC>

0xd4 - L1 instruction Cache 3 preload size configure register

pub fn l1_cache_preload_ctrl(&self) -> &Reg<L1_CACHE_PRELOAD_CTRL_SPEC>

0xd8 - L1 Cache preload-operation control register

pub fn l1_dcache_preload_addr(&self) -> &Reg<L1_DCACHE_PRELOAD_ADDR_SPEC>

0xdc - L1 Cache preload address configure register

pub fn l1_dcache_preload_size(&self) -> &Reg<L1_DCACHE_PRELOAD_SIZE_SPEC>

0xe0 - L1 Cache preload size configure register

pub fn l1_icache0_autoload_ctrl(&self) -> &Reg<L1_ICACHE0_AUTOLOAD_CTRL_SPEC>

0xe4 - L1 instruction Cache 0 autoload-operation control register

pub fn l1_icache0_autoload_sct0_addr( &self, ) -> &Reg<L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC>

0xe8 - L1 instruction Cache 0 autoload section 0 address configure register

pub fn l1_icache0_autoload_sct0_size( &self, ) -> &Reg<L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC>

0xec - L1 instruction Cache 0 autoload section 0 size configure register

pub fn l1_icache0_autoload_sct1_addr( &self, ) -> &Reg<L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC>

0xf0 - L1 instruction Cache 0 autoload section 1 address configure register

pub fn l1_icache0_autoload_sct1_size( &self, ) -> &Reg<L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC>

0xf4 - L1 instruction Cache 0 autoload section 1 size configure register

pub fn l1_icache1_autoload_ctrl(&self) -> &Reg<L1_ICACHE1_AUTOLOAD_CTRL_SPEC>

0xf8 - L1 instruction Cache 1 autoload-operation control register

pub fn l1_icache1_autoload_sct0_addr( &self, ) -> &Reg<L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC>

0xfc - L1 instruction Cache 1 autoload section 0 address configure register

pub fn l1_icache1_autoload_sct0_size( &self, ) -> &Reg<L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC>

0x100 - L1 instruction Cache 1 autoload section 0 size configure register

pub fn l1_icache1_autoload_sct1_addr( &self, ) -> &Reg<L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC>

0x104 - L1 instruction Cache 1 autoload section 1 address configure register

pub fn l1_icache1_autoload_sct1_size( &self, ) -> &Reg<L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC>

0x108 - L1 instruction Cache 1 autoload section 1 size configure register

pub fn l1_icache2_autoload_ctrl(&self) -> &Reg<L1_ICACHE2_AUTOLOAD_CTRL_SPEC>

0x10c - L1 instruction Cache 2 autoload-operation control register

pub fn l1_icache2_autoload_sct0_addr( &self, ) -> &Reg<L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC>

0x110 - L1 instruction Cache 2 autoload section 0 address configure register

pub fn l1_icache2_autoload_sct0_size( &self, ) -> &Reg<L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC>

0x114 - L1 instruction Cache 2 autoload section 0 size configure register

pub fn l1_icache2_autoload_sct1_addr( &self, ) -> &Reg<L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC>

0x118 - L1 instruction Cache 2 autoload section 1 address configure register

pub fn l1_icache2_autoload_sct1_size( &self, ) -> &Reg<L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC>

0x11c - L1 instruction Cache 2 autoload section 1 size configure register

pub fn l1_icache3_autoload_ctrl(&self) -> &Reg<L1_ICACHE3_AUTOLOAD_CTRL_SPEC>

0x120 - L1 instruction Cache 3 autoload-operation control register

pub fn l1_icache3_autoload_sct0_addr( &self, ) -> &Reg<L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC>

0x124 - L1 instruction Cache 3 autoload section 0 address configure register

pub fn l1_icache3_autoload_sct0_size( &self, ) -> &Reg<L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC>

0x128 - L1 instruction Cache 3 autoload section 0 size configure register

pub fn l1_icache3_autoload_sct1_addr( &self, ) -> &Reg<L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC>

0x12c - L1 instruction Cache 3 autoload section 1 address configure register

pub fn l1_icache3_autoload_sct1_size( &self, ) -> &Reg<L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC>

0x130 - L1 instruction Cache 3 autoload section 1 size configure register

pub fn l1_cache_autoload_ctrl(&self) -> &Reg<L1_CACHE_AUTOLOAD_CTRL_SPEC>

0x134 - L1 Cache autoload-operation control register

pub fn l1_cache_autoload_sct0_addr( &self, ) -> &Reg<L1_CACHE_AUTOLOAD_SCT0_ADDR_SPEC>

0x138 - L1 Cache autoload section 0 address configure register

pub fn l1_cache_autoload_sct0_size( &self, ) -> &Reg<L1_CACHE_AUTOLOAD_SCT0_SIZE_SPEC>

0x13c - L1 Cache autoload section 0 size configure register

pub fn l1_cache_autoload_sct1_addr( &self, ) -> &Reg<L1_CACHE_AUTOLOAD_SCT1_ADDR_SPEC>

0x140 - L1 Cache autoload section 1 address configure register

pub fn l1_cache_autoload_sct1_size( &self, ) -> &Reg<L1_CACHE_AUTOLOAD_SCT1_SIZE_SPEC>

0x144 - L1 Cache autoload section 1 size configure register

pub fn l1_cache_autoload_sct2_addr( &self, ) -> &Reg<L1_CACHE_AUTOLOAD_SCT2_ADDR_SPEC>

0x148 - L1 Cache autoload section 2 address configure register

pub fn l1_cache_autoload_sct2_size( &self, ) -> &Reg<L1_CACHE_AUTOLOAD_SCT2_SIZE_SPEC>

0x14c - L1 Cache autoload section 2 size configure register

pub fn l1_cache_autoload_sct3_addr( &self, ) -> &Reg<L1_CACHE_AUTOLOAD_SCT3_ADDR_SPEC>

0x150 - L1 Cache autoload section 1 address configure register

pub fn l1_cache_autoload_sct3_size( &self, ) -> &Reg<L1_CACHE_AUTOLOAD_SCT3_SIZE_SPEC>

0x154 - L1 Cache autoload section 1 size configure register

pub fn l1_cache_acs_cnt_int_ena(&self) -> &Reg<L1_CACHE_ACS_CNT_INT_ENA_SPEC>

0x158 - Cache Access Counter Interrupt enable register

pub fn l1_cache_acs_cnt_int_clr(&self) -> &Reg<L1_CACHE_ACS_CNT_INT_CLR_SPEC>

0x15c - Cache Access Counter Interrupt clear register

pub fn l1_cache_acs_cnt_int_raw(&self) -> &Reg<L1_CACHE_ACS_CNT_INT_RAW_SPEC>

0x160 - Cache Access Counter Interrupt raw register

pub fn l1_cache_acs_cnt_int_st(&self) -> &Reg<L1_CACHE_ACS_CNT_INT_ST_SPEC>

0x164 - Cache Access Counter Interrupt status register

pub fn l1_cache_acs_fail_int_ena(&self) -> &Reg<L1_CACHE_ACS_FAIL_INT_ENA_SPEC>

0x168 - Cache Access Fail Interrupt enable register

pub fn l1_cache_acs_fail_int_clr(&self) -> &Reg<L1_CACHE_ACS_FAIL_INT_CLR_SPEC>

0x16c - L1-Cache Access Fail Interrupt clear register

pub fn l1_cache_acs_fail_int_raw(&self) -> &Reg<L1_CACHE_ACS_FAIL_INT_RAW_SPEC>

0x170 - Cache Access Fail Interrupt raw register

pub fn l1_cache_acs_fail_int_st(&self) -> &Reg<L1_CACHE_ACS_FAIL_INT_ST_SPEC>

0x174 - Cache Access Fail Interrupt status register

pub fn l1_cache_acs_cnt_ctrl(&self) -> &Reg<L1_CACHE_ACS_CNT_CTRL_SPEC>

0x178 - Cache Access Counter enable and clear register

pub fn l1_ibus0_acs_hit_cnt(&self) -> &Reg<L1_IBUS0_ACS_HIT_CNT_SPEC>

0x17c - L1-ICache bus0 Hit-Access Counter register

pub fn l1_ibus0_acs_miss_cnt(&self) -> &Reg<L1_IBUS0_ACS_MISS_CNT_SPEC>

0x180 - L1-ICache bus0 Miss-Access Counter register

pub fn l1_ibus0_acs_conflict_cnt(&self) -> &Reg<L1_IBUS0_ACS_CONFLICT_CNT_SPEC>

0x184 - L1-ICache bus0 Conflict-Access Counter register

pub fn l1_ibus0_acs_nxtlvl_cnt(&self) -> &Reg<L1_IBUS0_ACS_NXTLVL_CNT_SPEC>

0x188 - L1-ICache bus0 Next-Level-Access Counter register

pub fn l1_ibus1_acs_hit_cnt(&self) -> &Reg<L1_IBUS1_ACS_HIT_CNT_SPEC>

0x18c - L1-ICache bus1 Hit-Access Counter register

pub fn l1_ibus1_acs_miss_cnt(&self) -> &Reg<L1_IBUS1_ACS_MISS_CNT_SPEC>

0x190 - L1-ICache bus1 Miss-Access Counter register

pub fn l1_ibus1_acs_conflict_cnt(&self) -> &Reg<L1_IBUS1_ACS_CONFLICT_CNT_SPEC>

0x194 - L1-ICache bus1 Conflict-Access Counter register

pub fn l1_ibus1_acs_nxtlvl_cnt(&self) -> &Reg<L1_IBUS1_ACS_NXTLVL_CNT_SPEC>

0x198 - L1-ICache bus1 Next-Level-Access Counter register

pub fn l1_ibus2_acs_hit_cnt(&self) -> &Reg<L1_IBUS2_ACS_HIT_CNT_SPEC>

0x19c - L1-ICache bus2 Hit-Access Counter register

pub fn l1_ibus2_acs_miss_cnt(&self) -> &Reg<L1_IBUS2_ACS_MISS_CNT_SPEC>

0x1a0 - L1-ICache bus2 Miss-Access Counter register

pub fn l1_ibus2_acs_conflict_cnt(&self) -> &Reg<L1_IBUS2_ACS_CONFLICT_CNT_SPEC>

0x1a4 - L1-ICache bus2 Conflict-Access Counter register

pub fn l1_ibus2_acs_nxtlvl_cnt(&self) -> &Reg<L1_IBUS2_ACS_NXTLVL_CNT_SPEC>

0x1a8 - L1-ICache bus2 Next-Level-Access Counter register

pub fn l1_ibus3_acs_hit_cnt(&self) -> &Reg<L1_IBUS3_ACS_HIT_CNT_SPEC>

0x1ac - L1-ICache bus3 Hit-Access Counter register

pub fn l1_ibus3_acs_miss_cnt(&self) -> &Reg<L1_IBUS3_ACS_MISS_CNT_SPEC>

0x1b0 - L1-ICache bus3 Miss-Access Counter register

pub fn l1_ibus3_acs_conflict_cnt(&self) -> &Reg<L1_IBUS3_ACS_CONFLICT_CNT_SPEC>

0x1b4 - L1-ICache bus3 Conflict-Access Counter register

pub fn l1_ibus3_acs_nxtlvl_cnt(&self) -> &Reg<L1_IBUS3_ACS_NXTLVL_CNT_SPEC>

0x1b8 - L1-ICache bus3 Next-Level-Access Counter register

pub fn l1_bus0_acs_hit_cnt(&self) -> &Reg<L1_BUS0_ACS_HIT_CNT_SPEC>

0x1bc - L1-Cache bus0 Hit-Access Counter register

pub fn l1_bus0_acs_miss_cnt(&self) -> &Reg<L1_BUS0_ACS_MISS_CNT_SPEC>

0x1c0 - L1-Cache bus0 Miss-Access Counter register

pub fn l1_bus0_acs_conflict_cnt(&self) -> &Reg<L1_BUS0_ACS_CONFLICT_CNT_SPEC>

0x1c4 - L1-Cache bus0 Conflict-Access Counter register

pub fn l1_bus0_acs_nxtlvl_cnt(&self) -> &Reg<L1_BUS0_ACS_NXTLVL_CNT_SPEC>

0x1c8 - L1-Cache bus0 Next-Level-Access Counter register

pub fn l1_bus1_acs_hit_cnt(&self) -> &Reg<L1_BUS1_ACS_HIT_CNT_SPEC>

0x1cc - L1-Cache bus1 Hit-Access Counter register

pub fn l1_bus1_acs_miss_cnt(&self) -> &Reg<L1_BUS1_ACS_MISS_CNT_SPEC>

0x1d0 - L1-Cache bus1 Miss-Access Counter register

pub fn l1_bus1_acs_conflict_cnt(&self) -> &Reg<L1_BUS1_ACS_CONFLICT_CNT_SPEC>

0x1d4 - L1-Cache bus1 Conflict-Access Counter register

pub fn l1_bus1_acs_nxtlvl_cnt(&self) -> &Reg<L1_BUS1_ACS_NXTLVL_CNT_SPEC>

0x1d8 - L1-Cache bus1 Next-Level-Access Counter register

pub fn l1_dbus2_acs_hit_cnt(&self) -> &Reg<L1_DBUS2_ACS_HIT_CNT_SPEC>

0x1dc - L1-DCache bus2 Hit-Access Counter register

pub fn l1_dbus2_acs_miss_cnt(&self) -> &Reg<L1_DBUS2_ACS_MISS_CNT_SPEC>

0x1e0 - L1-DCache bus2 Miss-Access Counter register

pub fn l1_dbus2_acs_conflict_cnt(&self) -> &Reg<L1_DBUS2_ACS_CONFLICT_CNT_SPEC>

0x1e4 - L1-DCache bus2 Conflict-Access Counter register

pub fn l1_dbus2_acs_nxtlvl_cnt(&self) -> &Reg<L1_DBUS2_ACS_NXTLVL_CNT_SPEC>

0x1e8 - L1-DCache bus2 Next-Level-Access Counter register

pub fn l1_dbus3_acs_hit_cnt(&self) -> &Reg<L1_DBUS3_ACS_HIT_CNT_SPEC>

0x1ec - L1-DCache bus3 Hit-Access Counter register

pub fn l1_dbus3_acs_miss_cnt(&self) -> &Reg<L1_DBUS3_ACS_MISS_CNT_SPEC>

0x1f0 - L1-DCache bus3 Miss-Access Counter register

pub fn l1_dbus3_acs_conflict_cnt(&self) -> &Reg<L1_DBUS3_ACS_CONFLICT_CNT_SPEC>

0x1f4 - L1-DCache bus3 Conflict-Access Counter register

pub fn l1_dbus3_acs_nxtlvl_cnt(&self) -> &Reg<L1_DBUS3_ACS_NXTLVL_CNT_SPEC>

0x1f8 - L1-DCache bus3 Next-Level-Access Counter register

pub fn l1_icache0_acs_fail_id_attr( &self, ) -> &Reg<L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC>

0x1fc - L1-ICache0 Access Fail ID/attribution information register

pub fn l1_icache0_acs_fail_addr(&self) -> &Reg<L1_ICACHE0_ACS_FAIL_ADDR_SPEC>

0x200 - L1-ICache0 Access Fail Address information register

pub fn l1_icache1_acs_fail_id_attr( &self, ) -> &Reg<L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC>

0x204 - L1-ICache0 Access Fail ID/attribution information register

pub fn l1_icache1_acs_fail_addr(&self) -> &Reg<L1_ICACHE1_ACS_FAIL_ADDR_SPEC>

0x208 - L1-ICache0 Access Fail Address information register

pub fn l1_icache2_acs_fail_id_attr( &self, ) -> &Reg<L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC>

0x20c - L1-ICache0 Access Fail ID/attribution information register

pub fn l1_icache2_acs_fail_addr(&self) -> &Reg<L1_ICACHE2_ACS_FAIL_ADDR_SPEC>

0x210 - L1-ICache0 Access Fail Address information register

pub fn l1_icache3_acs_fail_id_attr( &self, ) -> &Reg<L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC>

0x214 - L1-ICache0 Access Fail ID/attribution information register

pub fn l1_icache3_acs_fail_addr(&self) -> &Reg<L1_ICACHE3_ACS_FAIL_ADDR_SPEC>

0x218 - L1-ICache0 Access Fail Address information register

pub fn l1_cache_acs_fail_id_attr(&self) -> &Reg<L1_CACHE_ACS_FAIL_ID_ATTR_SPEC>

0x21c - L1-Cache Access Fail ID/attribution information register

pub fn l1_dcache_acs_fail_addr(&self) -> &Reg<L1_DCACHE_ACS_FAIL_ADDR_SPEC>

0x220 - L1-Cache Access Fail Address information register

pub fn l1_cache_sync_preload_int_ena( &self, ) -> &Reg<L1_CACHE_SYNC_PRELOAD_INT_ENA_SPEC>

0x224 - L1-Cache Access Fail Interrupt enable register

pub fn l1_cache_sync_preload_int_clr( &self, ) -> &Reg<L1_CACHE_SYNC_PRELOAD_INT_CLR_SPEC>

0x228 - Sync Preload operation Interrupt clear register

pub fn l1_cache_sync_preload_int_raw( &self, ) -> &Reg<L1_CACHE_SYNC_PRELOAD_INT_RAW_SPEC>

0x22c - Sync Preload operation Interrupt raw register

pub fn l1_cache_sync_preload_int_st( &self, ) -> &Reg<L1_CACHE_SYNC_PRELOAD_INT_ST_SPEC>

0x230 - L1-Cache Access Fail Interrupt status register

pub fn l1_cache_sync_preload_exception( &self, ) -> &Reg<L1_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC>

0x234 - Cache Sync/Preload Operation exception register

pub fn l1_cache_sync_rst_ctrl(&self) -> &Reg<L1_CACHE_SYNC_RST_CTRL_SPEC>

0x238 - Cache Sync Reset control register

pub fn l1_cache_preload_rst_ctrl(&self) -> &Reg<L1_CACHE_PRELOAD_RST_CTRL_SPEC>

0x23c - Cache Preload Reset control register

pub fn l1_cache_autoload_buf_clr_ctrl( &self, ) -> &Reg<L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC>

0x240 - Cache Autoload buffer clear control register

pub fn l1_unallocate_buffer_clear( &self, ) -> &Reg<L1_UNALLOCATE_BUFFER_CLEAR_SPEC>

0x244 - Unallocate request buffer clear registers

pub fn l1_cache_object_ctrl(&self) -> &Reg<L1_CACHE_OBJECT_CTRL_SPEC>

0x248 - Cache Tag and Data memory Object control register

pub fn l1_cache_way_object(&self) -> &Reg<L1_CACHE_WAY_OBJECT_SPEC>

0x24c - Cache Tag and Data memory way register

pub fn l1_cache_vaddr(&self) -> &Reg<L1_CACHE_VADDR_SPEC>

0x250 - Cache Vaddr register

pub fn l1_cache_debug_bus(&self) -> &Reg<L1_CACHE_DEBUG_BUS_SPEC>

0x254 - Cache Tag/data memory content register

pub fn level_split0(&self) -> &Reg<LEVEL_SPLIT0_SPEC>

0x258 - USED TO SPLIT L1 CACHE AND L2 CACHE

pub fn l2_cache_ctrl(&self) -> &Reg<L2_CACHE_CTRL_SPEC>

0x25c - L2 Cache(L2-Cache) control register

pub fn l2_bypass_cache_conf(&self) -> &Reg<L2_BYPASS_CACHE_CONF_SPEC>

0x260 - Bypass Cache configure register

pub fn l2_cache_cachesize_conf(&self) -> &Reg<L2_CACHE_CACHESIZE_CONF_SPEC>

0x264 - L2 Cache CacheSize mode configure register

pub fn l2_cache_blocksize_conf(&self) -> &Reg<L2_CACHE_BLOCKSIZE_CONF_SPEC>

0x268 - L2 Cache BlockSize mode configure register

pub fn l2_cache_wrap_around_ctrl(&self) -> &Reg<L2_CACHE_WRAP_AROUND_CTRL_SPEC>

0x26c - Cache wrap around control register

pub fn l2_cache_tag_mem_power_ctrl( &self, ) -> &Reg<L2_CACHE_TAG_MEM_POWER_CTRL_SPEC>

0x270 - Cache tag memory power control register

pub fn l2_cache_data_mem_power_ctrl( &self, ) -> &Reg<L2_CACHE_DATA_MEM_POWER_CTRL_SPEC>

0x274 - Cache data memory power control register

pub fn l2_cache_freeze_ctrl(&self) -> &Reg<L2_CACHE_FREEZE_CTRL_SPEC>

0x278 - Cache Freeze control register

pub fn l2_cache_data_mem_acs_conf( &self, ) -> &Reg<L2_CACHE_DATA_MEM_ACS_CONF_SPEC>

0x27c - Cache data memory access configure register

pub fn l2_cache_tag_mem_acs_conf(&self) -> &Reg<L2_CACHE_TAG_MEM_ACS_CONF_SPEC>

0x280 - Cache tag memory access configure register

pub fn l2_cache_prelock_conf(&self) -> &Reg<L2_CACHE_PRELOCK_CONF_SPEC>

0x284 - L2 Cache prelock configure register

pub fn l2_cache_prelock_sct0_addr( &self, ) -> &Reg<L2_CACHE_PRELOCK_SCT0_ADDR_SPEC>

0x288 - L2 Cache prelock section0 address configure register

pub fn l2_cache_prelock_sct1_addr( &self, ) -> &Reg<L2_CACHE_PRELOCK_SCT1_ADDR_SPEC>

0x28c - L2 Cache prelock section1 address configure register

pub fn l2_cache_prelock_sct_size(&self) -> &Reg<L2_CACHE_PRELOCK_SCT_SIZE_SPEC>

0x290 - L2 Cache prelock section size configure register

pub fn l2_cache_preload_ctrl(&self) -> &Reg<L2_CACHE_PRELOAD_CTRL_SPEC>

0x294 - L2 Cache preload-operation control register

pub fn l2_cache_preload_addr(&self) -> &Reg<L2_CACHE_PRELOAD_ADDR_SPEC>

0x298 - L2 Cache preload address configure register

pub fn l2_cache_preload_size(&self) -> &Reg<L2_CACHE_PRELOAD_SIZE_SPEC>

0x29c - L2 Cache preload size configure register

pub fn l2_cache_autoload_ctrl(&self) -> &Reg<L2_CACHE_AUTOLOAD_CTRL_SPEC>

0x2a0 - L2 Cache autoload-operation control register

pub fn l2_cache_autoload_sct0_addr( &self, ) -> &Reg<L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC>

0x2a4 - L2 Cache autoload section 0 address configure register

pub fn l2_cache_autoload_sct0_size( &self, ) -> &Reg<L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC>

0x2a8 - L2 Cache autoload section 0 size configure register

pub fn l2_cache_autoload_sct1_addr( &self, ) -> &Reg<L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC>

0x2ac - L2 Cache autoload section 1 address configure register

pub fn l2_cache_autoload_sct1_size( &self, ) -> &Reg<L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC>

0x2b0 - L2 Cache autoload section 1 size configure register

pub fn l2_cache_autoload_sct2_addr( &self, ) -> &Reg<L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC>

0x2b4 - L2 Cache autoload section 2 address configure register

pub fn l2_cache_autoload_sct2_size( &self, ) -> &Reg<L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC>

0x2b8 - L2 Cache autoload section 2 size configure register

pub fn l2_cache_autoload_sct3_addr( &self, ) -> &Reg<L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC>

0x2bc - L2 Cache autoload section 3 address configure register

pub fn l2_cache_autoload_sct3_size( &self, ) -> &Reg<L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC>

0x2c0 - L2 Cache autoload section 3 size configure register

pub fn l2_cache_acs_cnt_int_ena(&self) -> &Reg<L2_CACHE_ACS_CNT_INT_ENA_SPEC>

0x2c4 - Cache Access Counter Interrupt enable register

pub fn l2_cache_acs_cnt_int_clr(&self) -> &Reg<L2_CACHE_ACS_CNT_INT_CLR_SPEC>

0x2c8 - Cache Access Counter Interrupt clear register

pub fn l2_cache_acs_cnt_int_raw(&self) -> &Reg<L2_CACHE_ACS_CNT_INT_RAW_SPEC>

0x2cc - Cache Access Counter Interrupt raw register

pub fn l2_cache_acs_cnt_int_st(&self) -> &Reg<L2_CACHE_ACS_CNT_INT_ST_SPEC>

0x2d0 - Cache Access Counter Interrupt status register

pub fn l2_cache_acs_fail_int_ena(&self) -> &Reg<L2_CACHE_ACS_FAIL_INT_ENA_SPEC>

0x2d4 - Cache Access Fail Interrupt enable register

pub fn l2_cache_acs_fail_int_clr(&self) -> &Reg<L2_CACHE_ACS_FAIL_INT_CLR_SPEC>

0x2d8 - L1-Cache Access Fail Interrupt clear register

pub fn l2_cache_acs_fail_int_raw(&self) -> &Reg<L2_CACHE_ACS_FAIL_INT_RAW_SPEC>

0x2dc - Cache Access Fail Interrupt raw register

pub fn l2_cache_acs_fail_int_st(&self) -> &Reg<L2_CACHE_ACS_FAIL_INT_ST_SPEC>

0x2e0 - Cache Access Fail Interrupt status register

pub fn l2_cache_acs_cnt_ctrl(&self) -> &Reg<L2_CACHE_ACS_CNT_CTRL_SPEC>

0x2e4 - Cache Access Counter enable and clear register

pub fn l2_ibus0_acs_hit_cnt(&self) -> &Reg<L2_IBUS0_ACS_HIT_CNT_SPEC>

0x2e8 - L2-Cache bus0 Hit-Access Counter register

pub fn l2_ibus0_acs_miss_cnt(&self) -> &Reg<L2_IBUS0_ACS_MISS_CNT_SPEC>

0x2ec - L2-Cache bus0 Miss-Access Counter register

pub fn l2_ibus0_acs_conflict_cnt(&self) -> &Reg<L2_IBUS0_ACS_CONFLICT_CNT_SPEC>

0x2f0 - L2-Cache bus0 Conflict-Access Counter register

pub fn l2_ibus0_acs_nxtlvl_cnt(&self) -> &Reg<L2_IBUS0_ACS_NXTLVL_CNT_SPEC>

0x2f4 - L2-Cache bus0 Next-Level-Access Counter register

pub fn l2_ibus1_acs_hit_cnt(&self) -> &Reg<L2_IBUS1_ACS_HIT_CNT_SPEC>

0x2f8 - L2-Cache bus1 Hit-Access Counter register

pub fn l2_ibus1_acs_miss_cnt(&self) -> &Reg<L2_IBUS1_ACS_MISS_CNT_SPEC>

0x2fc - L2-Cache bus1 Miss-Access Counter register

pub fn l2_ibus1_acs_conflict_cnt(&self) -> &Reg<L2_IBUS1_ACS_CONFLICT_CNT_SPEC>

0x300 - L2-Cache bus1 Conflict-Access Counter register

pub fn l2_ibus1_acs_nxtlvl_cnt(&self) -> &Reg<L2_IBUS1_ACS_NXTLVL_CNT_SPEC>

0x304 - L2-Cache bus1 Next-Level-Access Counter register

pub fn l2_ibus2_acs_hit_cnt(&self) -> &Reg<L2_IBUS2_ACS_HIT_CNT_SPEC>

0x308 - L2-Cache bus2 Hit-Access Counter register

pub fn l2_ibus2_acs_miss_cnt(&self) -> &Reg<L2_IBUS2_ACS_MISS_CNT_SPEC>

0x30c - L2-Cache bus2 Miss-Access Counter register

pub fn l2_ibus2_acs_conflict_cnt(&self) -> &Reg<L2_IBUS2_ACS_CONFLICT_CNT_SPEC>

0x310 - L2-Cache bus2 Conflict-Access Counter register

pub fn l2_ibus2_acs_nxtlvl_cnt(&self) -> &Reg<L2_IBUS2_ACS_NXTLVL_CNT_SPEC>

0x314 - L2-Cache bus2 Next-Level-Access Counter register

pub fn l2_ibus3_acs_hit_cnt(&self) -> &Reg<L2_IBUS3_ACS_HIT_CNT_SPEC>

0x318 - L2-Cache bus3 Hit-Access Counter register

pub fn l2_ibus3_acs_miss_cnt(&self) -> &Reg<L2_IBUS3_ACS_MISS_CNT_SPEC>

0x31c - L2-Cache bus3 Miss-Access Counter register

pub fn l2_ibus3_acs_conflict_cnt(&self) -> &Reg<L2_IBUS3_ACS_CONFLICT_CNT_SPEC>

0x320 - L2-Cache bus3 Conflict-Access Counter register

pub fn l2_ibus3_acs_nxtlvl_cnt(&self) -> &Reg<L2_IBUS3_ACS_NXTLVL_CNT_SPEC>

0x324 - L2-Cache bus3 Next-Level-Access Counter register

pub fn l2_dbus0_acs_hit_cnt(&self) -> &Reg<L2_DBUS0_ACS_HIT_CNT_SPEC>

0x328 - L2-Cache bus0 Hit-Access Counter register

pub fn l2_dbus0_acs_miss_cnt(&self) -> &Reg<L2_DBUS0_ACS_MISS_CNT_SPEC>

0x32c - L2-Cache bus0 Miss-Access Counter register

pub fn l2_dbus0_acs_conflict_cnt(&self) -> &Reg<L2_DBUS0_ACS_CONFLICT_CNT_SPEC>

0x330 - L2-Cache bus0 Conflict-Access Counter register

pub fn l2_dbus0_acs_nxtlvl_cnt(&self) -> &Reg<L2_DBUS0_ACS_NXTLVL_CNT_SPEC>

0x334 - L2-Cache bus0 Next-Level-Access Counter register

pub fn l2_dbus1_acs_hit_cnt(&self) -> &Reg<L2_DBUS1_ACS_HIT_CNT_SPEC>

0x338 - L2-Cache bus1 Hit-Access Counter register

pub fn l2_dbus1_acs_miss_cnt(&self) -> &Reg<L2_DBUS1_ACS_MISS_CNT_SPEC>

0x33c - L2-Cache bus1 Miss-Access Counter register

pub fn l2_dbus1_acs_conflict_cnt(&self) -> &Reg<L2_DBUS1_ACS_CONFLICT_CNT_SPEC>

0x340 - L2-Cache bus1 Conflict-Access Counter register

pub fn l2_dbus1_acs_nxtlvl_cnt(&self) -> &Reg<L2_DBUS1_ACS_NXTLVL_CNT_SPEC>

0x344 - L2-Cache bus1 Next-Level-Access Counter register

pub fn l2_dbus2_acs_hit_cnt(&self) -> &Reg<L2_DBUS2_ACS_HIT_CNT_SPEC>

0x348 - L2-Cache bus2 Hit-Access Counter register

pub fn l2_dbus2_acs_miss_cnt(&self) -> &Reg<L2_DBUS2_ACS_MISS_CNT_SPEC>

0x34c - L2-Cache bus2 Miss-Access Counter register

pub fn l2_dbus2_acs_conflict_cnt(&self) -> &Reg<L2_DBUS2_ACS_CONFLICT_CNT_SPEC>

0x350 - L2-Cache bus2 Conflict-Access Counter register

pub fn l2_dbus2_acs_nxtlvl_cnt(&self) -> &Reg<L2_DBUS2_ACS_NXTLVL_CNT_SPEC>

0x354 - L2-Cache bus2 Next-Level-Access Counter register

pub fn l2_dbus3_acs_hit_cnt(&self) -> &Reg<L2_DBUS3_ACS_HIT_CNT_SPEC>

0x358 - L2-Cache bus3 Hit-Access Counter register

pub fn l2_dbus3_acs_miss_cnt(&self) -> &Reg<L2_DBUS3_ACS_MISS_CNT_SPEC>

0x35c - L2-Cache bus3 Miss-Access Counter register

pub fn l2_dbus3_acs_conflict_cnt(&self) -> &Reg<L2_DBUS3_ACS_CONFLICT_CNT_SPEC>

0x360 - L2-Cache bus3 Conflict-Access Counter register

pub fn l2_dbus3_acs_nxtlvl_cnt(&self) -> &Reg<L2_DBUS3_ACS_NXTLVL_CNT_SPEC>

0x364 - L2-Cache bus3 Next-Level-Access Counter register

pub fn l2_cache_acs_fail_id_attr(&self) -> &Reg<L2_CACHE_ACS_FAIL_ID_ATTR_SPEC>

0x368 - L2-Cache Access Fail ID/attribution information register

pub fn l2_cache_acs_fail_addr(&self) -> &Reg<L2_CACHE_ACS_FAIL_ADDR_SPEC>

0x36c - L2-Cache Access Fail Address information register

pub fn l2_cache_sync_preload_int_ena( &self, ) -> &Reg<L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC>

0x370 - L1-Cache Access Fail Interrupt enable register

pub fn l2_cache_sync_preload_int_clr( &self, ) -> &Reg<L2_CACHE_SYNC_PRELOAD_INT_CLR_SPEC>

0x374 - Sync Preload operation Interrupt clear register

pub fn l2_cache_sync_preload_int_raw( &self, ) -> &Reg<L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC>

0x378 - Sync Preload operation Interrupt raw register

pub fn l2_cache_sync_preload_int_st( &self, ) -> &Reg<L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC>

0x37c - L1-Cache Access Fail Interrupt status register

pub fn l2_cache_sync_preload_exception( &self, ) -> &Reg<L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC>

0x380 - Cache Sync/Preload Operation exception register

pub fn l2_cache_sync_rst_ctrl(&self) -> &Reg<L2_CACHE_SYNC_RST_CTRL_SPEC>

0x384 - Cache Sync Reset control register

pub fn l2_cache_preload_rst_ctrl(&self) -> &Reg<L2_CACHE_PRELOAD_RST_CTRL_SPEC>

0x388 - Cache Preload Reset control register

pub fn l2_cache_autoload_buf_clr_ctrl( &self, ) -> &Reg<L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC>

0x38c - Cache Autoload buffer clear control register

pub fn l2_unallocate_buffer_clear( &self, ) -> &Reg<L2_UNALLOCATE_BUFFER_CLEAR_SPEC>

0x390 - Unallocate request buffer clear registers

pub fn l2_cache_access_attr_ctrl(&self) -> &Reg<L2_CACHE_ACCESS_ATTR_CTRL_SPEC>

0x394 - L1 Cache access Attribute propagation control register

pub fn l2_cache_object_ctrl(&self) -> &Reg<L2_CACHE_OBJECT_CTRL_SPEC>

0x398 - Cache Tag and Data memory Object control register

pub fn l2_cache_way_object(&self) -> &Reg<L2_CACHE_WAY_OBJECT_SPEC>

0x39c - Cache Tag and Data memory way register

pub fn l2_cache_vaddr(&self) -> &Reg<L2_CACHE_VADDR_SPEC>

0x3a0 - Cache Vaddr register

pub fn l2_cache_debug_bus(&self) -> &Reg<L2_CACHE_DEBUG_BUS_SPEC>

0x3a4 - Cache Tag/data memory content register

pub fn level_split1(&self) -> &Reg<LEVEL_SPLIT1_SPEC>

0x3a8 - USED TO SPLIT L1 CACHE AND L2 CACHE

pub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>

0x3ac - Clock gate control register

pub fn redundancy_sig0(&self) -> &Reg<REDUNDANCY_SIG0_SPEC>

0x3b0 - Cache redundancy signal 0 register

pub fn redundancy_sig1(&self) -> &Reg<REDUNDANCY_SIG1_SPEC>

0x3b4 - Cache redundancy signal 1 register

pub fn redundancy_sig2(&self) -> &Reg<REDUNDANCY_SIG2_SPEC>

0x3b8 - Cache redundancy signal 2 register

pub fn redundancy_sig3(&self) -> &Reg<REDUNDANCY_SIG3_SPEC>

0x3bc - Cache redundancy signal 3 register

pub fn redundancy_sig4(&self) -> &Reg<REDUNDANCY_SIG4_SPEC>

0x3c0 - Cache redundancy signal 0 register

pub fn date(&self) -> &Reg<DATE_SPEC>

0x3fc - Version control register

Trait Implementations

impl Debug for EXTMEM

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for EXTMEM

type Target = <EXTMEM as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<EXTMEM as Deref>::Target

Dereferences the value.

impl DerefMut for EXTMEM

fn deref_mut(&mut self) -> &mut <EXTMEM as Deref>::Target

Mutably dereferences the value.

impl Peripheral for EXTMEM

type P = EXTMEM

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <EXTMEM as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.