Struct I2C0

pub struct I2C0 { /* private fields */ }

Implementations

impl I2C0

pub const PTR: *const <I2C0 as Deref>::Target = {0x60004000 as *const <esp32c6::I2C0 as core::ops::Deref>::Target}

Pointer to the register block

pub unsafe fn steal() -> I2C0

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const fn ptr() -> *const <I2C0 as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn scl_low_period(&self) -> &Reg<SCL_LOW_PERIOD_SPEC>

0x00 - Configures the low level width of the SCL Clock

pub fn ctr(&self) -> &Reg<CTR_SPEC>

0x04 - Transmission setting

pub fn sr(&self) -> &Reg<SR_SPEC>

0x08 - Describe I2C work status.

pub fn to(&self) -> &Reg<TO_SPEC>

0x0c - Setting time out control for receiving data.

pub fn slave_addr(&self) -> &Reg<SLAVE_ADDR_SPEC>

0x10 - Local slave address setting

pub fn fifo_st(&self) -> &Reg<FIFO_ST_SPEC>

0x14 - FIFO status register.

pub fn fifo_conf(&self) -> &Reg<FIFO_CONF_SPEC>

0x18 - FIFO configuration register.

pub fn data(&self) -> &Reg<DATA_SPEC>

0x1c - Rx FIFO read data.

pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>

0x20 - Raw interrupt status

pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>

0x24 - Interrupt clear bits

pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>

0x28 - Interrupt enable bits

pub fn int_status(&self) -> &Reg<INT_STATUS_SPEC>

0x2c - Status of captured I2C communication events

pub fn sda_hold(&self) -> &Reg<SDA_HOLD_SPEC>

0x30 - Configures the hold time after a negative SCL edge.

pub fn sda_sample(&self) -> &Reg<SDA_SAMPLE_SPEC>

0x34 - Configures the sample time after a positive SCL edge.

pub fn scl_high_period(&self) -> &Reg<SCL_HIGH_PERIOD_SPEC>

0x38 - Configures the high level width of SCL

pub fn scl_start_hold(&self) -> &Reg<SCL_START_HOLD_SPEC>

0x40 - Configures the delay between the SDA and SCL negative edge for a start condition

pub fn scl_rstart_setup(&self) -> &Reg<SCL_RSTART_SETUP_SPEC>

0x44 - Configures the delay between the positive edge of SCL and the negative edge of SDA

pub fn scl_stop_hold(&self) -> &Reg<SCL_STOP_HOLD_SPEC>

0x48 - Configures the delay after the SCL clock edge for a stop condition

pub fn scl_stop_setup(&self) -> &Reg<SCL_STOP_SETUP_SPEC>

0x4c - Configures the delay between the SDA and SCL positive edge for a stop condition

pub fn filter_cfg(&self) -> &Reg<FILTER_CFG_SPEC>

0x50 - SCL and SDA filter configuration register

pub fn clk_conf(&self) -> &Reg<CLK_CONF_SPEC>

0x54 - I2C CLK configuration register

pub fn comd(&self, n: usize) -> &Reg<COMD_SPEC>

0x58..0x78 - I2C command register %s

pub fn comd_iter(&self) -> impl Iterator<Item = &Reg<COMD_SPEC>>

Iterator for array of: 0x58..0x78 - I2C command register %s

pub fn scl_st_time_out(&self) -> &Reg<SCL_ST_TIME_OUT_SPEC>

0x78 - SCL status time out register

pub fn scl_main_st_time_out(&self) -> &Reg<SCL_MAIN_ST_TIME_OUT_SPEC>

0x7c - SCL main status time out register

pub fn scl_sp_conf(&self) -> &Reg<SCL_SP_CONF_SPEC>

0x80 - Power configuration register

pub fn scl_stretch_conf(&self) -> &Reg<SCL_STRETCH_CONF_SPEC>

0x84 - Set SCL stretch of I2C slave

pub fn date(&self) -> &Reg<DATE_SPEC>

0xf8 - Version register

pub fn txfifo_start_addr(&self) -> &Reg<TXFIFO_START_ADDR_SPEC>

0x100 - I2C TXFIFO base address register

pub fn rxfifo_start_addr(&self) -> &Reg<RXFIFO_START_ADDR_SPEC>

0x180 - I2C RXFIFO base address register

Trait Implementations

impl Debug for I2C0

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for I2C0

type Target = <I2C0 as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<I2C0 as Deref>::Target

Dereferences the value.

impl DerefMut for I2C0

fn deref_mut(&mut self) -> &mut <I2C0 as Deref>::Target

Mutably dereferences the value.

impl Instance for I2C0

fn scl_output_signal(&self) -> OutputSignal

fn scl_input_signal(&self) -> InputSignal

fn sda_output_signal(&self) -> OutputSignal

fn sda_input_signal(&self) -> InputSignal

fn register_block(&self) -> &RegisterBlock

fn i2c_number(&self) -> usize

fn setup( &mut self, frequency: Rate<u32, 1, 1>, clocks: &Clocks<'_>, timeout: Option<u32>, )

fn reset(&self)

Resets the I2C controller (FIFO + FSM + command list)

fn reset_command_list(&self)

Resets the I2C peripheral’s command registers

fn set_filter(&mut self, sda_threshold: Option<u8>, scl_threshold: Option<u8>)

Sets the filter with a supplied threshold in clock cycles for which a pulse must be present to pass the filter

fn set_frequency( &mut self, source_clk: Rate<u32, 1, 1>, bus_freq: Rate<u32, 1, 1>, timeout: Option<u32>, )

Sets the frequency of the I2C interface by calculating and applying the associated timings - corresponds to i2c_ll_cal_bus_clk and i2c_ll_set_bus_timing in ESP-IDF

fn configure_clock( &mut self, sclk_div: u32, scl_low_period: u32, scl_high_period: u32, scl_wait_high_period: u32, sda_hold_time: u32, sda_sample_time: u32, scl_rstart_setup_time: u32, scl_stop_setup_time: u32, scl_start_hold_time: u32, scl_stop_hold_time: u32, time_out_value: u32, time_out_en: bool, )

fn setup_write<'a, I>( &self, addr: u8, bytes: &[u8], cmd_iterator: &mut I, ) -> Result<(), Error>

where I: Iterator<Item = &'a Reg<COMD_SPEC>>,

fn perform_write<'a, I>( &self, addr: u8, bytes: &[u8], cmd_iterator: &mut I, ) -> Result<(), Error>

where I: Iterator<Item = &'a Reg<COMD_SPEC>>,

fn setup_read<'a, I>( &self, addr: u8, buffer: &mut [u8], cmd_iterator: &mut I, ) -> Result<(), Error>

where I: Iterator<Item = &'a Reg<COMD_SPEC>>,

fn perform_read<'a, I>( &self, addr: u8, buffer: &mut [u8], cmd_iterator: &mut I, ) -> Result<(), Error>

where I: Iterator<Item = &'a Reg<COMD_SPEC>>,

fn read_all_from_fifo(&self, buffer: &mut [u8]) -> Result<(), Error>

fn clear_all_interrupts(&self)

fn wait_for_completion(&self) -> Result<(), Error>

fn check_errors(&self) -> Result<(), Error>

fn update_config(&self)

fn start_transmission(&self)

fn fill_tx_fifo(&self, bytes: &[u8]) -> usize

fn write_remaining_tx_fifo( &self, start_index: usize, bytes: &[u8], ) -> Result<(), Error>

fn reset_fifo(&self)

Resets the transmit and receive FIFO buffers

fn master_write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error>

Send data bytes from the bytes array to a target slave with the address addr

fn master_read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Error>

Read bytes from a target slave with the address addr The number of read bytes is deterimed by the size of the buffer argument

fn master_write_read( &mut self, addr: u8, bytes: &[u8], buffer: &mut [u8], ) -> Result<(), Error>

Write bytes from the bytes array first and then read n bytes into the buffer array with n being the size of the array.

impl Peripheral for I2C0

type P = I2C0

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <I2C0 as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.