#[doc = "Register `PLLCFGR` reader"]
pub struct R(crate::R<PLLCFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PLLCFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PLLCFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PLLCFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PLLCFGR` writer"]
pub struct W(crate::W<PLLCFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PLLCFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PLLCFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PLLCFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PLLR` reader - Main PLL division factor for PLLCLK (system clock)"]
pub struct PLLR_R(crate::FieldReader<u8, u8>);
impl PLLR_R {
pub(crate) fn new(bits: u8) -> Self {
PLLR_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PLLR_R {
type Target = crate::FieldReader<u8, u8>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PLLR` writer - Main PLL division factor for PLLCLK (system clock)"]
pub struct PLLR_W<'a> {
w: &'a mut W,
}
impl<'a> PLLR_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 25)) | ((value as u32 & 0x03) << 25);
self.w
}
}
#[doc = "Field `PLLREN` reader - Main PLL PLLCLK output enable"]
pub struct PLLREN_R(crate::FieldReader<bool, bool>);
impl PLLREN_R {
pub(crate) fn new(bits: bool) -> Self {
PLLREN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PLLREN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PLLREN` writer - Main PLL PLLCLK output enable"]
pub struct PLLREN_W<'a> {
w: &'a mut W,
}
impl<'a> PLLREN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
self.w
}
}
#[doc = "Field `PLLQ` reader - Main PLL division factor for PLLUSB1CLK(48 MHz clock)"]
pub struct PLLQ_R(crate::FieldReader<u8, u8>);
impl PLLQ_R {
pub(crate) fn new(bits: u8) -> Self {
PLLQ_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PLLQ_R {
type Target = crate::FieldReader<u8, u8>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PLLQ` writer - Main PLL division factor for PLLUSB1CLK(48 MHz clock)"]
pub struct PLLQ_W<'a> {
w: &'a mut W,
}
impl<'a> PLLQ_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21);
self.w
}
}
#[doc = "Field `PLLQEN` reader - Main PLL PLLUSB1CLK output enable"]
pub struct PLLQEN_R(crate::FieldReader<bool, bool>);
impl PLLQEN_R {
pub(crate) fn new(bits: bool) -> Self {
PLLQEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PLLQEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PLLQEN` writer - Main PLL PLLUSB1CLK output enable"]
pub struct PLLQEN_W<'a> {
w: &'a mut W,
}
impl<'a> PLLQEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
self.w
}
}
#[doc = "Field `PLLP` reader - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)"]
pub struct PLLP_R(crate::FieldReader<bool, bool>);
impl PLLP_R {
pub(crate) fn new(bits: bool) -> Self {
PLLP_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PLLP_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PLLP` writer - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)"]
pub struct PLLP_W<'a> {
w: &'a mut W,
}
impl<'a> PLLP_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
self.w
}
}
#[doc = "Field `PLLPEN` reader - Main PLL PLLSAI3CLK output enable"]
pub struct PLLPEN_R(crate::FieldReader<bool, bool>);
impl PLLPEN_R {
pub(crate) fn new(bits: bool) -> Self {
PLLPEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PLLPEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PLLPEN` writer - Main PLL PLLSAI3CLK output enable"]
pub struct PLLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> PLLPEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
self.w
}
}
#[doc = "Field `PLLN` reader - Main PLL multiplication factor for VCO"]
pub struct PLLN_R(crate::FieldReader<u8, u8>);
impl PLLN_R {
pub(crate) fn new(bits: u8) -> Self {
PLLN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PLLN_R {
type Target = crate::FieldReader<u8, u8>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PLLN` writer - Main PLL multiplication factor for VCO"]
pub struct PLLN_W<'a> {
w: &'a mut W,
}
impl<'a> PLLN_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x7f << 8)) | ((value as u32 & 0x7f) << 8);
self.w
}
}
#[doc = "Field `PLLM` reader - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock"]
pub struct PLLM_R(crate::FieldReader<u8, u8>);
impl PLLM_R {
pub(crate) fn new(bits: u8) -> Self {
PLLM_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PLLM_R {
type Target = crate::FieldReader<u8, u8>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PLLM` writer - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock"]
pub struct PLLM_W<'a> {
w: &'a mut W,
}
impl<'a> PLLM_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4);
self.w
}
}
#[doc = "Field `PLLSRC` reader - Main PLL, PLLSAI1 and PLLSAI2 entry clock source"]
pub struct PLLSRC_R(crate::FieldReader<u8, u8>);
impl PLLSRC_R {
pub(crate) fn new(bits: u8) -> Self {
PLLSRC_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PLLSRC_R {
type Target = crate::FieldReader<u8, u8>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PLLSRC` writer - Main PLL, PLLSAI1 and PLLSAI2 entry clock source"]
pub struct PLLSRC_W<'a> {
w: &'a mut W,
}
impl<'a> PLLSRC_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
self.w
}
}
impl R {
#[doc = "Bits 25:26 - Main PLL division factor for PLLCLK (system clock)"]
#[inline(always)]
pub fn pllr(&self) -> PLLR_R {
PLLR_R::new(((self.bits >> 25) & 0x03) as u8)
}
#[doc = "Bit 24 - Main PLL PLLCLK output enable"]
#[inline(always)]
pub fn pllren(&self) -> PLLREN_R {
PLLREN_R::new(((self.bits >> 24) & 0x01) != 0)
}
#[doc = "Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)"]
#[inline(always)]
pub fn pllq(&self) -> PLLQ_R {
PLLQ_R::new(((self.bits >> 21) & 0x03) as u8)
}
#[doc = "Bit 20 - Main PLL PLLUSB1CLK output enable"]
#[inline(always)]
pub fn pllqen(&self) -> PLLQEN_R {
PLLQEN_R::new(((self.bits >> 20) & 0x01) != 0)
}
#[doc = "Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)"]
#[inline(always)]
pub fn pllp(&self) -> PLLP_R {
PLLP_R::new(((self.bits >> 17) & 0x01) != 0)
}
#[doc = "Bit 16 - Main PLL PLLSAI3CLK output enable"]
#[inline(always)]
pub fn pllpen(&self) -> PLLPEN_R {
PLLPEN_R::new(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bits 8:14 - Main PLL multiplication factor for VCO"]
#[inline(always)]
pub fn plln(&self) -> PLLN_R {
PLLN_R::new(((self.bits >> 8) & 0x7f) as u8)
}
#[doc = "Bits 4:6 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock"]
#[inline(always)]
pub fn pllm(&self) -> PLLM_R {
PLLM_R::new(((self.bits >> 4) & 0x07) as u8)
}
#[doc = "Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source"]
#[inline(always)]
pub fn pllsrc(&self) -> PLLSRC_R {
PLLSRC_R::new((self.bits & 0x03) as u8)
}
}
impl W {
#[doc = "Bits 25:26 - Main PLL division factor for PLLCLK (system clock)"]
#[inline(always)]
pub fn pllr(&mut self) -> PLLR_W {
PLLR_W { w: self }
}
#[doc = "Bit 24 - Main PLL PLLCLK output enable"]
#[inline(always)]
pub fn pllren(&mut self) -> PLLREN_W {
PLLREN_W { w: self }
}
#[doc = "Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)"]
#[inline(always)]
pub fn pllq(&mut self) -> PLLQ_W {
PLLQ_W { w: self }
}
#[doc = "Bit 20 - Main PLL PLLUSB1CLK output enable"]
#[inline(always)]
pub fn pllqen(&mut self) -> PLLQEN_W {
PLLQEN_W { w: self }
}
#[doc = "Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)"]
#[inline(always)]
pub fn pllp(&mut self) -> PLLP_W {
PLLP_W { w: self }
}
#[doc = "Bit 16 - Main PLL PLLSAI3CLK output enable"]
#[inline(always)]
pub fn pllpen(&mut self) -> PLLPEN_W {
PLLPEN_W { w: self }
}
#[doc = "Bits 8:14 - Main PLL multiplication factor for VCO"]
#[inline(always)]
pub fn plln(&mut self) -> PLLN_W {
PLLN_W { w: self }
}
#[doc = "Bits 4:6 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock"]
#[inline(always)]
pub fn pllm(&mut self) -> PLLM_W {
PLLM_W { w: self }
}
#[doc = "Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source"]
#[inline(always)]
pub fn pllsrc(&mut self) -> PLLSRC_W {
PLLSRC_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PLL configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pllcfgr](index.html) module"]
pub struct PLLCFGR_SPEC;
impl crate::RegisterSpec for PLLCFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [pllcfgr::R](R) reader structure"]
impl crate::Readable for PLLCFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pllcfgr::W](W) writer structure"]
impl crate::Writable for PLLCFGR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets PLLCFGR to value 0x1000"]
impl crate::Resettable for PLLCFGR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0x1000
}
}