#[doc = "Register `AHB2ENR` reader"]
pub struct R(crate::R<AHB2ENR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<AHB2ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<AHB2ENR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<AHB2ENR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `AHB2ENR` writer"]
pub struct W(crate::W<AHB2ENR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<AHB2ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<AHB2ENR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<AHB2ENR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RNGEN` reader - Random Number Generator clock enable"]
pub struct RNGEN_R(crate::FieldReader<bool, bool>);
impl RNGEN_R {
pub(crate) fn new(bits: bool) -> Self {
RNGEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for RNGEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `RNGEN` writer - Random Number Generator clock enable"]
pub struct RNGEN_W<'a> {
w: &'a mut W,
}
impl<'a> RNGEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
self.w
}
}
#[doc = "Field `AESEN` reader - AES accelerator clock enable"]
pub struct AESEN_R(crate::FieldReader<bool, bool>);
impl AESEN_R {
pub(crate) fn new(bits: bool) -> Self {
AESEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for AESEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `AESEN` writer - AES accelerator clock enable"]
pub struct AESEN_W<'a> {
w: &'a mut W,
}
impl<'a> AESEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
self.w
}
}
#[doc = "Field `ADCEN` reader - ADC clock enable"]
pub struct ADCEN_R(crate::FieldReader<bool, bool>);
impl ADCEN_R {
pub(crate) fn new(bits: bool) -> Self {
ADCEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for ADCEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `ADCEN` writer - ADC clock enable"]
pub struct ADCEN_W<'a> {
w: &'a mut W,
}
impl<'a> ADCEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
self.w
}
}
#[doc = "Field `OTGFSEN` reader - OTG full speed clock enable"]
pub struct OTGFSEN_R(crate::FieldReader<bool, bool>);
impl OTGFSEN_R {
pub(crate) fn new(bits: bool) -> Self {
OTGFSEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for OTGFSEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `OTGFSEN` writer - OTG full speed clock enable"]
pub struct OTGFSEN_W<'a> {
w: &'a mut W,
}
impl<'a> OTGFSEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
self.w
}
}
#[doc = "Field `GPIOHEN` reader - IO port H clock enable"]
pub struct GPIOHEN_R(crate::FieldReader<bool, bool>);
impl GPIOHEN_R {
pub(crate) fn new(bits: bool) -> Self {
GPIOHEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for GPIOHEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `GPIOHEN` writer - IO port H clock enable"]
pub struct GPIOHEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOHEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
self.w
}
}
#[doc = "Field `GPIOGEN` reader - IO port G clock enable"]
pub struct GPIOGEN_R(crate::FieldReader<bool, bool>);
impl GPIOGEN_R {
pub(crate) fn new(bits: bool) -> Self {
GPIOGEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for GPIOGEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `GPIOGEN` writer - IO port G clock enable"]
pub struct GPIOGEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOGEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
self.w
}
}
#[doc = "Field `GPIOFEN` reader - IO port F clock enable"]
pub struct GPIOFEN_R(crate::FieldReader<bool, bool>);
impl GPIOFEN_R {
pub(crate) fn new(bits: bool) -> Self {
GPIOFEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for GPIOFEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `GPIOFEN` writer - IO port F clock enable"]
pub struct GPIOFEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOFEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
self.w
}
}
#[doc = "Field `GPIOEEN` reader - IO port E clock enable"]
pub struct GPIOEEN_R(crate::FieldReader<bool, bool>);
impl GPIOEEN_R {
pub(crate) fn new(bits: bool) -> Self {
GPIOEEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for GPIOEEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `GPIOEEN` writer - IO port E clock enable"]
pub struct GPIOEEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOEEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
self.w
}
}
#[doc = "Field `GPIODEN` reader - IO port D clock enable"]
pub struct GPIODEN_R(crate::FieldReader<bool, bool>);
impl GPIODEN_R {
pub(crate) fn new(bits: bool) -> Self {
GPIODEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for GPIODEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `GPIODEN` writer - IO port D clock enable"]
pub struct GPIODEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIODEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
self.w
}
}
#[doc = "Field `GPIOCEN` reader - IO port C clock enable"]
pub struct GPIOCEN_R(crate::FieldReader<bool, bool>);
impl GPIOCEN_R {
pub(crate) fn new(bits: bool) -> Self {
GPIOCEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for GPIOCEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `GPIOCEN` writer - IO port C clock enable"]
pub struct GPIOCEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOCEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
self.w
}
}
#[doc = "Field `GPIOBEN` reader - IO port B clock enable"]
pub struct GPIOBEN_R(crate::FieldReader<bool, bool>);
impl GPIOBEN_R {
pub(crate) fn new(bits: bool) -> Self {
GPIOBEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for GPIOBEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `GPIOBEN` writer - IO port B clock enable"]
pub struct GPIOBEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOBEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
self.w
}
}
#[doc = "Field `GPIOAEN` reader - IO port A clock enable"]
pub struct GPIOAEN_R(crate::FieldReader<bool, bool>);
impl GPIOAEN_R {
pub(crate) fn new(bits: bool) -> Self {
GPIOAEN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for GPIOAEN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `GPIOAEN` writer - IO port A clock enable"]
pub struct GPIOAEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOAEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
impl R {
#[doc = "Bit 18 - Random Number Generator clock enable"]
#[inline(always)]
pub fn rngen(&self) -> RNGEN_R {
RNGEN_R::new(((self.bits >> 18) & 0x01) != 0)
}
#[doc = "Bit 16 - AES accelerator clock enable"]
#[inline(always)]
pub fn aesen(&self) -> AESEN_R {
AESEN_R::new(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bit 13 - ADC clock enable"]
#[inline(always)]
pub fn adcen(&self) -> ADCEN_R {
ADCEN_R::new(((self.bits >> 13) & 0x01) != 0)
}
#[doc = "Bit 12 - OTG full speed clock enable"]
#[inline(always)]
pub fn otgfsen(&self) -> OTGFSEN_R {
OTGFSEN_R::new(((self.bits >> 12) & 0x01) != 0)
}
#[doc = "Bit 7 - IO port H clock enable"]
#[inline(always)]
pub fn gpiohen(&self) -> GPIOHEN_R {
GPIOHEN_R::new(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bit 6 - IO port G clock enable"]
#[inline(always)]
pub fn gpiogen(&self) -> GPIOGEN_R {
GPIOGEN_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 5 - IO port F clock enable"]
#[inline(always)]
pub fn gpiofen(&self) -> GPIOFEN_R {
GPIOFEN_R::new(((self.bits >> 5) & 0x01) != 0)
}
#[doc = "Bit 4 - IO port E clock enable"]
#[inline(always)]
pub fn gpioeen(&self) -> GPIOEEN_R {
GPIOEEN_R::new(((self.bits >> 4) & 0x01) != 0)
}
#[doc = "Bit 3 - IO port D clock enable"]
#[inline(always)]
pub fn gpioden(&self) -> GPIODEN_R {
GPIODEN_R::new(((self.bits >> 3) & 0x01) != 0)
}
#[doc = "Bit 2 - IO port C clock enable"]
#[inline(always)]
pub fn gpiocen(&self) -> GPIOCEN_R {
GPIOCEN_R::new(((self.bits >> 2) & 0x01) != 0)
}
#[doc = "Bit 1 - IO port B clock enable"]
#[inline(always)]
pub fn gpioben(&self) -> GPIOBEN_R {
GPIOBEN_R::new(((self.bits >> 1) & 0x01) != 0)
}
#[doc = "Bit 0 - IO port A clock enable"]
#[inline(always)]
pub fn gpioaen(&self) -> GPIOAEN_R {
GPIOAEN_R::new((self.bits & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 18 - Random Number Generator clock enable"]
#[inline(always)]
pub fn rngen(&mut self) -> RNGEN_W {
RNGEN_W { w: self }
}
#[doc = "Bit 16 - AES accelerator clock enable"]
#[inline(always)]
pub fn aesen(&mut self) -> AESEN_W {
AESEN_W { w: self }
}
#[doc = "Bit 13 - ADC clock enable"]
#[inline(always)]
pub fn adcen(&mut self) -> ADCEN_W {
ADCEN_W { w: self }
}
#[doc = "Bit 12 - OTG full speed clock enable"]
#[inline(always)]
pub fn otgfsen(&mut self) -> OTGFSEN_W {
OTGFSEN_W { w: self }
}
#[doc = "Bit 7 - IO port H clock enable"]
#[inline(always)]
pub fn gpiohen(&mut self) -> GPIOHEN_W {
GPIOHEN_W { w: self }
}
#[doc = "Bit 6 - IO port G clock enable"]
#[inline(always)]
pub fn gpiogen(&mut self) -> GPIOGEN_W {
GPIOGEN_W { w: self }
}
#[doc = "Bit 5 - IO port F clock enable"]
#[inline(always)]
pub fn gpiofen(&mut self) -> GPIOFEN_W {
GPIOFEN_W { w: self }
}
#[doc = "Bit 4 - IO port E clock enable"]
#[inline(always)]
pub fn gpioeen(&mut self) -> GPIOEEN_W {
GPIOEEN_W { w: self }
}
#[doc = "Bit 3 - IO port D clock enable"]
#[inline(always)]
pub fn gpioden(&mut self) -> GPIODEN_W {
GPIODEN_W { w: self }
}
#[doc = "Bit 2 - IO port C clock enable"]
#[inline(always)]
pub fn gpiocen(&mut self) -> GPIOCEN_W {
GPIOCEN_W { w: self }
}
#[doc = "Bit 1 - IO port B clock enable"]
#[inline(always)]
pub fn gpioben(&mut self) -> GPIOBEN_W {
GPIOBEN_W { w: self }
}
#[doc = "Bit 0 - IO port A clock enable"]
#[inline(always)]
pub fn gpioaen(&mut self) -> GPIOAEN_W {
GPIOAEN_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "AHB2 peripheral clock enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahb2enr](index.html) module"]
pub struct AHB2ENR_SPEC;
impl crate::RegisterSpec for AHB2ENR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ahb2enr::R](R) reader structure"]
impl crate::Readable for AHB2ENR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ahb2enr::W](W) writer structure"]
impl crate::Writable for AHB2ENR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets AHB2ENR to value 0"]
impl crate::Resettable for AHB2ENR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}