hc32f448_driver_sys 0.1.1

/* automatically generated by rust-bindgen 0.72.1 */

pub const __MPU_PRESENT: u32 = 1;
pub const __VTOR_PRESENT: u32 = 1;
pub const __NVIC_PRIO_BITS: u32 = 4;
pub const __Vendor_SysTickConfig: u32 = 0;
pub const __FPU_PRESENT: u32 = 1;
pub const EFM_BASE: u32 = 0;
pub const SRAM_BASE: u32 = 536838144;
pub const SMC_BASE: u32 = 1610612736;
pub const QSPI_BASE: u32 = 2550136832;
pub const CM_ADC1_BASE: u32 = 1074003968;
pub const CM_ADC2_BASE: u32 = 1074004992;
pub const CM_ADC3_BASE: u32 = 1074006016;
pub const CM_AES_BASE: u32 = 1073774592;
pub const CM_AOS_BASE: u32 = 1073809408;
pub const CM_CMP1_BASE: u32 = 1073973248;
pub const CM_CMP2_BASE: u32 = 1073973504;
pub const CM_CMP3_BASE: u32 = 1073974272;
pub const CM_CMP4_BASE: u32 = 1073974528;
pub const CM_CMU_BASE: u32 = 1074036736;
pub const CM_CRC_BASE: u32 = 1073777664;
pub const CM_CTC_BASE: u32 = 1074043904;
pub const CM_DAC_BASE: u32 = 1074008064;
pub const CM_DBGC_BASE: u32 = 3758366720;
pub const CM_DCU1_BASE: u32 = 1074094080;
pub const CM_DCU2_BASE: u32 = 1074095104;
pub const CM_DCU3_BASE: u32 = 1074096128;
pub const CM_DCU4_BASE: u32 = 1074097152;
pub const CM_DMA1_BASE: u32 = 1074081792;
pub const CM_DMA2_BASE: u32 = 1074082816;
pub const CM_EFM_BASE: u32 = 1073808384;
pub const CM_EMB0_BASE: u32 = 1073839104;
pub const CM_EMB1_BASE: u32 = 1073839136;
pub const CM_EMB2_BASE: u32 = 1073839168;
pub const CM_EMB3_BASE: u32 = 1073839200;
pub const CM_FCM_BASE: u32 = 1074037760;
pub const CM_GPIO_BASE: u32 = 1074083840;
pub const CM_HASH_BASE: u32 = 1073775616;
pub const CM_I2C1_BASE: u32 = 1073984512;
pub const CM_I2C2_BASE: u32 = 1073985536;
pub const CM_ICG_BASE: u32 = 1024;
pub const CM_INTC_BASE: u32 = 1074073600;
pub const CM_KEYSCAN_BASE: u32 = 1074072576;
pub const CM_MCAN1_BASE: u32 = 1073909760;
pub const CM_MCAN2_BASE: u32 = 1073910784;
pub const CM_MPU_BASE: u32 = 1074069504;
pub const CM_PERIC_BASE: u32 = 1074091008;
pub const CM_PWC_BASE: u32 = 1074036736;
pub const CM_QSPI_BASE: u32 = 2617245696;
pub const CM_RMU_BASE: u32 = 1074056416;
pub const CM_RTC_BASE: u32 = 1074053120;
pub const CM_SMC_BASE: u32 = 2281701376;
pub const CM_SPI1_BASE: u32 = 1073856512;
pub const CM_SPI2_BASE: u32 = 1073857536;
pub const CM_SPI3_BASE: u32 = 1073872896;
pub const CM_SRAMC_BASE: u32 = 1074071552;
pub const CM_SWDT_BASE: u32 = 1074041856;
pub const CM_TMR0_1_BASE: u32 = 1073889280;
pub const CM_TMR0_2_BASE: u32 = 1073890304;
pub const CM_TMR4_1_BASE: u32 = 1073971200;
pub const CM_TMR4_2_BASE: u32 = 1073972224;
pub const CM_TMR4_3_BASE: u32 = 1073974784;
pub const CM_TMR6_1_BASE: u32 = 1073987584;
pub const CM_TMR6_2_BASE: u32 = 1073988608;
pub const CM_TMR6_COMMON_BASE: u32 = 1073988352;
pub const CM_TMRA_1_BASE: u32 = 1073979392;
pub const CM_TMRA_2_BASE: u32 = 1073980416;
pub const CM_TMRA_3_BASE: u32 = 1073981440;
pub const CM_TMRA_4_BASE: u32 = 1073982464;
pub const CM_TMRA_5_BASE: u32 = 1073897472;
pub const CM_TRNG_BASE: u32 = 1074012160;
pub const CM_USART1_BASE: u32 = 1073859584;
pub const CM_USART2_BASE: u32 = 1073860608;
pub const CM_USART3_BASE: u32 = 1073861632;
pub const CM_USART4_BASE: u32 = 1073875968;
pub const CM_USART5_BASE: u32 = 1073876992;
pub const CM_USART6_BASE: u32 = 1073878016;
pub const CM_WDT_BASE: u32 = 1074040832;
pub const ADC_STR_STRT: u32 = 1;
pub const ADC_CR0_MS_POS: u32 = 0;
pub const ADC_CR0_MS: u32 = 7;
pub const ADC_CR0_ACCSEL_POS: u32 = 4;
pub const ADC_CR0_ACCSEL: u32 = 48;
pub const ADC_CR0_ACCSEL_0: u32 = 16;
pub const ADC_CR0_ACCSEL_1: u32 = 32;
pub const ADC_CR0_CLREN_POS: u32 = 6;
pub const ADC_CR0_CLREN: u32 = 64;
pub const ADC_CR0_DFMT_POS: u32 = 7;
pub const ADC_CR0_DFMT: u32 = 128;
pub const ADC_CR0_AVCNT_POS: u32 = 8;
pub const ADC_CR0_AVCNT: u32 = 1792;
pub const ADC_CR1_RSCHSEL_POS: u32 = 2;
pub const ADC_CR1_RSCHSEL: u32 = 4;
pub const ADC_CR2_OVSS_POS: u32 = 8;
pub const ADC_CR2_OVSS: u32 = 3840;
pub const ADC_CR2_OVSMOD_POS: u32 = 12;
pub const ADC_CR2_OVSMOD: u32 = 4096;
pub const ADC_TRGSR_TRGSELA_POS: u32 = 0;
pub const ADC_TRGSR_TRGSELA: u32 = 3;
pub const ADC_TRGSR_TRGSELA_0: u32 = 1;
pub const ADC_TRGSR_TRGSELA_1: u32 = 2;
pub const ADC_TRGSR_TRGENA_POS: u32 = 7;
pub const ADC_TRGSR_TRGENA: u32 = 128;
pub const ADC_TRGSR_TRGSELB_POS: u32 = 8;
pub const ADC_TRGSR_TRGSELB: u32 = 768;
pub const ADC_TRGSR_TRGSELB_0: u32 = 256;
pub const ADC_TRGSR_TRGSELB_1: u32 = 512;
pub const ADC_TRGSR_TRGENB_POS: u32 = 15;
pub const ADC_TRGSR_TRGENB: u32 = 32768;
pub const ADC_CHSELRA_CHSELA: u32 = 65535;
pub const ADC_CHSELRB_CHSELB: u32 = 65535;
pub const ADC_AVCHSELR_AVCHSEL: u32 = 65535;
pub const ADC_EXCHSELR_EXCHSEL: u32 = 1;
pub const ADC_SSTR0: u32 = 255;
pub const ADC_SSTR1: u32 = 255;
pub const ADC_SSTR2: u32 = 255;
pub const ADC_SSTR3: u32 = 255;
pub const ADC_SSTR4: u32 = 255;
pub const ADC_SSTR5: u32 = 255;
pub const ADC_SSTR6: u32 = 255;
pub const ADC_SSTR7: u32 = 255;
pub const ADC_SSTR8: u32 = 255;
pub const ADC_SSTR9: u32 = 255;
pub const ADC_SSTR10: u32 = 255;
pub const ADC_SSTR11: u32 = 255;
pub const ADC_SSTR12: u32 = 255;
pub const ADC_SSTR13: u32 = 255;
pub const ADC_SSTR14: u32 = 255;
pub const ADC_SSTR15: u32 = 255;
pub const ADC_CHMUXR0_CH00MUX_POS: u32 = 0;
pub const ADC_CHMUXR0_CH00MUX: u32 = 15;
pub const ADC_CHMUXR0_CH01MUX_POS: u32 = 4;
pub const ADC_CHMUXR0_CH01MUX: u32 = 240;
pub const ADC_CHMUXR0_CH02MUX_POS: u32 = 8;
pub const ADC_CHMUXR0_CH02MUX: u32 = 3840;
pub const ADC_CHMUXR0_CH03MUX_POS: u32 = 12;
pub const ADC_CHMUXR0_CH03MUX: u32 = 61440;
pub const ADC_CHMUXR1_CH04MUX_POS: u32 = 0;
pub const ADC_CHMUXR1_CH04MUX: u32 = 15;
pub const ADC_CHMUXR1_CH05MUX_POS: u32 = 4;
pub const ADC_CHMUXR1_CH05MUX: u32 = 240;
pub const ADC_CHMUXR1_CH06MUX_POS: u32 = 8;
pub const ADC_CHMUXR1_CH06MUX: u32 = 3840;
pub const ADC_CHMUXR1_CH07MUX_POS: u32 = 12;
pub const ADC_CHMUXR1_CH07MUX: u32 = 61440;
pub const ADC_CHMUXR2_CH08MUX_POS: u32 = 0;
pub const ADC_CHMUXR2_CH08MUX: u32 = 15;
pub const ADC_CHMUXR2_CH09MUX_POS: u32 = 4;
pub const ADC_CHMUXR2_CH09MUX: u32 = 240;
pub const ADC_CHMUXR2_CH10MUX_POS: u32 = 8;
pub const ADC_CHMUXR2_CH10MUX: u32 = 3840;
pub const ADC_CHMUXR2_CH11MUX_POS: u32 = 12;
pub const ADC_CHMUXR2_CH11MUX: u32 = 61440;
pub const ADC_CHMUXR3_CH12MUX_POS: u32 = 0;
pub const ADC_CHMUXR3_CH12MUX: u32 = 15;
pub const ADC_CHMUXR3_CH13MUX_POS: u32 = 4;
pub const ADC_CHMUXR3_CH13MUX: u32 = 240;
pub const ADC_CHMUXR3_CH14MUX_POS: u32 = 8;
pub const ADC_CHMUXR3_CH14MUX: u32 = 3840;
pub const ADC_CHMUXR3_CH15MUX_POS: u32 = 12;
pub const ADC_CHMUXR3_CH15MUX: u32 = 61440;
pub const ADC_ISR_EOCAF_POS: u32 = 0;
pub const ADC_ISR_EOCAF: u32 = 1;
pub const ADC_ISR_EOCBF_POS: u32 = 1;
pub const ADC_ISR_EOCBF: u32 = 2;
pub const ADC_ISR_SASTPDF_POS: u32 = 4;
pub const ADC_ISR_SASTPDF: u32 = 16;
pub const ADC_ICR_EOCAIEN_POS: u32 = 0;
pub const ADC_ICR_EOCAIEN: u32 = 1;
pub const ADC_ICR_EOCBIEN_POS: u32 = 1;
pub const ADC_ICR_EOCBIEN: u32 = 2;
pub const ADC_ISCLRR_CLREOCAF_POS: u32 = 0;
pub const ADC_ISCLRR_CLREOCAF: u32 = 1;
pub const ADC_ISCLRR_CLREOCBF_POS: u32 = 1;
pub const ADC_ISCLRR_CLREOCBF: u32 = 2;
pub const ADC_ISCLRR_CLRSASTPDF_POS: u32 = 4;
pub const ADC_ISCLRR_CLRSASTPDF: u32 = 16;
pub const ADC_SYNCCR_SYNCEN_POS: u32 = 0;
pub const ADC_SYNCCR_SYNCEN: u32 = 1;
pub const ADC_SYNCCR_SYNCMD_POS: u32 = 4;
pub const ADC_SYNCCR_SYNCMD: u32 = 112;
pub const ADC_SYNCCR_SYNCDLY_POS: u32 = 8;
pub const ADC_SYNCCR_SYNCDLY: u32 = 65280;
pub const ADC_DR0: u32 = 65535;
pub const ADC_DR1: u32 = 65535;
pub const ADC_DR2: u32 = 65535;
pub const ADC_DR3: u32 = 65535;
pub const ADC_DR4: u32 = 65535;
pub const ADC_DR5: u32 = 65535;
pub const ADC_DR6: u32 = 65535;
pub const ADC_DR7: u32 = 65535;
pub const ADC_DR8: u32 = 65535;
pub const ADC_DR9: u32 = 65535;
pub const ADC_DR10: u32 = 65535;
pub const ADC_DR11: u32 = 65535;
pub const ADC_DR12: u32 = 65535;
pub const ADC_DR13: u32 = 65535;
pub const ADC_DR14: u32 = 65535;
pub const ADC_DR15: u32 = 65535;
pub const ADC_AWDCR_AWD0EN_POS: u32 = 0;
pub const ADC_AWDCR_AWD0EN: u32 = 1;
pub const ADC_AWDCR_AWD0IEN_POS: u32 = 1;
pub const ADC_AWDCR_AWD0IEN: u32 = 2;
pub const ADC_AWDCR_AWD0MD_POS: u32 = 2;
pub const ADC_AWDCR_AWD0MD: u32 = 4;
pub const ADC_AWDCR_AWD1EN_POS: u32 = 4;
pub const ADC_AWDCR_AWD1EN: u32 = 16;
pub const ADC_AWDCR_AWD1IEN_POS: u32 = 5;
pub const ADC_AWDCR_AWD1IEN: u32 = 32;
pub const ADC_AWDCR_AWD1MD_POS: u32 = 6;
pub const ADC_AWDCR_AWD1MD: u32 = 64;
pub const ADC_AWDCR_AWDCM_POS: u32 = 8;
pub const ADC_AWDCR_AWDCM: u32 = 768;
pub const ADC_AWDCR_AWDCM_0: u32 = 256;
pub const ADC_AWDCR_AWDCM_1: u32 = 512;
pub const ADC_AWDSR_AWD0F_POS: u32 = 0;
pub const ADC_AWDSR_AWD0F: u32 = 1;
pub const ADC_AWDSR_AWD1F_POS: u32 = 1;
pub const ADC_AWDSR_AWD1F: u32 = 2;
pub const ADC_AWDSR_AWDCMF_POS: u32 = 4;
pub const ADC_AWDSR_AWDCMF: u32 = 16;
pub const ADC_AWDSCLRR_CLRAWD0F_POS: u32 = 0;
pub const ADC_AWDSCLRR_CLRAWD0F: u32 = 1;
pub const ADC_AWDSCLRR_CLRAWD1F_POS: u32 = 1;
pub const ADC_AWDSCLRR_CLRAWD1F: u32 = 2;
pub const ADC_AWDSCLRR_CLRAWDCMF_POS: u32 = 4;
pub const ADC_AWDSCLRR_CLRAWDCMF: u32 = 16;
pub const ADC_AWD0DR0: u32 = 65535;
pub const ADC_AWD0DR1: u32 = 65535;
pub const ADC_AWD0CHSR_AWDCH: u32 = 31;
pub const ADC_AWD1DR0: u32 = 65535;
pub const ADC_AWD1DR1: u32 = 65535;
pub const ADC_AWD1CHSR_AWDCH: u32 = 31;
pub const AES_CR_START_POS: u32 = 0;
pub const AES_CR_START: u32 = 1;
pub const AES_CR_MODE_POS: u32 = 1;
pub const AES_CR_MODE: u32 = 2;
pub const AES_CR_KEYSIZE_POS: u32 = 3;
pub const AES_CR_KEYSIZE: u32 = 24;
pub const AES_DR0: u32 = 4294967295;
pub const AES_DR1: u32 = 4294967295;
pub const AES_DR2: u32 = 4294967295;
pub const AES_DR3: u32 = 4294967295;
pub const AES_KR0: u32 = 4294967295;
pub const AES_KR1: u32 = 4294967295;
pub const AES_KR2: u32 = 4294967295;
pub const AES_KR3: u32 = 4294967295;
pub const AES_KR4: u32 = 4294967295;
pub const AES_KR5: u32 = 4294967295;
pub const AES_KR6: u32 = 4294967295;
pub const AES_KR7: u32 = 4294967295;
pub const AOS_INTSFTTRG_STRG: u32 = 1;
pub const AOS_DCU_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_DCU_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_DCU_TRGSEL_PLCHSEL_POS: u32 = 16;
pub const AOS_DCU_TRGSEL_PLCHSEL: u32 = 458752;
pub const AOS_DCU_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_DCU_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_DCU_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_DCU_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_DMA1_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_DMA1_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_DMA1_TRGSEL_PLCHSEL_POS: u32 = 16;
pub const AOS_DMA1_TRGSEL_PLCHSEL: u32 = 458752;
pub const AOS_DMA1_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_DMA1_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_DMA1_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_DMA1_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_DMA2_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_DMA2_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_DMA2_TRGSEL_PLCHSEL_POS: u32 = 16;
pub const AOS_DMA2_TRGSEL_PLCHSEL: u32 = 458752;
pub const AOS_DMA2_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_DMA2_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_DMA2_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_DMA2_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_DMA_RC_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_DMA_RC_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_DMA_RC_TRGSEL_PLCHSEL_POS: u32 = 16;
pub const AOS_DMA_RC_TRGSEL_PLCHSEL: u32 = 458752;
pub const AOS_DMA_RC_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_DMA_RC_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_DMA_RC_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_DMA_RC_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_TMR6_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_TMR6_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_TMR6_TRGSEL_PLCHSEL_POS: u32 = 16;
pub const AOS_TMR6_TRGSEL_PLCHSEL: u32 = 458752;
pub const AOS_TMR6_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_TMR6_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_TMR6_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_TMR6_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_TMR4_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_TMR4_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_TMR4_TRGSEL_PLCHSEL_POS: u32 = 16;
pub const AOS_TMR4_TRGSEL_PLCHSEL: u32 = 458752;
pub const AOS_TMR4_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_TMR4_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_TMR4_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_TMR4_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_PEVNT_TRGSEL12_TRGSEL_POS: u32 = 0;
pub const AOS_PEVNT_TRGSEL12_TRGSEL: u32 = 511;
pub const AOS_PEVNT_TRGSEL12_PLCHSEL_POS: u32 = 16;
pub const AOS_PEVNT_TRGSEL12_PLCHSEL: u32 = 458752;
pub const AOS_PEVNT_TRGSEL12_COMEN_POS: u32 = 30;
pub const AOS_PEVNT_TRGSEL12_COMEN: u32 = 3221225472;
pub const AOS_PEVNT_TRGSEL12_COMEN_0: u32 = 1073741824;
pub const AOS_PEVNT_TRGSEL12_COMEN_1: u32 = 2147483648;
pub const AOS_PEVNT_TRGSEL34_TRGSEL_POS: u32 = 0;
pub const AOS_PEVNT_TRGSEL34_TRGSEL: u32 = 511;
pub const AOS_PEVNT_TRGSEL34_PLCHSEL_POS: u32 = 16;
pub const AOS_PEVNT_TRGSEL34_PLCHSEL: u32 = 458752;
pub const AOS_PEVNT_TRGSEL34_COMEN_POS: u32 = 30;
pub const AOS_PEVNT_TRGSEL34_COMEN: u32 = 3221225472;
pub const AOS_PEVNT_TRGSEL34_COMEN_0: u32 = 1073741824;
pub const AOS_PEVNT_TRGSEL34_COMEN_1: u32 = 2147483648;
pub const AOS_TMR0_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_TMR0_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_TMR0_TRGSEL_PLCHSEL_POS: u32 = 16;
pub const AOS_TMR0_TRGSEL_PLCHSEL: u32 = 458752;
pub const AOS_TMR0_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_TMR0_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_TMR0_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_TMR0_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_TMRA_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_TMRA_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_TMRA_TRGSEL_PLCHSEL_POS: u32 = 16;
pub const AOS_TMRA_TRGSEL_PLCHSEL: u32 = 458752;
pub const AOS_TMRA_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_TMRA_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_TMRA_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_TMRA_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_ADC1_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_ADC1_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_ADC1_TRGSEL_PLCHSEL_POS: u32 = 16;
pub const AOS_ADC1_TRGSEL_PLCHSEL: u32 = 458752;
pub const AOS_ADC1_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_ADC1_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_ADC1_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_ADC1_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_ADC2_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_ADC2_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_ADC2_TRGSEL_PLCHSEL_POS: u32 = 16;
pub const AOS_ADC2_TRGSEL_PLCHSEL: u32 = 458752;
pub const AOS_ADC2_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_ADC2_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_ADC2_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_ADC2_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_ADC3_TRGSEL_TRGSEL_POS: u32 = 0;
pub const AOS_ADC3_TRGSEL_TRGSEL: u32 = 511;
pub const AOS_ADC3_TRGSEL_PLCHSEL_POS: u32 = 16;
pub const AOS_ADC3_TRGSEL_PLCHSEL: u32 = 458752;
pub const AOS_ADC3_TRGSEL_COMEN_POS: u32 = 30;
pub const AOS_ADC3_TRGSEL_COMEN: u32 = 3221225472;
pub const AOS_ADC3_TRGSEL_COMEN_0: u32 = 1073741824;
pub const AOS_ADC3_TRGSEL_COMEN_1: u32 = 2147483648;
pub const AOS_COMTRGSEL_TRGSEL: u32 = 511;
pub const AOS_PEVNTDIRR_PDIR: u32 = 65535;
pub const AOS_PEVNTIDR_PIN: u32 = 65535;
pub const AOS_PEVNTODR_POUT: u32 = 65535;
pub const AOS_PEVNTORR_POR: u32 = 65535;
pub const AOS_PEVNTOSR_POS: u32 = 65535;
pub const AOS_PEVNTRISR_RIS: u32 = 65535;
pub const AOS_PEVNTFALR_FAL: u32 = 65535;
pub const AOS_PEVNTNFCR_NFEN1_POS: u32 = 0;
pub const AOS_PEVNTNFCR_NFEN1: u32 = 1;
pub const AOS_PEVNTNFCR_DIVS1_POS: u32 = 1;
pub const AOS_PEVNTNFCR_DIVS1: u32 = 6;
pub const AOS_PEVNTNFCR_NFEN2_POS: u32 = 8;
pub const AOS_PEVNTNFCR_NFEN2: u32 = 256;
pub const AOS_PEVNTNFCR_DIVS2_POS: u32 = 9;
pub const AOS_PEVNTNFCR_DIVS2: u32 = 1536;
pub const AOS_PEVNTNFCR_NFEN3_POS: u32 = 16;
pub const AOS_PEVNTNFCR_NFEN3: u32 = 65536;
pub const AOS_PEVNTNFCR_DIVS3_POS: u32 = 17;
pub const AOS_PEVNTNFCR_DIVS3: u32 = 393216;
pub const AOS_PEVNTNFCR_NFEN4_POS: u32 = 24;
pub const AOS_PEVNTNFCR_NFEN4: u32 = 16777216;
pub const AOS_PEVNTNFCR_DIVS4_POS: u32 = 25;
pub const AOS_PEVNTNFCR_DIVS4: u32 = 100663296;
pub const AOS_PLU_CR_PLMODE_POS: u32 = 0;
pub const AOS_PLU_CR_PLMODE: u32 = 3;
pub const AOS_PLU_CR_PLINASEL_POS: u32 = 8;
pub const AOS_PLU_CR_PLINASEL: u32 = 768;
pub const AOS_PLU_CR_PLINBSEL_POS: u32 = 10;
pub const AOS_PLU_CR_PLINBSEL: u32 = 3072;
pub const AOS_PLU_CR_PLINCSEL_POS: u32 = 12;
pub const AOS_PLU_CR_PLINCSEL: u32 = 12288;
pub const AOS_PLU_CR_PLINDSEL_POS: u32 = 14;
pub const AOS_PLU_CR_PLINDSEL: u32 = 49152;
pub const AOS_PLU_TRGSELA_PLTRGSEL: u32 = 511;
pub const AOS_PLU_TRGSELB_PLTRGSEL: u32 = 511;
pub const AOS_PLU_TRGSELC_PLTRGSEL: u32 = 511;
pub const AOS_PLU_TRGSELD_PLTRGSEL: u32 = 511;
pub const CMP_MDR_CENA_POS: u32 = 0;
pub const CMP_MDR_CENA: u32 = 1;
pub const CMP_MDR_CWDE_POS: u32 = 1;
pub const CMP_MDR_CWDE: u32 = 2;
pub const CMP_MDR_CSMD_POS: u32 = 2;
pub const CMP_MDR_CSMD: u32 = 12;
pub const CMP_MDR_CSMD_0: u32 = 4;
pub const CMP_MDR_CSMD_1: u32 = 8;
pub const CMP_MDR_CSST_POS: u32 = 4;
pub const CMP_MDR_CSST: u32 = 16;
pub const CMP_MDR_CMON_POS: u32 = 7;
pub const CMP_MDR_CMON: u32 = 128;
pub const CMP_FIR_FCKS_POS: u32 = 0;
pub const CMP_FIR_FCKS: u32 = 7;
pub const CMP_FIR_CIEN_POS: u32 = 3;
pub const CMP_FIR_CIEN: u32 = 8;
pub const CMP_FIR_EDGS_POS: u32 = 4;
pub const CMP_FIR_EDGS: u32 = 48;
pub const CMP_FIR_EDGS_0: u32 = 16;
pub const CMP_FIR_EDGS_1: u32 = 32;
pub const CMP_FIR_CFF_POS: u32 = 6;
pub const CMP_FIR_CFF: u32 = 64;
pub const CMP_FIR_CRF_POS: u32 = 7;
pub const CMP_FIR_CRF: u32 = 128;
pub const CMP_OCR_COEN_POS: u32 = 0;
pub const CMP_OCR_COEN: u32 = 1;
pub const CMP_OCR_COPS_POS: u32 = 1;
pub const CMP_OCR_COPS: u32 = 2;
pub const CMP_OCR_CPOE_POS: u32 = 2;
pub const CMP_OCR_CPOE: u32 = 4;
pub const CMP_OCR_BWEN_POS: u32 = 4;
pub const CMP_OCR_BWEN: u32 = 16;
pub const CMP_OCR_BWMD_POS: u32 = 5;
pub const CMP_OCR_BWMD: u32 = 32;
pub const CMP_OCR_BWOL_POS: u32 = 6;
pub const CMP_OCR_BWOL: u32 = 192;
pub const CMP_OCR_BWOL_0: u32 = 64;
pub const CMP_OCR_BWOL_1: u32 = 128;
pub const CMP_PMSR_RVSL_POS: u32 = 0;
pub const CMP_PMSR_RVSL: u32 = 15;
pub const CMP_PMSR_RVSL_0: u32 = 1;
pub const CMP_PMSR_RVSL_1: u32 = 2;
pub const CMP_PMSR_RVSL_2: u32 = 4;
pub const CMP_PMSR_RVSL_3: u32 = 8;
pub const CMP_PMSR_CVSL_POS: u32 = 16;
pub const CMP_PMSR_CVSL: u32 = 983040;
pub const CMP_PMSR_CVSL_0: u32 = 65536;
pub const CMP_PMSR_CVSL_1: u32 = 131072;
pub const CMP_PMSR_CVSL_2: u32 = 262144;
pub const CMP_PMSR_CVSL_3: u32 = 524288;
pub const CMP_BWSR1_CTWS0_POS: u32 = 0;
pub const CMP_BWSR1_CTWS0: u32 = 1;
pub const CMP_BWSR1_CTWS1_POS: u32 = 1;
pub const CMP_BWSR1_CTWS1: u32 = 2;
pub const CMP_BWSR1_CTWS2_POS: u32 = 2;
pub const CMP_BWSR1_CTWS2: u32 = 4;
pub const CMP_BWSR1_CTWS3_POS: u32 = 3;
pub const CMP_BWSR1_CTWS3: u32 = 8;
pub const CMP_BWSR1_CTWS4_POS: u32 = 4;
pub const CMP_BWSR1_CTWS4: u32 = 16;
pub const CMP_BWSR1_CTWS5_POS: u32 = 5;
pub const CMP_BWSR1_CTWS5: u32 = 32;
pub const CMP_BWSR1_CTWS6_POS: u32 = 6;
pub const CMP_BWSR1_CTWS6: u32 = 64;
pub const CMP_BWSR1_CTWS7_POS: u32 = 7;
pub const CMP_BWSR1_CTWS7: u32 = 128;
pub const CMP_BWSR1_CTWS8_POS: u32 = 8;
pub const CMP_BWSR1_CTWS8: u32 = 256;
pub const CMP_BWSR1_CTWS9_POS: u32 = 9;
pub const CMP_BWSR1_CTWS9: u32 = 512;
pub const CMP_BWSR1_CTWS10_POS: u32 = 10;
pub const CMP_BWSR1_CTWS10: u32 = 1024;
pub const CMP_BWSR1_CTWS11_POS: u32 = 11;
pub const CMP_BWSR1_CTWS11: u32 = 2048;
pub const CMP_BWSR1_CTWS12_POS: u32 = 12;
pub const CMP_BWSR1_CTWS12: u32 = 4096;
pub const CMP_BWSR1_CTWS13_POS: u32 = 13;
pub const CMP_BWSR1_CTWS13: u32 = 8192;
pub const CMP_BWSR1_CTWS14_POS: u32 = 14;
pub const CMP_BWSR1_CTWS14: u32 = 16384;
pub const CMP_BWSR1_CTWS15_POS: u32 = 15;
pub const CMP_BWSR1_CTWS15: u32 = 32768;
pub const CMP_BWSR1_CTWP0_POS: u32 = 16;
pub const CMP_BWSR1_CTWP0: u32 = 65536;
pub const CMP_BWSR1_CTWP1_POS: u32 = 17;
pub const CMP_BWSR1_CTWP1: u32 = 131072;
pub const CMP_BWSR1_CTWP2_POS: u32 = 18;
pub const CMP_BWSR1_CTWP2: u32 = 262144;
pub const CMP_BWSR1_CTWP3_POS: u32 = 19;
pub const CMP_BWSR1_CTWP3: u32 = 524288;
pub const CMP_BWSR1_CTWP4_POS: u32 = 20;
pub const CMP_BWSR1_CTWP4: u32 = 1048576;
pub const CMP_BWSR1_CTWP5_POS: u32 = 21;
pub const CMP_BWSR1_CTWP5: u32 = 2097152;
pub const CMP_BWSR1_CTWP6_POS: u32 = 22;
pub const CMP_BWSR1_CTWP6: u32 = 4194304;
pub const CMP_BWSR1_CTWP7_POS: u32 = 23;
pub const CMP_BWSR1_CTWP7: u32 = 8388608;
pub const CMP_BWSR1_CTWP8_POS: u32 = 24;
pub const CMP_BWSR1_CTWP8: u32 = 16777216;
pub const CMP_BWSR1_CTWP9_POS: u32 = 25;
pub const CMP_BWSR1_CTWP9: u32 = 33554432;
pub const CMP_BWSR1_CTWP10_POS: u32 = 26;
pub const CMP_BWSR1_CTWP10: u32 = 67108864;
pub const CMP_BWSR1_CTWP11_POS: u32 = 27;
pub const CMP_BWSR1_CTWP11: u32 = 134217728;
pub const CMP_BWSR1_CTWP12_POS: u32 = 28;
pub const CMP_BWSR1_CTWP12: u32 = 268435456;
pub const CMP_BWSR1_CTWP13_POS: u32 = 29;
pub const CMP_BWSR1_CTWP13: u32 = 536870912;
pub const CMP_BWSR1_CTWP14_POS: u32 = 30;
pub const CMP_BWSR1_CTWP14: u32 = 1073741824;
pub const CMP_BWSR1_CTWP15_POS: u32 = 31;
pub const CMP_BWSR1_CTWP15: u32 = 2147483648;
pub const CMP_BWSR2_MSKW_POS: u32 = 0;
pub const CMP_BWSR2_MSKW: u32 = 255;
pub const CMP_BWSR2_TWEG_POS: u32 = 8;
pub const CMP_BWSR2_TWEG: u32 = 768;
pub const CMP_BWSR2_TWEG_0: u32 = 256;
pub const CMP_BWSR2_TWEG_1: u32 = 512;
pub const CMP_SCCR_SISL_POS: u32 = 0;
pub const CMP_SCCR_SISL: u32 = 15;
pub const CMP_SCCR_SPRD_POS: u32 = 16;
pub const CMP_SCCR_SPRD: u32 = 16711680;
pub const CMP_SCCR_SSTB_POS: u32 = 24;
pub const CMP_SCCR_SSTB: u32 = 1056964608;
pub const CMP_SCMR_RVST_POS: u32 = 0;
pub const CMP_SCMR_RVST: u32 = 15;
pub const CMP_SCMR_CVST_POS: u32 = 16;
pub const CMP_SCMR_CVST: u32 = 983040;
pub const CMU_XTALDIVR_DEMON_POS: u32 = 0;
pub const CMU_XTALDIVR_DEMON: u32 = 2047;
pub const CMU_XTALDIVR_NUMER_POS: u32 = 12;
pub const CMU_XTALDIVR_NUMER: u32 = 536866816;
pub const CMU_XTALDIVCR_FRADIVEN: u32 = 1;
pub const CMU_XTALCFGR_XTALDRV_POS: u32 = 4;
pub const CMU_XTALCFGR_XTALDRV: u32 = 48;
pub const CMU_XTALCFGR_XTALDRV_0: u32 = 16;
pub const CMU_XTALCFGR_XTALDRV_1: u32 = 32;
pub const CMU_XTALCFGR_XTALMS_POS: u32 = 6;
pub const CMU_XTALCFGR_XTALMS: u32 = 64;
pub const CMU_XTAL32CR_XTAL32STP: u32 = 1;
pub const CMU_XTAL32CFGR_XTAL32DRV: u32 = 7;
pub const CMU_XTAL32NFR_XTAL32NF: u32 = 3;
pub const CMU_XTAL32NFR_XTAL32NF_0: u32 = 1;
pub const CMU_XTAL32NFR_XTAL32NF_1: u32 = 2;
pub const CMU_LRCCR_LRCSTP: u32 = 1;
pub const CMU_LRCTRM: u32 = 255;
pub const CMU_PERICKSEL_PERICKSEL: u32 = 15;
pub const CMU_CANCKCFGR_MCAN1CKS_POS: u32 = 0;
pub const CMU_CANCKCFGR_MCAN1CKS: u32 = 15;
pub const CMU_CANCKCFGR_MCAN2CKS_POS: u32 = 4;
pub const CMU_CANCKCFGR_MCAN2CKS: u32 = 240;
pub const CMU_SCFGR_PCLK0S_POS: u32 = 0;
pub const CMU_SCFGR_PCLK0S: u32 = 7;
pub const CMU_SCFGR_PCLK1S_POS: u32 = 4;
pub const CMU_SCFGR_PCLK1S: u32 = 112;
pub const CMU_SCFGR_PCLK2S_POS: u32 = 8;
pub const CMU_SCFGR_PCLK2S: u32 = 1792;
pub const CMU_SCFGR_PCLK3S_POS: u32 = 12;
pub const CMU_SCFGR_PCLK3S: u32 = 28672;
pub const CMU_SCFGR_PCLK4S_POS: u32 = 16;
pub const CMU_SCFGR_PCLK4S: u32 = 458752;
pub const CMU_SCFGR_EXCKS_POS: u32 = 20;
pub const CMU_SCFGR_EXCKS: u32 = 7340032;
pub const CMU_SCFGR_HCLKS_POS: u32 = 24;
pub const CMU_SCFGR_HCLKS: u32 = 117440512;
pub const CMU_CKSWR_CKSW: u32 = 7;
pub const CMU_PLLHCR_PLLHOFF: u32 = 1;
pub const CMU_XTALCR_XTALSTP: u32 = 1;
pub const CMU_HRCCR_HRCSTP: u32 = 1;
pub const CMU_MRCCR_MRCSTP: u32 = 1;
pub const CMU_OSCSTBSR_HRCSTBF_POS: u32 = 0;
pub const CMU_OSCSTBSR_HRCSTBF: u32 = 1;
pub const CMU_OSCSTBSR_XTALSTBF_POS: u32 = 3;
pub const CMU_OSCSTBSR_XTALSTBF: u32 = 8;
pub const CMU_OSCSTBSR_PLLHSTBF_POS: u32 = 5;
pub const CMU_OSCSTBSR_PLLHSTBF: u32 = 32;
pub const CMU_MCOCFGR_MCOSEL_POS: u32 = 0;
pub const CMU_MCOCFGR_MCOSEL: u32 = 15;
pub const CMU_MCOCFGR_MCODIV_POS: u32 = 4;
pub const CMU_MCOCFGR_MCODIV: u32 = 112;
pub const CMU_MCOCFGR_MCOEN_POS: u32 = 7;
pub const CMU_MCOCFGR_MCOEN: u32 = 128;
pub const CMU_TPIUCKCFGR_TPIUCKS_POS: u32 = 0;
pub const CMU_TPIUCKCFGR_TPIUCKS: u32 = 3;
pub const CMU_TPIUCKCFGR_TPIUCKS_0: u32 = 1;
pub const CMU_TPIUCKCFGR_TPIUCKS_1: u32 = 2;
pub const CMU_TPIUCKCFGR_TPIUCKOE_POS: u32 = 7;
pub const CMU_TPIUCKCFGR_TPIUCKOE: u32 = 128;
pub const CMU_XTALSTDCR_XTALSTDIE_POS: u32 = 0;
pub const CMU_XTALSTDCR_XTALSTDIE: u32 = 1;
pub const CMU_XTALSTDCR_XTALSTDRE_POS: u32 = 1;
pub const CMU_XTALSTDCR_XTALSTDRE: u32 = 2;
pub const CMU_XTALSTDCR_XTALSTDRIS_POS: u32 = 2;
pub const CMU_XTALSTDCR_XTALSTDRIS: u32 = 4;
pub const CMU_XTALSTDCR_XTALSTDE_POS: u32 = 7;
pub const CMU_XTALSTDCR_XTALSTDE: u32 = 128;
pub const CMU_XTALSTDSR_XTALSTDF: u32 = 1;
pub const CMU_MRCTRM: u32 = 255;
pub const CMU_HRCTRM: u32 = 255;
pub const CMU_XTALSTBCR_XTALSTB: u32 = 15;
pub const CMU_PLLHCFGR_PLLHM_POS: u32 = 0;
pub const CMU_PLLHCFGR_PLLHM: u32 = 3;
pub const CMU_PLLHCFGR_PLLHM_0: u32 = 1;
pub const CMU_PLLHCFGR_PLLHM_1: u32 = 2;
pub const CMU_PLLHCFGR_PLLSRC_POS: u32 = 7;
pub const CMU_PLLHCFGR_PLLSRC: u32 = 128;
pub const CMU_PLLHCFGR_PLLHN_POS: u32 = 8;
pub const CMU_PLLHCFGR_PLLHN: u32 = 65280;
pub const CMU_PLLHCFGR_PLLHR_POS: u32 = 20;
pub const CMU_PLLHCFGR_PLLHR: u32 = 15728640;
pub const CMU_PLLHCFGR_PLLHQ_POS: u32 = 24;
pub const CMU_PLLHCFGR_PLLHQ: u32 = 251658240;
pub const CMU_PLLHCFGR_PLLHP_POS: u32 = 28;
pub const CMU_PLLHCFGR_PLLHP: u32 = 4026531840;
pub const CRC_CR_CR_POS: u32 = 0;
pub const CRC_CR_CR: u32 = 1;
pub const CRC_CR_FLAG_POS: u32 = 1;
pub const CRC_CR_FLAG: u32 = 2;
pub const CRC_RESLT: u32 = 4294967295;
pub const CRC_DAT0: u32 = 4294967295;
pub const CRC_DAT1: u32 = 4294967295;
pub const CRC_DAT2: u32 = 4294967295;
pub const CRC_DAT3: u32 = 4294967295;
pub const CRC_DAT4: u32 = 4294967295;
pub const CRC_DAT5: u32 = 4294967295;
pub const CRC_DAT6: u32 = 4294967295;
pub const CRC_DAT7: u32 = 4294967295;
pub const CRC_DAT8: u32 = 4294967295;
pub const CRC_DAT9: u32 = 4294967295;
pub const CRC_DAT10: u32 = 4294967295;
pub const CRC_DAT11: u32 = 4294967295;
pub const CRC_DAT12: u32 = 4294967295;
pub const CRC_DAT13: u32 = 4294967295;
pub const CRC_DAT14: u32 = 4294967295;
pub const CRC_DAT15: u32 = 4294967295;
pub const CRC_DAT16: u32 = 4294967295;
pub const CRC_DAT17: u32 = 4294967295;
pub const CRC_DAT18: u32 = 4294967295;
pub const CRC_DAT19: u32 = 4294967295;
pub const CRC_DAT20: u32 = 4294967295;
pub const CRC_DAT21: u32 = 4294967295;
pub const CRC_DAT22: u32 = 4294967295;
pub const CRC_DAT23: u32 = 4294967295;
pub const CRC_DAT24: u32 = 4294967295;
pub const CRC_DAT25: u32 = 4294967295;
pub const CRC_DAT26: u32 = 4294967295;
pub const CRC_DAT27: u32 = 4294967295;
pub const CRC_DAT28: u32 = 4294967295;
pub const CRC_DAT29: u32 = 4294967295;
pub const CRC_DAT30: u32 = 4294967295;
pub const CRC_DAT31: u32 = 4294967295;
pub const CTC_CR1_REFPSC_POS: u32 = 0;
pub const CTC_CR1_REFPSC: u32 = 7;
pub const CTC_CR1_REFCKS_POS: u32 = 4;
pub const CTC_CR1_REFCKS: u32 = 48;
pub const CTC_CR1_REFCKS_0: u32 = 16;
pub const CTC_CR1_REFCKS_1: u32 = 32;
pub const CTC_CR1_ERRIE_POS: u32 = 6;
pub const CTC_CR1_ERRIE: u32 = 64;
pub const CTC_CR1_CTCEN_POS: u32 = 7;
pub const CTC_CR1_CTCEN: u32 = 128;
pub const CTC_CR1_HRCPSC_POS: u32 = 8;
pub const CTC_CR1_HRCPSC: u32 = 1792;
pub const CTC_CR1_REFEDG_POS: u32 = 12;
pub const CTC_CR1_REFEDG: u32 = 12288;
pub const CTC_CR1_REFEDG_0: u32 = 4096;
pub const CTC_CR1_REFEDG_1: u32 = 8192;
pub const CTC_CR1_TRMVAL_POS: u32 = 16;
pub const CTC_CR1_TRMVAL: u32 = 4128768;
pub const CTC_CR2_OFSVAL_POS: u32 = 0;
pub const CTC_CR2_OFSVAL: u32 = 255;
pub const CTC_CR2_RLDVAL_POS: u32 = 16;
pub const CTC_CR2_RLDVAL: u32 = 4294901760;
pub const CTC_STR_TRIMOK_POS: u32 = 0;
pub const CTC_STR_TRIMOK: u32 = 1;
pub const CTC_STR_TRMOVF_POS: u32 = 1;
pub const CTC_STR_TRMOVF: u32 = 2;
pub const CTC_STR_TRMUDF_POS: u32 = 2;
pub const CTC_STR_TRMUDF: u32 = 4;
pub const CTC_STR_CTCBSY_POS: u32 = 3;
pub const CTC_STR_CTCBSY: u32 = 8;
pub const CTC_CNT: u32 = 65535;
pub const DAC_DADR1_DR0_POS: u32 = 0;
pub const DAC_DADR1_DR0: u32 = 1;
pub const DAC_DADR1_DR1_POS: u32 = 1;
pub const DAC_DADR1_DR1: u32 = 2;
pub const DAC_DADR1_DR2_POS: u32 = 2;
pub const DAC_DADR1_DR2: u32 = 4;
pub const DAC_DADR1_DR3_POS: u32 = 3;
pub const DAC_DADR1_DR3: u32 = 8;
pub const DAC_DADR1_DL0R4_POS: u32 = 4;
pub const DAC_DADR1_DL0R4: u32 = 16;
pub const DAC_DADR1_DL1R5_POS: u32 = 5;
pub const DAC_DADR1_DL1R5: u32 = 32;
pub const DAC_DADR1_DL2R6_POS: u32 = 6;
pub const DAC_DADR1_DL2R6: u32 = 64;
pub const DAC_DADR1_DL3R7_POS: u32 = 7;
pub const DAC_DADR1_DL3R7: u32 = 128;
pub const DAC_DADR1_DL4R8_POS: u32 = 8;
pub const DAC_DADR1_DL4R8: u32 = 256;
pub const DAC_DADR1_DL5R9_POS: u32 = 9;
pub const DAC_DADR1_DL5R9: u32 = 512;
pub const DAC_DADR1_DL6R10_POS: u32 = 10;
pub const DAC_DADR1_DL6R10: u32 = 1024;
pub const DAC_DADR1_DL7R11_POS: u32 = 11;
pub const DAC_DADR1_DL7R11: u32 = 2048;
pub const DAC_DADR1_DL8_POS: u32 = 12;
pub const DAC_DADR1_DL8: u32 = 4096;
pub const DAC_DADR1_DL9_POS: u32 = 13;
pub const DAC_DADR1_DL9: u32 = 8192;
pub const DAC_DADR1_DL10_POS: u32 = 14;
pub const DAC_DADR1_DL10: u32 = 16384;
pub const DAC_DADR1_DL11_POS: u32 = 15;
pub const DAC_DADR1_DL11: u32 = 32768;
pub const DAC_DADR2_DR0_POS: u32 = 0;
pub const DAC_DADR2_DR0: u32 = 1;
pub const DAC_DADR2_DR1_POS: u32 = 1;
pub const DAC_DADR2_DR1: u32 = 2;
pub const DAC_DADR2_DR2_POS: u32 = 2;
pub const DAC_DADR2_DR2: u32 = 4;
pub const DAC_DADR2_DR3_POS: u32 = 3;
pub const DAC_DADR2_DR3: u32 = 8;
pub const DAC_DADR2_DL0R4_POS: u32 = 4;
pub const DAC_DADR2_DL0R4: u32 = 16;
pub const DAC_DADR2_DL1R5_POS: u32 = 5;
pub const DAC_DADR2_DL1R5: u32 = 32;
pub const DAC_DADR2_DL2R6_POS: u32 = 6;
pub const DAC_DADR2_DL2R6: u32 = 64;
pub const DAC_DADR2_DL3R7_POS: u32 = 7;
pub const DAC_DADR2_DL3R7: u32 = 128;
pub const DAC_DADR2_DL4R8_POS: u32 = 8;
pub const DAC_DADR2_DL4R8: u32 = 256;
pub const DAC_DADR2_DL5R9_POS: u32 = 9;
pub const DAC_DADR2_DL5R9: u32 = 512;
pub const DAC_DADR2_DL6R10_POS: u32 = 10;
pub const DAC_DADR2_DL6R10: u32 = 1024;
pub const DAC_DADR2_DL7R11_POS: u32 = 11;
pub const DAC_DADR2_DL7R11: u32 = 2048;
pub const DAC_DADR2_DL8_POS: u32 = 12;
pub const DAC_DADR2_DL8: u32 = 4096;
pub const DAC_DADR2_DL9_POS: u32 = 13;
pub const DAC_DADR2_DL9: u32 = 8192;
pub const DAC_DADR2_DL10_POS: u32 = 14;
pub const DAC_DADR2_DL10: u32 = 16384;
pub const DAC_DADR2_DL11_POS: u32 = 15;
pub const DAC_DADR2_DL11: u32 = 32768;
pub const DAC_DACR_DAE_POS: u32 = 0;
pub const DAC_DACR_DAE: u32 = 1;
pub const DAC_DACR_DA1E_POS: u32 = 1;
pub const DAC_DACR_DA1E: u32 = 2;
pub const DAC_DACR_DA2E_POS: u32 = 2;
pub const DAC_DACR_DA2E: u32 = 4;
pub const DAC_DACR_DPSEL_POS: u32 = 8;
pub const DAC_DACR_DPSEL: u32 = 256;
pub const DAC_DACR_DAAMP1_POS: u32 = 9;
pub const DAC_DACR_DAAMP1: u32 = 512;
pub const DAC_DACR_DAAMP2_POS: u32 = 10;
pub const DAC_DACR_DAAMP2: u32 = 1024;
pub const DAC_DACR_EXTDSL1_POS: u32 = 11;
pub const DAC_DACR_EXTDSL1: u32 = 2048;
pub const DAC_DACR_EXTDSL2_POS: u32 = 12;
pub const DAC_DACR_EXTDSL2: u32 = 4096;
pub const DAC_DAADPCR_ADCSL1_POS: u32 = 0;
pub const DAC_DAADPCR_ADCSL1: u32 = 1;
pub const DAC_DAADPCR_ADCSL2_POS: u32 = 1;
pub const DAC_DAADPCR_ADCSL2: u32 = 2;
pub const DAC_DAADPCR_ADCSL3_POS: u32 = 2;
pub const DAC_DAADPCR_ADCSL3: u32 = 4;
pub const DAC_DAADPCR_DA1SF_POS: u32 = 8;
pub const DAC_DAADPCR_DA1SF: u32 = 256;
pub const DAC_DAADPCR_DA2SF_POS: u32 = 9;
pub const DAC_DAADPCR_DA2SF: u32 = 512;
pub const DAC_DAADPCR_ADPEN_POS: u32 = 15;
pub const DAC_DAADPCR_ADPEN: u32 = 32768;
pub const DAC_DAOCR_DAODIS1_POS: u32 = 14;
pub const DAC_DAOCR_DAODIS1: u32 = 16384;
pub const DAC_DAOCR_DAODIS2_POS: u32 = 15;
pub const DAC_DAOCR_DAODIS2: u32 = 32768;
pub const DBGC_CHIPID: u32 = 4294967295;
pub const DBGC_MCUDBGCSTAT_CDBGPWRUPREQ_POS: u32 = 0;
pub const DBGC_MCUDBGCSTAT_CDBGPWRUPREQ: u32 = 1;
pub const DBGC_MCUDBGCSTAT_CDBGPWRUPACK_POS: u32 = 1;
pub const DBGC_MCUDBGCSTAT_CDBGPWRUPACK: u32 = 2;
pub const DBGC_MCUSTPCTL_SWDTSTP_POS: u32 = 0;
pub const DBGC_MCUSTPCTL_SWDTSTP: u32 = 1;
pub const DBGC_MCUSTPCTL_WDTSTP_POS: u32 = 1;
pub const DBGC_MCUSTPCTL_WDTSTP: u32 = 2;
pub const DBGC_MCUSTPCTL_RTCSTP_POS: u32 = 2;
pub const DBGC_MCUSTPCTL_RTCSTP: u32 = 4;
pub const DBGC_MCUSTPCTL_M06STP_POS: u32 = 6;
pub const DBGC_MCUSTPCTL_M06STP: u32 = 64;
pub const DBGC_MCUSTPCTL_M07STP_POS: u32 = 7;
pub const DBGC_MCUSTPCTL_M07STP: u32 = 128;
pub const DBGC_MCUSTPCTL_M12STP_POS: u32 = 12;
pub const DBGC_MCUSTPCTL_M12STP: u32 = 4096;
pub const DBGC_MCUSTPCTL_M13STP_POS: u32 = 13;
pub const DBGC_MCUSTPCTL_M13STP: u32 = 8192;
pub const DBGC_MCUSTPCTL_M14STP_POS: u32 = 14;
pub const DBGC_MCUSTPCTL_M14STP: u32 = 16384;
pub const DBGC_MCUSTPCTL_M15STP_POS: u32 = 15;
pub const DBGC_MCUSTPCTL_M15STP: u32 = 32768;
pub const DBGC_MCUSTPCTL_M16STP_POS: u32 = 16;
pub const DBGC_MCUSTPCTL_M16STP: u32 = 65536;
pub const DBGC_MCUTRACECTL_TRACEMODE_POS: u32 = 0;
pub const DBGC_MCUTRACECTL_TRACEMODE: u32 = 3;
pub const DBGC_MCUTRACECTL_TRACEMODE_0: u32 = 1;
pub const DBGC_MCUTRACECTL_TRACEMODE_1: u32 = 2;
pub const DBGC_MCUTRACECTL_TRACEIOEN_POS: u32 = 2;
pub const DBGC_MCUTRACECTL_TRACEIOEN: u32 = 4;
pub const DBGC_MCUSTPCTL2_M32STP_POS: u32 = 0;
pub const DBGC_MCUSTPCTL2_M32STP: u32 = 1;
pub const DBGC_MCUSTPCTL2_M33STP_POS: u32 = 1;
pub const DBGC_MCUSTPCTL2_M33STP: u32 = 2;
pub const DBGC_MCUSTPCTL2_M34STP_POS: u32 = 2;
pub const DBGC_MCUSTPCTL2_M34STP: u32 = 4;
pub const DBGC_MCUSTPCTL2_M35STP_POS: u32 = 3;
pub const DBGC_MCUSTPCTL2_M35STP: u32 = 8;
pub const DBGC_MCUSTPCTL2_M36STP_POS: u32 = 4;
pub const DBGC_MCUSTPCTL2_M36STP: u32 = 16;
pub const DCU_CTL_MODE_POS: u32 = 0;
pub const DCU_CTL_MODE: u32 = 15;
pub const DCU_CTL_DATASIZE_POS: u32 = 4;
pub const DCU_CTL_DATASIZE: u32 = 48;
pub const DCU_CTL_DATASIZE_0: u32 = 16;
pub const DCU_CTL_DATASIZE_1: u32 = 32;
pub const DCU_CTL_COMPTRG_POS: u32 = 8;
pub const DCU_CTL_COMPTRG: u32 = 256;
pub const DCU_CTL_INTEN_POS: u32 = 31;
pub const DCU_CTL_INTEN: u32 = 2147483648;
pub const DCU_FLAG_FLAG_OP_POS: u32 = 0;
pub const DCU_FLAG_FLAG_OP: u32 = 1;
pub const DCU_FLAG_FLAG_LS2_POS: u32 = 1;
pub const DCU_FLAG_FLAG_LS2: u32 = 2;
pub const DCU_FLAG_FLAG_EQ2_POS: u32 = 2;
pub const DCU_FLAG_FLAG_EQ2: u32 = 4;
pub const DCU_FLAG_FLAG_GT2_POS: u32 = 3;
pub const DCU_FLAG_FLAG_GT2: u32 = 8;
pub const DCU_FLAG_FLAG_LS1_POS: u32 = 4;
pub const DCU_FLAG_FLAG_LS1: u32 = 16;
pub const DCU_FLAG_FLAG_EQ1_POS: u32 = 5;
pub const DCU_FLAG_FLAG_EQ1: u32 = 32;
pub const DCU_FLAG_FLAG_GT1_POS: u32 = 6;
pub const DCU_FLAG_FLAG_GT1: u32 = 64;
pub const DCU_FLAG_FLAG_RLD_POS: u32 = 9;
pub const DCU_FLAG_FLAG_RLD: u32 = 512;
pub const DCU_FLAG_FLAG_BTM_POS: u32 = 10;
pub const DCU_FLAG_FLAG_BTM: u32 = 1024;
pub const DCU_FLAG_FLAG_TOP_POS: u32 = 11;
pub const DCU_FLAG_FLAG_TOP: u32 = 2048;
pub const DCU_DATA0: u32 = 4294967295;
pub const DCU_DATA1: u32 = 4294967295;
pub const DCU_DATA2: u32 = 4294967295;
pub const DCU_FLAGCLR_CLR_OP_POS: u32 = 0;
pub const DCU_FLAGCLR_CLR_OP: u32 = 1;
pub const DCU_FLAGCLR_CLR_LS2_POS: u32 = 1;
pub const DCU_FLAGCLR_CLR_LS2: u32 = 2;
pub const DCU_FLAGCLR_CLR_EQ2_POS: u32 = 2;
pub const DCU_FLAGCLR_CLR_EQ2: u32 = 4;
pub const DCU_FLAGCLR_CLR_GT2_POS: u32 = 3;
pub const DCU_FLAGCLR_CLR_GT2: u32 = 8;
pub const DCU_FLAGCLR_CLR_LS1_POS: u32 = 4;
pub const DCU_FLAGCLR_CLR_LS1: u32 = 16;
pub const DCU_FLAGCLR_CLR_EQ1_POS: u32 = 5;
pub const DCU_FLAGCLR_CLR_EQ1: u32 = 32;
pub const DCU_FLAGCLR_CLR_GT1_POS: u32 = 6;
pub const DCU_FLAGCLR_CLR_GT1: u32 = 64;
pub const DCU_FLAGCLR_CLR_RLD_POS: u32 = 9;
pub const DCU_FLAGCLR_CLR_RLD: u32 = 512;
pub const DCU_FLAGCLR_CLR_BTM_POS: u32 = 10;
pub const DCU_FLAGCLR_CLR_BTM: u32 = 1024;
pub const DCU_FLAGCLR_CLR_TOP_POS: u32 = 11;
pub const DCU_FLAGCLR_CLR_TOP: u32 = 2048;
pub const DCU_INTEVTSEL_SEL_OP_POS: u32 = 0;
pub const DCU_INTEVTSEL_SEL_OP: u32 = 1;
pub const DCU_INTEVTSEL_SEL_LS2_POS: u32 = 1;
pub const DCU_INTEVTSEL_SEL_LS2: u32 = 2;
pub const DCU_INTEVTSEL_SEL_EQ2_POS: u32 = 2;
pub const DCU_INTEVTSEL_SEL_EQ2: u32 = 4;
pub const DCU_INTEVTSEL_SEL_GT2_POS: u32 = 3;
pub const DCU_INTEVTSEL_SEL_GT2: u32 = 8;
pub const DCU_INTEVTSEL_SEL_LS1_POS: u32 = 4;
pub const DCU_INTEVTSEL_SEL_LS1: u32 = 16;
pub const DCU_INTEVTSEL_SEL_EQ1_POS: u32 = 5;
pub const DCU_INTEVTSEL_SEL_EQ1: u32 = 32;
pub const DCU_INTEVTSEL_SEL_GT1_POS: u32 = 6;
pub const DCU_INTEVTSEL_SEL_GT1: u32 = 64;
pub const DCU_INTEVTSEL_SEL_WIN_POS: u32 = 7;
pub const DCU_INTEVTSEL_SEL_WIN: u32 = 384;
pub const DCU_INTEVTSEL_SEL_WIN_0: u32 = 128;
pub const DCU_INTEVTSEL_SEL_WIN_1: u32 = 256;
pub const DCU_INTEVTSEL_SEL_BTM_POS: u32 = 10;
pub const DCU_INTEVTSEL_SEL_BTM: u32 = 1024;
pub const DCU_INTEVTSEL_SEL_TOP_POS: u32 = 11;
pub const DCU_INTEVTSEL_SEL_TOP: u32 = 2048;
pub const DMA_EN_EN: u32 = 1;
pub const DMA_INTSTAT0_TRNERR_POS: u32 = 0;
pub const DMA_INTSTAT0_TRNERR: u32 = 63;
pub const DMA_INTSTAT0_TRNERR_0: u32 = 1;
pub const DMA_INTSTAT0_TRNERR_1: u32 = 2;
pub const DMA_INTSTAT0_TRNERR_2: u32 = 4;
pub const DMA_INTSTAT0_TRNERR_3: u32 = 8;
pub const DMA_INTSTAT0_TRNERR_4: u32 = 16;
pub const DMA_INTSTAT0_TRNERR_5: u32 = 32;
pub const DMA_INTSTAT0_REQERR_POS: u32 = 16;
pub const DMA_INTSTAT0_REQERR: u32 = 4128768;
pub const DMA_INTSTAT0_REQERR_0: u32 = 65536;
pub const DMA_INTSTAT0_REQERR_1: u32 = 131072;
pub const DMA_INTSTAT0_REQERR_2: u32 = 262144;
pub const DMA_INTSTAT0_REQERR_3: u32 = 524288;
pub const DMA_INTSTAT0_REQERR_4: u32 = 1048576;
pub const DMA_INTSTAT0_REQERR_5: u32 = 2097152;
pub const DMA_INTSTAT1_TC_POS: u32 = 0;
pub const DMA_INTSTAT1_TC: u32 = 63;
pub const DMA_INTSTAT1_TC_0: u32 = 1;
pub const DMA_INTSTAT1_TC_1: u32 = 2;
pub const DMA_INTSTAT1_TC_2: u32 = 4;
pub const DMA_INTSTAT1_TC_3: u32 = 8;
pub const DMA_INTSTAT1_TC_4: u32 = 16;
pub const DMA_INTSTAT1_TC_5: u32 = 32;
pub const DMA_INTSTAT1_BTC_POS: u32 = 16;
pub const DMA_INTSTAT1_BTC: u32 = 4128768;
pub const DMA_INTSTAT1_BTC_0: u32 = 65536;
pub const DMA_INTSTAT1_BTC_1: u32 = 131072;
pub const DMA_INTSTAT1_BTC_2: u32 = 262144;
pub const DMA_INTSTAT1_BTC_3: u32 = 524288;
pub const DMA_INTSTAT1_BTC_4: u32 = 1048576;
pub const DMA_INTSTAT1_BTC_5: u32 = 2097152;
pub const DMA_INTMASK0_MSKTRNERR_POS: u32 = 0;
pub const DMA_INTMASK0_MSKTRNERR: u32 = 63;
pub const DMA_INTMASK0_MSKTRNERR_0: u32 = 1;
pub const DMA_INTMASK0_MSKTRNERR_1: u32 = 2;
pub const DMA_INTMASK0_MSKTRNERR_2: u32 = 4;
pub const DMA_INTMASK0_MSKTRNERR_3: u32 = 8;
pub const DMA_INTMASK0_MSKTRNERR_4: u32 = 16;
pub const DMA_INTMASK0_MSKTRNERR_5: u32 = 32;
pub const DMA_INTMASK0_MSKREQERR_POS: u32 = 16;
pub const DMA_INTMASK0_MSKREQERR: u32 = 4128768;
pub const DMA_INTMASK0_MSKREQERR_0: u32 = 65536;
pub const DMA_INTMASK0_MSKREQERR_1: u32 = 131072;
pub const DMA_INTMASK0_MSKREQERR_2: u32 = 262144;
pub const DMA_INTMASK0_MSKREQERR_3: u32 = 524288;
pub const DMA_INTMASK0_MSKREQERR_4: u32 = 1048576;
pub const DMA_INTMASK0_MSKREQERR_5: u32 = 2097152;
pub const DMA_INTMASK1_MSKTC_POS: u32 = 0;
pub const DMA_INTMASK1_MSKTC: u32 = 63;
pub const DMA_INTMASK1_MSKTC_0: u32 = 1;
pub const DMA_INTMASK1_MSKTC_1: u32 = 2;
pub const DMA_INTMASK1_MSKTC_2: u32 = 4;
pub const DMA_INTMASK1_MSKTC_3: u32 = 8;
pub const DMA_INTMASK1_MSKTC_4: u32 = 16;
pub const DMA_INTMASK1_MSKTC_5: u32 = 32;
pub const DMA_INTMASK1_MSKBTC_POS: u32 = 16;
pub const DMA_INTMASK1_MSKBTC: u32 = 4128768;
pub const DMA_INTMASK1_MSKBTC_0: u32 = 65536;
pub const DMA_INTMASK1_MSKBTC_1: u32 = 131072;
pub const DMA_INTMASK1_MSKBTC_2: u32 = 262144;
pub const DMA_INTMASK1_MSKBTC_3: u32 = 524288;
pub const DMA_INTMASK1_MSKBTC_4: u32 = 1048576;
pub const DMA_INTMASK1_MSKBTC_5: u32 = 2097152;
pub const DMA_INTCLR0_CLRTRNERR_POS: u32 = 0;
pub const DMA_INTCLR0_CLRTRNERR: u32 = 63;
pub const DMA_INTCLR0_CLRTRNERR_0: u32 = 1;
pub const DMA_INTCLR0_CLRTRNERR_1: u32 = 2;
pub const DMA_INTCLR0_CLRTRNERR_2: u32 = 4;
pub const DMA_INTCLR0_CLRTRNERR_3: u32 = 8;
pub const DMA_INTCLR0_CLRTRNERR_4: u32 = 16;
pub const DMA_INTCLR0_CLRTRNERR_5: u32 = 32;
pub const DMA_INTCLR0_CLRREQERR_POS: u32 = 16;
pub const DMA_INTCLR0_CLRREQERR: u32 = 4128768;
pub const DMA_INTCLR0_CLRREQERR_0: u32 = 65536;
pub const DMA_INTCLR0_CLRREQERR_1: u32 = 131072;
pub const DMA_INTCLR0_CLRREQERR_2: u32 = 262144;
pub const DMA_INTCLR0_CLRREQERR_3: u32 = 524288;
pub const DMA_INTCLR0_CLRREQERR_4: u32 = 1048576;
pub const DMA_INTCLR0_CLRREQERR_5: u32 = 2097152;
pub const DMA_INTCLR1_CLRTC_POS: u32 = 0;
pub const DMA_INTCLR1_CLRTC: u32 = 63;
pub const DMA_INTCLR1_CLRTC_0: u32 = 1;
pub const DMA_INTCLR1_CLRTC_1: u32 = 2;
pub const DMA_INTCLR1_CLRTC_2: u32 = 4;
pub const DMA_INTCLR1_CLRTC_3: u32 = 8;
pub const DMA_INTCLR1_CLRTC_4: u32 = 16;
pub const DMA_INTCLR1_CLRTC_5: u32 = 32;
pub const DMA_INTCLR1_CLRBTC_POS: u32 = 16;
pub const DMA_INTCLR1_CLRBTC: u32 = 4128768;
pub const DMA_INTCLR1_CLRBTC_0: u32 = 65536;
pub const DMA_INTCLR1_CLRBTC_1: u32 = 131072;
pub const DMA_INTCLR1_CLRBTC_2: u32 = 262144;
pub const DMA_INTCLR1_CLRBTC_3: u32 = 524288;
pub const DMA_INTCLR1_CLRBTC_4: u32 = 1048576;
pub const DMA_INTCLR1_CLRBTC_5: u32 = 2097152;
pub const DMA_CHEN_CHEN: u32 = 63;
pub const DMA_CHEN_CHEN_0: u32 = 1;
pub const DMA_CHEN_CHEN_1: u32 = 2;
pub const DMA_CHEN_CHEN_2: u32 = 4;
pub const DMA_CHEN_CHEN_3: u32 = 8;
pub const DMA_CHEN_CHEN_4: u32 = 16;
pub const DMA_CHEN_CHEN_5: u32 = 32;
pub const DMA_REQSTAT_CHREQ_POS: u32 = 0;
pub const DMA_REQSTAT_CHREQ: u32 = 63;
pub const DMA_REQSTAT_CHREQ_0: u32 = 1;
pub const DMA_REQSTAT_CHREQ_1: u32 = 2;
pub const DMA_REQSTAT_CHREQ_2: u32 = 4;
pub const DMA_REQSTAT_CHREQ_3: u32 = 8;
pub const DMA_REQSTAT_CHREQ_4: u32 = 16;
pub const DMA_REQSTAT_CHREQ_5: u32 = 32;
pub const DMA_REQSTAT_RCFGREQ_POS: u32 = 15;
pub const DMA_REQSTAT_RCFGREQ: u32 = 32768;
pub const DMA_CHSTAT_DMAACT_POS: u32 = 0;
pub const DMA_CHSTAT_DMAACT: u32 = 1;
pub const DMA_CHSTAT_RCFGACT_POS: u32 = 1;
pub const DMA_CHSTAT_RCFGACT: u32 = 2;
pub const DMA_CHSTAT_CHACT_POS: u32 = 16;
pub const DMA_CHSTAT_CHACT: u32 = 4128768;
pub const DMA_CHSTAT_CHACT_0: u32 = 65536;
pub const DMA_CHSTAT_CHACT_1: u32 = 131072;
pub const DMA_CHSTAT_CHACT_2: u32 = 262144;
pub const DMA_CHSTAT_CHACT_3: u32 = 524288;
pub const DMA_CHSTAT_CHACT_4: u32 = 1048576;
pub const DMA_CHSTAT_CHACT_5: u32 = 2097152;
pub const DMA_RCFGCTL_RCFGEN_POS: u32 = 0;
pub const DMA_RCFGCTL_RCFGEN: u32 = 1;
pub const DMA_RCFGCTL_RCFGLLP_POS: u32 = 1;
pub const DMA_RCFGCTL_RCFGLLP: u32 = 2;
pub const DMA_RCFGCTL_RCFGCHS_POS: u32 = 8;
pub const DMA_RCFGCTL_RCFGCHS: u32 = 3840;
pub const DMA_RCFGCTL_SARMD_POS: u32 = 16;
pub const DMA_RCFGCTL_SARMD: u32 = 196608;
pub const DMA_RCFGCTL_SARMD_0: u32 = 65536;
pub const DMA_RCFGCTL_SARMD_1: u32 = 131072;
pub const DMA_RCFGCTL_DARMD_POS: u32 = 18;
pub const DMA_RCFGCTL_DARMD: u32 = 786432;
pub const DMA_RCFGCTL_DARMD_0: u32 = 262144;
pub const DMA_RCFGCTL_DARMD_1: u32 = 524288;
pub const DMA_RCFGCTL_CNTMD_POS: u32 = 20;
pub const DMA_RCFGCTL_CNTMD: u32 = 3145728;
pub const DMA_RCFGCTL_CNTMD_0: u32 = 1048576;
pub const DMA_RCFGCTL_CNTMD_1: u32 = 2097152;
pub const DMA_SWREQ_SWREQ_POS: u32 = 0;
pub const DMA_SWREQ_SWREQ: u32 = 255;
pub const DMA_SWREQ_SWREQ_0: u32 = 1;
pub const DMA_SWREQ_SWREQ_1: u32 = 2;
pub const DMA_SWREQ_SWREQ_2: u32 = 4;
pub const DMA_SWREQ_SWREQ_3: u32 = 8;
pub const DMA_SWREQ_SWREQ_4: u32 = 16;
pub const DMA_SWREQ_SWREQ_5: u32 = 32;
pub const DMA_SWREQ_SWREQ_6: u32 = 64;
pub const DMA_SWREQ_SWREQ_7: u32 = 128;
pub const DMA_SWREQ_SWRCFGREQ_POS: u32 = 15;
pub const DMA_SWREQ_SWRCFGREQ: u32 = 32768;
pub const DMA_SWREQ_SWREQWP_POS: u32 = 16;
pub const DMA_SWREQ_SWREQWP: u32 = 16711680;
pub const DMA_SWREQ_SWRCFGWP_POS: u32 = 24;
pub const DMA_SWREQ_SWRCFGWP: u32 = 4278190080;
pub const DMA_CHENCLR_CHENCLR: u32 = 63;
pub const DMA_CHENCLR_CHENCLR_0: u32 = 1;
pub const DMA_CHENCLR_CHENCLR_1: u32 = 2;
pub const DMA_CHENCLR_CHENCLR_2: u32 = 4;
pub const DMA_CHENCLR_CHENCLR_3: u32 = 8;
pub const DMA_CHENCLR_CHENCLR_4: u32 = 16;
pub const DMA_CHENCLR_CHENCLR_5: u32 = 32;
pub const DMA_SAR: u32 = 4294967295;
pub const DMA_DAR: u32 = 4294967295;
pub const DMA_DTCTL_BLKSIZE_POS: u32 = 0;
pub const DMA_DTCTL_BLKSIZE: u32 = 1023;
pub const DMA_DTCTL_CNT_POS: u32 = 16;
pub const DMA_DTCTL_CNT: u32 = 4294901760;
pub const DMA_RPT_SRPT_POS: u32 = 0;
pub const DMA_RPT_SRPT: u32 = 1023;
pub const DMA_RPT_DRPT_POS: u32 = 16;
pub const DMA_RPT_DRPT: u32 = 67043328;
pub const DMA_RPTB_SRPTB_POS: u32 = 0;
pub const DMA_RPTB_SRPTB: u32 = 1023;
pub const DMA_RPTB_DRPTB_POS: u32 = 16;
pub const DMA_RPTB_DRPTB: u32 = 67043328;
pub const DMA_SNSEQCTL_SOFFSET_POS: u32 = 0;
pub const DMA_SNSEQCTL_SOFFSET: u32 = 1048575;
pub const DMA_SNSEQCTL_SNSCNT_POS: u32 = 20;
pub const DMA_SNSEQCTL_SNSCNT: u32 = 4293918720;
pub const DMA_SNSEQCTLB_SNSDIST_POS: u32 = 0;
pub const DMA_SNSEQCTLB_SNSDIST: u32 = 1048575;
pub const DMA_SNSEQCTLB_SNSCNTB_POS: u32 = 20;
pub const DMA_SNSEQCTLB_SNSCNTB: u32 = 4293918720;
pub const DMA_DNSEQCTL_DOFFSET_POS: u32 = 0;
pub const DMA_DNSEQCTL_DOFFSET: u32 = 1048575;
pub const DMA_DNSEQCTL_DNSCNT_POS: u32 = 20;
pub const DMA_DNSEQCTL_DNSCNT: u32 = 4293918720;
pub const DMA_DNSEQCTLB_DNSDIST_POS: u32 = 0;
pub const DMA_DNSEQCTLB_DNSDIST: u32 = 1048575;
pub const DMA_DNSEQCTLB_DNSCNTB_POS: u32 = 20;
pub const DMA_DNSEQCTLB_DNSCNTB: u32 = 4293918720;
pub const DMA_LLP_LLP_POS: u32 = 2;
pub const DMA_LLP_LLP: u32 = 4294967292;
pub const DMA_CHCTL_SINC_POS: u32 = 0;
pub const DMA_CHCTL_SINC: u32 = 3;
pub const DMA_CHCTL_SINC_0: u32 = 1;
pub const DMA_CHCTL_SINC_1: u32 = 2;
pub const DMA_CHCTL_DINC_POS: u32 = 2;
pub const DMA_CHCTL_DINC: u32 = 12;
pub const DMA_CHCTL_DINC_0: u32 = 4;
pub const DMA_CHCTL_DINC_1: u32 = 8;
pub const DMA_CHCTL_SRPTEN_POS: u32 = 4;
pub const DMA_CHCTL_SRPTEN: u32 = 16;
pub const DMA_CHCTL_DRPTEN_POS: u32 = 5;
pub const DMA_CHCTL_DRPTEN: u32 = 32;
pub const DMA_CHCTL_SNSEQEN_POS: u32 = 6;
pub const DMA_CHCTL_SNSEQEN: u32 = 64;
pub const DMA_CHCTL_DNSEQEN_POS: u32 = 7;
pub const DMA_CHCTL_DNSEQEN: u32 = 128;
pub const DMA_CHCTL_HSIZE_POS: u32 = 8;
pub const DMA_CHCTL_HSIZE: u32 = 768;
pub const DMA_CHCTL_HSIZE_0: u32 = 256;
pub const DMA_CHCTL_HSIZE_1: u32 = 512;
pub const DMA_CHCTL_LLPEN_POS: u32 = 10;
pub const DMA_CHCTL_LLPEN: u32 = 1024;
pub const DMA_CHCTL_LLPRUN_POS: u32 = 11;
pub const DMA_CHCTL_LLPRUN: u32 = 2048;
pub const DMA_CHCTL_IE_POS: u32 = 12;
pub const DMA_CHCTL_IE: u32 = 4096;
pub const DMA_CHCTL_HPROT_POS: u32 = 14;
pub const DMA_CHCTL_HPROT: u32 = 49152;
pub const DMA_MONSAR: u32 = 4294967295;
pub const DMA_MONDAR: u32 = 4294967295;
pub const DMA_MONDTCTL_BLKSIZE_POS: u32 = 0;
pub const DMA_MONDTCTL_BLKSIZE: u32 = 1023;
pub const DMA_MONDTCTL_CNT_POS: u32 = 16;
pub const DMA_MONDTCTL_CNT: u32 = 4294901760;
pub const DMA_MONRPT_SRPT_POS: u32 = 0;
pub const DMA_MONRPT_SRPT: u32 = 1023;
pub const DMA_MONRPT_DRPT_POS: u32 = 16;
pub const DMA_MONRPT_DRPT: u32 = 67043328;
pub const DMA_MONSNSEQCTL_SOFFSET_POS: u32 = 0;
pub const DMA_MONSNSEQCTL_SOFFSET: u32 = 1048575;
pub const DMA_MONSNSEQCTL_SNSCNT_POS: u32 = 20;
pub const DMA_MONSNSEQCTL_SNSCNT: u32 = 4293918720;
pub const DMA_MONDNSEQCTL_DOFFSET_POS: u32 = 0;
pub const DMA_MONDNSEQCTL_DOFFSET: u32 = 1048575;
pub const DMA_MONDNSEQCTL_DNSCNT_POS: u32 = 20;
pub const DMA_MONDNSEQCTL_DNSCNT: u32 = 4293918720;
pub const EFM_FAPRT_FAPRT: u32 = 65535;
pub const EFM_KEY1: u32 = 4294967295;
pub const EFM_KEY2: u32 = 4294967295;
pub const EFM_FSTP_FSTP: u32 = 1;
pub const EFM_FRMC_FLWT_POS: u32 = 0;
pub const EFM_FRMC_FLWT: u32 = 15;
pub const EFM_FRMC_LVM_POS: u32 = 8;
pub const EFM_FRMC_LVM: u32 = 256;
pub const EFM_FRMC_ICACHE_POS: u32 = 16;
pub const EFM_FRMC_ICACHE: u32 = 65536;
pub const EFM_FRMC_DCACHE_POS: u32 = 17;
pub const EFM_FRMC_DCACHE: u32 = 131072;
pub const EFM_FRMC_PREFETE_POS: u32 = 18;
pub const EFM_FRMC_PREFETE: u32 = 262144;
pub const EFM_FRMC_CRST_POS: u32 = 19;
pub const EFM_FRMC_CRST: u32 = 524288;
pub const EFM_FWMC_PEMOD_POS: u32 = 0;
pub const EFM_FWMC_PEMOD: u32 = 7;
pub const EFM_FWMC_BUSHLDCTL_POS: u32 = 8;
pub const EFM_FWMC_BUSHLDCTL: u32 = 256;
pub const EFM_FWMC_KEY1LOCK_POS: u32 = 16;
pub const EFM_FWMC_KEY1LOCK: u32 = 65536;
pub const EFM_FWMC_KEY2LOCK_POS: u32 = 17;
pub const EFM_FWMC_KEY2LOCK: u32 = 131072;
pub const EFM_FSR_OTPWERR_POS: u32 = 0;
pub const EFM_FSR_OTPWERR: u32 = 1;
pub const EFM_FSR_PRTWERR_POS: u32 = 1;
pub const EFM_FSR_PRTWERR: u32 = 2;
pub const EFM_FSR_PGSZERR_POS: u32 = 2;
pub const EFM_FSR_PGSZERR: u32 = 4;
pub const EFM_FSR_MISMTCH_POS: u32 = 3;
pub const EFM_FSR_MISMTCH: u32 = 8;
pub const EFM_FSR_OPTEND_POS: u32 = 4;
pub const EFM_FSR_OPTEND: u32 = 16;
pub const EFM_FSR_COLERR_POS: u32 = 5;
pub const EFM_FSR_COLERR: u32 = 32;
pub const EFM_FSR_RDY_POS: u32 = 8;
pub const EFM_FSR_RDY: u32 = 256;
pub const EFM_FSCLR_OTPWERRCLR_POS: u32 = 0;
pub const EFM_FSCLR_OTPWERRCLR: u32 = 1;
pub const EFM_FSCLR_PRTWERRCLR_POS: u32 = 1;
pub const EFM_FSCLR_PRTWERRCLR: u32 = 2;
pub const EFM_FSCLR_PGSZERRCLR_POS: u32 = 2;
pub const EFM_FSCLR_PGSZERRCLR: u32 = 4;
pub const EFM_FSCLR_MISMTCHCLR_POS: u32 = 3;
pub const EFM_FSCLR_MISMTCHCLR: u32 = 8;
pub const EFM_FSCLR_OPTENDCLR_POS: u32 = 4;
pub const EFM_FSCLR_OPTENDCLR: u32 = 16;
pub const EFM_FSCLR_COLERRCLR_POS: u32 = 5;
pub const EFM_FSCLR_COLERRCLR: u32 = 32;
pub const EFM_FITE_PEERRITE_POS: u32 = 0;
pub const EFM_FITE_PEERRITE: u32 = 1;
pub const EFM_FITE_OPTENDITE_POS: u32 = 1;
pub const EFM_FITE_OPTENDITE: u32 = 2;
pub const EFM_FITE_COLERRITE_POS: u32 = 2;
pub const EFM_FITE_COLERRITE: u32 = 4;
pub const EFM_FSWP_FSWP: u32 = 1;
pub const EFM_CHIPID: u32 = 4294967295;
pub const EFM_UQID0_Y_LOCATION_POS: u32 = 0;
pub const EFM_UQID0_Y_LOCATION: u32 = 255;
pub const EFM_UQID0_X_LOCATION_POS: u32 = 8;
pub const EFM_UQID0_X_LOCATION: u32 = 65280;
pub const EFM_UQID0_WAFER_ID_POS: u32 = 16;
pub const EFM_UQID0_WAFER_ID: u32 = 16711680;
pub const EFM_UQID0_LOT_ID_POS: u32 = 24;
pub const EFM_UQID0_LOT_ID: u32 = 4278190080;
pub const EFM_UQID1_LOT_ID: u32 = 4294967295;
pub const EFM_UQID2_LOT_ID: u32 = 255;
pub const EFM_MMF_REMPRT_MMF_REMPRT: u32 = 65535;
pub const EFM_MMF_REMCR_RMSIZE_POS: u32 = 0;
pub const EFM_MMF_REMCR_RMSIZE: u32 = 31;
pub const EFM_MMF_REMCR_RMTADDR_POS: u32 = 12;
pub const EFM_MMF_REMCR_RMTADDR: u32 = 536866816;
pub const EFM_MMF_REMCR_EN_POS: u32 = 31;
pub const EFM_MMF_REMCR_EN: u32 = 2147483648;
pub const EFM_WLOCK_WLOCK0: u32 = 1;
pub const EFM_F0NWPRT_F0NWPRT0_POS: u32 = 0;
pub const EFM_F0NWPRT_F0NWPRT0: u32 = 1;
pub const EFM_F0NWPRT_F0NWPRT1_POS: u32 = 1;
pub const EFM_F0NWPRT_F0NWPRT1: u32 = 2;
pub const EFM_F0NWPRT_F0NWPRT2_POS: u32 = 2;
pub const EFM_F0NWPRT_F0NWPRT2: u32 = 4;
pub const EFM_F0NWPRT_F0NWPRT3_POS: u32 = 3;
pub const EFM_F0NWPRT_F0NWPRT3: u32 = 8;
pub const EFM_F0NWPRT_F0NWPRT4_POS: u32 = 4;
pub const EFM_F0NWPRT_F0NWPRT4: u32 = 16;
pub const EFM_F0NWPRT_F0NWPRT5_POS: u32 = 5;
pub const EFM_F0NWPRT_F0NWPRT5: u32 = 32;
pub const EFM_F0NWPRT_F0NWPRT6_POS: u32 = 6;
pub const EFM_F0NWPRT_F0NWPRT6: u32 = 64;
pub const EFM_F0NWPRT_F0NWPRT7_POS: u32 = 7;
pub const EFM_F0NWPRT_F0NWPRT7: u32 = 128;
pub const EFM_F0NWPRT_F0NWPRT8_POS: u32 = 8;
pub const EFM_F0NWPRT_F0NWPRT8: u32 = 256;
pub const EFM_F0NWPRT_F0NWPRT9_POS: u32 = 9;
pub const EFM_F0NWPRT_F0NWPRT9: u32 = 512;
pub const EFM_F0NWPRT_F0NWPRT10_POS: u32 = 10;
pub const EFM_F0NWPRT_F0NWPRT10: u32 = 1024;
pub const EFM_F0NWPRT_F0NWPRT11_POS: u32 = 11;
pub const EFM_F0NWPRT_F0NWPRT11: u32 = 2048;
pub const EFM_F0NWPRT_F0NWPRT12_POS: u32 = 12;
pub const EFM_F0NWPRT_F0NWPRT12: u32 = 4096;
pub const EFM_F0NWPRT_F0NWPRT13_POS: u32 = 13;
pub const EFM_F0NWPRT_F0NWPRT13: u32 = 8192;
pub const EFM_F0NWPRT_F0NWPRT14_POS: u32 = 14;
pub const EFM_F0NWPRT_F0NWPRT14: u32 = 16384;
pub const EFM_F0NWPRT_F0NWPRT15_POS: u32 = 15;
pub const EFM_F0NWPRT_F0NWPRT15: u32 = 32768;
pub const EFM_F0NWPRT_F0NWPRT16_POS: u32 = 16;
pub const EFM_F0NWPRT_F0NWPRT16: u32 = 65536;
pub const EFM_F0NWPRT_F0NWPRT17_POS: u32 = 17;
pub const EFM_F0NWPRT_F0NWPRT17: u32 = 131072;
pub const EFM_F0NWPRT_F0NWPRT18_POS: u32 = 18;
pub const EFM_F0NWPRT_F0NWPRT18: u32 = 262144;
pub const EFM_F0NWPRT_F0NWPRT19_POS: u32 = 19;
pub const EFM_F0NWPRT_F0NWPRT19: u32 = 524288;
pub const EFM_F0NWPRT_F0NWPRT20_POS: u32 = 20;
pub const EFM_F0NWPRT_F0NWPRT20: u32 = 1048576;
pub const EFM_F0NWPRT_F0NWPRT21_POS: u32 = 21;
pub const EFM_F0NWPRT_F0NWPRT21: u32 = 2097152;
pub const EFM_F0NWPRT_F0NWPRT22_POS: u32 = 22;
pub const EFM_F0NWPRT_F0NWPRT22: u32 = 4194304;
pub const EFM_F0NWPRT_F0NWPRT23_POS: u32 = 23;
pub const EFM_F0NWPRT_F0NWPRT23: u32 = 8388608;
pub const EFM_F0NWPRT_F0NWPRT24_POS: u32 = 24;
pub const EFM_F0NWPRT_F0NWPRT24: u32 = 16777216;
pub const EFM_F0NWPRT_F0NWPRT25_POS: u32 = 25;
pub const EFM_F0NWPRT_F0NWPRT25: u32 = 33554432;
pub const EFM_F0NWPRT_F0NWPRT26_POS: u32 = 26;
pub const EFM_F0NWPRT_F0NWPRT26: u32 = 67108864;
pub const EFM_F0NWPRT_F0NWPRT27_POS: u32 = 27;
pub const EFM_F0NWPRT_F0NWPRT27: u32 = 134217728;
pub const EFM_F0NWPRT_F0NWPRT28_POS: u32 = 28;
pub const EFM_F0NWPRT_F0NWPRT28: u32 = 268435456;
pub const EFM_F0NWPRT_F0NWPRT29_POS: u32 = 29;
pub const EFM_F0NWPRT_F0NWPRT29: u32 = 536870912;
pub const EFM_F0NWPRT_F0NWPRT30_POS: u32 = 30;
pub const EFM_F0NWPRT_F0NWPRT30: u32 = 1073741824;
pub const EFM_F0NWPRT_F0NWPRT31_POS: u32 = 31;
pub const EFM_F0NWPRT_F0NWPRT31: u32 = 2147483648;
pub const EMB_CTL1_CMPEN1_POS: u32 = 0;
pub const EMB_CTL1_CMPEN1: u32 = 1;
pub const EMB_CTL1_CMPEN2_POS: u32 = 1;
pub const EMB_CTL1_CMPEN2: u32 = 2;
pub const EMB_CTL1_CMPEN3_POS: u32 = 2;
pub const EMB_CTL1_CMPEN3: u32 = 4;
pub const EMB_CTL1_CMPEN4_POS: u32 = 3;
pub const EMB_CTL1_CMPEN4: u32 = 8;
pub const EMB_CTL1_SYSEN_POS: u32 = 4;
pub const EMB_CTL1_SYSEN: u32 = 16;
pub const EMB_CTL1_PWMSEN0_POS: u32 = 5;
pub const EMB_CTL1_PWMSEN0: u32 = 32;
pub const EMB_CTL1_PWMSEN1_POS: u32 = 6;
pub const EMB_CTL1_PWMSEN1: u32 = 64;
pub const EMB_CTL1_PWMSEN2_POS: u32 = 7;
pub const EMB_CTL1_PWMSEN2: u32 = 128;
pub const EMB_CTL1_PWMSEN3_POS: u32 = 8;
pub const EMB_CTL1_PWMSEN3: u32 = 256;
pub const EMB_CTL1_PORTINEN1_POS: u32 = 16;
pub const EMB_CTL1_PORTINEN1: u32 = 65536;
pub const EMB_CTL1_PORTINEN2_POS: u32 = 17;
pub const EMB_CTL1_PORTINEN2: u32 = 131072;
pub const EMB_CTL1_PORTINEN3_POS: u32 = 18;
pub const EMB_CTL1_PORTINEN3: u32 = 262144;
pub const EMB_CTL1_PORTINEN4_POS: u32 = 19;
pub const EMB_CTL1_PORTINEN4: u32 = 524288;
pub const EMB_CTL1_INVSEL1_POS: u32 = 22;
pub const EMB_CTL1_INVSEL1: u32 = 4194304;
pub const EMB_CTL1_INVSEL2_POS: u32 = 23;
pub const EMB_CTL1_INVSEL2: u32 = 8388608;
pub const EMB_CTL1_INVSEL3_POS: u32 = 24;
pub const EMB_CTL1_INVSEL3: u32 = 16777216;
pub const EMB_CTL1_INVSEL4_POS: u32 = 25;
pub const EMB_CTL1_INVSEL4: u32 = 33554432;
pub const EMB_CTL1_OSCSTPEN_POS: u32 = 27;
pub const EMB_CTL1_OSCSTPEN: u32 = 134217728;
pub const EMB_CTL1_SRAMECCERREN_POS: u32 = 28;
pub const EMB_CTL1_SRAMECCERREN: u32 = 268435456;
pub const EMB_CTL1_SRAMPYERREN_POS: u32 = 29;
pub const EMB_CTL1_SRAMPYERREN: u32 = 536870912;
pub const EMB_CTL1_LOCKUPEN_POS: u32 = 30;
pub const EMB_CTL1_LOCKUPEN: u32 = 1073741824;
pub const EMB_CTL1_PVDEN_POS: u32 = 31;
pub const EMB_CTL1_PVDEN: u32 = 2147483648;
pub const EMB_CTL2_PWMLV0_POS: u32 = 0;
pub const EMB_CTL2_PWMLV0: u32 = 1;
pub const EMB_CTL2_PWMLV1_POS: u32 = 1;
pub const EMB_CTL2_PWMLV1: u32 = 2;
pub const EMB_CTL2_PWMLV2_POS: u32 = 2;
pub const EMB_CTL2_PWMLV2: u32 = 4;
pub const EMB_CTL2_PWMLV3_POS: u32 = 3;
pub const EMB_CTL2_PWMLV3: u32 = 8;
pub const EMB_CTL2_NFSEL1_POS: u32 = 16;
pub const EMB_CTL2_NFSEL1: u32 = 196608;
pub const EMB_CTL2_NFEN1_POS: u32 = 18;
pub const EMB_CTL2_NFEN1: u32 = 262144;
pub const EMB_CTL2_NFSEL2_POS: u32 = 19;
pub const EMB_CTL2_NFSEL2: u32 = 1572864;
pub const EMB_CTL2_NFEN2_POS: u32 = 21;
pub const EMB_CTL2_NFEN2: u32 = 2097152;
pub const EMB_CTL2_NFSEL3_POS: u32 = 22;
pub const EMB_CTL2_NFSEL3: u32 = 12582912;
pub const EMB_CTL2_NFEN3_POS: u32 = 24;
pub const EMB_CTL2_NFEN3: u32 = 16777216;
pub const EMB_CTL2_NFSEL4_POS: u32 = 25;
pub const EMB_CTL2_NFSEL4: u32 = 100663296;
pub const EMB_CTL2_NFEN4_POS: u32 = 27;
pub const EMB_CTL2_NFEN4: u32 = 134217728;
pub const EMB_SOE_SOE: u32 = 1;
pub const EMB_STAT_PWMSF_POS: u32 = 1;
pub const EMB_STAT_PWMSF: u32 = 2;
pub const EMB_STAT_CMPF_POS: u32 = 2;
pub const EMB_STAT_CMPF: u32 = 4;
pub const EMB_STAT_SYSF_POS: u32 = 3;
pub const EMB_STAT_SYSF: u32 = 8;
pub const EMB_STAT_PWMST_POS: u32 = 5;
pub const EMB_STAT_PWMST: u32 = 32;
pub const EMB_STAT_CMPST_POS: u32 = 6;
pub const EMB_STAT_CMPST: u32 = 64;
pub const EMB_STAT_SYSST_POS: u32 = 7;
pub const EMB_STAT_SYSST: u32 = 128;
pub const EMB_STAT_PORTINF1_POS: u32 = 8;
pub const EMB_STAT_PORTINF1: u32 = 256;
pub const EMB_STAT_PORTINF2_POS: u32 = 9;
pub const EMB_STAT_PORTINF2: u32 = 512;
pub const EMB_STAT_PORTINF3_POS: u32 = 10;
pub const EMB_STAT_PORTINF3: u32 = 1024;
pub const EMB_STAT_PORTINF4_POS: u32 = 11;
pub const EMB_STAT_PORTINF4: u32 = 2048;
pub const EMB_STAT_PORTINST1_POS: u32 = 14;
pub const EMB_STAT_PORTINST1: u32 = 16384;
pub const EMB_STAT_PORTINST2_POS: u32 = 15;
pub const EMB_STAT_PORTINST2: u32 = 32768;
pub const EMB_STAT_PORTINST3_POS: u32 = 16;
pub const EMB_STAT_PORTINST3: u32 = 65536;
pub const EMB_STAT_PORTINST4_POS: u32 = 17;
pub const EMB_STAT_PORTINST4: u32 = 131072;
pub const EMB_STATCLR_PWMSFCLR_POS: u32 = 1;
pub const EMB_STATCLR_PWMSFCLR: u32 = 2;
pub const EMB_STATCLR_CMPFCLR_POS: u32 = 2;
pub const EMB_STATCLR_CMPFCLR: u32 = 4;
pub const EMB_STATCLR_SYSFCLR_POS: u32 = 3;
pub const EMB_STATCLR_SYSFCLR: u32 = 8;
pub const EMB_STATCLR_PORTINFCLR1_POS: u32 = 8;
pub const EMB_STATCLR_PORTINFCLR1: u32 = 256;
pub const EMB_STATCLR_PORTINFCLR2_POS: u32 = 9;
pub const EMB_STATCLR_PORTINFCLR2: u32 = 512;
pub const EMB_STATCLR_PORTINFCLR3_POS: u32 = 10;
pub const EMB_STATCLR_PORTINFCLR3: u32 = 1024;
pub const EMB_STATCLR_PORTINFCLR4_POS: u32 = 11;
pub const EMB_STATCLR_PORTINFCLR4: u32 = 2048;
pub const EMB_INTEN_PWMSINTEN_POS: u32 = 1;
pub const EMB_INTEN_PWMSINTEN: u32 = 2;
pub const EMB_INTEN_CMPINTEN_POS: u32 = 2;
pub const EMB_INTEN_CMPINTEN: u32 = 4;
pub const EMB_INTEN_SYSINTEN_POS: u32 = 3;
pub const EMB_INTEN_SYSINTEN: u32 = 8;
pub const EMB_INTEN_PORTININTEN1_POS: u32 = 8;
pub const EMB_INTEN_PORTININTEN1: u32 = 256;
pub const EMB_INTEN_PORTININTEN2_POS: u32 = 9;
pub const EMB_INTEN_PORTININTEN2: u32 = 512;
pub const EMB_INTEN_PORTININTEN3_POS: u32 = 10;
pub const EMB_INTEN_PORTININTEN3: u32 = 1024;
pub const EMB_INTEN_PORTININTEN4_POS: u32 = 11;
pub const EMB_INTEN_PORTININTEN4: u32 = 2048;
pub const EMB_RLSSEL_PWMRSEL_POS: u32 = 1;
pub const EMB_RLSSEL_PWMRSEL: u32 = 2;
pub const EMB_RLSSEL_CMPRSEL_POS: u32 = 2;
pub const EMB_RLSSEL_CMPRSEL: u32 = 4;
pub const EMB_RLSSEL_SYSRSEL_POS: u32 = 3;
pub const EMB_RLSSEL_SYSRSEL: u32 = 8;
pub const EMB_RLSSEL_PORTINRSEL1_POS: u32 = 8;
pub const EMB_RLSSEL_PORTINRSEL1: u32 = 256;
pub const EMB_RLSSEL_PORTINRSEL2_POS: u32 = 9;
pub const EMB_RLSSEL_PORTINRSEL2: u32 = 512;
pub const EMB_RLSSEL_PORTINRSEL3_POS: u32 = 10;
pub const EMB_RLSSEL_PORTINRSEL3: u32 = 1024;
pub const EMB_RLSSEL_PORTINRSEL4_POS: u32 = 11;
pub const EMB_RLSSEL_PORTINRSEL4: u32 = 2048;
pub const FCM_LVR_LVR: u32 = 65535;
pub const FCM_UVR_UVR: u32 = 65535;
pub const FCM_CNTR_CNTR: u32 = 65535;
pub const FCM_STR_START: u32 = 1;
pub const FCM_MCCR_MDIVS_POS: u32 = 0;
pub const FCM_MCCR_MDIVS: u32 = 3;
pub const FCM_MCCR_MDIVS_0: u32 = 1;
pub const FCM_MCCR_MDIVS_1: u32 = 2;
pub const FCM_MCCR_MCKS_POS: u32 = 4;
pub const FCM_MCCR_MCKS: u32 = 240;
pub const FCM_RCCR_RDIVS_POS: u32 = 0;
pub const FCM_RCCR_RDIVS: u32 = 3;
pub const FCM_RCCR_RDIVS_0: u32 = 1;
pub const FCM_RCCR_RDIVS_1: u32 = 2;
pub const FCM_RCCR_RCKS_POS: u32 = 3;
pub const FCM_RCCR_RCKS: u32 = 120;
pub const FCM_RCCR_INEXS_POS: u32 = 7;
pub const FCM_RCCR_INEXS: u32 = 128;
pub const FCM_RCCR_DNFS_POS: u32 = 8;
pub const FCM_RCCR_DNFS: u32 = 768;
pub const FCM_RCCR_DNFS_0: u32 = 256;
pub const FCM_RCCR_DNFS_1: u32 = 512;
pub const FCM_RCCR_EDGES_POS: u32 = 12;
pub const FCM_RCCR_EDGES: u32 = 12288;
pub const FCM_RCCR_EDGES_0: u32 = 4096;
pub const FCM_RCCR_EDGES_1: u32 = 8192;
pub const FCM_RCCR_EXREFE_POS: u32 = 15;
pub const FCM_RCCR_EXREFE: u32 = 32768;
pub const FCM_RIER_ERRIE_POS: u32 = 0;
pub const FCM_RIER_ERRIE: u32 = 1;
pub const FCM_RIER_MENDIE_POS: u32 = 1;
pub const FCM_RIER_MENDIE: u32 = 2;
pub const FCM_RIER_OVFIE_POS: u32 = 2;
pub const FCM_RIER_OVFIE: u32 = 4;
pub const FCM_RIER_ERRINTRS_POS: u32 = 4;
pub const FCM_RIER_ERRINTRS: u32 = 16;
pub const FCM_RIER_ERRE_POS: u32 = 7;
pub const FCM_RIER_ERRE: u32 = 128;
pub const FCM_SR_ERRF_POS: u32 = 0;
pub const FCM_SR_ERRF: u32 = 1;
pub const FCM_SR_MENDF_POS: u32 = 1;
pub const FCM_SR_MENDF: u32 = 2;
pub const FCM_SR_OVF_POS: u32 = 2;
pub const FCM_SR_OVF: u32 = 4;
pub const FCM_CLR_ERRFCLR_POS: u32 = 0;
pub const FCM_CLR_ERRFCLR: u32 = 1;
pub const FCM_CLR_MENDFCLR_POS: u32 = 1;
pub const FCM_CLR_MENDFCLR: u32 = 2;
pub const FCM_CLR_OVFCLR_POS: u32 = 2;
pub const FCM_CLR_OVFCLR: u32 = 4;
pub const GPIO_PIDR_PIN00_POS: u32 = 0;
pub const GPIO_PIDR_PIN00: u32 = 1;
pub const GPIO_PIDR_PIN01_POS: u32 = 1;
pub const GPIO_PIDR_PIN01: u32 = 2;
pub const GPIO_PIDR_PIN02_POS: u32 = 2;
pub const GPIO_PIDR_PIN02: u32 = 4;
pub const GPIO_PIDR_PIN03_POS: u32 = 3;
pub const GPIO_PIDR_PIN03: u32 = 8;
pub const GPIO_PIDR_PIN04_POS: u32 = 4;
pub const GPIO_PIDR_PIN04: u32 = 16;
pub const GPIO_PIDR_PIN05_POS: u32 = 5;
pub const GPIO_PIDR_PIN05: u32 = 32;
pub const GPIO_PIDR_PIN06_POS: u32 = 6;
pub const GPIO_PIDR_PIN06: u32 = 64;
pub const GPIO_PIDR_PIN07_POS: u32 = 7;
pub const GPIO_PIDR_PIN07: u32 = 128;
pub const GPIO_PIDR_PIN08_POS: u32 = 8;
pub const GPIO_PIDR_PIN08: u32 = 256;
pub const GPIO_PIDR_PIN09_POS: u32 = 9;
pub const GPIO_PIDR_PIN09: u32 = 512;
pub const GPIO_PIDR_PIN10_POS: u32 = 10;
pub const GPIO_PIDR_PIN10: u32 = 1024;
pub const GPIO_PIDR_PIN11_POS: u32 = 11;
pub const GPIO_PIDR_PIN11: u32 = 2048;
pub const GPIO_PIDR_PIN12_POS: u32 = 12;
pub const GPIO_PIDR_PIN12: u32 = 4096;
pub const GPIO_PIDR_PIN13_POS: u32 = 13;
pub const GPIO_PIDR_PIN13: u32 = 8192;
pub const GPIO_PIDR_PIN14_POS: u32 = 14;
pub const GPIO_PIDR_PIN14: u32 = 16384;
pub const GPIO_PIDR_PIN15_POS: u32 = 15;
pub const GPIO_PIDR_PIN15: u32 = 32768;
pub const GPIO_PODR_POUT00_POS: u32 = 0;
pub const GPIO_PODR_POUT00: u32 = 1;
pub const GPIO_PODR_POUT01_POS: u32 = 1;
pub const GPIO_PODR_POUT01: u32 = 2;
pub const GPIO_PODR_POUT02_POS: u32 = 2;
pub const GPIO_PODR_POUT02: u32 = 4;
pub const GPIO_PODR_POUT03_POS: u32 = 3;
pub const GPIO_PODR_POUT03: u32 = 8;
pub const GPIO_PODR_POUT04_POS: u32 = 4;
pub const GPIO_PODR_POUT04: u32 = 16;
pub const GPIO_PODR_POUT05_POS: u32 = 5;
pub const GPIO_PODR_POUT05: u32 = 32;
pub const GPIO_PODR_POUT06_POS: u32 = 6;
pub const GPIO_PODR_POUT06: u32 = 64;
pub const GPIO_PODR_POUT07_POS: u32 = 7;
pub const GPIO_PODR_POUT07: u32 = 128;
pub const GPIO_PODR_POUT08_POS: u32 = 8;
pub const GPIO_PODR_POUT08: u32 = 256;
pub const GPIO_PODR_POUT09_POS: u32 = 9;
pub const GPIO_PODR_POUT09: u32 = 512;
pub const GPIO_PODR_POUT10_POS: u32 = 10;
pub const GPIO_PODR_POUT10: u32 = 1024;
pub const GPIO_PODR_POUT11_POS: u32 = 11;
pub const GPIO_PODR_POUT11: u32 = 2048;
pub const GPIO_PODR_POUT12_POS: u32 = 12;
pub const GPIO_PODR_POUT12: u32 = 4096;
pub const GPIO_PODR_POUT13_POS: u32 = 13;
pub const GPIO_PODR_POUT13: u32 = 8192;
pub const GPIO_PODR_POUT14_POS: u32 = 14;
pub const GPIO_PODR_POUT14: u32 = 16384;
pub const GPIO_PODR_POUT15_POS: u32 = 15;
pub const GPIO_PODR_POUT15: u32 = 32768;
pub const GPIO_POER_POUTE00_POS: u32 = 0;
pub const GPIO_POER_POUTE00: u32 = 1;
pub const GPIO_POER_POUTE01_POS: u32 = 1;
pub const GPIO_POER_POUTE01: u32 = 2;
pub const GPIO_POER_POUTE02_POS: u32 = 2;
pub const GPIO_POER_POUTE02: u32 = 4;
pub const GPIO_POER_POUTE03_POS: u32 = 3;
pub const GPIO_POER_POUTE03: u32 = 8;
pub const GPIO_POER_POUTE04_POS: u32 = 4;
pub const GPIO_POER_POUTE04: u32 = 16;
pub const GPIO_POER_POUTE05_POS: u32 = 5;
pub const GPIO_POER_POUTE05: u32 = 32;
pub const GPIO_POER_POUTE06_POS: u32 = 6;
pub const GPIO_POER_POUTE06: u32 = 64;
pub const GPIO_POER_POUTE07_POS: u32 = 7;
pub const GPIO_POER_POUTE07: u32 = 128;
pub const GPIO_POER_POUTE08_POS: u32 = 8;
pub const GPIO_POER_POUTE08: u32 = 256;
pub const GPIO_POER_POUTE09_POS: u32 = 9;
pub const GPIO_POER_POUTE09: u32 = 512;
pub const GPIO_POER_POUTE10_POS: u32 = 10;
pub const GPIO_POER_POUTE10: u32 = 1024;
pub const GPIO_POER_POUTE11_POS: u32 = 11;
pub const GPIO_POER_POUTE11: u32 = 2048;
pub const GPIO_POER_POUTE12_POS: u32 = 12;
pub const GPIO_POER_POUTE12: u32 = 4096;
pub const GPIO_POER_POUTE13_POS: u32 = 13;
pub const GPIO_POER_POUTE13: u32 = 8192;
pub const GPIO_POER_POUTE14_POS: u32 = 14;
pub const GPIO_POER_POUTE14: u32 = 16384;
pub const GPIO_POER_POUTE15_POS: u32 = 15;
pub const GPIO_POER_POUTE15: u32 = 32768;
pub const GPIO_POSR_POS00_POS: u32 = 0;
pub const GPIO_POSR_POS00: u32 = 1;
pub const GPIO_POSR_POS01_POS: u32 = 1;
pub const GPIO_POSR_POS01: u32 = 2;
pub const GPIO_POSR_POS02_POS: u32 = 2;
pub const GPIO_POSR_POS02: u32 = 4;
pub const GPIO_POSR_POS03_POS: u32 = 3;
pub const GPIO_POSR_POS03: u32 = 8;
pub const GPIO_POSR_POS04_POS: u32 = 4;
pub const GPIO_POSR_POS04: u32 = 16;
pub const GPIO_POSR_POS05_POS: u32 = 5;
pub const GPIO_POSR_POS05: u32 = 32;
pub const GPIO_POSR_POS06_POS: u32 = 6;
pub const GPIO_POSR_POS06: u32 = 64;
pub const GPIO_POSR_POS07_POS: u32 = 7;
pub const GPIO_POSR_POS07: u32 = 128;
pub const GPIO_POSR_POS08_POS: u32 = 8;
pub const GPIO_POSR_POS08: u32 = 256;
pub const GPIO_POSR_POS09_POS: u32 = 9;
pub const GPIO_POSR_POS09: u32 = 512;
pub const GPIO_POSR_POS10_POS: u32 = 10;
pub const GPIO_POSR_POS10: u32 = 1024;
pub const GPIO_POSR_POS11_POS: u32 = 11;
pub const GPIO_POSR_POS11: u32 = 2048;
pub const GPIO_POSR_POS12_POS: u32 = 12;
pub const GPIO_POSR_POS12: u32 = 4096;
pub const GPIO_POSR_POS13_POS: u32 = 13;
pub const GPIO_POSR_POS13: u32 = 8192;
pub const GPIO_POSR_POS14_POS: u32 = 14;
pub const GPIO_POSR_POS14: u32 = 16384;
pub const GPIO_POSR_POS15_POS: u32 = 15;
pub const GPIO_POSR_POS15: u32 = 32768;
pub const GPIO_PORR_POR00_POS: u32 = 0;
pub const GPIO_PORR_POR00: u32 = 1;
pub const GPIO_PORR_POR01_POS: u32 = 1;
pub const GPIO_PORR_POR01: u32 = 2;
pub const GPIO_PORR_POR02_POS: u32 = 2;
pub const GPIO_PORR_POR02: u32 = 4;
pub const GPIO_PORR_POR03_POS: u32 = 3;
pub const GPIO_PORR_POR03: u32 = 8;
pub const GPIO_PORR_POR04_POS: u32 = 4;
pub const GPIO_PORR_POR04: u32 = 16;
pub const GPIO_PORR_POR05_POS: u32 = 5;
pub const GPIO_PORR_POR05: u32 = 32;
pub const GPIO_PORR_POR06_POS: u32 = 6;
pub const GPIO_PORR_POR06: u32 = 64;
pub const GPIO_PORR_POR07_POS: u32 = 7;
pub const GPIO_PORR_POR07: u32 = 128;
pub const GPIO_PORR_POR08_POS: u32 = 8;
pub const GPIO_PORR_POR08: u32 = 256;
pub const GPIO_PORR_POR09_POS: u32 = 9;
pub const GPIO_PORR_POR09: u32 = 512;
pub const GPIO_PORR_POR10_POS: u32 = 10;
pub const GPIO_PORR_POR10: u32 = 1024;
pub const GPIO_PORR_POR11_POS: u32 = 11;
pub const GPIO_PORR_POR11: u32 = 2048;
pub const GPIO_PORR_POR12_POS: u32 = 12;
pub const GPIO_PORR_POR12: u32 = 4096;
pub const GPIO_PORR_POR13_POS: u32 = 13;
pub const GPIO_PORR_POR13: u32 = 8192;
pub const GPIO_PORR_POR14_POS: u32 = 14;
pub const GPIO_PORR_POR14: u32 = 16384;
pub const GPIO_PORR_POR15_POS: u32 = 15;
pub const GPIO_PORR_POR15: u32 = 32768;
pub const GPIO_POTR_POT00_POS: u32 = 0;
pub const GPIO_POTR_POT00: u32 = 1;
pub const GPIO_POTR_POT01_POS: u32 = 1;
pub const GPIO_POTR_POT01: u32 = 2;
pub const GPIO_POTR_POT02_POS: u32 = 2;
pub const GPIO_POTR_POT02: u32 = 4;
pub const GPIO_POTR_POT03_POS: u32 = 3;
pub const GPIO_POTR_POT03: u32 = 8;
pub const GPIO_POTR_POT04_POS: u32 = 4;
pub const GPIO_POTR_POT04: u32 = 16;
pub const GPIO_POTR_POT05_POS: u32 = 5;
pub const GPIO_POTR_POT05: u32 = 32;
pub const GPIO_POTR_POT06_POS: u32 = 6;
pub const GPIO_POTR_POT06: u32 = 64;
pub const GPIO_POTR_POT07_POS: u32 = 7;
pub const GPIO_POTR_POT07: u32 = 128;
pub const GPIO_POTR_POT08_POS: u32 = 8;
pub const GPIO_POTR_POT08: u32 = 256;
pub const GPIO_POTR_POT09_POS: u32 = 9;
pub const GPIO_POTR_POT09: u32 = 512;
pub const GPIO_POTR_POT10_POS: u32 = 10;
pub const GPIO_POTR_POT10: u32 = 1024;
pub const GPIO_POTR_POT11_POS: u32 = 11;
pub const GPIO_POTR_POT11: u32 = 2048;
pub const GPIO_POTR_POT12_POS: u32 = 12;
pub const GPIO_POTR_POT12: u32 = 4096;
pub const GPIO_POTR_POT13_POS: u32 = 13;
pub const GPIO_POTR_POT13: u32 = 8192;
pub const GPIO_POTR_POT14_POS: u32 = 14;
pub const GPIO_POTR_POT14: u32 = 16384;
pub const GPIO_POTR_POT15_POS: u32 = 15;
pub const GPIO_POTR_POT15: u32 = 32768;
pub const GPIO_PSPCR_SPFE: u32 = 31;
pub const GPIO_PCCR_BFSEL_POS: u32 = 0;
pub const GPIO_PCCR_BFSEL: u32 = 63;
pub const GPIO_PCCR_RDWT_POS: u32 = 12;
pub const GPIO_PCCR_RDWT: u32 = 28672;
pub const GPIO_PWPR_WE_POS: u32 = 0;
pub const GPIO_PWPR_WE: u32 = 1;
pub const GPIO_PWPR_WP_POS: u32 = 8;
pub const GPIO_PWPR_WP: u32 = 65280;
pub const GPIO_PCR_POUT_POS: u32 = 0;
pub const GPIO_PCR_POUT: u32 = 1;
pub const GPIO_PCR_POUTE_POS: u32 = 1;
pub const GPIO_PCR_POUTE: u32 = 2;
pub const GPIO_PCR_NOD_POS: u32 = 2;
pub const GPIO_PCR_NOD: u32 = 4;
pub const GPIO_PCR_DRV_POS: u32 = 4;
pub const GPIO_PCR_DRV: u32 = 48;
pub const GPIO_PCR_DRV_0: u32 = 16;
pub const GPIO_PCR_DRV_1: u32 = 32;
pub const GPIO_PCR_PUU_POS: u32 = 6;
pub const GPIO_PCR_PUU: u32 = 64;
pub const GPIO_PCR_PUD_POS: u32 = 7;
pub const GPIO_PCR_PUD: u32 = 128;
pub const GPIO_PCR_PIN_POS: u32 = 8;
pub const GPIO_PCR_PIN: u32 = 256;
pub const GPIO_PCR_INVE_POS: u32 = 9;
pub const GPIO_PCR_INVE: u32 = 512;
pub const GPIO_PCR_CINSEL_POS: u32 = 10;
pub const GPIO_PCR_CINSEL: u32 = 1024;
pub const GPIO_PCR_INTE_POS: u32 = 12;
pub const GPIO_PCR_INTE: u32 = 4096;
pub const GPIO_PCR_PINAE_POS: u32 = 13;
pub const GPIO_PCR_PINAE: u32 = 8192;
pub const GPIO_PCR_LTE_POS: u32 = 14;
pub const GPIO_PCR_LTE: u32 = 16384;
pub const GPIO_PCR_DDIS_POS: u32 = 15;
pub const GPIO_PCR_DDIS: u32 = 32768;
pub const GPIO_PFSR_FSEL_POS: u32 = 0;
pub const GPIO_PFSR_FSEL: u32 = 63;
pub const GPIO_PFSR_BFE_POS: u32 = 8;
pub const GPIO_PFSR_BFE: u32 = 256;
pub const HASH_CR_START_POS: u32 = 0;
pub const HASH_CR_START: u32 = 1;
pub const HASH_CR_FST_GRP_POS: u32 = 1;
pub const HASH_CR_FST_GRP: u32 = 2;
pub const HASH_HR7: u32 = 4294967295;
pub const HASH_HR6: u32 = 4294967295;
pub const HASH_HR5: u32 = 4294967295;
pub const HASH_HR4: u32 = 4294967295;
pub const HASH_HR3: u32 = 4294967295;
pub const HASH_HR2: u32 = 4294967295;
pub const HASH_HR1: u32 = 4294967295;
pub const HASH_HR0: u32 = 4294967295;
pub const HASH_DR15: u32 = 4294967295;
pub const HASH_DR14: u32 = 4294967295;
pub const HASH_DR13: u32 = 4294967295;
pub const HASH_DR12: u32 = 4294967295;
pub const HASH_DR11: u32 = 4294967295;
pub const HASH_DR10: u32 = 4294967295;
pub const HASH_DR9: u32 = 4294967295;
pub const HASH_DR8: u32 = 4294967295;
pub const HASH_DR7: u32 = 4294967295;
pub const HASH_DR6: u32 = 4294967295;
pub const HASH_DR5: u32 = 4294967295;
pub const HASH_DR4: u32 = 4294967295;
pub const HASH_DR3: u32 = 4294967295;
pub const HASH_DR2: u32 = 4294967295;
pub const HASH_DR1: u32 = 4294967295;
pub const HASH_DR0: u32 = 4294967295;
pub const I2C_CR1_PE_POS: u32 = 0;
pub const I2C_CR1_PE: u32 = 1;
pub const I2C_CR1_SMBUS_POS: u32 = 1;
pub const I2C_CR1_SMBUS: u32 = 2;
pub const I2C_CR1_SMBALRTEN_POS: u32 = 2;
pub const I2C_CR1_SMBALRTEN: u32 = 4;
pub const I2C_CR1_SMBDEFAULTEN_POS: u32 = 3;
pub const I2C_CR1_SMBDEFAULTEN: u32 = 8;
pub const I2C_CR1_SMBHOSTEN_POS: u32 = 4;
pub const I2C_CR1_SMBHOSTEN: u32 = 16;
pub const I2C_CR1_GCEN_POS: u32 = 6;
pub const I2C_CR1_GCEN: u32 = 64;
pub const I2C_CR1_RESTART_POS: u32 = 7;
pub const I2C_CR1_RESTART: u32 = 128;
pub const I2C_CR1_START_POS: u32 = 8;
pub const I2C_CR1_START: u32 = 256;
pub const I2C_CR1_STOP_POS: u32 = 9;
pub const I2C_CR1_STOP: u32 = 512;
pub const I2C_CR1_ACK_POS: u32 = 10;
pub const I2C_CR1_ACK: u32 = 1024;
pub const I2C_CR1_SWRST_POS: u32 = 15;
pub const I2C_CR1_SWRST: u32 = 32768;
pub const I2C_CR2_STARTIE_POS: u32 = 0;
pub const I2C_CR2_STARTIE: u32 = 1;
pub const I2C_CR2_SLADDR0IE_POS: u32 = 1;
pub const I2C_CR2_SLADDR0IE: u32 = 2;
pub const I2C_CR2_SLADDR1IE_POS: u32 = 2;
pub const I2C_CR2_SLADDR1IE: u32 = 4;
pub const I2C_CR2_TENDIE_POS: u32 = 3;
pub const I2C_CR2_TENDIE: u32 = 8;
pub const I2C_CR2_STOPIE_POS: u32 = 4;
pub const I2C_CR2_STOPIE: u32 = 16;
pub const I2C_CR2_RFULLIE_POS: u32 = 6;
pub const I2C_CR2_RFULLIE: u32 = 64;
pub const I2C_CR2_TEMPTYIE_POS: u32 = 7;
pub const I2C_CR2_TEMPTYIE: u32 = 128;
pub const I2C_CR2_ARLOIE_POS: u32 = 9;
pub const I2C_CR2_ARLOIE: u32 = 512;
pub const I2C_CR2_RFREQIE_POS: u32 = 11;
pub const I2C_CR2_RFREQIE: u32 = 2048;
pub const I2C_CR2_NACKIE_POS: u32 = 12;
pub const I2C_CR2_NACKIE: u32 = 4096;
pub const I2C_CR2_TMOUTIE_POS: u32 = 14;
pub const I2C_CR2_TMOUTIE: u32 = 16384;
pub const I2C_CR2_GENCALLIE_POS: u32 = 20;
pub const I2C_CR2_GENCALLIE: u32 = 1048576;
pub const I2C_CR2_SMBDEFAULTIE_POS: u32 = 21;
pub const I2C_CR2_SMBDEFAULTIE: u32 = 2097152;
pub const I2C_CR2_SMBHOSTIE_POS: u32 = 22;
pub const I2C_CR2_SMBHOSTIE: u32 = 4194304;
pub const I2C_CR2_SMBALRTIE_POS: u32 = 23;
pub const I2C_CR2_SMBALRTIE: u32 = 8388608;
pub const I2C_CR3_TMOUTEN_POS: u32 = 0;
pub const I2C_CR3_TMOUTEN: u32 = 1;
pub const I2C_CR3_LTMOUT_POS: u32 = 1;
pub const I2C_CR3_LTMOUT: u32 = 2;
pub const I2C_CR3_HTMOUT_POS: u32 = 2;
pub const I2C_CR3_HTMOUT: u32 = 4;
pub const I2C_CR3_FACKEN_POS: u32 = 7;
pub const I2C_CR3_FACKEN: u32 = 128;
pub const I2C_CR4_BUSWAIT_POS: u32 = 10;
pub const I2C_CR4_BUSWAIT: u32 = 1024;
pub const I2C_CR4_BUSFREE_CLREN_POS: u32 = 12;
pub const I2C_CR4_BUSFREE_CLREN: u32 = 4096;
pub const I2C_CR4_SDADLY_POS: u32 = 16;
pub const I2C_CR4_SDADLY: u32 = 983040;
pub const I2C_SLR0_SLADDR0_POS: u32 = 0;
pub const I2C_SLR0_SLADDR0: u32 = 1023;
pub const I2C_SLR0_SLADDR0EN_POS: u32 = 12;
pub const I2C_SLR0_SLADDR0EN: u32 = 4096;
pub const I2C_SLR0_ADDRMOD0_POS: u32 = 15;
pub const I2C_SLR0_ADDRMOD0: u32 = 32768;
pub const I2C_SLR0_MSLADDR0_POS: u32 = 16;
pub const I2C_SLR0_MSLADDR0: u32 = 67043328;
pub const I2C_SLR0_MASK0EN_POS: u32 = 26;
pub const I2C_SLR0_MASK0EN: u32 = 67108864;
pub const I2C_SLR1_SLADDR1_POS: u32 = 0;
pub const I2C_SLR1_SLADDR1: u32 = 1023;
pub const I2C_SLR1_SLADDR1EN_POS: u32 = 12;
pub const I2C_SLR1_SLADDR1EN: u32 = 4096;
pub const I2C_SLR1_ADDRMOD1_POS: u32 = 15;
pub const I2C_SLR1_ADDRMOD1: u32 = 32768;
pub const I2C_SLR1_MSLADDR1_POS: u32 = 16;
pub const I2C_SLR1_MSLADDR1: u32 = 67043328;
pub const I2C_SLR1_MASK1EN_POS: u32 = 26;
pub const I2C_SLR1_MASK1EN: u32 = 67108864;
pub const I2C_SLTR_TOUTLOW_POS: u32 = 0;
pub const I2C_SLTR_TOUTLOW: u32 = 65535;
pub const I2C_SLTR_TOUTHIGH_POS: u32 = 16;
pub const I2C_SLTR_TOUTHIGH: u32 = 4294901760;
pub const I2C_SR_STARTF_POS: u32 = 0;
pub const I2C_SR_STARTF: u32 = 1;
pub const I2C_SR_SLADDR0F_POS: u32 = 1;
pub const I2C_SR_SLADDR0F: u32 = 2;
pub const I2C_SR_SLADDR1F_POS: u32 = 2;
pub const I2C_SR_SLADDR1F: u32 = 4;
pub const I2C_SR_TENDF_POS: u32 = 3;
pub const I2C_SR_TENDF: u32 = 8;
pub const I2C_SR_STOPF_POS: u32 = 4;
pub const I2C_SR_STOPF: u32 = 16;
pub const I2C_SR_RFULLF_POS: u32 = 6;
pub const I2C_SR_RFULLF: u32 = 64;
pub const I2C_SR_TEMPTYF_POS: u32 = 7;
pub const I2C_SR_TEMPTYF: u32 = 128;
pub const I2C_SR_ARLOF_POS: u32 = 9;
pub const I2C_SR_ARLOF: u32 = 512;
pub const I2C_SR_ACKRF_POS: u32 = 10;
pub const I2C_SR_ACKRF: u32 = 1024;
pub const I2C_SR_NACKF_POS: u32 = 12;
pub const I2C_SR_NACKF: u32 = 4096;
pub const I2C_SR_TMOUTF_POS: u32 = 14;
pub const I2C_SR_TMOUTF: u32 = 16384;
pub const I2C_SR_MSL_POS: u32 = 16;
pub const I2C_SR_MSL: u32 = 65536;
pub const I2C_SR_BUSY_POS: u32 = 17;
pub const I2C_SR_BUSY: u32 = 131072;
pub const I2C_SR_TRA_POS: u32 = 18;
pub const I2C_SR_TRA: u32 = 262144;
pub const I2C_SR_GENCALLF_POS: u32 = 20;
pub const I2C_SR_GENCALLF: u32 = 1048576;
pub const I2C_SR_SMBDEFAULTF_POS: u32 = 21;
pub const I2C_SR_SMBDEFAULTF: u32 = 2097152;
pub const I2C_SR_SMBHOSTF_POS: u32 = 22;
pub const I2C_SR_SMBHOSTF: u32 = 4194304;
pub const I2C_SR_SMBALRTF_POS: u32 = 23;
pub const I2C_SR_SMBALRTF: u32 = 8388608;
pub const I2C_SR_TFEMPTY_POS: u32 = 24;
pub const I2C_SR_TFEMPTY: u32 = 16777216;
pub const I2C_SR_TFFULL_POS: u32 = 25;
pub const I2C_SR_TFFULL: u32 = 33554432;
pub const I2C_SR_RFEMPTY_POS: u32 = 26;
pub const I2C_SR_RFEMPTY: u32 = 67108864;
pub const I2C_SR_RFFULL_POS: u32 = 27;
pub const I2C_SR_RFFULL: u32 = 134217728;
pub const I2C_SR_TFST_POS: u32 = 28;
pub const I2C_SR_TFST: u32 = 805306368;
pub const I2C_SR_TFST_0: u32 = 268435456;
pub const I2C_SR_TFST_1: u32 = 536870912;
pub const I2C_SR_RFREQ_POS: u32 = 31;
pub const I2C_SR_RFREQ: u32 = 2147483648;
pub const I2C_CLR_STARTFCLR_POS: u32 = 0;
pub const I2C_CLR_STARTFCLR: u32 = 1;
pub const I2C_CLR_SLADDR0FCLR_POS: u32 = 1;
pub const I2C_CLR_SLADDR0FCLR: u32 = 2;
pub const I2C_CLR_SLADDR1FCLR_POS: u32 = 2;
pub const I2C_CLR_SLADDR1FCLR: u32 = 4;
pub const I2C_CLR_TENDFCLR_POS: u32 = 3;
pub const I2C_CLR_TENDFCLR: u32 = 8;
pub const I2C_CLR_STOPFCLR_POS: u32 = 4;
pub const I2C_CLR_STOPFCLR: u32 = 16;
pub const I2C_CLR_RFULLFCLR_POS: u32 = 6;
pub const I2C_CLR_RFULLFCLR: u32 = 64;
pub const I2C_CLR_ARLOFCLR_POS: u32 = 9;
pub const I2C_CLR_ARLOFCLR: u32 = 512;
pub const I2C_CLR_RFREQCLR_POS: u32 = 10;
pub const I2C_CLR_RFREQCLR: u32 = 1024;
pub const I2C_CLR_NACKFCLR_POS: u32 = 12;
pub const I2C_CLR_NACKFCLR: u32 = 4096;
pub const I2C_CLR_TMOUTFCLR_POS: u32 = 14;
pub const I2C_CLR_TMOUTFCLR: u32 = 16384;
pub const I2C_CLR_GENCALLFCLR_POS: u32 = 20;
pub const I2C_CLR_GENCALLFCLR: u32 = 1048576;
pub const I2C_CLR_SMBDEFAULTFCLR_POS: u32 = 21;
pub const I2C_CLR_SMBDEFAULTFCLR: u32 = 2097152;
pub const I2C_CLR_SMBHOSTFCLR_POS: u32 = 22;
pub const I2C_CLR_SMBHOSTFCLR: u32 = 4194304;
pub const I2C_CLR_SMBALRTFCLR_POS: u32 = 23;
pub const I2C_CLR_SMBALRTFCLR: u32 = 8388608;
pub const I2C_DTR: u32 = 255;
pub const I2C_DRR: u32 = 255;
pub const I2C_CCR_SLOWW_POS: u32 = 0;
pub const I2C_CCR_SLOWW: u32 = 255;
pub const I2C_CCR_SHIGHW_POS: u32 = 8;
pub const I2C_CCR_SHIGHW: u32 = 65280;
pub const I2C_CCR_CKDIV_POS: u32 = 16;
pub const I2C_CCR_CKDIV: u32 = 458752;
pub const I2C_FLTR_DNF_POS: u32 = 0;
pub const I2C_FLTR_DNF: u32 = 3;
pub const I2C_FLTR_DNFEN_POS: u32 = 4;
pub const I2C_FLTR_DNFEN: u32 = 16;
pub const I2C_FLTR_ANFEN_POS: u32 = 5;
pub const I2C_FLTR_ANFEN: u32 = 32;
pub const I2C_FSTR_FEN_POS: u32 = 0;
pub const I2C_FSTR_FEN: u32 = 1;
pub const I2C_FSTR_TFFLUSH_POS: u32 = 1;
pub const I2C_FSTR_TFFLUSH: u32 = 2;
pub const I2C_FSTR_RFFLUSH_POS: u32 = 2;
pub const I2C_FSTR_RFFLUSH: u32 = 4;
pub const I2C_FSTR_NACKTFFLUSH_POS: u32 = 3;
pub const I2C_FSTR_NACKTFFLUSH: u32 = 8;
pub const I2C_FSTR_TFST_POS: u32 = 4;
pub const I2C_FSTR_TFST: u32 = 48;
pub const I2C_FSTR_TFST_0: u32 = 16;
pub const I2C_FSTR_TFST_1: u32 = 32;
pub const I2C_FSTR_RFST_POS: u32 = 6;
pub const I2C_FSTR_RFST: u32 = 192;
pub const I2C_FSTR_RFST_0: u32 = 64;
pub const I2C_FSTR_RFST_1: u32 = 128;
pub const I2C_SLVADDR_SLVADRR: u32 = 1023;
pub const ICG_ICG0_SWDTAUTS_POS: u32 = 0;
pub const ICG_ICG0_SWDTAUTS: u32 = 1;
pub const ICG_ICG0_SWDTITS_POS: u32 = 1;
pub const ICG_ICG0_SWDTITS: u32 = 2;
pub const ICG_ICG0_SWDTPERI_POS: u32 = 2;
pub const ICG_ICG0_SWDTPERI: u32 = 12;
pub const ICG_ICG0_SWDTPERI_0: u32 = 4;
pub const ICG_ICG0_SWDTPERI_1: u32 = 8;
pub const ICG_ICG0_SWDTCKS_POS: u32 = 4;
pub const ICG_ICG0_SWDTCKS: u32 = 240;
pub const ICG_ICG0_SWDTWDPT_POS: u32 = 8;
pub const ICG_ICG0_SWDTWDPT: u32 = 3840;
pub const ICG_ICG0_SWDTSLPOFF_POS: u32 = 12;
pub const ICG_ICG0_SWDTSLPOFF: u32 = 4096;
pub const ICG_ICG0_WDTAUTS_POS: u32 = 16;
pub const ICG_ICG0_WDTAUTS: u32 = 65536;
pub const ICG_ICG0_WDTITS_POS: u32 = 17;
pub const ICG_ICG0_WDTITS: u32 = 131072;
pub const ICG_ICG0_WDTPERI_POS: u32 = 18;
pub const ICG_ICG0_WDTPERI: u32 = 786432;
pub const ICG_ICG0_WDTPERI_0: u32 = 262144;
pub const ICG_ICG0_WDTPERI_1: u32 = 524288;
pub const ICG_ICG0_WDTCKS_POS: u32 = 20;
pub const ICG_ICG0_WDTCKS: u32 = 15728640;
pub const ICG_ICG0_WDTWDPT_POS: u32 = 24;
pub const ICG_ICG0_WDTWDPT: u32 = 251658240;
pub const ICG_ICG0_WDTSLPOFF_POS: u32 = 28;
pub const ICG_ICG0_WDTSLPOFF: u32 = 268435456;
pub const ICG_ICG1_HRCFREQSEL_POS: u32 = 0;
pub const ICG_ICG1_HRCFREQSEL: u32 = 1;
pub const ICG_ICG1_HRCSTOP_POS: u32 = 8;
pub const ICG_ICG1_HRCSTOP: u32 = 256;
pub const ICG_ICG1_BOR_LEV_POS: u32 = 16;
pub const ICG_ICG1_BOR_LEV: u32 = 196608;
pub const ICG_ICG1_BOR_LEV_0: u32 = 65536;
pub const ICG_ICG1_BOR_LEV_1: u32 = 131072;
pub const ICG_ICG1_BORDIS_POS: u32 = 18;
pub const ICG_ICG1_BORDIS: u32 = 262144;
pub const ICG_ICG3_DBUSPRT: u32 = 65535;
pub const INTC_NMIER_SWDTEN_POS: u32 = 1;
pub const INTC_NMIER_SWDTEN: u32 = 2;
pub const INTC_NMIER_PVD1EN_POS: u32 = 2;
pub const INTC_NMIER_PVD1EN: u32 = 4;
pub const INTC_NMIER_PVD2EN_POS: u32 = 3;
pub const INTC_NMIER_PVD2EN: u32 = 8;
pub const INTC_NMIER_XTALSTPEN_POS: u32 = 5;
pub const INTC_NMIER_XTALSTPEN: u32 = 32;
pub const INTC_NMIER_RPARERREN_POS: u32 = 8;
pub const INTC_NMIER_RPARERREN: u32 = 256;
pub const INTC_NMIER_RECCERREN_POS: u32 = 9;
pub const INTC_NMIER_RECCERREN: u32 = 512;
pub const INTC_NMIER_BUSERREN_POS: u32 = 10;
pub const INTC_NMIER_BUSERREN: u32 = 1024;
pub const INTC_NMIER_WDTEN_POS: u32 = 11;
pub const INTC_NMIER_WDTEN: u32 = 2048;
pub const INTC_NMIFR_SWDTF_POS: u32 = 1;
pub const INTC_NMIFR_SWDTF: u32 = 2;
pub const INTC_NMIFR_PVD1F_POS: u32 = 2;
pub const INTC_NMIFR_PVD1F: u32 = 4;
pub const INTC_NMIFR_PVD2F_POS: u32 = 3;
pub const INTC_NMIFR_PVD2F: u32 = 8;
pub const INTC_NMIFR_XTALSTPF_POS: u32 = 5;
pub const INTC_NMIFR_XTALSTPF: u32 = 32;
pub const INTC_NMIFR_RPARERRF_POS: u32 = 8;
pub const INTC_NMIFR_RPARERRF: u32 = 256;
pub const INTC_NMIFR_RECCERRF_POS: u32 = 9;
pub const INTC_NMIFR_RECCERRF: u32 = 512;
pub const INTC_NMIFR_BUSERRF_POS: u32 = 10;
pub const INTC_NMIFR_BUSERRF: u32 = 1024;
pub const INTC_NMIFR_WDTF_POS: u32 = 11;
pub const INTC_NMIFR_WDTF: u32 = 2048;
pub const INTC_NMIFCR_SWDTFCLR_POS: u32 = 1;
pub const INTC_NMIFCR_SWDTFCLR: u32 = 2;
pub const INTC_NMIFCR_PVD1FCLR_POS: u32 = 2;
pub const INTC_NMIFCR_PVD1FCLR: u32 = 4;
pub const INTC_NMIFCR_PVD2FCLR_POS: u32 = 3;
pub const INTC_NMIFCR_PVD2FCLR: u32 = 8;
pub const INTC_NMIFCR_XTALSTPFCLR_POS: u32 = 5;
pub const INTC_NMIFCR_XTALSTPFCLR: u32 = 32;
pub const INTC_NMIFCR_RPARERRFCLR_POS: u32 = 8;
pub const INTC_NMIFCR_RPARERRFCLR: u32 = 256;
pub const INTC_NMIFCR_RECCERRFCLR_POS: u32 = 9;
pub const INTC_NMIFCR_RECCERRFCLR: u32 = 512;
pub const INTC_NMIFCR_BUSERRFCLR_POS: u32 = 10;
pub const INTC_NMIFCR_BUSERRFCLR: u32 = 1024;
pub const INTC_NMIFCR_WDTFCLR_POS: u32 = 11;
pub const INTC_NMIFCR_WDTFCLR: u32 = 2048;
pub const INTC_EIRQCR_EIRQTRG_POS: u32 = 0;
pub const INTC_EIRQCR_EIRQTRG: u32 = 3;
pub const INTC_EIRQCR_EIRQTRG_0: u32 = 1;
pub const INTC_EIRQCR_EIRQTRG_1: u32 = 2;
pub const INTC_EIRQCR_EISMPCLK_POS: u32 = 4;
pub const INTC_EIRQCR_EISMPCLK: u32 = 48;
pub const INTC_EIRQCR_EISMPCLK_0: u32 = 16;
pub const INTC_EIRQCR_EISMPCLK_1: u32 = 32;
pub const INTC_EIRQCR_EFEN_POS: u32 = 7;
pub const INTC_EIRQCR_EFEN: u32 = 128;
pub const INTC_EIRQCR_NOCSEL_POS: u32 = 12;
pub const INTC_EIRQCR_NOCSEL: u32 = 12288;
pub const INTC_EIRQCR_NOCSEL_0: u32 = 4096;
pub const INTC_EIRQCR_NOCSEL_1: u32 = 8192;
pub const INTC_EIRQCR_NOCEN_POS: u32 = 15;
pub const INTC_EIRQCR_NOCEN: u32 = 32768;
pub const INTC_WKEN_EIRQWKEN_POS: u32 = 0;
pub const INTC_WKEN_EIRQWKEN: u32 = 65535;
pub const INTC_WKEN_EIRQWKEN_0: u32 = 1;
pub const INTC_WKEN_EIRQWKEN_1: u32 = 2;
pub const INTC_WKEN_EIRQWKEN_2: u32 = 4;
pub const INTC_WKEN_EIRQWKEN_3: u32 = 8;
pub const INTC_WKEN_EIRQWKEN_4: u32 = 16;
pub const INTC_WKEN_EIRQWKEN_5: u32 = 32;
pub const INTC_WKEN_EIRQWKEN_6: u32 = 64;
pub const INTC_WKEN_EIRQWKEN_7: u32 = 128;
pub const INTC_WKEN_EIRQWKEN_8: u32 = 256;
pub const INTC_WKEN_EIRQWKEN_9: u32 = 512;
pub const INTC_WKEN_EIRQWKEN_10: u32 = 1024;
pub const INTC_WKEN_EIRQWKEN_11: u32 = 2048;
pub const INTC_WKEN_EIRQWKEN_12: u32 = 4096;
pub const INTC_WKEN_EIRQWKEN_13: u32 = 8192;
pub const INTC_WKEN_EIRQWKEN_14: u32 = 16384;
pub const INTC_WKEN_EIRQWKEN_15: u32 = 32768;
pub const INTC_WKEN_SWDTWKEN_POS: u32 = 16;
pub const INTC_WKEN_SWDTWKEN: u32 = 65536;
pub const INTC_WKEN_CMP1WKEN_POS: u32 = 19;
pub const INTC_WKEN_CMP1WKEN: u32 = 524288;
pub const INTC_WKEN_WKTMWKEN_POS: u32 = 20;
pub const INTC_WKEN_WKTMWKEN: u32 = 1048576;
pub const INTC_WKEN_RTCALMWKEN_POS: u32 = 21;
pub const INTC_WKEN_RTCALMWKEN: u32 = 2097152;
pub const INTC_WKEN_RTCPRDWKEN_POS: u32 = 22;
pub const INTC_WKEN_RTCPRDWKEN: u32 = 4194304;
pub const INTC_WKEN_TMR0CMPWKEN_POS: u32 = 23;
pub const INTC_WKEN_TMR0CMPWKEN: u32 = 8388608;
pub const INTC_WKEN_RXWKEN_POS: u32 = 26;
pub const INTC_WKEN_RXWKEN: u32 = 67108864;
pub const INTC_WKEN_CMP2WKEN_POS: u32 = 29;
pub const INTC_WKEN_CMP2WKEN: u32 = 536870912;
pub const INTC_WKEN_CMP3WKEN_POS: u32 = 30;
pub const INTC_WKEN_CMP3WKEN: u32 = 1073741824;
pub const INTC_WKEN_CMP4WKEN_POS: u32 = 31;
pub const INTC_WKEN_CMP4WKEN: u32 = 2147483648;
pub const INTC_EIFR_EIF0_POS: u32 = 0;
pub const INTC_EIFR_EIF0: u32 = 1;
pub const INTC_EIFR_EIF1_POS: u32 = 1;
pub const INTC_EIFR_EIF1: u32 = 2;
pub const INTC_EIFR_EIF2_POS: u32 = 2;
pub const INTC_EIFR_EIF2: u32 = 4;
pub const INTC_EIFR_EIF3_POS: u32 = 3;
pub const INTC_EIFR_EIF3: u32 = 8;
pub const INTC_EIFR_EIF4_POS: u32 = 4;
pub const INTC_EIFR_EIF4: u32 = 16;
pub const INTC_EIFR_EIF5_POS: u32 = 5;
pub const INTC_EIFR_EIF5: u32 = 32;
pub const INTC_EIFR_EIF6_POS: u32 = 6;
pub const INTC_EIFR_EIF6: u32 = 64;
pub const INTC_EIFR_EIF7_POS: u32 = 7;
pub const INTC_EIFR_EIF7: u32 = 128;
pub const INTC_EIFR_EIF8_POS: u32 = 8;
pub const INTC_EIFR_EIF8: u32 = 256;
pub const INTC_EIFR_EIF9_POS: u32 = 9;
pub const INTC_EIFR_EIF9: u32 = 512;
pub const INTC_EIFR_EIF10_POS: u32 = 10;
pub const INTC_EIFR_EIF10: u32 = 1024;
pub const INTC_EIFR_EIF11_POS: u32 = 11;
pub const INTC_EIFR_EIF11: u32 = 2048;
pub const INTC_EIFR_EIF12_POS: u32 = 12;
pub const INTC_EIFR_EIF12: u32 = 4096;
pub const INTC_EIFR_EIF13_POS: u32 = 13;
pub const INTC_EIFR_EIF13: u32 = 8192;
pub const INTC_EIFR_EIF14_POS: u32 = 14;
pub const INTC_EIFR_EIF14: u32 = 16384;
pub const INTC_EIFR_EIF15_POS: u32 = 15;
pub const INTC_EIFR_EIF15: u32 = 32768;
pub const INTC_EIFCR_EIFCLR0_POS: u32 = 0;
pub const INTC_EIFCR_EIFCLR0: u32 = 1;
pub const INTC_EIFCR_EIFCLR1_POS: u32 = 1;
pub const INTC_EIFCR_EIFCLR1: u32 = 2;
pub const INTC_EIFCR_EIFCLR2_POS: u32 = 2;
pub const INTC_EIFCR_EIFCLR2: u32 = 4;
pub const INTC_EIFCR_EIFCLR3_POS: u32 = 3;
pub const INTC_EIFCR_EIFCLR3: u32 = 8;
pub const INTC_EIFCR_EIFCLR4_POS: u32 = 4;
pub const INTC_EIFCR_EIFCLR4: u32 = 16;
pub const INTC_EIFCR_EIFCLR5_POS: u32 = 5;
pub const INTC_EIFCR_EIFCLR5: u32 = 32;
pub const INTC_EIFCR_EIFCLR6_POS: u32 = 6;
pub const INTC_EIFCR_EIFCLR6: u32 = 64;
pub const INTC_EIFCR_EIFCLR7_POS: u32 = 7;
pub const INTC_EIFCR_EIFCLR7: u32 = 128;
pub const INTC_EIFCR_EIFCLR8_POS: u32 = 8;
pub const INTC_EIFCR_EIFCLR8: u32 = 256;
pub const INTC_EIFCR_EIFCLR9_POS: u32 = 9;
pub const INTC_EIFCR_EIFCLR9: u32 = 512;
pub const INTC_EIFCR_EIFCLR10_POS: u32 = 10;
pub const INTC_EIFCR_EIFCLR10: u32 = 1024;
pub const INTC_EIFCR_EIFCLR11_POS: u32 = 11;
pub const INTC_EIFCR_EIFCLR11: u32 = 2048;
pub const INTC_EIFCR_EIFCLR12_POS: u32 = 12;
pub const INTC_EIFCR_EIFCLR12: u32 = 4096;
pub const INTC_EIFCR_EIFCLR13_POS: u32 = 13;
pub const INTC_EIFCR_EIFCLR13: u32 = 8192;
pub const INTC_EIFCR_EIFCLR14_POS: u32 = 14;
pub const INTC_EIFCR_EIFCLR14: u32 = 16384;
pub const INTC_EIFCR_EIFCLR15_POS: u32 = 15;
pub const INTC_EIFCR_EIFCLR15: u32 = 32768;
pub const INTC_INTSEL_INTSEL: u32 = 511;
pub const INTC_INTEN_INTEN: u32 = 4294967295;
pub const INTC_INTEN_INTEN_0: u32 = 1;
pub const INTC_INTEN_INTEN_1: u32 = 2;
pub const INTC_INTEN_INTEN_2: u32 = 4;
pub const INTC_INTEN_INTEN_3: u32 = 8;
pub const INTC_INTEN_INTEN_4: u32 = 16;
pub const INTC_INTEN_INTEN_5: u32 = 32;
pub const INTC_INTEN_INTEN_6: u32 = 64;
pub const INTC_INTEN_INTEN_7: u32 = 128;
pub const INTC_INTEN_INTEN_8: u32 = 256;
pub const INTC_INTEN_INTEN_9: u32 = 512;
pub const INTC_INTEN_INTEN_10: u32 = 1024;
pub const INTC_INTEN_INTEN_11: u32 = 2048;
pub const INTC_INTEN_INTEN_12: u32 = 4096;
pub const INTC_INTEN_INTEN_13: u32 = 8192;
pub const INTC_INTEN_INTEN_14: u32 = 16384;
pub const INTC_INTEN_INTEN_15: u32 = 32768;
pub const INTC_INTEN_INTEN_16: u32 = 65536;
pub const INTC_INTEN_INTEN_17: u32 = 131072;
pub const INTC_INTEN_INTEN_18: u32 = 262144;
pub const INTC_INTEN_INTEN_19: u32 = 524288;
pub const INTC_INTEN_INTEN_20: u32 = 1048576;
pub const INTC_INTEN_INTEN_21: u32 = 2097152;
pub const INTC_INTEN_INTEN_22: u32 = 4194304;
pub const INTC_INTEN_INTEN_23: u32 = 8388608;
pub const INTC_INTEN_INTEN_24: u32 = 16777216;
pub const INTC_INTEN_INTEN_25: u32 = 33554432;
pub const INTC_INTEN_INTEN_26: u32 = 67108864;
pub const INTC_INTEN_INTEN_27: u32 = 134217728;
pub const INTC_INTEN_INTEN_28: u32 = 268435456;
pub const INTC_INTEN_INTEN_29: u32 = 536870912;
pub const INTC_INTEN_INTEN_30: u32 = 1073741824;
pub const INTC_INTEN_INTEN_31: u32 = 2147483648;
pub const INTC_SWIER_SWIE0_POS: u32 = 0;
pub const INTC_SWIER_SWIE0: u32 = 1;
pub const INTC_SWIER_SWIE1_POS: u32 = 1;
pub const INTC_SWIER_SWIE1: u32 = 2;
pub const INTC_SWIER_SWIE2_POS: u32 = 2;
pub const INTC_SWIER_SWIE2: u32 = 4;
pub const INTC_SWIER_SWIE3_POS: u32 = 3;
pub const INTC_SWIER_SWIE3: u32 = 8;
pub const INTC_SWIER_SWIE4_POS: u32 = 4;
pub const INTC_SWIER_SWIE4: u32 = 16;
pub const INTC_SWIER_SWIE5_POS: u32 = 5;
pub const INTC_SWIER_SWIE5: u32 = 32;
pub const INTC_SWIER_SWIE6_POS: u32 = 6;
pub const INTC_SWIER_SWIE6: u32 = 64;
pub const INTC_SWIER_SWIE7_POS: u32 = 7;
pub const INTC_SWIER_SWIE7: u32 = 128;
pub const INTC_SWIER_SWIE8_POS: u32 = 8;
pub const INTC_SWIER_SWIE8: u32 = 256;
pub const INTC_SWIER_SWIE9_POS: u32 = 9;
pub const INTC_SWIER_SWIE9: u32 = 512;
pub const INTC_SWIER_SWIE10_POS: u32 = 10;
pub const INTC_SWIER_SWIE10: u32 = 1024;
pub const INTC_SWIER_SWIE11_POS: u32 = 11;
pub const INTC_SWIER_SWIE11: u32 = 2048;
pub const INTC_SWIER_SWIE12_POS: u32 = 12;
pub const INTC_SWIER_SWIE12: u32 = 4096;
pub const INTC_SWIER_SWIE13_POS: u32 = 13;
pub const INTC_SWIER_SWIE13: u32 = 8192;
pub const INTC_SWIER_SWIE14_POS: u32 = 14;
pub const INTC_SWIER_SWIE14: u32 = 16384;
pub const INTC_SWIER_SWIE15_POS: u32 = 15;
pub const INTC_SWIER_SWIE15: u32 = 32768;
pub const INTC_SWIER_SWIE16_POS: u32 = 16;
pub const INTC_SWIER_SWIE16: u32 = 65536;
pub const INTC_SWIER_SWIE17_POS: u32 = 17;
pub const INTC_SWIER_SWIE17: u32 = 131072;
pub const INTC_SWIER_SWIE18_POS: u32 = 18;
pub const INTC_SWIER_SWIE18: u32 = 262144;
pub const INTC_SWIER_SWIE19_POS: u32 = 19;
pub const INTC_SWIER_SWIE19: u32 = 524288;
pub const INTC_SWIER_SWIE20_POS: u32 = 20;
pub const INTC_SWIER_SWIE20: u32 = 1048576;
pub const INTC_SWIER_SWIE21_POS: u32 = 21;
pub const INTC_SWIER_SWIE21: u32 = 2097152;
pub const INTC_SWIER_SWIE22_POS: u32 = 22;
pub const INTC_SWIER_SWIE22: u32 = 4194304;
pub const INTC_SWIER_SWIE23_POS: u32 = 23;
pub const INTC_SWIER_SWIE23: u32 = 8388608;
pub const INTC_SWIER_SWIE24_POS: u32 = 24;
pub const INTC_SWIER_SWIE24: u32 = 16777216;
pub const INTC_SWIER_SWIE25_POS: u32 = 25;
pub const INTC_SWIER_SWIE25: u32 = 33554432;
pub const INTC_SWIER_SWIE26_POS: u32 = 26;
pub const INTC_SWIER_SWIE26: u32 = 67108864;
pub const INTC_SWIER_SWIE27_POS: u32 = 27;
pub const INTC_SWIER_SWIE27: u32 = 134217728;
pub const INTC_SWIER_SWIE28_POS: u32 = 28;
pub const INTC_SWIER_SWIE28: u32 = 268435456;
pub const INTC_SWIER_SWIE29_POS: u32 = 29;
pub const INTC_SWIER_SWIE29: u32 = 536870912;
pub const INTC_SWIER_SWIE30_POS: u32 = 30;
pub const INTC_SWIER_SWIE30: u32 = 1073741824;
pub const INTC_SWIER_SWIE31_POS: u32 = 31;
pub const INTC_SWIER_SWIE31: u32 = 2147483648;
pub const INTC_EVTER_EVTE0_POS: u32 = 0;
pub const INTC_EVTER_EVTE0: u32 = 1;
pub const INTC_EVTER_EVTE1_POS: u32 = 1;
pub const INTC_EVTER_EVTE1: u32 = 2;
pub const INTC_EVTER_EVTE2_POS: u32 = 2;
pub const INTC_EVTER_EVTE2: u32 = 4;
pub const INTC_EVTER_EVTE3_POS: u32 = 3;
pub const INTC_EVTER_EVTE3: u32 = 8;
pub const INTC_EVTER_EVTE4_POS: u32 = 4;
pub const INTC_EVTER_EVTE4: u32 = 16;
pub const INTC_EVTER_EVTE5_POS: u32 = 5;
pub const INTC_EVTER_EVTE5: u32 = 32;
pub const INTC_EVTER_EVTE6_POS: u32 = 6;
pub const INTC_EVTER_EVTE6: u32 = 64;
pub const INTC_EVTER_EVTE7_POS: u32 = 7;
pub const INTC_EVTER_EVTE7: u32 = 128;
pub const INTC_EVTER_EVTE8_POS: u32 = 8;
pub const INTC_EVTER_EVTE8: u32 = 256;
pub const INTC_EVTER_EVTE9_POS: u32 = 9;
pub const INTC_EVTER_EVTE9: u32 = 512;
pub const INTC_EVTER_EVTE10_POS: u32 = 10;
pub const INTC_EVTER_EVTE10: u32 = 1024;
pub const INTC_EVTER_EVTE11_POS: u32 = 11;
pub const INTC_EVTER_EVTE11: u32 = 2048;
pub const INTC_EVTER_EVTE12_POS: u32 = 12;
pub const INTC_EVTER_EVTE12: u32 = 4096;
pub const INTC_EVTER_EVTE13_POS: u32 = 13;
pub const INTC_EVTER_EVTE13: u32 = 8192;
pub const INTC_EVTER_EVTE14_POS: u32 = 14;
pub const INTC_EVTER_EVTE14: u32 = 16384;
pub const INTC_EVTER_EVTE15_POS: u32 = 15;
pub const INTC_EVTER_EVTE15: u32 = 32768;
pub const INTC_EVTER_EVTE16_POS: u32 = 16;
pub const INTC_EVTER_EVTE16: u32 = 65536;
pub const INTC_EVTER_EVTE17_POS: u32 = 17;
pub const INTC_EVTER_EVTE17: u32 = 131072;
pub const INTC_EVTER_EVTE18_POS: u32 = 18;
pub const INTC_EVTER_EVTE18: u32 = 262144;
pub const INTC_EVTER_EVTE19_POS: u32 = 19;
pub const INTC_EVTER_EVTE19: u32 = 524288;
pub const INTC_EVTER_EVTE20_POS: u32 = 20;
pub const INTC_EVTER_EVTE20: u32 = 1048576;
pub const INTC_EVTER_EVTE21_POS: u32 = 21;
pub const INTC_EVTER_EVTE21: u32 = 2097152;
pub const INTC_EVTER_EVTE22_POS: u32 = 22;
pub const INTC_EVTER_EVTE22: u32 = 4194304;
pub const INTC_EVTER_EVTE23_POS: u32 = 23;
pub const INTC_EVTER_EVTE23: u32 = 8388608;
pub const INTC_EVTER_EVTE24_POS: u32 = 24;
pub const INTC_EVTER_EVTE24: u32 = 16777216;
pub const INTC_EVTER_EVTE25_POS: u32 = 25;
pub const INTC_EVTER_EVTE25: u32 = 33554432;
pub const INTC_EVTER_EVTE26_POS: u32 = 26;
pub const INTC_EVTER_EVTE26: u32 = 67108864;
pub const INTC_EVTER_EVTE27_POS: u32 = 27;
pub const INTC_EVTER_EVTE27: u32 = 134217728;
pub const INTC_EVTER_EVTE28_POS: u32 = 28;
pub const INTC_EVTER_EVTE28: u32 = 268435456;
pub const INTC_EVTER_EVTE29_POS: u32 = 29;
pub const INTC_EVTER_EVTE29: u32 = 536870912;
pub const INTC_EVTER_EVTE30_POS: u32 = 30;
pub const INTC_EVTER_EVTE30: u32 = 1073741824;
pub const INTC_EVTER_EVTE31_POS: u32 = 31;
pub const INTC_EVTER_EVTE31: u32 = 2147483648;
pub const INTC_IER_IEN0_POS: u32 = 0;
pub const INTC_IER_IEN0: u32 = 1;
pub const INTC_IER_IEN1_POS: u32 = 1;
pub const INTC_IER_IEN1: u32 = 2;
pub const INTC_IER_IEN2_POS: u32 = 2;
pub const INTC_IER_IEN2: u32 = 4;
pub const INTC_IER_IEN3_POS: u32 = 3;
pub const INTC_IER_IEN3: u32 = 8;
pub const INTC_IER_IEN4_POS: u32 = 4;
pub const INTC_IER_IEN4: u32 = 16;
pub const INTC_IER_IEN5_POS: u32 = 5;
pub const INTC_IER_IEN5: u32 = 32;
pub const INTC_IER_IEN6_POS: u32 = 6;
pub const INTC_IER_IEN6: u32 = 64;
pub const INTC_IER_IEN7_POS: u32 = 7;
pub const INTC_IER_IEN7: u32 = 128;
pub const INTC_IER_IEN8_POS: u32 = 8;
pub const INTC_IER_IEN8: u32 = 256;
pub const INTC_IER_IEN9_POS: u32 = 9;
pub const INTC_IER_IEN9: u32 = 512;
pub const INTC_IER_IEN10_POS: u32 = 10;
pub const INTC_IER_IEN10: u32 = 1024;
pub const INTC_IER_IEN11_POS: u32 = 11;
pub const INTC_IER_IEN11: u32 = 2048;
pub const INTC_IER_IEN12_POS: u32 = 12;
pub const INTC_IER_IEN12: u32 = 4096;
pub const INTC_IER_IEN13_POS: u32 = 13;
pub const INTC_IER_IEN13: u32 = 8192;
pub const INTC_IER_IEN14_POS: u32 = 14;
pub const INTC_IER_IEN14: u32 = 16384;
pub const INTC_IER_IEN15_POS: u32 = 15;
pub const INTC_IER_IEN15: u32 = 32768;
pub const INTC_IER_IEN16_POS: u32 = 16;
pub const INTC_IER_IEN16: u32 = 65536;
pub const INTC_IER_IEN17_POS: u32 = 17;
pub const INTC_IER_IEN17: u32 = 131072;
pub const INTC_IER_IEN18_POS: u32 = 18;
pub const INTC_IER_IEN18: u32 = 262144;
pub const INTC_IER_IEN19_POS: u32 = 19;
pub const INTC_IER_IEN19: u32 = 524288;
pub const INTC_IER_IEN20_POS: u32 = 20;
pub const INTC_IER_IEN20: u32 = 1048576;
pub const INTC_IER_IEN21_POS: u32 = 21;
pub const INTC_IER_IEN21: u32 = 2097152;
pub const INTC_IER_IEN22_POS: u32 = 22;
pub const INTC_IER_IEN22: u32 = 4194304;
pub const INTC_IER_IEN23_POS: u32 = 23;
pub const INTC_IER_IEN23: u32 = 8388608;
pub const INTC_IER_IEN24_POS: u32 = 24;
pub const INTC_IER_IEN24: u32 = 16777216;
pub const INTC_IER_IEN25_POS: u32 = 25;
pub const INTC_IER_IEN25: u32 = 33554432;
pub const INTC_IER_IEN26_POS: u32 = 26;
pub const INTC_IER_IEN26: u32 = 67108864;
pub const INTC_IER_IEN27_POS: u32 = 27;
pub const INTC_IER_IEN27: u32 = 134217728;
pub const INTC_IER_IEN28_POS: u32 = 28;
pub const INTC_IER_IEN28: u32 = 268435456;
pub const INTC_IER_IEN29_POS: u32 = 29;
pub const INTC_IER_IEN29: u32 = 536870912;
pub const INTC_IER_IEN30_POS: u32 = 30;
pub const INTC_IER_IEN30: u32 = 1073741824;
pub const INTC_IER_IEN31_POS: u32 = 31;
pub const INTC_IER_IEN31: u32 = 2147483648;
pub const KEYSCAN_SCR_KEYINSEL_POS: u32 = 0;
pub const KEYSCAN_SCR_KEYINSEL: u32 = 65535;
pub const KEYSCAN_SCR_KEYOUTSEL_POS: u32 = 16;
pub const KEYSCAN_SCR_KEYOUTSEL: u32 = 458752;
pub const KEYSCAN_SCR_CKSEL_POS: u32 = 20;
pub const KEYSCAN_SCR_CKSEL: u32 = 3145728;
pub const KEYSCAN_SCR_CKSEL_0: u32 = 1048576;
pub const KEYSCAN_SCR_CKSEL_1: u32 = 2097152;
pub const KEYSCAN_SCR_T_LLEVEL_POS: u32 = 24;
pub const KEYSCAN_SCR_T_LLEVEL: u32 = 520093696;
pub const KEYSCAN_SCR_T_HIZ_POS: u32 = 29;
pub const KEYSCAN_SCR_T_HIZ: u32 = 3758096384;
pub const KEYSCAN_SER_SEN: u32 = 1;
pub const KEYSCAN_SSR_INDEX: u32 = 7;
pub const MCAN_ENDN: u32 = 4294967295;
pub const MCAN_DBTP_DSJW_POS: u32 = 0;
pub const MCAN_DBTP_DSJW: u32 = 15;
pub const MCAN_DBTP_DTSEG2_POS: u32 = 4;
pub const MCAN_DBTP_DTSEG2: u32 = 240;
pub const MCAN_DBTP_DTSEG1_POS: u32 = 8;
pub const MCAN_DBTP_DTSEG1: u32 = 7936;
pub const MCAN_DBTP_DBRP_POS: u32 = 16;
pub const MCAN_DBTP_DBRP: u32 = 2031616;
pub const MCAN_DBTP_TDC_POS: u32 = 23;
pub const MCAN_DBTP_TDC: u32 = 8388608;
pub const MCAN_TEST_LBCK_POS: u32 = 4;
pub const MCAN_TEST_LBCK: u32 = 16;
pub const MCAN_TEST_TX_POS: u32 = 5;
pub const MCAN_TEST_TX: u32 = 96;
pub const MCAN_TEST_TX_0: u32 = 32;
pub const MCAN_TEST_TX_1: u32 = 64;
pub const MCAN_TEST_RX_POS: u32 = 7;
pub const MCAN_TEST_RX: u32 = 128;
pub const MCAN_TEST_TXBNP_POS: u32 = 8;
pub const MCAN_TEST_TXBNP: u32 = 7936;
pub const MCAN_TEST_PVAL_POS: u32 = 13;
pub const MCAN_TEST_PVAL: u32 = 8192;
pub const MCAN_TEST_TXBNS_POS: u32 = 16;
pub const MCAN_TEST_TXBNS: u32 = 2031616;
pub const MCAN_TEST_SVAL_POS: u32 = 21;
pub const MCAN_TEST_SVAL: u32 = 2097152;
pub const MCAN_RWD_WDC_POS: u32 = 0;
pub const MCAN_RWD_WDC: u32 = 255;
pub const MCAN_RWD_WDV_POS: u32 = 8;
pub const MCAN_RWD_WDV: u32 = 65280;
pub const MCAN_CCCR_INIT_POS: u32 = 0;
pub const MCAN_CCCR_INIT: u32 = 1;
pub const MCAN_CCCR_CCE_POS: u32 = 1;
pub const MCAN_CCCR_CCE: u32 = 2;
pub const MCAN_CCCR_ASM_POS: u32 = 2;
pub const MCAN_CCCR_ASM: u32 = 4;
pub const MCAN_CCCR_CSA_POS: u32 = 3;
pub const MCAN_CCCR_CSA: u32 = 8;
pub const MCAN_CCCR_CSR_POS: u32 = 4;
pub const MCAN_CCCR_CSR: u32 = 16;
pub const MCAN_CCCR_MON_POS: u32 = 5;
pub const MCAN_CCCR_MON: u32 = 32;
pub const MCAN_CCCR_DAR_POS: u32 = 6;
pub const MCAN_CCCR_DAR: u32 = 64;
pub const MCAN_CCCR_TEST_POS: u32 = 7;
pub const MCAN_CCCR_TEST: u32 = 128;
pub const MCAN_CCCR_FDOE_POS: u32 = 8;
pub const MCAN_CCCR_FDOE: u32 = 256;
pub const MCAN_CCCR_BRSE_POS: u32 = 9;
pub const MCAN_CCCR_BRSE: u32 = 512;
pub const MCAN_CCCR_UTSU_POS: u32 = 10;
pub const MCAN_CCCR_UTSU: u32 = 1024;
pub const MCAN_CCCR_WMM_POS: u32 = 11;
pub const MCAN_CCCR_WMM: u32 = 2048;
pub const MCAN_CCCR_PXHD_POS: u32 = 12;
pub const MCAN_CCCR_PXHD: u32 = 4096;
pub const MCAN_CCCR_EFBI_POS: u32 = 13;
pub const MCAN_CCCR_EFBI: u32 = 8192;
pub const MCAN_CCCR_TXP_POS: u32 = 14;
pub const MCAN_CCCR_TXP: u32 = 16384;
pub const MCAN_CCCR_NISO_POS: u32 = 15;
pub const MCAN_CCCR_NISO: u32 = 32768;
pub const MCAN_NBTP_NTSEG2_POS: u32 = 0;
pub const MCAN_NBTP_NTSEG2: u32 = 127;
pub const MCAN_NBTP_NTSEG1_POS: u32 = 8;
pub const MCAN_NBTP_NTSEG1: u32 = 65280;
pub const MCAN_NBTP_NBRP_POS: u32 = 16;
pub const MCAN_NBTP_NBRP: u32 = 33488896;
pub const MCAN_NBTP_NSJW_POS: u32 = 25;
pub const MCAN_NBTP_NSJW: u32 = 4261412864;
pub const MCAN_TSCC_TSS_POS: u32 = 0;
pub const MCAN_TSCC_TSS: u32 = 3;
pub const MCAN_TSCC_TSS_0: u32 = 1;
pub const MCAN_TSCC_TSS_1: u32 = 2;
pub const MCAN_TSCC_TCP_POS: u32 = 16;
pub const MCAN_TSCC_TCP: u32 = 983040;
pub const MCAN_TSCV_TSC: u32 = 65535;
pub const MCAN_TOCC_ETOC_POS: u32 = 0;
pub const MCAN_TOCC_ETOC: u32 = 1;
pub const MCAN_TOCC_TOS_POS: u32 = 1;
pub const MCAN_TOCC_TOS: u32 = 6;
pub const MCAN_TOCC_TOS_0: u32 = 2;
pub const MCAN_TOCC_TOS_1: u32 = 4;
pub const MCAN_TOCC_TOP_POS: u32 = 16;
pub const MCAN_TOCC_TOP: u32 = 4294901760;
pub const MCAN_TOCV_TOC: u32 = 65535;
pub const MCAN_ECR_TEC_POS: u32 = 0;
pub const MCAN_ECR_TEC: u32 = 255;
pub const MCAN_ECR_REC_POS: u32 = 8;
pub const MCAN_ECR_REC: u32 = 32512;
pub const MCAN_ECR_RP_POS: u32 = 15;
pub const MCAN_ECR_RP: u32 = 32768;
pub const MCAN_ECR_CEL_POS: u32 = 16;
pub const MCAN_ECR_CEL: u32 = 16711680;
pub const MCAN_PSR_LEC_POS: u32 = 0;
pub const MCAN_PSR_LEC: u32 = 7;
pub const MCAN_PSR_ACT_POS: u32 = 3;
pub const MCAN_PSR_ACT: u32 = 24;
pub const MCAN_PSR_ACT_0: u32 = 8;
pub const MCAN_PSR_ACT_1: u32 = 16;
pub const MCAN_PSR_EP_POS: u32 = 5;
pub const MCAN_PSR_EP: u32 = 32;
pub const MCAN_PSR_EW_POS: u32 = 6;
pub const MCAN_PSR_EW: u32 = 64;
pub const MCAN_PSR_BO_POS: u32 = 7;
pub const MCAN_PSR_BO: u32 = 128;
pub const MCAN_PSR_DLEC_POS: u32 = 8;
pub const MCAN_PSR_DLEC: u32 = 1792;
pub const MCAN_PSR_RESI_POS: u32 = 11;
pub const MCAN_PSR_RESI: u32 = 2048;
pub const MCAN_PSR_RBRS_POS: u32 = 12;
pub const MCAN_PSR_RBRS: u32 = 4096;
pub const MCAN_PSR_RFDF_POS: u32 = 13;
pub const MCAN_PSR_RFDF: u32 = 8192;
pub const MCAN_PSR_PXE_POS: u32 = 14;
pub const MCAN_PSR_PXE: u32 = 16384;
pub const MCAN_PSR_TDCV_POS: u32 = 16;
pub const MCAN_PSR_TDCV: u32 = 8323072;
pub const MCAN_TDCR_TDCF_POS: u32 = 0;
pub const MCAN_TDCR_TDCF: u32 = 127;
pub const MCAN_TDCR_TDCO_POS: u32 = 8;
pub const MCAN_TDCR_TDCO: u32 = 32512;
pub const MCAN_IR_RF0N_POS: u32 = 0;
pub const MCAN_IR_RF0N: u32 = 1;
pub const MCAN_IR_RF0W_POS: u32 = 1;
pub const MCAN_IR_RF0W: u32 = 2;
pub const MCAN_IR_RF0F_POS: u32 = 2;
pub const MCAN_IR_RF0F: u32 = 4;
pub const MCAN_IR_RF0L_POS: u32 = 3;
pub const MCAN_IR_RF0L: u32 = 8;
pub const MCAN_IR_RF1N_POS: u32 = 4;
pub const MCAN_IR_RF1N: u32 = 16;
pub const MCAN_IR_RF1W_POS: u32 = 5;
pub const MCAN_IR_RF1W: u32 = 32;
pub const MCAN_IR_RF1F_POS: u32 = 6;
pub const MCAN_IR_RF1F: u32 = 64;
pub const MCAN_IR_RF1L_POS: u32 = 7;
pub const MCAN_IR_RF1L: u32 = 128;
pub const MCAN_IR_HPM_POS: u32 = 8;
pub const MCAN_IR_HPM: u32 = 256;
pub const MCAN_IR_TC_POS: u32 = 9;
pub const MCAN_IR_TC: u32 = 512;
pub const MCAN_IR_TCF_POS: u32 = 10;
pub const MCAN_IR_TCF: u32 = 1024;
pub const MCAN_IR_TFE_POS: u32 = 11;
pub const MCAN_IR_TFE: u32 = 2048;
pub const MCAN_IR_TEFN_POS: u32 = 12;
pub const MCAN_IR_TEFN: u32 = 4096;
pub const MCAN_IR_TEFW_POS: u32 = 13;
pub const MCAN_IR_TEFW: u32 = 8192;
pub const MCAN_IR_TEFF_POS: u32 = 14;
pub const MCAN_IR_TEFF: u32 = 16384;
pub const MCAN_IR_TEFL_POS: u32 = 15;
pub const MCAN_IR_TEFL: u32 = 32768;
pub const MCAN_IR_TSW_POS: u32 = 16;
pub const MCAN_IR_TSW: u32 = 65536;
pub const MCAN_IR_MRAF_POS: u32 = 17;
pub const MCAN_IR_MRAF: u32 = 131072;
pub const MCAN_IR_TOO_POS: u32 = 18;
pub const MCAN_IR_TOO: u32 = 262144;
pub const MCAN_IR_DRX_POS: u32 = 19;
pub const MCAN_IR_DRX: u32 = 524288;
pub const MCAN_IR_BEC_POS: u32 = 20;
pub const MCAN_IR_BEC: u32 = 1048576;
pub const MCAN_IR_BEU_POS: u32 = 21;
pub const MCAN_IR_BEU: u32 = 2097152;
pub const MCAN_IR_ELO_POS: u32 = 22;
pub const MCAN_IR_ELO: u32 = 4194304;
pub const MCAN_IR_EP_POS: u32 = 23;
pub const MCAN_IR_EP: u32 = 8388608;
pub const MCAN_IR_EW_POS: u32 = 24;
pub const MCAN_IR_EW: u32 = 16777216;
pub const MCAN_IR_BO_POS: u32 = 25;
pub const MCAN_IR_BO: u32 = 33554432;
pub const MCAN_IR_WDI_POS: u32 = 26;
pub const MCAN_IR_WDI: u32 = 67108864;
pub const MCAN_IR_PEA_POS: u32 = 27;
pub const MCAN_IR_PEA: u32 = 134217728;
pub const MCAN_IR_PED_POS: u32 = 28;
pub const MCAN_IR_PED: u32 = 268435456;
pub const MCAN_IR_ARA_POS: u32 = 29;
pub const MCAN_IR_ARA: u32 = 536870912;
pub const MCAN_IE_RF0NE_POS: u32 = 0;
pub const MCAN_IE_RF0NE: u32 = 1;
pub const MCAN_IE_RF0WE_POS: u32 = 1;
pub const MCAN_IE_RF0WE: u32 = 2;
pub const MCAN_IE_RF0FE_POS: u32 = 2;
pub const MCAN_IE_RF0FE: u32 = 4;
pub const MCAN_IE_RF0LE_POS: u32 = 3;
pub const MCAN_IE_RF0LE: u32 = 8;
pub const MCAN_IE_RF1NE_POS: u32 = 4;
pub const MCAN_IE_RF1NE: u32 = 16;
pub const MCAN_IE_RF1WE_POS: u32 = 5;
pub const MCAN_IE_RF1WE: u32 = 32;
pub const MCAN_IE_RF1FE_POS: u32 = 6;
pub const MCAN_IE_RF1FE: u32 = 64;
pub const MCAN_IE_RF1LE_POS: u32 = 7;
pub const MCAN_IE_RF1LE: u32 = 128;
pub const MCAN_IE_HPME_POS: u32 = 8;
pub const MCAN_IE_HPME: u32 = 256;
pub const MCAN_IE_TCE_POS: u32 = 9;
pub const MCAN_IE_TCE: u32 = 512;
pub const MCAN_IE_TCFE_POS: u32 = 10;
pub const MCAN_IE_TCFE: u32 = 1024;
pub const MCAN_IE_TFEE_POS: u32 = 11;
pub const MCAN_IE_TFEE: u32 = 2048;
pub const MCAN_IE_TEFNE_POS: u32 = 12;
pub const MCAN_IE_TEFNE: u32 = 4096;
pub const MCAN_IE_TEFWE_POS: u32 = 13;
pub const MCAN_IE_TEFWE: u32 = 8192;
pub const MCAN_IE_TEFFE_POS: u32 = 14;
pub const MCAN_IE_TEFFE: u32 = 16384;
pub const MCAN_IE_TEFLE_POS: u32 = 15;
pub const MCAN_IE_TEFLE: u32 = 32768;
pub const MCAN_IE_TSWE_POS: u32 = 16;
pub const MCAN_IE_TSWE: u32 = 65536;
pub const MCAN_IE_MRAFE_POS: u32 = 17;
pub const MCAN_IE_MRAFE: u32 = 131072;
pub const MCAN_IE_TOOE_POS: u32 = 18;
pub const MCAN_IE_TOOE: u32 = 262144;
pub const MCAN_IE_DRXE_POS: u32 = 19;
pub const MCAN_IE_DRXE: u32 = 524288;
pub const MCAN_IE_BECE_POS: u32 = 20;
pub const MCAN_IE_BECE: u32 = 1048576;
pub const MCAN_IE_BEUE_POS: u32 = 21;
pub const MCAN_IE_BEUE: u32 = 2097152;
pub const MCAN_IE_ELOE_POS: u32 = 22;
pub const MCAN_IE_ELOE: u32 = 4194304;
pub const MCAN_IE_EPE_POS: u32 = 23;
pub const MCAN_IE_EPE: u32 = 8388608;
pub const MCAN_IE_EWE_POS: u32 = 24;
pub const MCAN_IE_EWE: u32 = 16777216;
pub const MCAN_IE_BOE_POS: u32 = 25;
pub const MCAN_IE_BOE: u32 = 33554432;
pub const MCAN_IE_WDIE_POS: u32 = 26;
pub const MCAN_IE_WDIE: u32 = 67108864;
pub const MCAN_IE_PEAE_POS: u32 = 27;
pub const MCAN_IE_PEAE: u32 = 134217728;
pub const MCAN_IE_PEDE_POS: u32 = 28;
pub const MCAN_IE_PEDE: u32 = 268435456;
pub const MCAN_IE_ARAE_POS: u32 = 29;
pub const MCAN_IE_ARAE: u32 = 536870912;
pub const MCAN_ILS_RF0NL_POS: u32 = 0;
pub const MCAN_ILS_RF0NL: u32 = 1;
pub const MCAN_ILS_RF0WL_POS: u32 = 1;
pub const MCAN_ILS_RF0WL: u32 = 2;
pub const MCAN_ILS_RF0FL_POS: u32 = 2;
pub const MCAN_ILS_RF0FL: u32 = 4;
pub const MCAN_ILS_RF0LL_POS: u32 = 3;
pub const MCAN_ILS_RF0LL: u32 = 8;
pub const MCAN_ILS_RF1NL_POS: u32 = 4;
pub const MCAN_ILS_RF1NL: u32 = 16;
pub const MCAN_ILS_RF1WL_POS: u32 = 5;
pub const MCAN_ILS_RF1WL: u32 = 32;
pub const MCAN_ILS_RF1FL_POS: u32 = 6;
pub const MCAN_ILS_RF1FL: u32 = 64;
pub const MCAN_ILS_RF1LL_POS: u32 = 7;
pub const MCAN_ILS_RF1LL: u32 = 128;
pub const MCAN_ILS_HPML_POS: u32 = 8;
pub const MCAN_ILS_HPML: u32 = 256;
pub const MCAN_ILS_TCL_POS: u32 = 9;
pub const MCAN_ILS_TCL: u32 = 512;
pub const MCAN_ILS_TCFL_POS: u32 = 10;
pub const MCAN_ILS_TCFL: u32 = 1024;
pub const MCAN_ILS_TFEL_POS: u32 = 11;
pub const MCAN_ILS_TFEL: u32 = 2048;
pub const MCAN_ILS_TEFNL_POS: u32 = 12;
pub const MCAN_ILS_TEFNL: u32 = 4096;
pub const MCAN_ILS_TEFWL_POS: u32 = 13;
pub const MCAN_ILS_TEFWL: u32 = 8192;
pub const MCAN_ILS_TEFFL_POS: u32 = 14;
pub const MCAN_ILS_TEFFL: u32 = 16384;
pub const MCAN_ILS_TEFLL_POS: u32 = 15;
pub const MCAN_ILS_TEFLL: u32 = 32768;
pub const MCAN_ILS_TSWL_POS: u32 = 16;
pub const MCAN_ILS_TSWL: u32 = 65536;
pub const MCAN_ILS_MRAFL_POS: u32 = 17;
pub const MCAN_ILS_MRAFL: u32 = 131072;
pub const MCAN_ILS_TOOL_POS: u32 = 18;
pub const MCAN_ILS_TOOL: u32 = 262144;
pub const MCAN_ILS_DRXL_POS: u32 = 19;
pub const MCAN_ILS_DRXL: u32 = 524288;
pub const MCAN_ILS_BECL_POS: u32 = 20;
pub const MCAN_ILS_BECL: u32 = 1048576;
pub const MCAN_ILS_BEUL_POS: u32 = 21;
pub const MCAN_ILS_BEUL: u32 = 2097152;
pub const MCAN_ILS_ELOL_POS: u32 = 22;
pub const MCAN_ILS_ELOL: u32 = 4194304;
pub const MCAN_ILS_EPL_POS: u32 = 23;
pub const MCAN_ILS_EPL: u32 = 8388608;
pub const MCAN_ILS_EWL_POS: u32 = 24;
pub const MCAN_ILS_EWL: u32 = 16777216;
pub const MCAN_ILS_BOL_POS: u32 = 25;
pub const MCAN_ILS_BOL: u32 = 33554432;
pub const MCAN_ILS_WDIL_POS: u32 = 26;
pub const MCAN_ILS_WDIL: u32 = 67108864;
pub const MCAN_ILS_PEAL_POS: u32 = 27;
pub const MCAN_ILS_PEAL: u32 = 134217728;
pub const MCAN_ILS_PEDL_POS: u32 = 28;
pub const MCAN_ILS_PEDL: u32 = 268435456;
pub const MCAN_ILS_ARAL_POS: u32 = 29;
pub const MCAN_ILS_ARAL: u32 = 536870912;
pub const MCAN_ILE_EINT0_POS: u32 = 0;
pub const MCAN_ILE_EINT0: u32 = 1;
pub const MCAN_ILE_EINT1_POS: u32 = 1;
pub const MCAN_ILE_EINT1: u32 = 2;
pub const MCAN_GFC_RRFE_POS: u32 = 0;
pub const MCAN_GFC_RRFE: u32 = 1;
pub const MCAN_GFC_RRFS_POS: u32 = 1;
pub const MCAN_GFC_RRFS: u32 = 2;
pub const MCAN_GFC_ANFE_POS: u32 = 2;
pub const MCAN_GFC_ANFE: u32 = 12;
pub const MCAN_GFC_ANFE_0: u32 = 4;
pub const MCAN_GFC_ANFE_1: u32 = 8;
pub const MCAN_GFC_ANFS_POS: u32 = 4;
pub const MCAN_GFC_ANFS: u32 = 48;
pub const MCAN_GFC_ANFS_0: u32 = 16;
pub const MCAN_GFC_ANFS_1: u32 = 32;
pub const MCAN_SIDFC_FLSSA_POS: u32 = 2;
pub const MCAN_SIDFC_FLSSA: u32 = 65532;
pub const MCAN_SIDFC_LSS_POS: u32 = 16;
pub const MCAN_SIDFC_LSS: u32 = 16711680;
pub const MCAN_XIDFC_FLESA_POS: u32 = 2;
pub const MCAN_XIDFC_FLESA: u32 = 65532;
pub const MCAN_XIDFC_LSE_POS: u32 = 16;
pub const MCAN_XIDFC_LSE: u32 = 8323072;
pub const MCAN_XIDAM_EIDM: u32 = 536870911;
pub const MCAN_HPMS_BIDX_POS: u32 = 0;
pub const MCAN_HPMS_BIDX: u32 = 63;
pub const MCAN_HPMS_MSI_POS: u32 = 6;
pub const MCAN_HPMS_MSI: u32 = 192;
pub const MCAN_HPMS_MSI_0: u32 = 64;
pub const MCAN_HPMS_MSI_1: u32 = 128;
pub const MCAN_HPMS_FIDX_POS: u32 = 8;
pub const MCAN_HPMS_FIDX: u32 = 32512;
pub const MCAN_HPMS_FLST_POS: u32 = 15;
pub const MCAN_HPMS_FLST: u32 = 32768;
pub const MCAN_NDAT1_ND0_POS: u32 = 0;
pub const MCAN_NDAT1_ND0: u32 = 1;
pub const MCAN_NDAT1_ND1_POS: u32 = 1;
pub const MCAN_NDAT1_ND1: u32 = 2;
pub const MCAN_NDAT1_ND2_POS: u32 = 2;
pub const MCAN_NDAT1_ND2: u32 = 4;
pub const MCAN_NDAT1_ND3_POS: u32 = 3;
pub const MCAN_NDAT1_ND3: u32 = 8;
pub const MCAN_NDAT1_ND4_POS: u32 = 4;
pub const MCAN_NDAT1_ND4: u32 = 16;
pub const MCAN_NDAT1_ND5_POS: u32 = 5;
pub const MCAN_NDAT1_ND5: u32 = 32;
pub const MCAN_NDAT1_ND6_POS: u32 = 6;
pub const MCAN_NDAT1_ND6: u32 = 64;
pub const MCAN_NDAT1_ND7_POS: u32 = 7;
pub const MCAN_NDAT1_ND7: u32 = 128;
pub const MCAN_NDAT1_ND8_POS: u32 = 8;
pub const MCAN_NDAT1_ND8: u32 = 256;
pub const MCAN_NDAT1_ND9_POS: u32 = 9;
pub const MCAN_NDAT1_ND9: u32 = 512;
pub const MCAN_NDAT1_ND10_POS: u32 = 10;
pub const MCAN_NDAT1_ND10: u32 = 1024;
pub const MCAN_NDAT1_ND11_POS: u32 = 11;
pub const MCAN_NDAT1_ND11: u32 = 2048;
pub const MCAN_NDAT1_ND12_POS: u32 = 12;
pub const MCAN_NDAT1_ND12: u32 = 4096;
pub const MCAN_NDAT1_ND13_POS: u32 = 13;
pub const MCAN_NDAT1_ND13: u32 = 8192;
pub const MCAN_NDAT1_ND14_POS: u32 = 14;
pub const MCAN_NDAT1_ND14: u32 = 16384;
pub const MCAN_NDAT1_ND15_POS: u32 = 15;
pub const MCAN_NDAT1_ND15: u32 = 32768;
pub const MCAN_NDAT1_ND16_POS: u32 = 16;
pub const MCAN_NDAT1_ND16: u32 = 65536;
pub const MCAN_NDAT1_ND17_POS: u32 = 17;
pub const MCAN_NDAT1_ND17: u32 = 131072;
pub const MCAN_NDAT1_ND18_POS: u32 = 18;
pub const MCAN_NDAT1_ND18: u32 = 262144;
pub const MCAN_NDAT1_ND19_POS: u32 = 19;
pub const MCAN_NDAT1_ND19: u32 = 524288;
pub const MCAN_NDAT1_ND20_POS: u32 = 20;
pub const MCAN_NDAT1_ND20: u32 = 1048576;
pub const MCAN_NDAT1_ND21_POS: u32 = 21;
pub const MCAN_NDAT1_ND21: u32 = 2097152;
pub const MCAN_NDAT1_ND22_POS: u32 = 22;
pub const MCAN_NDAT1_ND22: u32 = 4194304;
pub const MCAN_NDAT1_ND23_POS: u32 = 23;
pub const MCAN_NDAT1_ND23: u32 = 8388608;
pub const MCAN_NDAT1_ND24_POS: u32 = 24;
pub const MCAN_NDAT1_ND24: u32 = 16777216;
pub const MCAN_NDAT1_ND25_POS: u32 = 25;
pub const MCAN_NDAT1_ND25: u32 = 33554432;
pub const MCAN_NDAT1_ND26_POS: u32 = 26;
pub const MCAN_NDAT1_ND26: u32 = 67108864;
pub const MCAN_NDAT1_ND27_POS: u32 = 27;
pub const MCAN_NDAT1_ND27: u32 = 134217728;
pub const MCAN_NDAT1_ND28_POS: u32 = 28;
pub const MCAN_NDAT1_ND28: u32 = 268435456;
pub const MCAN_NDAT1_ND29_POS: u32 = 29;
pub const MCAN_NDAT1_ND29: u32 = 536870912;
pub const MCAN_NDAT1_ND30_POS: u32 = 30;
pub const MCAN_NDAT1_ND30: u32 = 1073741824;
pub const MCAN_NDAT1_ND31_POS: u32 = 31;
pub const MCAN_NDAT1_ND31: u32 = 2147483648;
pub const MCAN_NDAT2_ND32_POS: u32 = 0;
pub const MCAN_NDAT2_ND32: u32 = 1;
pub const MCAN_NDAT2_ND33_POS: u32 = 1;
pub const MCAN_NDAT2_ND33: u32 = 2;
pub const MCAN_NDAT2_ND34_POS: u32 = 2;
pub const MCAN_NDAT2_ND34: u32 = 4;
pub const MCAN_NDAT2_ND35_POS: u32 = 3;
pub const MCAN_NDAT2_ND35: u32 = 8;
pub const MCAN_NDAT2_ND36_POS: u32 = 4;
pub const MCAN_NDAT2_ND36: u32 = 16;
pub const MCAN_NDAT2_ND37_POS: u32 = 5;
pub const MCAN_NDAT2_ND37: u32 = 32;
pub const MCAN_NDAT2_ND38_POS: u32 = 6;
pub const MCAN_NDAT2_ND38: u32 = 64;
pub const MCAN_NDAT2_ND39_POS: u32 = 7;
pub const MCAN_NDAT2_ND39: u32 = 128;
pub const MCAN_NDAT2_ND40_POS: u32 = 8;
pub const MCAN_NDAT2_ND40: u32 = 256;
pub const MCAN_NDAT2_ND41_POS: u32 = 9;
pub const MCAN_NDAT2_ND41: u32 = 512;
pub const MCAN_NDAT2_ND42_POS: u32 = 10;
pub const MCAN_NDAT2_ND42: u32 = 1024;
pub const MCAN_NDAT2_ND43_POS: u32 = 11;
pub const MCAN_NDAT2_ND43: u32 = 2048;
pub const MCAN_NDAT2_ND44_POS: u32 = 12;
pub const MCAN_NDAT2_ND44: u32 = 4096;
pub const MCAN_NDAT2_ND45_POS: u32 = 13;
pub const MCAN_NDAT2_ND45: u32 = 8192;
pub const MCAN_NDAT2_ND46_POS: u32 = 14;
pub const MCAN_NDAT2_ND46: u32 = 16384;
pub const MCAN_NDAT2_ND47_POS: u32 = 15;
pub const MCAN_NDAT2_ND47: u32 = 32768;
pub const MCAN_NDAT2_ND48_POS: u32 = 16;
pub const MCAN_NDAT2_ND48: u32 = 65536;
pub const MCAN_NDAT2_ND49_POS: u32 = 17;
pub const MCAN_NDAT2_ND49: u32 = 131072;
pub const MCAN_NDAT2_ND50_POS: u32 = 18;
pub const MCAN_NDAT2_ND50: u32 = 262144;
pub const MCAN_NDAT2_ND51_POS: u32 = 19;
pub const MCAN_NDAT2_ND51: u32 = 524288;
pub const MCAN_NDAT2_ND52_POS: u32 = 20;
pub const MCAN_NDAT2_ND52: u32 = 1048576;
pub const MCAN_NDAT2_ND53_POS: u32 = 21;
pub const MCAN_NDAT2_ND53: u32 = 2097152;
pub const MCAN_NDAT2_ND54_POS: u32 = 22;
pub const MCAN_NDAT2_ND54: u32 = 4194304;
pub const MCAN_NDAT2_ND55_POS: u32 = 23;
pub const MCAN_NDAT2_ND55: u32 = 8388608;
pub const MCAN_NDAT2_ND56_POS: u32 = 24;
pub const MCAN_NDAT2_ND56: u32 = 16777216;
pub const MCAN_NDAT2_ND57_POS: u32 = 25;
pub const MCAN_NDAT2_ND57: u32 = 33554432;
pub const MCAN_NDAT2_ND58_POS: u32 = 26;
pub const MCAN_NDAT2_ND58: u32 = 67108864;
pub const MCAN_NDAT2_ND59_POS: u32 = 27;
pub const MCAN_NDAT2_ND59: u32 = 134217728;
pub const MCAN_NDAT2_ND60_POS: u32 = 28;
pub const MCAN_NDAT2_ND60: u32 = 268435456;
pub const MCAN_NDAT2_ND61_POS: u32 = 29;
pub const MCAN_NDAT2_ND61: u32 = 536870912;
pub const MCAN_NDAT2_ND62_POS: u32 = 30;
pub const MCAN_NDAT2_ND62: u32 = 1073741824;
pub const MCAN_NDAT2_ND63_POS: u32 = 31;
pub const MCAN_NDAT2_ND63: u32 = 2147483648;
pub const MCAN_RXF0C_F0SA_POS: u32 = 2;
pub const MCAN_RXF0C_F0SA: u32 = 65532;
pub const MCAN_RXF0C_F0S_POS: u32 = 16;
pub const MCAN_RXF0C_F0S: u32 = 8323072;
pub const MCAN_RXF0C_F0WM_POS: u32 = 24;
pub const MCAN_RXF0C_F0WM: u32 = 2130706432;
pub const MCAN_RXF0C_F0OM_POS: u32 = 31;
pub const MCAN_RXF0C_F0OM: u32 = 2147483648;
pub const MCAN_RXF0S_F0FL_POS: u32 = 0;
pub const MCAN_RXF0S_F0FL: u32 = 127;
pub const MCAN_RXF0S_F0GI_POS: u32 = 8;
pub const MCAN_RXF0S_F0GI: u32 = 16128;
pub const MCAN_RXF0S_F0PI_POS: u32 = 16;
pub const MCAN_RXF0S_F0PI: u32 = 4128768;
pub const MCAN_RXF0S_F0F_POS: u32 = 24;
pub const MCAN_RXF0S_F0F: u32 = 16777216;
pub const MCAN_RXF0S_RF0L_POS: u32 = 25;
pub const MCAN_RXF0S_RF0L: u32 = 33554432;
pub const MCAN_RXF0A_F0AI: u32 = 63;
pub const MCAN_RXBC_RBSA_POS: u32 = 2;
pub const MCAN_RXBC_RBSA: u32 = 65532;
pub const MCAN_RXF1C_F1SA_POS: u32 = 2;
pub const MCAN_RXF1C_F1SA: u32 = 65532;
pub const MCAN_RXF1C_F1S_POS: u32 = 16;
pub const MCAN_RXF1C_F1S: u32 = 8323072;
pub const MCAN_RXF1C_F1WM_POS: u32 = 24;
pub const MCAN_RXF1C_F1WM: u32 = 2130706432;
pub const MCAN_RXF1C_F1OM_POS: u32 = 31;
pub const MCAN_RXF1C_F1OM: u32 = 2147483648;
pub const MCAN_RXF1S_F1FL_POS: u32 = 0;
pub const MCAN_RXF1S_F1FL: u32 = 127;
pub const MCAN_RXF1S_F1GI_POS: u32 = 8;
pub const MCAN_RXF1S_F1GI: u32 = 16128;
pub const MCAN_RXF1S_F1PI_POS: u32 = 16;
pub const MCAN_RXF1S_F1PI: u32 = 4128768;
pub const MCAN_RXF1S_F1F_POS: u32 = 24;
pub const MCAN_RXF1S_F1F: u32 = 16777216;
pub const MCAN_RXF1S_RF1L_POS: u32 = 25;
pub const MCAN_RXF1S_RF1L: u32 = 33554432;
pub const MCAN_RXF1S_DMS_POS: u32 = 30;
pub const MCAN_RXF1S_DMS: u32 = 3221225472;
pub const MCAN_RXF1S_DMS_0: u32 = 1073741824;
pub const MCAN_RXF1S_DMS_1: u32 = 2147483648;
pub const MCAN_RXF1A_F1AI: u32 = 63;
pub const MCAN_RXESC_F0DS_POS: u32 = 0;
pub const MCAN_RXESC_F0DS: u32 = 7;
pub const MCAN_RXESC_F1DS_POS: u32 = 4;
pub const MCAN_RXESC_F1DS: u32 = 112;
pub const MCAN_RXESC_RBDS_POS: u32 = 8;
pub const MCAN_RXESC_RBDS: u32 = 1792;
pub const MCAN_TXBC_TBSA_POS: u32 = 2;
pub const MCAN_TXBC_TBSA: u32 = 65532;
pub const MCAN_TXBC_NDTB_POS: u32 = 16;
pub const MCAN_TXBC_NDTB: u32 = 4128768;
pub const MCAN_TXBC_TFQS_POS: u32 = 24;
pub const MCAN_TXBC_TFQS: u32 = 1056964608;
pub const MCAN_TXBC_TFQM_POS: u32 = 30;
pub const MCAN_TXBC_TFQM: u32 = 1073741824;
pub const MCAN_TXFQS_TFFL_POS: u32 = 0;
pub const MCAN_TXFQS_TFFL: u32 = 63;
pub const MCAN_TXFQS_TFGI_POS: u32 = 8;
pub const MCAN_TXFQS_TFGI: u32 = 7936;
pub const MCAN_TXFQS_TFQPI_POS: u32 = 16;
pub const MCAN_TXFQS_TFQPI: u32 = 2031616;
pub const MCAN_TXFQS_TFQF_POS: u32 = 21;
pub const MCAN_TXFQS_TFQF: u32 = 2097152;
pub const MCAN_TXESC_TBDS: u32 = 7;
pub const MCAN_TXBRP_TRP0_POS: u32 = 0;
pub const MCAN_TXBRP_TRP0: u32 = 1;
pub const MCAN_TXBRP_TRP1_POS: u32 = 1;
pub const MCAN_TXBRP_TRP1: u32 = 2;
pub const MCAN_TXBRP_TRP2_POS: u32 = 2;
pub const MCAN_TXBRP_TRP2: u32 = 4;
pub const MCAN_TXBRP_TRP3_POS: u32 = 3;
pub const MCAN_TXBRP_TRP3: u32 = 8;
pub const MCAN_TXBRP_TRP4_POS: u32 = 4;
pub const MCAN_TXBRP_TRP4: u32 = 16;
pub const MCAN_TXBRP_TRP5_POS: u32 = 5;
pub const MCAN_TXBRP_TRP5: u32 = 32;
pub const MCAN_TXBRP_TRP6_POS: u32 = 6;
pub const MCAN_TXBRP_TRP6: u32 = 64;
pub const MCAN_TXBRP_TRP7_POS: u32 = 7;
pub const MCAN_TXBRP_TRP7: u32 = 128;
pub const MCAN_TXBRP_TRP8_POS: u32 = 8;
pub const MCAN_TXBRP_TRP8: u32 = 256;
pub const MCAN_TXBRP_TRP9_POS: u32 = 9;
pub const MCAN_TXBRP_TRP9: u32 = 512;
pub const MCAN_TXBRP_TRP10_POS: u32 = 10;
pub const MCAN_TXBRP_TRP10: u32 = 1024;
pub const MCAN_TXBRP_TRP11_POS: u32 = 11;
pub const MCAN_TXBRP_TRP11: u32 = 2048;
pub const MCAN_TXBRP_TRP12_POS: u32 = 12;
pub const MCAN_TXBRP_TRP12: u32 = 4096;
pub const MCAN_TXBRP_TRP13_POS: u32 = 13;
pub const MCAN_TXBRP_TRP13: u32 = 8192;
pub const MCAN_TXBRP_TRP14_POS: u32 = 14;
pub const MCAN_TXBRP_TRP14: u32 = 16384;
pub const MCAN_TXBRP_TRP15_POS: u32 = 15;
pub const MCAN_TXBRP_TRP15: u32 = 32768;
pub const MCAN_TXBRP_TRP16_POS: u32 = 16;
pub const MCAN_TXBRP_TRP16: u32 = 65536;
pub const MCAN_TXBRP_TRP17_POS: u32 = 17;
pub const MCAN_TXBRP_TRP17: u32 = 131072;
pub const MCAN_TXBRP_TRP18_POS: u32 = 18;
pub const MCAN_TXBRP_TRP18: u32 = 262144;
pub const MCAN_TXBRP_TRP19_POS: u32 = 19;
pub const MCAN_TXBRP_TRP19: u32 = 524288;
pub const MCAN_TXBRP_TRP20_POS: u32 = 20;
pub const MCAN_TXBRP_TRP20: u32 = 1048576;
pub const MCAN_TXBRP_TRP21_POS: u32 = 21;
pub const MCAN_TXBRP_TRP21: u32 = 2097152;
pub const MCAN_TXBRP_TRP22_POS: u32 = 22;
pub const MCAN_TXBRP_TRP22: u32 = 4194304;
pub const MCAN_TXBRP_TRP23_POS: u32 = 23;
pub const MCAN_TXBRP_TRP23: u32 = 8388608;
pub const MCAN_TXBRP_TRP24_POS: u32 = 24;
pub const MCAN_TXBRP_TRP24: u32 = 16777216;
pub const MCAN_TXBRP_TRP25_POS: u32 = 25;
pub const MCAN_TXBRP_TRP25: u32 = 33554432;
pub const MCAN_TXBRP_TRP26_POS: u32 = 26;
pub const MCAN_TXBRP_TRP26: u32 = 67108864;
pub const MCAN_TXBRP_TRP27_POS: u32 = 27;
pub const MCAN_TXBRP_TRP27: u32 = 134217728;
pub const MCAN_TXBRP_TRP28_POS: u32 = 28;
pub const MCAN_TXBRP_TRP28: u32 = 268435456;
pub const MCAN_TXBRP_TRP29_POS: u32 = 29;
pub const MCAN_TXBRP_TRP29: u32 = 536870912;
pub const MCAN_TXBRP_TRP30_POS: u32 = 30;
pub const MCAN_TXBRP_TRP30: u32 = 1073741824;
pub const MCAN_TXBRP_TRP31_POS: u32 = 31;
pub const MCAN_TXBRP_TRP31: u32 = 2147483648;
pub const MCAN_TXBAR_AR0_POS: u32 = 0;
pub const MCAN_TXBAR_AR0: u32 = 1;
pub const MCAN_TXBAR_AR1_POS: u32 = 1;
pub const MCAN_TXBAR_AR1: u32 = 2;
pub const MCAN_TXBAR_AR2_POS: u32 = 2;
pub const MCAN_TXBAR_AR2: u32 = 4;
pub const MCAN_TXBAR_AR3_POS: u32 = 3;
pub const MCAN_TXBAR_AR3: u32 = 8;
pub const MCAN_TXBAR_AR4_POS: u32 = 4;
pub const MCAN_TXBAR_AR4: u32 = 16;
pub const MCAN_TXBAR_AR5_POS: u32 = 5;
pub const MCAN_TXBAR_AR5: u32 = 32;
pub const MCAN_TXBAR_AR6_POS: u32 = 6;
pub const MCAN_TXBAR_AR6: u32 = 64;
pub const MCAN_TXBAR_AR7_POS: u32 = 7;
pub const MCAN_TXBAR_AR7: u32 = 128;
pub const MCAN_TXBAR_AR8_POS: u32 = 8;
pub const MCAN_TXBAR_AR8: u32 = 256;
pub const MCAN_TXBAR_AR9_POS: u32 = 9;
pub const MCAN_TXBAR_AR9: u32 = 512;
pub const MCAN_TXBAR_AR10_POS: u32 = 10;
pub const MCAN_TXBAR_AR10: u32 = 1024;
pub const MCAN_TXBAR_AR11_POS: u32 = 11;
pub const MCAN_TXBAR_AR11: u32 = 2048;
pub const MCAN_TXBAR_AR12_POS: u32 = 12;
pub const MCAN_TXBAR_AR12: u32 = 4096;
pub const MCAN_TXBAR_AR13_POS: u32 = 13;
pub const MCAN_TXBAR_AR13: u32 = 8192;
pub const MCAN_TXBAR_AR14_POS: u32 = 14;
pub const MCAN_TXBAR_AR14: u32 = 16384;
pub const MCAN_TXBAR_AR15_POS: u32 = 15;
pub const MCAN_TXBAR_AR15: u32 = 32768;
pub const MCAN_TXBAR_AR16_POS: u32 = 16;
pub const MCAN_TXBAR_AR16: u32 = 65536;
pub const MCAN_TXBAR_AR17_POS: u32 = 17;
pub const MCAN_TXBAR_AR17: u32 = 131072;
pub const MCAN_TXBAR_AR18_POS: u32 = 18;
pub const MCAN_TXBAR_AR18: u32 = 262144;
pub const MCAN_TXBAR_AR19_POS: u32 = 19;
pub const MCAN_TXBAR_AR19: u32 = 524288;
pub const MCAN_TXBAR_AR20_POS: u32 = 20;
pub const MCAN_TXBAR_AR20: u32 = 1048576;
pub const MCAN_TXBAR_AR21_POS: u32 = 21;
pub const MCAN_TXBAR_AR21: u32 = 2097152;
pub const MCAN_TXBAR_AR22_POS: u32 = 22;
pub const MCAN_TXBAR_AR22: u32 = 4194304;
pub const MCAN_TXBAR_AR23_POS: u32 = 23;
pub const MCAN_TXBAR_AR23: u32 = 8388608;
pub const MCAN_TXBAR_AR24_POS: u32 = 24;
pub const MCAN_TXBAR_AR24: u32 = 16777216;
pub const MCAN_TXBAR_AR25_POS: u32 = 25;
pub const MCAN_TXBAR_AR25: u32 = 33554432;
pub const MCAN_TXBAR_AR26_POS: u32 = 26;
pub const MCAN_TXBAR_AR26: u32 = 67108864;
pub const MCAN_TXBAR_AR27_POS: u32 = 27;
pub const MCAN_TXBAR_AR27: u32 = 134217728;
pub const MCAN_TXBAR_AR28_POS: u32 = 28;
pub const MCAN_TXBAR_AR28: u32 = 268435456;
pub const MCAN_TXBAR_AR29_POS: u32 = 29;
pub const MCAN_TXBAR_AR29: u32 = 536870912;
pub const MCAN_TXBAR_AR30_POS: u32 = 30;
pub const MCAN_TXBAR_AR30: u32 = 1073741824;
pub const MCAN_TXBAR_AR31_POS: u32 = 31;
pub const MCAN_TXBAR_AR31: u32 = 2147483648;
pub const MCAN_TXBCR_CR0_POS: u32 = 0;
pub const MCAN_TXBCR_CR0: u32 = 1;
pub const MCAN_TXBCR_CR1_POS: u32 = 1;
pub const MCAN_TXBCR_CR1: u32 = 2;
pub const MCAN_TXBCR_CR2_POS: u32 = 2;
pub const MCAN_TXBCR_CR2: u32 = 4;
pub const MCAN_TXBCR_CR3_POS: u32 = 3;
pub const MCAN_TXBCR_CR3: u32 = 8;
pub const MCAN_TXBCR_CR4_POS: u32 = 4;
pub const MCAN_TXBCR_CR4: u32 = 16;
pub const MCAN_TXBCR_CR5_POS: u32 = 5;
pub const MCAN_TXBCR_CR5: u32 = 32;
pub const MCAN_TXBCR_CR6_POS: u32 = 6;
pub const MCAN_TXBCR_CR6: u32 = 64;
pub const MCAN_TXBCR_CR7_POS: u32 = 7;
pub const MCAN_TXBCR_CR7: u32 = 128;
pub const MCAN_TXBCR_CR8_POS: u32 = 8;
pub const MCAN_TXBCR_CR8: u32 = 256;
pub const MCAN_TXBCR_CR9_POS: u32 = 9;
pub const MCAN_TXBCR_CR9: u32 = 512;
pub const MCAN_TXBCR_CR10_POS: u32 = 10;
pub const MCAN_TXBCR_CR10: u32 = 1024;
pub const MCAN_TXBCR_CR11_POS: u32 = 11;
pub const MCAN_TXBCR_CR11: u32 = 2048;
pub const MCAN_TXBCR_CR12_POS: u32 = 12;
pub const MCAN_TXBCR_CR12: u32 = 4096;
pub const MCAN_TXBCR_CR13_POS: u32 = 13;
pub const MCAN_TXBCR_CR13: u32 = 8192;
pub const MCAN_TXBCR_CR14_POS: u32 = 14;
pub const MCAN_TXBCR_CR14: u32 = 16384;
pub const MCAN_TXBCR_CR15_POS: u32 = 15;
pub const MCAN_TXBCR_CR15: u32 = 32768;
pub const MCAN_TXBCR_CR16_POS: u32 = 16;
pub const MCAN_TXBCR_CR16: u32 = 65536;
pub const MCAN_TXBCR_CR17_POS: u32 = 17;
pub const MCAN_TXBCR_CR17: u32 = 131072;
pub const MCAN_TXBCR_CR18_POS: u32 = 18;
pub const MCAN_TXBCR_CR18: u32 = 262144;
pub const MCAN_TXBCR_CR19_POS: u32 = 19;
pub const MCAN_TXBCR_CR19: u32 = 524288;
pub const MCAN_TXBCR_CR20_POS: u32 = 20;
pub const MCAN_TXBCR_CR20: u32 = 1048576;
pub const MCAN_TXBCR_CR21_POS: u32 = 21;
pub const MCAN_TXBCR_CR21: u32 = 2097152;
pub const MCAN_TXBCR_CR22_POS: u32 = 22;
pub const MCAN_TXBCR_CR22: u32 = 4194304;
pub const MCAN_TXBCR_CR23_POS: u32 = 23;
pub const MCAN_TXBCR_CR23: u32 = 8388608;
pub const MCAN_TXBCR_CR24_POS: u32 = 24;
pub const MCAN_TXBCR_CR24: u32 = 16777216;
pub const MCAN_TXBCR_CR25_POS: u32 = 25;
pub const MCAN_TXBCR_CR25: u32 = 33554432;
pub const MCAN_TXBCR_CR26_POS: u32 = 26;
pub const MCAN_TXBCR_CR26: u32 = 67108864;
pub const MCAN_TXBCR_CR27_POS: u32 = 27;
pub const MCAN_TXBCR_CR27: u32 = 134217728;
pub const MCAN_TXBCR_CR28_POS: u32 = 28;
pub const MCAN_TXBCR_CR28: u32 = 268435456;
pub const MCAN_TXBCR_CR29_POS: u32 = 29;
pub const MCAN_TXBCR_CR29: u32 = 536870912;
pub const MCAN_TXBCR_CR30_POS: u32 = 30;
pub const MCAN_TXBCR_CR30: u32 = 1073741824;
pub const MCAN_TXBCR_CR31_POS: u32 = 31;
pub const MCAN_TXBCR_CR31: u32 = 2147483648;
pub const MCAN_TXBTO_TO0_POS: u32 = 0;
pub const MCAN_TXBTO_TO0: u32 = 1;
pub const MCAN_TXBTO_TO1_POS: u32 = 1;
pub const MCAN_TXBTO_TO1: u32 = 2;
pub const MCAN_TXBTO_TO2_POS: u32 = 2;
pub const MCAN_TXBTO_TO2: u32 = 4;
pub const MCAN_TXBTO_TO3_POS: u32 = 3;
pub const MCAN_TXBTO_TO3: u32 = 8;
pub const MCAN_TXBTO_TO4_POS: u32 = 4;
pub const MCAN_TXBTO_TO4: u32 = 16;
pub const MCAN_TXBTO_TO5_POS: u32 = 5;
pub const MCAN_TXBTO_TO5: u32 = 32;
pub const MCAN_TXBTO_TO6_POS: u32 = 6;
pub const MCAN_TXBTO_TO6: u32 = 64;
pub const MCAN_TXBTO_TO7_POS: u32 = 7;
pub const MCAN_TXBTO_TO7: u32 = 128;
pub const MCAN_TXBTO_TO8_POS: u32 = 8;
pub const MCAN_TXBTO_TO8: u32 = 256;
pub const MCAN_TXBTO_TO9_POS: u32 = 9;
pub const MCAN_TXBTO_TO9: u32 = 512;
pub const MCAN_TXBTO_TO10_POS: u32 = 10;
pub const MCAN_TXBTO_TO10: u32 = 1024;
pub const MCAN_TXBTO_TO11_POS: u32 = 11;
pub const MCAN_TXBTO_TO11: u32 = 2048;
pub const MCAN_TXBTO_TO12_POS: u32 = 12;
pub const MCAN_TXBTO_TO12: u32 = 4096;
pub const MCAN_TXBTO_TO13_POS: u32 = 13;
pub const MCAN_TXBTO_TO13: u32 = 8192;
pub const MCAN_TXBTO_TO14_POS: u32 = 14;
pub const MCAN_TXBTO_TO14: u32 = 16384;
pub const MCAN_TXBTO_TO15_POS: u32 = 15;
pub const MCAN_TXBTO_TO15: u32 = 32768;
pub const MCAN_TXBTO_TO16_POS: u32 = 16;
pub const MCAN_TXBTO_TO16: u32 = 65536;
pub const MCAN_TXBTO_TO17_POS: u32 = 17;
pub const MCAN_TXBTO_TO17: u32 = 131072;
pub const MCAN_TXBTO_TO18_POS: u32 = 18;
pub const MCAN_TXBTO_TO18: u32 = 262144;
pub const MCAN_TXBTO_TO19_POS: u32 = 19;
pub const MCAN_TXBTO_TO19: u32 = 524288;
pub const MCAN_TXBTO_TO20_POS: u32 = 20;
pub const MCAN_TXBTO_TO20: u32 = 1048576;
pub const MCAN_TXBTO_TO21_POS: u32 = 21;
pub const MCAN_TXBTO_TO21: u32 = 2097152;
pub const MCAN_TXBTO_TO22_POS: u32 = 22;
pub const MCAN_TXBTO_TO22: u32 = 4194304;
pub const MCAN_TXBTO_TO23_POS: u32 = 23;
pub const MCAN_TXBTO_TO23: u32 = 8388608;
pub const MCAN_TXBTO_TO24_POS: u32 = 24;
pub const MCAN_TXBTO_TO24: u32 = 16777216;
pub const MCAN_TXBTO_TO25_POS: u32 = 25;
pub const MCAN_TXBTO_TO25: u32 = 33554432;
pub const MCAN_TXBTO_TO26_POS: u32 = 26;
pub const MCAN_TXBTO_TO26: u32 = 67108864;
pub const MCAN_TXBTO_TO27_POS: u32 = 27;
pub const MCAN_TXBTO_TO27: u32 = 134217728;
pub const MCAN_TXBTO_TO28_POS: u32 = 28;
pub const MCAN_TXBTO_TO28: u32 = 268435456;
pub const MCAN_TXBTO_TO29_POS: u32 = 29;
pub const MCAN_TXBTO_TO29: u32 = 536870912;
pub const MCAN_TXBTO_TO30_POS: u32 = 30;
pub const MCAN_TXBTO_TO30: u32 = 1073741824;
pub const MCAN_TXBTO_TO31_POS: u32 = 31;
pub const MCAN_TXBTO_TO31: u32 = 2147483648;
pub const MCAN_TXBCF_CF0_POS: u32 = 0;
pub const MCAN_TXBCF_CF0: u32 = 1;
pub const MCAN_TXBCF_CF1_POS: u32 = 1;
pub const MCAN_TXBCF_CF1: u32 = 2;
pub const MCAN_TXBCF_CF2_POS: u32 = 2;
pub const MCAN_TXBCF_CF2: u32 = 4;
pub const MCAN_TXBCF_CF3_POS: u32 = 3;
pub const MCAN_TXBCF_CF3: u32 = 8;
pub const MCAN_TXBCF_CF4_POS: u32 = 4;
pub const MCAN_TXBCF_CF4: u32 = 16;
pub const MCAN_TXBCF_CF5_POS: u32 = 5;
pub const MCAN_TXBCF_CF5: u32 = 32;
pub const MCAN_TXBCF_CF6_POS: u32 = 6;
pub const MCAN_TXBCF_CF6: u32 = 64;
pub const MCAN_TXBCF_CF7_POS: u32 = 7;
pub const MCAN_TXBCF_CF7: u32 = 128;
pub const MCAN_TXBCF_CF8_POS: u32 = 8;
pub const MCAN_TXBCF_CF8: u32 = 256;
pub const MCAN_TXBCF_CF9_POS: u32 = 9;
pub const MCAN_TXBCF_CF9: u32 = 512;
pub const MCAN_TXBCF_CF10_POS: u32 = 10;
pub const MCAN_TXBCF_CF10: u32 = 1024;
pub const MCAN_TXBCF_CF11_POS: u32 = 11;
pub const MCAN_TXBCF_CF11: u32 = 2048;
pub const MCAN_TXBCF_CF12_POS: u32 = 12;
pub const MCAN_TXBCF_CF12: u32 = 4096;
pub const MCAN_TXBCF_CF13_POS: u32 = 13;
pub const MCAN_TXBCF_CF13: u32 = 8192;
pub const MCAN_TXBCF_CF14_POS: u32 = 14;
pub const MCAN_TXBCF_CF14: u32 = 16384;
pub const MCAN_TXBCF_CF15_POS: u32 = 15;
pub const MCAN_TXBCF_CF15: u32 = 32768;
pub const MCAN_TXBCF_CF16_POS: u32 = 16;
pub const MCAN_TXBCF_CF16: u32 = 65536;
pub const MCAN_TXBCF_CF17_POS: u32 = 17;
pub const MCAN_TXBCF_CF17: u32 = 131072;
pub const MCAN_TXBCF_CF18_POS: u32 = 18;
pub const MCAN_TXBCF_CF18: u32 = 262144;
pub const MCAN_TXBCF_CF19_POS: u32 = 19;
pub const MCAN_TXBCF_CF19: u32 = 524288;
pub const MCAN_TXBCF_CF20_POS: u32 = 20;
pub const MCAN_TXBCF_CF20: u32 = 1048576;
pub const MCAN_TXBCF_CF21_POS: u32 = 21;
pub const MCAN_TXBCF_CF21: u32 = 2097152;
pub const MCAN_TXBCF_CF22_POS: u32 = 22;
pub const MCAN_TXBCF_CF22: u32 = 4194304;
pub const MCAN_TXBCF_CF23_POS: u32 = 23;
pub const MCAN_TXBCF_CF23: u32 = 8388608;
pub const MCAN_TXBCF_CF24_POS: u32 = 24;
pub const MCAN_TXBCF_CF24: u32 = 16777216;
pub const MCAN_TXBCF_CF25_POS: u32 = 25;
pub const MCAN_TXBCF_CF25: u32 = 33554432;
pub const MCAN_TXBCF_CF26_POS: u32 = 26;
pub const MCAN_TXBCF_CF26: u32 = 67108864;
pub const MCAN_TXBCF_CF27_POS: u32 = 27;
pub const MCAN_TXBCF_CF27: u32 = 134217728;
pub const MCAN_TXBCF_CF28_POS: u32 = 28;
pub const MCAN_TXBCF_CF28: u32 = 268435456;
pub const MCAN_TXBCF_CF29_POS: u32 = 29;
pub const MCAN_TXBCF_CF29: u32 = 536870912;
pub const MCAN_TXBCF_CF30_POS: u32 = 30;
pub const MCAN_TXBCF_CF30: u32 = 1073741824;
pub const MCAN_TXBCF_CF31_POS: u32 = 31;
pub const MCAN_TXBCF_CF31: u32 = 2147483648;
pub const MCAN_TXBTIE_TIE0_POS: u32 = 0;
pub const MCAN_TXBTIE_TIE0: u32 = 1;
pub const MCAN_TXBTIE_TIE1_POS: u32 = 1;
pub const MCAN_TXBTIE_TIE1: u32 = 2;
pub const MCAN_TXBTIE_TIE2_POS: u32 = 2;
pub const MCAN_TXBTIE_TIE2: u32 = 4;
pub const MCAN_TXBTIE_TIE3_POS: u32 = 3;
pub const MCAN_TXBTIE_TIE3: u32 = 8;
pub const MCAN_TXBTIE_TIE4_POS: u32 = 4;
pub const MCAN_TXBTIE_TIE4: u32 = 16;
pub const MCAN_TXBTIE_TIE5_POS: u32 = 5;
pub const MCAN_TXBTIE_TIE5: u32 = 32;
pub const MCAN_TXBTIE_TIE6_POS: u32 = 6;
pub const MCAN_TXBTIE_TIE6: u32 = 64;
pub const MCAN_TXBTIE_TIE7_POS: u32 = 7;
pub const MCAN_TXBTIE_TIE7: u32 = 128;
pub const MCAN_TXBTIE_TIE8_POS: u32 = 8;
pub const MCAN_TXBTIE_TIE8: u32 = 256;
pub const MCAN_TXBTIE_TIE9_POS: u32 = 9;
pub const MCAN_TXBTIE_TIE9: u32 = 512;
pub const MCAN_TXBTIE_TIE10_POS: u32 = 10;
pub const MCAN_TXBTIE_TIE10: u32 = 1024;
pub const MCAN_TXBTIE_TIE11_POS: u32 = 11;
pub const MCAN_TXBTIE_TIE11: u32 = 2048;
pub const MCAN_TXBTIE_TIE12_POS: u32 = 12;
pub const MCAN_TXBTIE_TIE12: u32 = 4096;
pub const MCAN_TXBTIE_TIE13_POS: u32 = 13;
pub const MCAN_TXBTIE_TIE13: u32 = 8192;
pub const MCAN_TXBTIE_TIE14_POS: u32 = 14;
pub const MCAN_TXBTIE_TIE14: u32 = 16384;
pub const MCAN_TXBTIE_TIE15_POS: u32 = 15;
pub const MCAN_TXBTIE_TIE15: u32 = 32768;
pub const MCAN_TXBTIE_TIE16_POS: u32 = 16;
pub const MCAN_TXBTIE_TIE16: u32 = 65536;
pub const MCAN_TXBTIE_TIE17_POS: u32 = 17;
pub const MCAN_TXBTIE_TIE17: u32 = 131072;
pub const MCAN_TXBTIE_TIE18_POS: u32 = 18;
pub const MCAN_TXBTIE_TIE18: u32 = 262144;
pub const MCAN_TXBTIE_TIE19_POS: u32 = 19;
pub const MCAN_TXBTIE_TIE19: u32 = 524288;
pub const MCAN_TXBTIE_TIE20_POS: u32 = 20;
pub const MCAN_TXBTIE_TIE20: u32 = 1048576;
pub const MCAN_TXBTIE_TIE21_POS: u32 = 21;
pub const MCAN_TXBTIE_TIE21: u32 = 2097152;
pub const MCAN_TXBTIE_TIE22_POS: u32 = 22;
pub const MCAN_TXBTIE_TIE22: u32 = 4194304;
pub const MCAN_TXBTIE_TIE23_POS: u32 = 23;
pub const MCAN_TXBTIE_TIE23: u32 = 8388608;
pub const MCAN_TXBTIE_TIE24_POS: u32 = 24;
pub const MCAN_TXBTIE_TIE24: u32 = 16777216;
pub const MCAN_TXBTIE_TIE25_POS: u32 = 25;
pub const MCAN_TXBTIE_TIE25: u32 = 33554432;
pub const MCAN_TXBTIE_TIE26_POS: u32 = 26;
pub const MCAN_TXBTIE_TIE26: u32 = 67108864;
pub const MCAN_TXBTIE_TIE27_POS: u32 = 27;
pub const MCAN_TXBTIE_TIE27: u32 = 134217728;
pub const MCAN_TXBTIE_TIE28_POS: u32 = 28;
pub const MCAN_TXBTIE_TIE28: u32 = 268435456;
pub const MCAN_TXBTIE_TIE29_POS: u32 = 29;
pub const MCAN_TXBTIE_TIE29: u32 = 536870912;
pub const MCAN_TXBTIE_TIE30_POS: u32 = 30;
pub const MCAN_TXBTIE_TIE30: u32 = 1073741824;
pub const MCAN_TXBTIE_TIE31_POS: u32 = 31;
pub const MCAN_TXBTIE_TIE31: u32 = 2147483648;
pub const MCAN_TXBCIE_CFIE0_POS: u32 = 0;
pub const MCAN_TXBCIE_CFIE0: u32 = 1;
pub const MCAN_TXBCIE_CFIE1_POS: u32 = 1;
pub const MCAN_TXBCIE_CFIE1: u32 = 2;
pub const MCAN_TXBCIE_CFIE2_POS: u32 = 2;
pub const MCAN_TXBCIE_CFIE2: u32 = 4;
pub const MCAN_TXBCIE_CFIE3_POS: u32 = 3;
pub const MCAN_TXBCIE_CFIE3: u32 = 8;
pub const MCAN_TXBCIE_CFIE4_POS: u32 = 4;
pub const MCAN_TXBCIE_CFIE4: u32 = 16;
pub const MCAN_TXBCIE_CFIE5_POS: u32 = 5;
pub const MCAN_TXBCIE_CFIE5: u32 = 32;
pub const MCAN_TXBCIE_CFIE6_POS: u32 = 6;
pub const MCAN_TXBCIE_CFIE6: u32 = 64;
pub const MCAN_TXBCIE_CFIE7_POS: u32 = 7;
pub const MCAN_TXBCIE_CFIE7: u32 = 128;
pub const MCAN_TXBCIE_CFIE8_POS: u32 = 8;
pub const MCAN_TXBCIE_CFIE8: u32 = 256;
pub const MCAN_TXBCIE_CFIE9_POS: u32 = 9;
pub const MCAN_TXBCIE_CFIE9: u32 = 512;
pub const MCAN_TXBCIE_CFIE10_POS: u32 = 10;
pub const MCAN_TXBCIE_CFIE10: u32 = 1024;
pub const MCAN_TXBCIE_CFIE11_POS: u32 = 11;
pub const MCAN_TXBCIE_CFIE11: u32 = 2048;
pub const MCAN_TXBCIE_CFIE12_POS: u32 = 12;
pub const MCAN_TXBCIE_CFIE12: u32 = 4096;
pub const MCAN_TXBCIE_CFIE13_POS: u32 = 13;
pub const MCAN_TXBCIE_CFIE13: u32 = 8192;
pub const MCAN_TXBCIE_CFIE14_POS: u32 = 14;
pub const MCAN_TXBCIE_CFIE14: u32 = 16384;
pub const MCAN_TXBCIE_CFIE15_POS: u32 = 15;
pub const MCAN_TXBCIE_CFIE15: u32 = 32768;
pub const MCAN_TXBCIE_CFIE16_POS: u32 = 16;
pub const MCAN_TXBCIE_CFIE16: u32 = 65536;
pub const MCAN_TXBCIE_CFIE17_POS: u32 = 17;
pub const MCAN_TXBCIE_CFIE17: u32 = 131072;
pub const MCAN_TXBCIE_CFIE18_POS: u32 = 18;
pub const MCAN_TXBCIE_CFIE18: u32 = 262144;
pub const MCAN_TXBCIE_CFIE19_POS: u32 = 19;
pub const MCAN_TXBCIE_CFIE19: u32 = 524288;
pub const MCAN_TXBCIE_CFIE20_POS: u32 = 20;
pub const MCAN_TXBCIE_CFIE20: u32 = 1048576;
pub const MCAN_TXBCIE_CFIE21_POS: u32 = 21;
pub const MCAN_TXBCIE_CFIE21: u32 = 2097152;
pub const MCAN_TXBCIE_CFIE22_POS: u32 = 22;
pub const MCAN_TXBCIE_CFIE22: u32 = 4194304;
pub const MCAN_TXBCIE_CFIE23_POS: u32 = 23;
pub const MCAN_TXBCIE_CFIE23: u32 = 8388608;
pub const MCAN_TXBCIE_CFIE24_POS: u32 = 24;
pub const MCAN_TXBCIE_CFIE24: u32 = 16777216;
pub const MCAN_TXBCIE_CFIE25_POS: u32 = 25;
pub const MCAN_TXBCIE_CFIE25: u32 = 33554432;
pub const MCAN_TXBCIE_CFIE26_POS: u32 = 26;
pub const MCAN_TXBCIE_CFIE26: u32 = 67108864;
pub const MCAN_TXBCIE_CFIE27_POS: u32 = 27;
pub const MCAN_TXBCIE_CFIE27: u32 = 134217728;
pub const MCAN_TXBCIE_CFIE28_POS: u32 = 28;
pub const MCAN_TXBCIE_CFIE28: u32 = 268435456;
pub const MCAN_TXBCIE_CFIE29_POS: u32 = 29;
pub const MCAN_TXBCIE_CFIE29: u32 = 536870912;
pub const MCAN_TXBCIE_CFIE30_POS: u32 = 30;
pub const MCAN_TXBCIE_CFIE30: u32 = 1073741824;
pub const MCAN_TXBCIE_CFIE31_POS: u32 = 31;
pub const MCAN_TXBCIE_CFIE31: u32 = 2147483648;
pub const MCAN_TXEFC_EFSA_POS: u32 = 2;
pub const MCAN_TXEFC_EFSA: u32 = 65532;
pub const MCAN_TXEFC_EFS_POS: u32 = 16;
pub const MCAN_TXEFC_EFS: u32 = 4128768;
pub const MCAN_TXEFC_EFWM_POS: u32 = 24;
pub const MCAN_TXEFC_EFWM: u32 = 1056964608;
pub const MCAN_TXEFS_EFFL_POS: u32 = 0;
pub const MCAN_TXEFS_EFFL: u32 = 63;
pub const MCAN_TXEFS_EFGI_POS: u32 = 8;
pub const MCAN_TXEFS_EFGI: u32 = 7936;
pub const MCAN_TXEFS_EFPI_POS: u32 = 16;
pub const MCAN_TXEFS_EFPI: u32 = 2031616;
pub const MCAN_TXEFS_EFF_POS: u32 = 24;
pub const MCAN_TXEFS_EFF: u32 = 16777216;
pub const MCAN_TXEFS_TEFL_POS: u32 = 25;
pub const MCAN_TXEFS_TEFL: u32 = 33554432;
pub const MCAN_TXEFA_EFAI: u32 = 31;
pub const MPU_RGD_MPURGSIZE_POS: u32 = 0;
pub const MPU_RGD_MPURGSIZE: u32 = 31;
pub const MPU_RGD_MPURGADDR_POS: u32 = 5;
pub const MPU_RGD_MPURGADDR: u32 = 4294967264;
pub const MPU_SR_SMPU1EAF_POS: u32 = 0;
pub const MPU_SR_SMPU1EAF: u32 = 1;
pub const MPU_SR_SMPU2EAF_POS: u32 = 1;
pub const MPU_SR_SMPU2EAF: u32 = 2;
pub const MPU_SR_PSPEF_POS: u32 = 2;
pub const MPU_SR_PSPEF: u32 = 4;
pub const MPU_SR_MSPEF_POS: u32 = 3;
pub const MPU_SR_MSPEF: u32 = 8;
pub const MPU_ECLR_SMPU1ECLR_POS: u32 = 0;
pub const MPU_ECLR_SMPU1ECLR: u32 = 1;
pub const MPU_ECLR_SMPU2ECLR_POS: u32 = 1;
pub const MPU_ECLR_SMPU2ECLR: u32 = 2;
pub const MPU_ECLR_PSPECLR_POS: u32 = 2;
pub const MPU_ECLR_PSPECLR: u32 = 4;
pub const MPU_ECLR_MSPECLR_POS: u32 = 3;
pub const MPU_ECLR_MSPECLR: u32 = 8;
pub const MPU_WP_MPUWE_POS: u32 = 0;
pub const MPU_WP_MPUWE: u32 = 1;
pub const MPU_WP_WKEY_POS: u32 = 1;
pub const MPU_WP_WKEY: u32 = 65534;
pub const MPU_IPPR_AESRDP_POS: u32 = 0;
pub const MPU_IPPR_AESRDP: u32 = 1;
pub const MPU_IPPR_AESWRP_POS: u32 = 1;
pub const MPU_IPPR_AESWRP: u32 = 2;
pub const MPU_IPPR_HASHRDP_POS: u32 = 2;
pub const MPU_IPPR_HASHRDP: u32 = 4;
pub const MPU_IPPR_HASHWRP_POS: u32 = 3;
pub const MPU_IPPR_HASHWRP: u32 = 8;
pub const MPU_IPPR_TRNGRDP_POS: u32 = 4;
pub const MPU_IPPR_TRNGRDP: u32 = 16;
pub const MPU_IPPR_TRNGWRP_POS: u32 = 5;
pub const MPU_IPPR_TRNGWRP: u32 = 32;
pub const MPU_IPPR_CRCRDP_POS: u32 = 6;
pub const MPU_IPPR_CRCRDP: u32 = 64;
pub const MPU_IPPR_CRCWRP_POS: u32 = 7;
pub const MPU_IPPR_CRCWRP: u32 = 128;
pub const MPU_IPPR_EFMRDP_POS: u32 = 8;
pub const MPU_IPPR_EFMRDP: u32 = 256;
pub const MPU_IPPR_EFMWRP_POS: u32 = 9;
pub const MPU_IPPR_EFMWRP: u32 = 512;
pub const MPU_IPPR_WDTRDP_POS: u32 = 12;
pub const MPU_IPPR_WDTRDP: u32 = 4096;
pub const MPU_IPPR_WDTWRP_POS: u32 = 13;
pub const MPU_IPPR_WDTWRP: u32 = 8192;
pub const MPU_IPPR_SWDTRDP_POS: u32 = 14;
pub const MPU_IPPR_SWDTRDP: u32 = 16384;
pub const MPU_IPPR_SWDTWRP_POS: u32 = 15;
pub const MPU_IPPR_SWDTWRP: u32 = 32768;
pub const MPU_IPPR_BKSRAMRDP_POS: u32 = 16;
pub const MPU_IPPR_BKSRAMRDP: u32 = 65536;
pub const MPU_IPPR_BKSRAMWRP_POS: u32 = 17;
pub const MPU_IPPR_BKSRAMWRP: u32 = 131072;
pub const MPU_IPPR_RTCRDP_POS: u32 = 18;
pub const MPU_IPPR_RTCRDP: u32 = 262144;
pub const MPU_IPPR_RTCWRP_POS: u32 = 19;
pub const MPU_IPPR_RTCWRP: u32 = 524288;
pub const MPU_IPPR_DMPURDP_POS: u32 = 20;
pub const MPU_IPPR_DMPURDP: u32 = 1048576;
pub const MPU_IPPR_DMPUWRP_POS: u32 = 21;
pub const MPU_IPPR_DMPUWRP: u32 = 2097152;
pub const MPU_IPPR_SRAMCRDP_POS: u32 = 22;
pub const MPU_IPPR_SRAMCRDP: u32 = 4194304;
pub const MPU_IPPR_SRAMCWRP_POS: u32 = 23;
pub const MPU_IPPR_SRAMCWRP: u32 = 8388608;
pub const MPU_IPPR_INTCRDP_POS: u32 = 24;
pub const MPU_IPPR_INTCRDP: u32 = 16777216;
pub const MPU_IPPR_INTCWRP_POS: u32 = 25;
pub const MPU_IPPR_INTCWRP: u32 = 33554432;
pub const MPU_IPPR_SYSCRDP_POS: u32 = 26;
pub const MPU_IPPR_SYSCRDP: u32 = 67108864;
pub const MPU_IPPR_SYSCWRP_POS: u32 = 27;
pub const MPU_IPPR_SYSCWRP: u32 = 134217728;
pub const MPU_IPPR_MSTPRDP_POS: u32 = 28;
pub const MPU_IPPR_MSTPRDP: u32 = 268435456;
pub const MPU_IPPR_MSPTWRP_POS: u32 = 29;
pub const MPU_IPPR_MSPTWRP: u32 = 536870912;
pub const MPU_IPPR_BUSERRE_POS: u32 = 31;
pub const MPU_IPPR_BUSERRE: u32 = 2147483648;
pub const MPU_MSPPBA_MSPPBA_POS: u32 = 2;
pub const MPU_MSPPBA_MSPPBA: u32 = 4294967292;
pub const MPU_MSPPCTL_MSPPSIZE_POS: u32 = 2;
pub const MPU_MSPPCTL_MSPPSIZE: u32 = 65532;
pub const MPU_MSPPCTL_MSPPACT_POS: u32 = 30;
pub const MPU_MSPPCTL_MSPPACT: u32 = 1073741824;
pub const MPU_MSPPCTL_MSPPE_POS: u32 = 31;
pub const MPU_MSPPCTL_MSPPE: u32 = 2147483648;
pub const MPU_PSPPBA_PSPPBA_POS: u32 = 2;
pub const MPU_PSPPBA_PSPPBA: u32 = 4294967292;
pub const MPU_PSPPCTL_PSPPSIZE_POS: u32 = 2;
pub const MPU_PSPPCTL_PSPPSIZE: u32 = 65532;
pub const MPU_PSPPCTL_PSPPACT_POS: u32 = 30;
pub const MPU_PSPPCTL_PSPPACT: u32 = 1073741824;
pub const MPU_PSPPCTL_PSPPE_POS: u32 = 31;
pub const MPU_PSPPCTL_PSPPE: u32 = 2147483648;
pub const MPU_SRGE_RG0E_POS: u32 = 0;
pub const MPU_SRGE_RG0E: u32 = 1;
pub const MPU_SRGE_RG1E_POS: u32 = 1;
pub const MPU_SRGE_RG1E: u32 = 2;
pub const MPU_SRGE_RG2E_POS: u32 = 2;
pub const MPU_SRGE_RG2E: u32 = 4;
pub const MPU_SRGE_RG3E_POS: u32 = 3;
pub const MPU_SRGE_RG3E: u32 = 8;
pub const MPU_SRGE_RG4E_POS: u32 = 4;
pub const MPU_SRGE_RG4E: u32 = 16;
pub const MPU_SRGE_RG5E_POS: u32 = 5;
pub const MPU_SRGE_RG5E: u32 = 32;
pub const MPU_SRGE_RG6E_POS: u32 = 6;
pub const MPU_SRGE_RG6E: u32 = 64;
pub const MPU_SRGE_RG7E_POS: u32 = 7;
pub const MPU_SRGE_RG7E: u32 = 128;
pub const MPU_SRGE_RG8E_POS: u32 = 8;
pub const MPU_SRGE_RG8E: u32 = 256;
pub const MPU_SRGE_RG9E_POS: u32 = 9;
pub const MPU_SRGE_RG9E: u32 = 512;
pub const MPU_SRGE_RG10E_POS: u32 = 10;
pub const MPU_SRGE_RG10E: u32 = 1024;
pub const MPU_SRGE_RG11E_POS: u32 = 11;
pub const MPU_SRGE_RG11E: u32 = 2048;
pub const MPU_SRGE_RG12E_POS: u32 = 12;
pub const MPU_SRGE_RG12E: u32 = 4096;
pub const MPU_SRGE_RG13E_POS: u32 = 13;
pub const MPU_SRGE_RG13E: u32 = 8192;
pub const MPU_SRGE_RG14E_POS: u32 = 14;
pub const MPU_SRGE_RG14E: u32 = 16384;
pub const MPU_SRGE_RG15E_POS: u32 = 15;
pub const MPU_SRGE_RG15E: u32 = 32768;
pub const MPU_SRGWP_RG0WP_POS: u32 = 0;
pub const MPU_SRGWP_RG0WP: u32 = 1;
pub const MPU_SRGWP_RG1WP_POS: u32 = 1;
pub const MPU_SRGWP_RG1WP: u32 = 2;
pub const MPU_SRGWP_RG2WP_POS: u32 = 2;
pub const MPU_SRGWP_RG2WP: u32 = 4;
pub const MPU_SRGWP_RG3WP_POS: u32 = 3;
pub const MPU_SRGWP_RG3WP: u32 = 8;
pub const MPU_SRGWP_RG4WP_POS: u32 = 4;
pub const MPU_SRGWP_RG4WP: u32 = 16;
pub const MPU_SRGWP_RG5WP_POS: u32 = 5;
pub const MPU_SRGWP_RG5WP: u32 = 32;
pub const MPU_SRGWP_RG6WP_POS: u32 = 6;
pub const MPU_SRGWP_RG6WP: u32 = 64;
pub const MPU_SRGWP_RG7WP_POS: u32 = 7;
pub const MPU_SRGWP_RG7WP: u32 = 128;
pub const MPU_SRGWP_RG8WP_POS: u32 = 8;
pub const MPU_SRGWP_RG8WP: u32 = 256;
pub const MPU_SRGWP_RG9WP_POS: u32 = 9;
pub const MPU_SRGWP_RG9WP: u32 = 512;
pub const MPU_SRGWP_RG10WP_POS: u32 = 10;
pub const MPU_SRGWP_RG10WP: u32 = 1024;
pub const MPU_SRGWP_RG11WP_POS: u32 = 11;
pub const MPU_SRGWP_RG11WP: u32 = 2048;
pub const MPU_SRGWP_RG12WP_POS: u32 = 12;
pub const MPU_SRGWP_RG12WP: u32 = 4096;
pub const MPU_SRGWP_RG13WP_POS: u32 = 13;
pub const MPU_SRGWP_RG13WP: u32 = 8192;
pub const MPU_SRGWP_RG14WP_POS: u32 = 14;
pub const MPU_SRGWP_RG14WP: u32 = 16384;
pub const MPU_SRGWP_RG15WP_POS: u32 = 15;
pub const MPU_SRGWP_RG15WP: u32 = 32768;
pub const MPU_SRGRP_RG0RP_POS: u32 = 0;
pub const MPU_SRGRP_RG0RP: u32 = 1;
pub const MPU_SRGRP_RG1RP_POS: u32 = 1;
pub const MPU_SRGRP_RG1RP: u32 = 2;
pub const MPU_SRGRP_RG2RP_POS: u32 = 2;
pub const MPU_SRGRP_RG2RP: u32 = 4;
pub const MPU_SRGRP_RG3RP_POS: u32 = 3;
pub const MPU_SRGRP_RG3RP: u32 = 8;
pub const MPU_SRGRP_RG4RP_POS: u32 = 4;
pub const MPU_SRGRP_RG4RP: u32 = 16;
pub const MPU_SRGRP_RG5RP_POS: u32 = 5;
pub const MPU_SRGRP_RG5RP: u32 = 32;
pub const MPU_SRGRP_RG6RP_POS: u32 = 6;
pub const MPU_SRGRP_RG6RP: u32 = 64;
pub const MPU_SRGRP_RG7RP_POS: u32 = 7;
pub const MPU_SRGRP_RG7RP: u32 = 128;
pub const MPU_SRGRP_RG8RP_POS: u32 = 8;
pub const MPU_SRGRP_RG8RP: u32 = 256;
pub const MPU_SRGRP_RG9RP_POS: u32 = 9;
pub const MPU_SRGRP_RG9RP: u32 = 512;
pub const MPU_SRGRP_RG10RP_POS: u32 = 10;
pub const MPU_SRGRP_RG10RP: u32 = 1024;
pub const MPU_SRGRP_RG11RP_POS: u32 = 11;
pub const MPU_SRGRP_RG11RP: u32 = 2048;
pub const MPU_SRGRP_RG12RP_POS: u32 = 12;
pub const MPU_SRGRP_RG12RP: u32 = 4096;
pub const MPU_SRGRP_RG13RP_POS: u32 = 13;
pub const MPU_SRGRP_RG13RP: u32 = 8192;
pub const MPU_SRGRP_RG14RP_POS: u32 = 14;
pub const MPU_SRGRP_RG14RP: u32 = 16384;
pub const MPU_SRGRP_RG15RP_POS: u32 = 15;
pub const MPU_SRGRP_RG15RP: u32 = 32768;
pub const MPU_SCR_SMPUBRP_POS: u32 = 0;
pub const MPU_SCR_SMPUBRP: u32 = 1;
pub const MPU_SCR_SMPUBWP_POS: u32 = 1;
pub const MPU_SCR_SMPUBWP: u32 = 2;
pub const MPU_SCR_SMPUACT_POS: u32 = 2;
pub const MPU_SCR_SMPUACT: u32 = 12;
pub const MPU_SCR_SMPUACT_0: u32 = 4;
pub const MPU_SCR_SMPUACT_1: u32 = 8;
pub const MPU_SCR_SMPUE_POS: u32 = 7;
pub const MPU_SCR_SMPUE: u32 = 128;
pub const PERIC_SMC_ENAR_SMCEN_POS: u32 = 1;
pub const PERIC_SMC_ENAR_SMCEN: u32 = 2;
pub const PERIC_TMR_SYNENR_TMR0U1A_POS: u32 = 0;
pub const PERIC_TMR_SYNENR_TMR0U1A: u32 = 1;
pub const PERIC_TMR_SYNENR_TMR0U1B_POS: u32 = 1;
pub const PERIC_TMR_SYNENR_TMR0U1B: u32 = 2;
pub const PERIC_TMR_SYNENR_TMR0U2A_POS: u32 = 2;
pub const PERIC_TMR_SYNENR_TMR0U2A: u32 = 4;
pub const PERIC_TMR_SYNENR_TMR0U2B_POS: u32 = 3;
pub const PERIC_TMR_SYNENR_TMR0U2B: u32 = 8;
pub const PERIC_TMR_SYNENR_TMR4U1_POS: u32 = 4;
pub const PERIC_TMR_SYNENR_TMR4U1: u32 = 16;
pub const PERIC_TMR_SYNENR_TMR4U2_POS: u32 = 5;
pub const PERIC_TMR_SYNENR_TMR4U2: u32 = 32;
pub const PERIC_TMR_SYNENR_TMR4U3_POS: u32 = 6;
pub const PERIC_TMR_SYNENR_TMR4U3: u32 = 64;
pub const PERIC_TMR_SYNENR_TMR6U1_POS: u32 = 8;
pub const PERIC_TMR_SYNENR_TMR6U1: u32 = 256;
pub const PERIC_TMR_SYNENR_TMR6U2_POS: u32 = 9;
pub const PERIC_TMR_SYNENR_TMR6U2: u32 = 512;
pub const PERIC_TMR_SYNENR_TMRAU1_POS: u32 = 10;
pub const PERIC_TMR_SYNENR_TMRAU1: u32 = 1024;
pub const PERIC_TMR_SYNENR_TMRAU2_POS: u32 = 11;
pub const PERIC_TMR_SYNENR_TMRAU2: u32 = 2048;
pub const PERIC_TMR_SYNENR_TMRAU3_POS: u32 = 12;
pub const PERIC_TMR_SYNENR_TMRAU3: u32 = 4096;
pub const PERIC_TMR_SYNENR_TMRAU4_POS: u32 = 13;
pub const PERIC_TMR_SYNENR_TMRAU4: u32 = 8192;
pub const PERIC_TMR_SYNENR_TMRAU5_POS: u32 = 14;
pub const PERIC_TMR_SYNENR_TMRAU5: u32 = 16384;
pub const PERIC_USART1_NFC_USASRT1_NFS_POS: u32 = 0;
pub const PERIC_USART1_NFC_USASRT1_NFS: u32 = 3;
pub const PERIC_USART1_NFC_USASRT1_NFS_0: u32 = 1;
pub const PERIC_USART1_NFC_USASRT1_NFS_1: u32 = 2;
pub const PERIC_USART1_NFC_USART1_NFE_POS: u32 = 2;
pub const PERIC_USART1_NFC_USART1_NFE: u32 = 4;
pub const PWC_FCG0_SRAMH_POS: u32 = 0;
pub const PWC_FCG0_SRAMH: u32 = 1;
pub const PWC_FCG0_SRAM0_POS: u32 = 4;
pub const PWC_FCG0_SRAM0: u32 = 16;
pub const PWC_FCG0_SRAMB_POS: u32 = 10;
pub const PWC_FCG0_SRAMB: u32 = 1024;
pub const PWC_FCG0_KEY_POS: u32 = 13;
pub const PWC_FCG0_KEY: u32 = 8192;
pub const PWC_FCG0_DMA1_POS: u32 = 14;
pub const PWC_FCG0_DMA1: u32 = 16384;
pub const PWC_FCG0_DMA2_POS: u32 = 15;
pub const PWC_FCG0_DMA2: u32 = 32768;
pub const PWC_FCG0_FCM_POS: u32 = 16;
pub const PWC_FCG0_FCM: u32 = 65536;
pub const PWC_FCG0_AOS_POS: u32 = 17;
pub const PWC_FCG0_AOS: u32 = 131072;
pub const PWC_FCG0_CTC_POS: u32 = 18;
pub const PWC_FCG0_CTC: u32 = 262144;
pub const PWC_FCG0_AES_POS: u32 = 20;
pub const PWC_FCG0_AES: u32 = 1048576;
pub const PWC_FCG0_HASH_POS: u32 = 21;
pub const PWC_FCG0_HASH: u32 = 2097152;
pub const PWC_FCG0_TRNG_POS: u32 = 22;
pub const PWC_FCG0_TRNG: u32 = 4194304;
pub const PWC_FCG0_CRC_POS: u32 = 23;
pub const PWC_FCG0_CRC: u32 = 8388608;
pub const PWC_FCG0_DCU1_POS: u32 = 24;
pub const PWC_FCG0_DCU1: u32 = 16777216;
pub const PWC_FCG0_DCU2_POS: u32 = 25;
pub const PWC_FCG0_DCU2: u32 = 33554432;
pub const PWC_FCG0_DCU3_POS: u32 = 26;
pub const PWC_FCG0_DCU3: u32 = 67108864;
pub const PWC_FCG0_DCU4_POS: u32 = 27;
pub const PWC_FCG0_DCU4: u32 = 134217728;
pub const PWC_FCG1_MCAN1_POS: u32 = 0;
pub const PWC_FCG1_MCAN1: u32 = 1;
pub const PWC_FCG1_MCAN2_POS: u32 = 1;
pub const PWC_FCG1_MCAN2: u32 = 2;
pub const PWC_FCG1_QSPI_POS: u32 = 3;
pub const PWC_FCG1_QSPI: u32 = 8;
pub const PWC_FCG1_I2C1_POS: u32 = 4;
pub const PWC_FCG1_I2C1: u32 = 16;
pub const PWC_FCG1_I2C2_POS: u32 = 5;
pub const PWC_FCG1_I2C2: u32 = 32;
pub const PWC_FCG1_SPI1_POS: u32 = 16;
pub const PWC_FCG1_SPI1: u32 = 65536;
pub const PWC_FCG1_SPI2_POS: u32 = 17;
pub const PWC_FCG1_SPI2: u32 = 131072;
pub const PWC_FCG1_SPI3_POS: u32 = 18;
pub const PWC_FCG1_SPI3: u32 = 262144;
pub const PWC_FCG2_TMR6_1_POS: u32 = 0;
pub const PWC_FCG2_TMR6_1: u32 = 1;
pub const PWC_FCG2_TMR6_2_POS: u32 = 1;
pub const PWC_FCG2_TMR6_2: u32 = 2;
pub const PWC_FCG2_TMR4_1_POS: u32 = 9;
pub const PWC_FCG2_TMR4_1: u32 = 512;
pub const PWC_FCG2_TMR4_2_POS: u32 = 10;
pub const PWC_FCG2_TMR4_2: u32 = 1024;
pub const PWC_FCG2_TMR4_3_POS: u32 = 11;
pub const PWC_FCG2_TMR4_3: u32 = 2048;
pub const PWC_FCG2_TMR0_1_POS: u32 = 12;
pub const PWC_FCG2_TMR0_1: u32 = 4096;
pub const PWC_FCG2_TMR0_2_POS: u32 = 13;
pub const PWC_FCG2_TMR0_2: u32 = 8192;
pub const PWC_FCG2_EMB_POS: u32 = 15;
pub const PWC_FCG2_EMB: u32 = 32768;
pub const PWC_FCG2_TMRA_1_POS: u32 = 20;
pub const PWC_FCG2_TMRA_1: u32 = 1048576;
pub const PWC_FCG2_TMRA_2_POS: u32 = 21;
pub const PWC_FCG2_TMRA_2: u32 = 2097152;
pub const PWC_FCG2_TMRA_3_POS: u32 = 22;
pub const PWC_FCG2_TMRA_3: u32 = 4194304;
pub const PWC_FCG2_TMRA_4_POS: u32 = 23;
pub const PWC_FCG2_TMRA_4: u32 = 8388608;
pub const PWC_FCG2_TMRA_5_POS: u32 = 24;
pub const PWC_FCG2_TMRA_5: u32 = 16777216;
pub const PWC_FCG3_ADC1_POS: u32 = 0;
pub const PWC_FCG3_ADC1: u32 = 1;
pub const PWC_FCG3_ADC2_POS: u32 = 1;
pub const PWC_FCG3_ADC2: u32 = 2;
pub const PWC_FCG3_ADC3_POS: u32 = 2;
pub const PWC_FCG3_ADC3: u32 = 4;
pub const PWC_FCG3_DAC_POS: u32 = 4;
pub const PWC_FCG3_DAC: u32 = 16;
pub const PWC_FCG3_CMP12_POS: u32 = 8;
pub const PWC_FCG3_CMP12: u32 = 256;
pub const PWC_FCG3_CMP34_POS: u32 = 9;
pub const PWC_FCG3_CMP34: u32 = 512;
pub const PWC_FCG3_SMC_POS: u32 = 16;
pub const PWC_FCG3_SMC: u32 = 65536;
pub const PWC_FCG3_USART1_POS: u32 = 20;
pub const PWC_FCG3_USART1: u32 = 1048576;
pub const PWC_FCG3_USART2_POS: u32 = 21;
pub const PWC_FCG3_USART2: u32 = 2097152;
pub const PWC_FCG3_USART3_POS: u32 = 22;
pub const PWC_FCG3_USART3: u32 = 4194304;
pub const PWC_FCG3_USART4_POS: u32 = 23;
pub const PWC_FCG3_USART4: u32 = 8388608;
pub const PWC_FCG3_USART5_POS: u32 = 24;
pub const PWC_FCG3_USART5: u32 = 16777216;
pub const PWC_FCG3_USART6_POS: u32 = 25;
pub const PWC_FCG3_USART6: u32 = 33554432;
pub const PWC_FCG0PC_PRT0_POS: u32 = 0;
pub const PWC_FCG0PC_PRT0: u32 = 1;
pub const PWC_FCG0PC_FCG0PCWE_POS: u32 = 16;
pub const PWC_FCG0PC_FCG0PCWE: u32 = 4294901760;
pub const PWC_WKTCR_WKTMCMP_POS: u32 = 0;
pub const PWC_WKTCR_WKTMCMP: u32 = 4095;
pub const PWC_WKTCR_WKOVF_POS: u32 = 12;
pub const PWC_WKTCR_WKOVF: u32 = 4096;
pub const PWC_WKTCR_WKCKS_POS: u32 = 13;
pub const PWC_WKTCR_WKCKS: u32 = 24576;
pub const PWC_WKTCR_WKCKS_0: u32 = 8192;
pub const PWC_WKTCR_WKCKS_1: u32 = 16384;
pub const PWC_WKTCR_WKTCE_POS: u32 = 15;
pub const PWC_WKTCR_WKTCE: u32 = 32768;
pub const PWC_PWRC0_PDMDS_POS: u32 = 0;
pub const PWC_PWRC0_PDMDS: u32 = 3;
pub const PWC_PWRC0_PDMDS_0: u32 = 1;
pub const PWC_PWRC0_PDMDS_1: u32 = 2;
pub const PWC_PWRC0_IORTN_POS: u32 = 4;
pub const PWC_PWRC0_IORTN: u32 = 48;
pub const PWC_PWRC0_IORTN_0: u32 = 16;
pub const PWC_PWRC0_IORTN_1: u32 = 32;
pub const PWC_PWRC0_PWDN_POS: u32 = 7;
pub const PWC_PWRC0_PWDN: u32 = 128;
pub const PWC_PWRC1_VPLLSD_POS: u32 = 0;
pub const PWC_PWRC1_VPLLSD: u32 = 3;
pub const PWC_PWRC1_VPLLSD_0: u32 = 1;
pub const PWC_PWRC1_VPLLSD_1: u32 = 2;
pub const PWC_PWRC1_VHRCSD_POS: u32 = 2;
pub const PWC_PWRC1_VHRCSD: u32 = 4;
pub const PWC_PWRC1_PDTS_POS: u32 = 3;
pub const PWC_PWRC1_PDTS: u32 = 8;
pub const PWC_PWRC1_STPDAS_POS: u32 = 6;
pub const PWC_PWRC1_STPDAS: u32 = 192;
pub const PWC_PWRC1_STPDAS_0: u32 = 64;
pub const PWC_PWRC1_STPDAS_1: u32 = 128;
pub const PWC_PWRC2_DVS_POS: u32 = 4;
pub const PWC_PWRC2_DVS: u32 = 48;
pub const PWC_PWRC2_DVS_0: u32 = 16;
pub const PWC_PWRC2_DVS_1: u32 = 32;
pub const PWC_PWRC3_DDAS: u32 = 15;
pub const PWC_PWRC4_ADBUFE_POS: u32 = 7;
pub const PWC_PWRC4_ADBUFE: u32 = 128;
pub const PWC_PVDCR0_EXVCCINEN_POS: u32 = 0;
pub const PWC_PVDCR0_EXVCCINEN: u32 = 1;
pub const PWC_PVDCR0_PVD1EN_POS: u32 = 5;
pub const PWC_PVDCR0_PVD1EN: u32 = 32;
pub const PWC_PVDCR0_PVD2EN_POS: u32 = 6;
pub const PWC_PVDCR0_PVD2EN: u32 = 64;
pub const PWC_PVDCR1_PVD1IRE_POS: u32 = 0;
pub const PWC_PVDCR1_PVD1IRE: u32 = 1;
pub const PWC_PVDCR1_PVD1IRS_POS: u32 = 1;
pub const PWC_PVDCR1_PVD1IRS: u32 = 2;
pub const PWC_PVDCR1_PVD1CMPOE_POS: u32 = 2;
pub const PWC_PVDCR1_PVD1CMPOE: u32 = 4;
pub const PWC_PVDCR1_PVD2IRE_POS: u32 = 4;
pub const PWC_PVDCR1_PVD2IRE: u32 = 16;
pub const PWC_PVDCR1_PVD2IRS_POS: u32 = 5;
pub const PWC_PVDCR1_PVD2IRS: u32 = 32;
pub const PWC_PVDCR1_PVD2CMPOE_POS: u32 = 6;
pub const PWC_PVDCR1_PVD2CMPOE: u32 = 64;
pub const PWC_PVDFCR_PVD1NFDIS_POS: u32 = 0;
pub const PWC_PVDFCR_PVD1NFDIS: u32 = 1;
pub const PWC_PVDFCR_PVD1NFCKS_POS: u32 = 1;
pub const PWC_PVDFCR_PVD1NFCKS: u32 = 6;
pub const PWC_PVDFCR_PVD1NFCKS_0: u32 = 2;
pub const PWC_PVDFCR_PVD1NFCKS_1: u32 = 4;
pub const PWC_PVDFCR_PVD2NFDIS_POS: u32 = 4;
pub const PWC_PVDFCR_PVD2NFDIS: u32 = 16;
pub const PWC_PVDFCR_PVD2NFCKS_POS: u32 = 5;
pub const PWC_PVDFCR_PVD2NFCKS: u32 = 96;
pub const PWC_PVDFCR_PVD2NFCKS_0: u32 = 32;
pub const PWC_PVDFCR_PVD2NFCKS_1: u32 = 64;
pub const PWC_PVDLCR_PVD1LVL_POS: u32 = 0;
pub const PWC_PVDLCR_PVD1LVL: u32 = 7;
pub const PWC_PVDLCR_PVD2LVL_POS: u32 = 4;
pub const PWC_PVDLCR_PVD2LVL: u32 = 112;
pub const PWC_PDWKE0_WKE00_POS: u32 = 0;
pub const PWC_PDWKE0_WKE00: u32 = 1;
pub const PWC_PDWKE0_WKE01_POS: u32 = 1;
pub const PWC_PDWKE0_WKE01: u32 = 2;
pub const PWC_PDWKE0_WKE02_POS: u32 = 2;
pub const PWC_PDWKE0_WKE02: u32 = 4;
pub const PWC_PDWKE0_WKE03_POS: u32 = 3;
pub const PWC_PDWKE0_WKE03: u32 = 8;
pub const PWC_PDWKE0_WKE10_POS: u32 = 4;
pub const PWC_PDWKE0_WKE10: u32 = 16;
pub const PWC_PDWKE0_WKE11_POS: u32 = 5;
pub const PWC_PDWKE0_WKE11: u32 = 32;
pub const PWC_PDWKE0_WKE12_POS: u32 = 6;
pub const PWC_PDWKE0_WKE12: u32 = 64;
pub const PWC_PDWKE0_WKE13_POS: u32 = 7;
pub const PWC_PDWKE0_WKE13: u32 = 128;
pub const PWC_PDWKE1_WKE20_POS: u32 = 0;
pub const PWC_PDWKE1_WKE20: u32 = 1;
pub const PWC_PDWKE1_WKE21_POS: u32 = 1;
pub const PWC_PDWKE1_WKE21: u32 = 2;
pub const PWC_PDWKE1_WKE22_POS: u32 = 2;
pub const PWC_PDWKE1_WKE22: u32 = 4;
pub const PWC_PDWKE1_WKE23_POS: u32 = 3;
pub const PWC_PDWKE1_WKE23: u32 = 8;
pub const PWC_PDWKE1_WKE30_POS: u32 = 4;
pub const PWC_PDWKE1_WKE30: u32 = 16;
pub const PWC_PDWKE1_WKE31_POS: u32 = 5;
pub const PWC_PDWKE1_WKE31: u32 = 32;
pub const PWC_PDWKE1_WKE32_POS: u32 = 6;
pub const PWC_PDWKE1_WKE32: u32 = 64;
pub const PWC_PDWKE1_WKE33_POS: u32 = 7;
pub const PWC_PDWKE1_WKE33: u32 = 128;
pub const PWC_PDWKE2_VD1WKE_POS: u32 = 0;
pub const PWC_PDWKE2_VD1WKE: u32 = 1;
pub const PWC_PDWKE2_VD2WKE_POS: u32 = 1;
pub const PWC_PDWKE2_VD2WKE: u32 = 2;
pub const PWC_PDWKE2_RTCPRDWKE_POS: u32 = 4;
pub const PWC_PDWKE2_RTCPRDWKE: u32 = 16;
pub const PWC_PDWKE2_RTCALMWKE_POS: u32 = 5;
pub const PWC_PDWKE2_RTCALMWKE: u32 = 32;
pub const PWC_PDWKE2_WKTMWKE_POS: u32 = 7;
pub const PWC_PDWKE2_WKTMWKE: u32 = 128;
pub const PWC_PDWKES_WK0EGS_POS: u32 = 0;
pub const PWC_PDWKES_WK0EGS: u32 = 1;
pub const PWC_PDWKES_WK1EGS_POS: u32 = 1;
pub const PWC_PDWKES_WK1EGS: u32 = 2;
pub const PWC_PDWKES_WK2EGS_POS: u32 = 2;
pub const PWC_PDWKES_WK2EGS: u32 = 4;
pub const PWC_PDWKES_WK3EGS_POS: u32 = 3;
pub const PWC_PDWKES_WK3EGS: u32 = 8;
pub const PWC_PDWKES_VD1EGS_POS: u32 = 4;
pub const PWC_PDWKES_VD1EGS: u32 = 16;
pub const PWC_PDWKES_VD2EGS_POS: u32 = 5;
pub const PWC_PDWKES_VD2EGS: u32 = 32;
pub const PWC_PDWKF0_PTWK0F_POS: u32 = 0;
pub const PWC_PDWKF0_PTWK0F: u32 = 1;
pub const PWC_PDWKF0_PTWK1F_POS: u32 = 1;
pub const PWC_PDWKF0_PTWK1F: u32 = 2;
pub const PWC_PDWKF0_PTWK2F_POS: u32 = 2;
pub const PWC_PDWKF0_PTWK2F: u32 = 4;
pub const PWC_PDWKF0_PTWK3F_POS: u32 = 3;
pub const PWC_PDWKF0_PTWK3F: u32 = 8;
pub const PWC_PDWKF0_VD1WKF_POS: u32 = 4;
pub const PWC_PDWKF0_VD1WKF: u32 = 16;
pub const PWC_PDWKF0_VD2WKF_POS: u32 = 5;
pub const PWC_PDWKF0_VD2WKF: u32 = 32;
pub const PWC_PDWKF1_RXD0WKF_POS: u32 = 3;
pub const PWC_PDWKF1_RXD0WKF: u32 = 8;
pub const PWC_PDWKF1_RTCPRDWKF_POS: u32 = 4;
pub const PWC_PDWKF1_RTCPRDWKF: u32 = 16;
pub const PWC_PDWKF1_RTCALMWKF_POS: u32 = 5;
pub const PWC_PDWKF1_RTCALMWKF: u32 = 32;
pub const PWC_PDWKF1_WKTMWKF_POS: u32 = 7;
pub const PWC_PDWKF1_WKTMWKF: u32 = 128;
pub const PWC_PWRC5_VVDRSD_POS: u32 = 0;
pub const PWC_PWRC5_VVDRSD: u32 = 1;
pub const PWC_PWRC5_SRAMBSD_POS: u32 = 1;
pub const PWC_PWRC5_SRAMBSD: u32 = 2;
pub const PWC_PWRC5_CSDIS_POS: u32 = 7;
pub const PWC_PWRC5_CSDIS: u32 = 128;
pub const PWC_PWRC6_RTCCKSEL: u32 = 3;
pub const PWC_PWRC6_RTCCKSEL_0: u32 = 1;
pub const PWC_PWRC6_RTCCKSEL_1: u32 = 2;
pub const PWC_PVDICR_PVD1EDGS_POS: u32 = 1;
pub const PWC_PVDICR_PVD1EDGS: u32 = 6;
pub const PWC_PVDICR_PVD1EDGS_0: u32 = 2;
pub const PWC_PVDICR_PVD1EDGS_1: u32 = 4;
pub const PWC_PVDICR_PVD2EDGS_POS: u32 = 5;
pub const PWC_PVDICR_PVD2EDGS: u32 = 96;
pub const PWC_PVDICR_PVD2EDGS_0: u32 = 32;
pub const PWC_PVDICR_PVD2EDGS_1: u32 = 64;
pub const PWC_PVDDSR_PVD1MON_POS: u32 = 0;
pub const PWC_PVDDSR_PVD1MON: u32 = 1;
pub const PWC_PVDDSR_PVD1DETFLG_POS: u32 = 1;
pub const PWC_PVDDSR_PVD1DETFLG: u32 = 2;
pub const PWC_PVDDSR_PVD2MON_POS: u32 = 4;
pub const PWC_PVDDSR_PVD2MON: u32 = 16;
pub const PWC_PVDDSR_PVD2DETFLG_POS: u32 = 5;
pub const PWC_PVDDSR_PVD2DETFLG: u32 = 32;
pub const PWC_RAMPC0_RAMPDC0_POS: u32 = 0;
pub const PWC_RAMPC0_RAMPDC0: u32 = 1;
pub const PWC_RAMPC0_RAMPDC10_POS: u32 = 10;
pub const PWC_RAMPC0_RAMPDC10: u32 = 1024;
pub const PWC_RAMOPM_RAMOPM: u32 = 65535;
pub const PWC_PRAMLPC_PRAMPDC0_POS: u32 = 0;
pub const PWC_PRAMLPC_PRAMPDC0: u32 = 1;
pub const PWC_PRAMLPC_PRAMPDC2_POS: u32 = 2;
pub const PWC_PRAMLPC_PRAMPDC2: u32 = 4;
pub const PWC_STPMCR_FLNWT_POS: u32 = 0;
pub const PWC_STPMCR_FLNWT: u32 = 1;
pub const PWC_STPMCR_CKSMRC_POS: u32 = 1;
pub const PWC_STPMCR_CKSMRC: u32 = 2;
pub const PWC_STPMCR_EXBUSOE_POS: u32 = 14;
pub const PWC_STPMCR_EXBUSOE: u32 = 16384;
pub const PWC_STPMCR_STOP_POS: u32 = 15;
pub const PWC_STPMCR_STOP: u32 = 32768;
pub const PWC_FPRC_FPRCB0_POS: u32 = 0;
pub const PWC_FPRC_FPRCB0: u32 = 1;
pub const PWC_FPRC_FPRCB1_POS: u32 = 1;
pub const PWC_FPRC_FPRCB1: u32 = 2;
pub const PWC_FPRC_FPRCB3_POS: u32 = 3;
pub const PWC_FPRC_FPRCB3: u32 = 8;
pub const PWC_FPRC_FPRCWE_POS: u32 = 8;
pub const PWC_FPRC_FPRCWE: u32 = 65280;
pub const QSPI_CR_MDSEL_POS: u32 = 0;
pub const QSPI_CR_MDSEL: u32 = 7;
pub const QSPI_CR_PFE_POS: u32 = 3;
pub const QSPI_CR_PFE: u32 = 8;
pub const QSPI_CR_PFSAE_POS: u32 = 4;
pub const QSPI_CR_PFSAE: u32 = 16;
pub const QSPI_CR_DCOME_POS: u32 = 5;
pub const QSPI_CR_DCOME: u32 = 32;
pub const QSPI_CR_XIPE_POS: u32 = 6;
pub const QSPI_CR_XIPE: u32 = 64;
pub const QSPI_CR_SPIMD3_POS: u32 = 7;
pub const QSPI_CR_SPIMD3: u32 = 128;
pub const QSPI_CR_IPRSL_POS: u32 = 8;
pub const QSPI_CR_IPRSL: u32 = 768;
pub const QSPI_CR_IPRSL_0: u32 = 256;
pub const QSPI_CR_IPRSL_1: u32 = 512;
pub const QSPI_CR_APRSL_POS: u32 = 10;
pub const QSPI_CR_APRSL: u32 = 3072;
pub const QSPI_CR_APRSL_0: u32 = 1024;
pub const QSPI_CR_APRSL_1: u32 = 2048;
pub const QSPI_CR_DPRSL_POS: u32 = 12;
pub const QSPI_CR_DPRSL: u32 = 12288;
pub const QSPI_CR_DPRSL_0: u32 = 4096;
pub const QSPI_CR_DPRSL_1: u32 = 8192;
pub const QSPI_CR_DIV_POS: u32 = 16;
pub const QSPI_CR_DIV: u32 = 4128768;
pub const QSPI_CSCR_SSHW_POS: u32 = 0;
pub const QSPI_CSCR_SSHW: u32 = 15;
pub const QSPI_CSCR_SSNW_POS: u32 = 4;
pub const QSPI_CSCR_SSNW: u32 = 48;
pub const QSPI_CSCR_SSNW_0: u32 = 16;
pub const QSPI_CSCR_SSNW_1: u32 = 32;
pub const QSPI_FCR_AWSL_POS: u32 = 0;
pub const QSPI_FCR_AWSL: u32 = 3;
pub const QSPI_FCR_AWSL_0: u32 = 1;
pub const QSPI_FCR_AWSL_1: u32 = 2;
pub const QSPI_FCR_FOUR_BIC_POS: u32 = 2;
pub const QSPI_FCR_FOUR_BIC: u32 = 4;
pub const QSPI_FCR_SSNHD_POS: u32 = 4;
pub const QSPI_FCR_SSNHD: u32 = 16;
pub const QSPI_FCR_SSNLD_POS: u32 = 5;
pub const QSPI_FCR_SSNLD: u32 = 32;
pub const QSPI_FCR_WPOL_POS: u32 = 6;
pub const QSPI_FCR_WPOL: u32 = 64;
pub const QSPI_FCR_DMCYCN_POS: u32 = 8;
pub const QSPI_FCR_DMCYCN: u32 = 3840;
pub const QSPI_FCR_DUTY_POS: u32 = 15;
pub const QSPI_FCR_DUTY: u32 = 32768;
pub const QSPI_SR_BUSY_POS: u32 = 0;
pub const QSPI_SR_BUSY: u32 = 1;
pub const QSPI_SR_XIPF_POS: u32 = 6;
pub const QSPI_SR_XIPF: u32 = 64;
pub const QSPI_SR_RAER_POS: u32 = 7;
pub const QSPI_SR_RAER: u32 = 128;
pub const QSPI_SR_PFNUM_POS: u32 = 8;
pub const QSPI_SR_PFNUM: u32 = 7936;
pub const QSPI_SR_PFFUL_POS: u32 = 14;
pub const QSPI_SR_PFFUL: u32 = 16384;
pub const QSPI_SR_PFAN_POS: u32 = 15;
pub const QSPI_SR_PFAN: u32 = 32768;
pub const QSPI_DCOM_DCOM_POS: u32 = 0;
pub const QSPI_DCOM_DCOM: u32 = 255;
pub const QSPI_DCOM_DCOMPRSL_POS: u32 = 8;
pub const QSPI_DCOM_DCOMPRSL: u32 = 768;
pub const QSPI_DCOM_DCOMPRSL_0: u32 = 256;
pub const QSPI_DCOM_DCOMPRSL_1: u32 = 512;
pub const QSPI_CCMD_RIC: u32 = 255;
pub const QSPI_XCMD_XIPMC: u32 = 255;
pub const QSPI_CLR_RAERCLR_POS: u32 = 7;
pub const QSPI_CLR_RAERCLR: u32 = 128;
pub const QSPI_EXAR_EXADR_POS: u32 = 26;
pub const QSPI_EXAR_EXADR: u32 = 4227858432;
pub const RMU_FRST0_KEY_POS: u32 = 13;
pub const RMU_FRST0_KEY: u32 = 8192;
pub const RMU_FRST0_DMA1_POS: u32 = 14;
pub const RMU_FRST0_DMA1: u32 = 16384;
pub const RMU_FRST0_DMA2_POS: u32 = 15;
pub const RMU_FRST0_DMA2: u32 = 32768;
pub const RMU_FRST0_FCM_POS: u32 = 16;
pub const RMU_FRST0_FCM: u32 = 65536;
pub const RMU_FRST0_AOS_POS: u32 = 17;
pub const RMU_FRST0_AOS: u32 = 131072;
pub const RMU_FRST0_CTC_POS: u32 = 18;
pub const RMU_FRST0_CTC: u32 = 262144;
pub const RMU_FRST0_AES_POS: u32 = 20;
pub const RMU_FRST0_AES: u32 = 1048576;
pub const RMU_FRST0_HASH_POS: u32 = 21;
pub const RMU_FRST0_HASH: u32 = 2097152;
pub const RMU_FRST0_TRNG_POS: u32 = 22;
pub const RMU_FRST0_TRNG: u32 = 4194304;
pub const RMU_FRST0_CRC_POS: u32 = 23;
pub const RMU_FRST0_CRC: u32 = 8388608;
pub const RMU_FRST0_DCU1_POS: u32 = 24;
pub const RMU_FRST0_DCU1: u32 = 16777216;
pub const RMU_FRST0_DCU2_POS: u32 = 25;
pub const RMU_FRST0_DCU2: u32 = 33554432;
pub const RMU_FRST0_DCU3_POS: u32 = 26;
pub const RMU_FRST0_DCU3: u32 = 67108864;
pub const RMU_FRST0_DCU4_POS: u32 = 27;
pub const RMU_FRST0_DCU4: u32 = 134217728;
pub const RMU_FRST1_QSPI_POS: u32 = 3;
pub const RMU_FRST1_QSPI: u32 = 8;
pub const RMU_FRST1_SPI1_POS: u32 = 16;
pub const RMU_FRST1_SPI1: u32 = 65536;
pub const RMU_FRST1_SPI2_POS: u32 = 17;
pub const RMU_FRST1_SPI2: u32 = 131072;
pub const RMU_FRST1_SPI3_POS: u32 = 18;
pub const RMU_FRST1_SPI3: u32 = 262144;
pub const RMU_FRST2_TMR6_POS: u32 = 0;
pub const RMU_FRST2_TMR6: u32 = 1;
pub const RMU_FRST2_TMR4_POS: u32 = 10;
pub const RMU_FRST2_TMR4: u32 = 1024;
pub const RMU_FRST2_TMR0_POS: u32 = 12;
pub const RMU_FRST2_TMR0: u32 = 4096;
pub const RMU_FRST2_EMB_POS: u32 = 15;
pub const RMU_FRST2_EMB: u32 = 32768;
pub const RMU_FRST2_TMRA_POS: u32 = 20;
pub const RMU_FRST2_TMRA: u32 = 1048576;
pub const RMU_FRST3_ADC1_POS: u32 = 0;
pub const RMU_FRST3_ADC1: u32 = 1;
pub const RMU_FRST3_ADC2_POS: u32 = 1;
pub const RMU_FRST3_ADC2: u32 = 2;
pub const RMU_FRST3_ADC3_POS: u32 = 2;
pub const RMU_FRST3_ADC3: u32 = 4;
pub const RMU_FRST3_DAC_POS: u32 = 4;
pub const RMU_FRST3_DAC: u32 = 16;
pub const RMU_FRST3_CMP12_POS: u32 = 8;
pub const RMU_FRST3_CMP12: u32 = 256;
pub const RMU_FRST3_CMP34_POS: u32 = 9;
pub const RMU_FRST3_CMP34: u32 = 512;
pub const RMU_FRST3_SMC_POS: u32 = 16;
pub const RMU_FRST3_SMC: u32 = 65536;
pub const RMU_FRST3_USART1_POS: u32 = 20;
pub const RMU_FRST3_USART1: u32 = 1048576;
pub const RMU_FRST3_USART2_POS: u32 = 21;
pub const RMU_FRST3_USART2: u32 = 2097152;
pub const RMU_FRST3_USART3_POS: u32 = 22;
pub const RMU_FRST3_USART3: u32 = 4194304;
pub const RMU_FRST3_USART4_POS: u32 = 23;
pub const RMU_FRST3_USART4: u32 = 8388608;
pub const RMU_FRST3_USART5_POS: u32 = 24;
pub const RMU_FRST3_USART5: u32 = 16777216;
pub const RMU_FRST3_USART6_POS: u32 = 25;
pub const RMU_FRST3_USART6: u32 = 33554432;
pub const RMU_PRSTCR0_LKUPREN_POS: u32 = 5;
pub const RMU_PRSTCR0_LKUPREN: u32 = 32;
pub const RMU_RSTF0_PORF_POS: u32 = 0;
pub const RMU_RSTF0_PORF: u32 = 1;
pub const RMU_RSTF0_PINRF_POS: u32 = 1;
pub const RMU_RSTF0_PINRF: u32 = 2;
pub const RMU_RSTF0_BORF_POS: u32 = 2;
pub const RMU_RSTF0_BORF: u32 = 4;
pub const RMU_RSTF0_PVD1RF_POS: u32 = 3;
pub const RMU_RSTF0_PVD1RF: u32 = 8;
pub const RMU_RSTF0_PVD2RF_POS: u32 = 4;
pub const RMU_RSTF0_PVD2RF: u32 = 16;
pub const RMU_RSTF0_WDRF_POS: u32 = 5;
pub const RMU_RSTF0_WDRF: u32 = 32;
pub const RMU_RSTF0_SWDRF_POS: u32 = 6;
pub const RMU_RSTF0_SWDRF: u32 = 64;
pub const RMU_RSTF0_PDRF_POS: u32 = 7;
pub const RMU_RSTF0_PDRF: u32 = 128;
pub const RMU_RSTF0_SWRF_POS: u32 = 8;
pub const RMU_RSTF0_SWRF: u32 = 256;
pub const RMU_RSTF0_MPUERF_POS: u32 = 9;
pub const RMU_RSTF0_MPUERF: u32 = 512;
pub const RMU_RSTF0_RAPERF_POS: u32 = 10;
pub const RMU_RSTF0_RAPERF: u32 = 1024;
pub const RMU_RSTF0_RAECRF_POS: u32 = 11;
pub const RMU_RSTF0_RAECRF: u32 = 2048;
pub const RMU_RSTF0_CKFERF_POS: u32 = 12;
pub const RMU_RSTF0_CKFERF: u32 = 4096;
pub const RMU_RSTF0_XTALERF_POS: u32 = 13;
pub const RMU_RSTF0_XTALERF: u32 = 8192;
pub const RMU_RSTF0_LKUPRF_POS: u32 = 14;
pub const RMU_RSTF0_LKUPRF: u32 = 16384;
pub const RMU_RSTF0_MULTIRF_POS: u32 = 30;
pub const RMU_RSTF0_MULTIRF: u32 = 1073741824;
pub const RMU_RSTF0_CLRF_POS: u32 = 31;
pub const RMU_RSTF0_CLRF: u32 = 2147483648;
pub const RTC_CR0_RESET: u32 = 1;
pub const RTC_CR1_PRDS_POS: u32 = 0;
pub const RTC_CR1_PRDS: u32 = 7;
pub const RTC_CR1_AMPM_POS: u32 = 3;
pub const RTC_CR1_AMPM: u32 = 8;
pub const RTC_CR1_ONEHZOE_POS: u32 = 5;
pub const RTC_CR1_ONEHZOE: u32 = 32;
pub const RTC_CR1_ONEHZSEL_POS: u32 = 6;
pub const RTC_CR1_ONEHZSEL: u32 = 64;
pub const RTC_CR1_START_POS: u32 = 7;
pub const RTC_CR1_START: u32 = 128;
pub const RTC_CR2_RWREQ_POS: u32 = 0;
pub const RTC_CR2_RWREQ: u32 = 1;
pub const RTC_CR2_RWEN_POS: u32 = 1;
pub const RTC_CR2_RWEN: u32 = 2;
pub const RTC_CR2_PRDF_POS: u32 = 2;
pub const RTC_CR2_PRDF: u32 = 4;
pub const RTC_CR2_ALMF_POS: u32 = 3;
pub const RTC_CR2_ALMF: u32 = 8;
pub const RTC_CR2_PRDIE_POS: u32 = 5;
pub const RTC_CR2_PRDIE: u32 = 32;
pub const RTC_CR2_ALMIE_POS: u32 = 6;
pub const RTC_CR2_ALMIE: u32 = 64;
pub const RTC_CR2_ALME_POS: u32 = 7;
pub const RTC_CR2_ALME: u32 = 128;
pub const RTC_CR3_LRCEN_POS: u32 = 4;
pub const RTC_CR3_LRCEN: u32 = 16;
pub const RTC_CR3_RCKSEL_POS: u32 = 7;
pub const RTC_CR3_RCKSEL: u32 = 128;
pub const RTC_SEC_SECU_POS: u32 = 0;
pub const RTC_SEC_SECU: u32 = 15;
pub const RTC_SEC_SECD_POS: u32 = 4;
pub const RTC_SEC_SECD: u32 = 112;
pub const RTC_MIN_MINU_POS: u32 = 0;
pub const RTC_MIN_MINU: u32 = 15;
pub const RTC_MIN_MIND_POS: u32 = 4;
pub const RTC_MIN_MIND: u32 = 112;
pub const RTC_HOUR_HOURU_POS: u32 = 0;
pub const RTC_HOUR_HOURU: u32 = 15;
pub const RTC_HOUR_HOURD_POS: u32 = 4;
pub const RTC_HOUR_HOURD: u32 = 48;
pub const RTC_HOUR_HOURD_0: u32 = 16;
pub const RTC_HOUR_HOURD_1: u32 = 32;
pub const RTC_WEEK_WEEK: u32 = 7;
pub const RTC_DAY_DAYU_POS: u32 = 0;
pub const RTC_DAY_DAYU: u32 = 15;
pub const RTC_DAY_DAYD_POS: u32 = 4;
pub const RTC_DAY_DAYD: u32 = 48;
pub const RTC_DAY_DAYD_0: u32 = 16;
pub const RTC_DAY_DAYD_1: u32 = 32;
pub const RTC_MON_MON: u32 = 31;
pub const RTC_YEAR_YEARU_POS: u32 = 0;
pub const RTC_YEAR_YEARU: u32 = 15;
pub const RTC_YEAR_YEARD_POS: u32 = 4;
pub const RTC_YEAR_YEARD: u32 = 240;
pub const RTC_ALMMIN_ALMMINU_POS: u32 = 0;
pub const RTC_ALMMIN_ALMMINU: u32 = 15;
pub const RTC_ALMMIN_ALMMIND_POS: u32 = 4;
pub const RTC_ALMMIN_ALMMIND: u32 = 112;
pub const RTC_ALMHOUR_ALMHOURU_POS: u32 = 0;
pub const RTC_ALMHOUR_ALMHOURU: u32 = 15;
pub const RTC_ALMHOUR_ALMHOURD_POS: u32 = 4;
pub const RTC_ALMHOUR_ALMHOURD: u32 = 48;
pub const RTC_ALMHOUR_ALMHOURD_0: u32 = 16;
pub const RTC_ALMHOUR_ALMHOURD_1: u32 = 32;
pub const RTC_ALMWEEK_ALMWEEK: u32 = 127;
pub const RTC_ERRCRH_COMP8_POS: u32 = 0;
pub const RTC_ERRCRH_COMP8: u32 = 1;
pub const RTC_ERRCRH_COMPEN_POS: u32 = 7;
pub const RTC_ERRCRH_COMPEN: u32 = 128;
pub const RTC_ERRCRL: u32 = 255;
pub const SMC_STSR_STATUS: u32 = 1;
pub const SMC_STCR0_LPWIR_POS: u32 = 2;
pub const SMC_STCR0_LPWIR: u32 = 4;
pub const SMC_STCR1_LPWOR_POS: u32 = 2;
pub const SMC_STCR1_LPWOR: u32 = 4;
pub const SMC_CMDR_CMDADD_POS: u32 = 0;
pub const SMC_CMDR_CMDADD: u32 = 1048575;
pub const SMC_CMDR_CRES_POS: u32 = 20;
pub const SMC_CMDR_CRES: u32 = 1048576;
pub const SMC_CMDR_CMD_POS: u32 = 21;
pub const SMC_CMDR_CMD: u32 = 6291456;
pub const SMC_CMDR_CMD_0: u32 = 2097152;
pub const SMC_CMDR_CMD_1: u32 = 4194304;
pub const SMC_CMDR_CMDCHIP_POS: u32 = 23;
pub const SMC_CMDR_CMDCHIP: u32 = 58720256;
pub const SMC_TMCR_T_RC_POS: u32 = 0;
pub const SMC_TMCR_T_RC: u32 = 15;
pub const SMC_TMCR_T_WC_POS: u32 = 4;
pub const SMC_TMCR_T_WC: u32 = 240;
pub const SMC_TMCR_T_CEOE_POS: u32 = 8;
pub const SMC_TMCR_T_CEOE: u32 = 1792;
pub const SMC_TMCR_T_WP_POS: u32 = 12;
pub const SMC_TMCR_T_WP: u32 = 28672;
pub const SMC_TMCR_T_TR_POS: u32 = 20;
pub const SMC_TMCR_T_TR: u32 = 7340032;
pub const SMC_TMCR_T_ADV_POS: u32 = 24;
pub const SMC_TMCR_T_ADV: u32 = 117440512;
pub const SMC_CPCR_RSYN_POS: u32 = 0;
pub const SMC_CPCR_RSYN: u32 = 1;
pub const SMC_CPCR_WSYN_POS: u32 = 4;
pub const SMC_CPCR_WSYN: u32 = 16;
pub const SMC_CPCR_MW_POS: u32 = 8;
pub const SMC_CPCR_MW: u32 = 768;
pub const SMC_CPCR_MW_0: u32 = 256;
pub const SMC_CPCR_MW_1: u32 = 512;
pub const SMC_CPCR_BAAS_POS: u32 = 10;
pub const SMC_CPCR_BAAS: u32 = 1024;
pub const SMC_CPCR_ADVS_POS: u32 = 11;
pub const SMC_CPCR_ADVS: u32 = 2048;
pub const SMC_CPCR_BLSS_POS: u32 = 12;
pub const SMC_CPCR_BLSS: u32 = 4096;
pub const SMC_RFTR_REFPRD: u32 = 15;
pub const SMC_TMSR_T_RC_POS: u32 = 0;
pub const SMC_TMSR_T_RC: u32 = 15;
pub const SMC_TMSR_T_WC_POS: u32 = 4;
pub const SMC_TMSR_T_WC: u32 = 240;
pub const SMC_TMSR_T_CEOE_POS: u32 = 8;
pub const SMC_TMSR_T_CEOE: u32 = 1792;
pub const SMC_TMSR_T_WP_POS: u32 = 12;
pub const SMC_TMSR_T_WP: u32 = 28672;
pub const SMC_TMSR_T_TR_POS: u32 = 20;
pub const SMC_TMSR_T_TR: u32 = 7340032;
pub const SMC_TMSR_T_ADV_POS: u32 = 24;
pub const SMC_TMSR_T_ADV: u32 = 117440512;
pub const SMC_CPSR_RSYN_POS: u32 = 0;
pub const SMC_CPSR_RSYN: u32 = 1;
pub const SMC_CPSR_WSYN_POS: u32 = 4;
pub const SMC_CPSR_WSYN: u32 = 16;
pub const SMC_CPSR_MW_POS: u32 = 8;
pub const SMC_CPSR_MW: u32 = 768;
pub const SMC_CPSR_BAAS_POS: u32 = 10;
pub const SMC_CPSR_BAAS: u32 = 1024;
pub const SMC_CPSR_ADVS_POS: u32 = 11;
pub const SMC_CPSR_ADVS: u32 = 2048;
pub const SMC_CPSR_BLSS_POS: u32 = 12;
pub const SMC_CPSR_BLSS: u32 = 4096;
pub const SMC_CPSR_ADDMSK_POS: u32 = 16;
pub const SMC_CPSR_ADDMSK: u32 = 16711680;
pub const SMC_CPSR_ADDMAT_POS: u32 = 24;
pub const SMC_CPSR_ADDMAT: u32 = 4278190080;
pub const SMC_BACR_MUXMD_POS: u32 = 4;
pub const SMC_BACR_MUXMD: u32 = 16;
pub const SMC_BACR_CKSEL_POS: u32 = 14;
pub const SMC_BACR_CKSEL: u32 = 49152;
pub const SMC_BACR_CKSEL_0: u32 = 16384;
pub const SMC_BACR_CKSEL_1: u32 = 32768;
pub const SMC_CSCR0_ADDMSK0: u32 = 255;
pub const SMC_CSCR1_ADDMAT0: u32 = 255;
pub const SPI_DR: u32 = 4294967295;
pub const SPI_CR_SPIMDS_POS: u32 = 0;
pub const SPI_CR_SPIMDS: u32 = 1;
pub const SPI_CR_TXMDS_POS: u32 = 1;
pub const SPI_CR_TXMDS: u32 = 2;
pub const SPI_CR_MSTR_POS: u32 = 3;
pub const SPI_CR_MSTR: u32 = 8;
pub const SPI_CR_SPLPBK_POS: u32 = 4;
pub const SPI_CR_SPLPBK: u32 = 16;
pub const SPI_CR_SPLPBK2_POS: u32 = 5;
pub const SPI_CR_SPLPBK2: u32 = 32;
pub const SPI_CR_SPE_POS: u32 = 6;
pub const SPI_CR_SPE: u32 = 64;
pub const SPI_CR_CSUSPE_POS: u32 = 7;
pub const SPI_CR_CSUSPE: u32 = 128;
pub const SPI_CR_EIE_POS: u32 = 8;
pub const SPI_CR_EIE: u32 = 256;
pub const SPI_CR_TXIE_POS: u32 = 9;
pub const SPI_CR_TXIE: u32 = 512;
pub const SPI_CR_RXIE_POS: u32 = 10;
pub const SPI_CR_RXIE: u32 = 1024;
pub const SPI_CR_IDIE_POS: u32 = 11;
pub const SPI_CR_IDIE: u32 = 2048;
pub const SPI_CR_MODFE_POS: u32 = 12;
pub const SPI_CR_MODFE: u32 = 4096;
pub const SPI_CR_PATE_POS: u32 = 13;
pub const SPI_CR_PATE: u32 = 8192;
pub const SPI_CR_PAOE_POS: u32 = 14;
pub const SPI_CR_PAOE: u32 = 16384;
pub const SPI_CR_PAE_POS: u32 = 15;
pub const SPI_CR_PAE: u32 = 32768;
pub const SPI_CFG1_FTHLV_POS: u32 = 0;
pub const SPI_CFG1_FTHLV: u32 = 3;
pub const SPI_CFG1_FTHLV_0: u32 = 1;
pub const SPI_CFG1_FTHLV_1: u32 = 2;
pub const SPI_CFG1_CTMDS_POS: u32 = 2;
pub const SPI_CFG1_CTMDS: u32 = 4;
pub const SPI_CFG1_SPRDTD_POS: u32 = 6;
pub const SPI_CFG1_SPRDTD: u32 = 64;
pub const SPI_CFG1_SS0PV_POS: u32 = 8;
pub const SPI_CFG1_SS0PV: u32 = 256;
pub const SPI_CFG1_SS1PV_POS: u32 = 9;
pub const SPI_CFG1_SS1PV: u32 = 512;
pub const SPI_CFG1_SS2PV_POS: u32 = 10;
pub const SPI_CFG1_SS2PV: u32 = 1024;
pub const SPI_CFG1_SS3PV_POS: u32 = 11;
pub const SPI_CFG1_SS3PV: u32 = 2048;
pub const SPI_CFG1_CLKDIV_POS: u32 = 12;
pub const SPI_CFG1_CLKDIV: u32 = 61440;
pub const SPI_CFG1_CLKDIV_0: u32 = 4096;
pub const SPI_CFG1_CLKDIV_1: u32 = 8192;
pub const SPI_CFG1_CLKDIV_2: u32 = 16384;
pub const SPI_CFG1_CLKDIV_3: u32 = 32768;
pub const SPI_CFG1_MSSI_POS: u32 = 20;
pub const SPI_CFG1_MSSI: u32 = 7340032;
pub const SPI_CFG1_MSSI_0: u32 = 1048576;
pub const SPI_CFG1_MSSI_1: u32 = 2097152;
pub const SPI_CFG1_MSSI_2: u32 = 4194304;
pub const SPI_CFG1_MSSDL_POS: u32 = 24;
pub const SPI_CFG1_MSSDL: u32 = 117440512;
pub const SPI_CFG1_MSSDL_0: u32 = 16777216;
pub const SPI_CFG1_MSSDL_1: u32 = 33554432;
pub const SPI_CFG1_MSSDL_2: u32 = 67108864;
pub const SPI_CFG1_MIDI_POS: u32 = 28;
pub const SPI_CFG1_MIDI: u32 = 1879048192;
pub const SPI_CFG1_MIDI_0: u32 = 268435456;
pub const SPI_CFG1_MIDI_1: u32 = 536870912;
pub const SPI_CFG1_MIDI_2: u32 = 1073741824;
pub const SPI_SR_OVRERF_POS: u32 = 0;
pub const SPI_SR_OVRERF: u32 = 1;
pub const SPI_SR_IDLNF_POS: u32 = 1;
pub const SPI_SR_IDLNF: u32 = 2;
pub const SPI_SR_MODFERF_POS: u32 = 2;
pub const SPI_SR_MODFERF: u32 = 4;
pub const SPI_SR_PERF_POS: u32 = 3;
pub const SPI_SR_PERF: u32 = 8;
pub const SPI_SR_UDRERF_POS: u32 = 4;
pub const SPI_SR_UDRERF: u32 = 16;
pub const SPI_SR_TDEF_POS: u32 = 5;
pub const SPI_SR_TDEF: u32 = 32;
pub const SPI_SR_RDFF_POS: u32 = 7;
pub const SPI_SR_RDFF: u32 = 128;
pub const SPI_CFG2_CPHA_POS: u32 = 0;
pub const SPI_CFG2_CPHA: u32 = 1;
pub const SPI_CFG2_CPOL_POS: u32 = 1;
pub const SPI_CFG2_CPOL: u32 = 2;
pub const SPI_CFG2_MBR_POS: u32 = 2;
pub const SPI_CFG2_MBR: u32 = 12;
pub const SPI_CFG2_MBR_0: u32 = 4;
pub const SPI_CFG2_MBR_1: u32 = 8;
pub const SPI_CFG2_SSA_POS: u32 = 5;
pub const SPI_CFG2_SSA: u32 = 224;
pub const SPI_CFG2_SSA_0: u32 = 32;
pub const SPI_CFG2_SSA_1: u32 = 64;
pub const SPI_CFG2_SSA_2: u32 = 128;
pub const SPI_CFG2_DSIZE_POS: u32 = 8;
pub const SPI_CFG2_DSIZE: u32 = 3840;
pub const SPI_CFG2_DSIZE_0: u32 = 256;
pub const SPI_CFG2_DSIZE_1: u32 = 512;
pub const SPI_CFG2_DSIZE_2: u32 = 1024;
pub const SPI_CFG2_DSIZE_3: u32 = 2048;
pub const SPI_CFG2_LSBF_POS: u32 = 12;
pub const SPI_CFG2_LSBF: u32 = 4096;
pub const SPI_CFG2_MIDIE_POS: u32 = 13;
pub const SPI_CFG2_MIDIE: u32 = 8192;
pub const SPI_CFG2_MSSDLE_POS: u32 = 14;
pub const SPI_CFG2_MSSDLE: u32 = 16384;
pub const SPI_CFG2_MSSIE_POS: u32 = 15;
pub const SPI_CFG2_MSSIE: u32 = 32768;
pub const SRAMC_CKCR_PYOAD_POS: u32 = 0;
pub const SRAMC_CKCR_PYOAD: u32 = 1;
pub const SRAMC_CKCR_ECCOAD_POS: u32 = 16;
pub const SRAMC_CKCR_ECCOAD: u32 = 65536;
pub const SRAMC_CKCR_BECCOAD_POS: u32 = 17;
pub const SRAMC_CKCR_BECCOAD: u32 = 131072;
pub const SRAMC_CKCR_ECCMOD_POS: u32 = 24;
pub const SRAMC_CKCR_ECCMOD: u32 = 50331648;
pub const SRAMC_CKCR_ECCMOD_0: u32 = 16777216;
pub const SRAMC_CKCR_ECCMOD_1: u32 = 33554432;
pub const SRAMC_CKCR_BECCMOD_POS: u32 = 26;
pub const SRAMC_CKCR_BECCMOD: u32 = 201326592;
pub const SRAMC_CKCR_BECCMOD_0: u32 = 67108864;
pub const SRAMC_CKCR_BECCMOD_1: u32 = 134217728;
pub const SRAMC_CKPR_CKPRC_POS: u32 = 0;
pub const SRAMC_CKPR_CKPRC: u32 = 1;
pub const SRAMC_CKPR_CKPRKW_POS: u32 = 1;
pub const SRAMC_CKPR_CKPRKW: u32 = 254;
pub const SRAMC_CKSR_SRAMH_PYERR_POS: u32 = 3;
pub const SRAMC_CKSR_SRAMH_PYERR: u32 = 8;
pub const SRAMC_CKSR_SRAM0_1ERR_POS: u32 = 4;
pub const SRAMC_CKSR_SRAM0_1ERR: u32 = 16;
pub const SRAMC_CKSR_SRAM0_2ERR_POS: u32 = 5;
pub const SRAMC_CKSR_SRAM0_2ERR: u32 = 32;
pub const SRAMC_CKSR_SRAMB_1ERR_POS: u32 = 6;
pub const SRAMC_CKSR_SRAMB_1ERR: u32 = 64;
pub const SRAMC_CKSR_SRAMB_2ERR_POS: u32 = 7;
pub const SRAMC_CKSR_SRAMB_2ERR: u32 = 128;
pub const SRAMC_CKSR_CACHE_PYERR_POS: u32 = 8;
pub const SRAMC_CKSR_CACHE_PYERR: u32 = 256;
pub const SRAMC_SRAM0_EIEN_EIEN: u32 = 1;
pub const SRAMC_SRAM0_EIBIT0: u32 = 4294967295;
pub const SRAMC_SRAM0_EIBIT1_EIBIT: u32 = 127;
pub const SRAMC_SRAM0_ECCERRADDR_ECCERRADDR: u32 = 32767;
pub const SRAMC_SRAMB_EIEN_EIEN: u32 = 1;
pub const SRAMC_SRAMB_EIBIT0: u32 = 4294967295;
pub const SRAMC_SRAMB_EIBIT1_EIBIT: u32 = 127;
pub const SRAMC_SRAMB_ECCERRADDR_ECCERRADDR: u32 = 4095;
pub const SWDT_CR_PERI_POS: u32 = 0;
pub const SWDT_CR_PERI: u32 = 3;
pub const SWDT_CR_PERI_0: u32 = 1;
pub const SWDT_CR_PERI_1: u32 = 2;
pub const SWDT_CR_CKS_POS: u32 = 4;
pub const SWDT_CR_CKS: u32 = 240;
pub const SWDT_CR_WDPT_POS: u32 = 8;
pub const SWDT_CR_WDPT: u32 = 3840;
pub const SWDT_CR_SLPOFF_POS: u32 = 16;
pub const SWDT_CR_SLPOFF: u32 = 65536;
pub const SWDT_CR_ITS_POS: u32 = 31;
pub const SWDT_CR_ITS: u32 = 2147483648;
pub const SWDT_SR_CNT_POS: u32 = 0;
pub const SWDT_SR_CNT: u32 = 65535;
pub const SWDT_SR_UDF_POS: u32 = 16;
pub const SWDT_SR_UDF: u32 = 65536;
pub const SWDT_SR_REF_POS: u32 = 17;
pub const SWDT_SR_REF: u32 = 131072;
pub const SWDT_RR_RF: u32 = 65535;
pub const TMR0_CNTAR_CNTA: u32 = 65535;
pub const TMR0_CNTBR_CNTB: u32 = 65535;
pub const TMR0_CMPAR_CMPA: u32 = 65535;
pub const TMR0_CMPBR_CMPB: u32 = 65535;
pub const TMR0_BCONR_CSTA_POS: u32 = 0;
pub const TMR0_BCONR_CSTA: u32 = 1;
pub const TMR0_BCONR_CAPMDA_POS: u32 = 1;
pub const TMR0_BCONR_CAPMDA: u32 = 2;
pub const TMR0_BCONR_CMENA_POS: u32 = 2;
pub const TMR0_BCONR_CMENA: u32 = 4;
pub const TMR0_BCONR_OVENA_POS: u32 = 3;
pub const TMR0_BCONR_OVENA: u32 = 8;
pub const TMR0_BCONR_CKDIVA_POS: u32 = 4;
pub const TMR0_BCONR_CKDIVA: u32 = 240;
pub const TMR0_BCONR_SYNSA_POS: u32 = 8;
pub const TMR0_BCONR_SYNSA: u32 = 256;
pub const TMR0_BCONR_SYNCLKA_POS: u32 = 9;
pub const TMR0_BCONR_SYNCLKA: u32 = 512;
pub const TMR0_BCONR_ASYNCLKA_POS: u32 = 10;
pub const TMR0_BCONR_ASYNCLKA: u32 = 1024;
pub const TMR0_BCONR_HSTAA_POS: u32 = 12;
pub const TMR0_BCONR_HSTAA: u32 = 4096;
pub const TMR0_BCONR_HSTPA_POS: u32 = 13;
pub const TMR0_BCONR_HSTPA: u32 = 8192;
pub const TMR0_BCONR_HCLEA_POS: u32 = 14;
pub const TMR0_BCONR_HCLEA: u32 = 16384;
pub const TMR0_BCONR_HICPA_POS: u32 = 15;
pub const TMR0_BCONR_HICPA: u32 = 32768;
pub const TMR0_BCONR_CSTB_POS: u32 = 16;
pub const TMR0_BCONR_CSTB: u32 = 65536;
pub const TMR0_BCONR_CAPMDB_POS: u32 = 17;
pub const TMR0_BCONR_CAPMDB: u32 = 131072;
pub const TMR0_BCONR_CMENB_POS: u32 = 18;
pub const TMR0_BCONR_CMENB: u32 = 262144;
pub const TMR0_BCONR_OVENB_POS: u32 = 19;
pub const TMR0_BCONR_OVENB: u32 = 524288;
pub const TMR0_BCONR_CKDIVB_POS: u32 = 20;
pub const TMR0_BCONR_CKDIVB: u32 = 15728640;
pub const TMR0_BCONR_SYNSB_POS: u32 = 24;
pub const TMR0_BCONR_SYNSB: u32 = 16777216;
pub const TMR0_BCONR_SYNCLKB_POS: u32 = 25;
pub const TMR0_BCONR_SYNCLKB: u32 = 33554432;
pub const TMR0_BCONR_ASYNCLKB_POS: u32 = 26;
pub const TMR0_BCONR_ASYNCLKB: u32 = 67108864;
pub const TMR0_BCONR_HSTAB_POS: u32 = 28;
pub const TMR0_BCONR_HSTAB: u32 = 268435456;
pub const TMR0_BCONR_HSTPB_POS: u32 = 29;
pub const TMR0_BCONR_HSTPB: u32 = 536870912;
pub const TMR0_BCONR_HCLEB_POS: u32 = 30;
pub const TMR0_BCONR_HCLEB: u32 = 1073741824;
pub const TMR0_BCONR_HICPB_POS: u32 = 31;
pub const TMR0_BCONR_HICPB: u32 = 2147483648;
pub const TMR0_STFLR_CMFA_POS: u32 = 0;
pub const TMR0_STFLR_CMFA: u32 = 1;
pub const TMR0_STFLR_OVFA_POS: u32 = 1;
pub const TMR0_STFLR_OVFA: u32 = 2;
pub const TMR0_STFLR_ICPA_POS: u32 = 2;
pub const TMR0_STFLR_ICPA: u32 = 4;
pub const TMR0_STFLR_CMFB_POS: u32 = 16;
pub const TMR0_STFLR_CMFB: u32 = 65536;
pub const TMR0_STFLR_OVFB_POS: u32 = 17;
pub const TMR0_STFLR_OVFB: u32 = 131072;
pub const TMR0_STFLR_ICPB_POS: u32 = 18;
pub const TMR0_STFLR_ICPB: u32 = 262144;
pub const TMR4_OCCRUH: u32 = 65535;
pub const TMR4_OCCRUL: u32 = 65535;
pub const TMR4_OCCRVH: u32 = 65535;
pub const TMR4_OCCRVL: u32 = 65535;
pub const TMR4_OCCRWH: u32 = 65535;
pub const TMR4_OCCRWL: u32 = 65535;
pub const TMR4_OCCRXH: u32 = 65535;
pub const TMR4_OCCRXL: u32 = 65535;
pub const TMR4_OCSR_OCEH_POS: u32 = 0;
pub const TMR4_OCSR_OCEH: u32 = 1;
pub const TMR4_OCSR_OCEL_POS: u32 = 1;
pub const TMR4_OCSR_OCEL: u32 = 2;
pub const TMR4_OCSR_OCPH_POS: u32 = 2;
pub const TMR4_OCSR_OCPH: u32 = 4;
pub const TMR4_OCSR_OCPL_POS: u32 = 3;
pub const TMR4_OCSR_OCPL: u32 = 8;
pub const TMR4_OCSR_OCIEH_POS: u32 = 4;
pub const TMR4_OCSR_OCIEH: u32 = 16;
pub const TMR4_OCSR_OCIEL_POS: u32 = 5;
pub const TMR4_OCSR_OCIEL: u32 = 32;
pub const TMR4_OCSR_OCFH_POS: u32 = 6;
pub const TMR4_OCSR_OCFH: u32 = 64;
pub const TMR4_OCSR_OCFL_POS: u32 = 7;
pub const TMR4_OCSR_OCFL: u32 = 128;
pub const TMR4_OCER_CHBUFEN_POS: u32 = 0;
pub const TMR4_OCER_CHBUFEN: u32 = 3;
pub const TMR4_OCER_CHBUFEN_0: u32 = 1;
pub const TMR4_OCER_CHBUFEN_1: u32 = 2;
pub const TMR4_OCER_CLBUFEN_POS: u32 = 2;
pub const TMR4_OCER_CLBUFEN: u32 = 12;
pub const TMR4_OCER_CLBUFEN_0: u32 = 4;
pub const TMR4_OCER_CLBUFEN_1: u32 = 8;
pub const TMR4_OCER_MHBUFEN_POS: u32 = 4;
pub const TMR4_OCER_MHBUFEN: u32 = 48;
pub const TMR4_OCER_MHBUFEN_0: u32 = 16;
pub const TMR4_OCER_MHBUFEN_1: u32 = 32;
pub const TMR4_OCER_MLBUFEN_POS: u32 = 6;
pub const TMR4_OCER_MLBUFEN: u32 = 192;
pub const TMR4_OCER_MLBUFEN_0: u32 = 64;
pub const TMR4_OCER_MLBUFEN_1: u32 = 128;
pub const TMR4_OCER_LMCH_POS: u32 = 8;
pub const TMR4_OCER_LMCH: u32 = 256;
pub const TMR4_OCER_LMCL_POS: u32 = 9;
pub const TMR4_OCER_LMCL: u32 = 512;
pub const TMR4_OCER_LMMH_POS: u32 = 10;
pub const TMR4_OCER_LMMH: u32 = 1024;
pub const TMR4_OCER_LMML_POS: u32 = 11;
pub const TMR4_OCER_LMML: u32 = 2048;
pub const TMR4_OCER_MCECH_POS: u32 = 12;
pub const TMR4_OCER_MCECH: u32 = 4096;
pub const TMR4_OCER_MCECL_POS: u32 = 13;
pub const TMR4_OCER_MCECL: u32 = 8192;
pub const TMR4_OCMRH_OCFDCH_POS: u32 = 0;
pub const TMR4_OCMRH_OCFDCH: u32 = 1;
pub const TMR4_OCMRH_OCFPKH_POS: u32 = 1;
pub const TMR4_OCMRH_OCFPKH: u32 = 2;
pub const TMR4_OCMRH_OCFUCH_POS: u32 = 2;
pub const TMR4_OCMRH_OCFUCH: u32 = 4;
pub const TMR4_OCMRH_OCFZRH_POS: u32 = 3;
pub const TMR4_OCMRH_OCFZRH: u32 = 8;
pub const TMR4_OCMRH_OPDCH_POS: u32 = 4;
pub const TMR4_OCMRH_OPDCH: u32 = 48;
pub const TMR4_OCMRH_OPDCH_0: u32 = 16;
pub const TMR4_OCMRH_OPDCH_1: u32 = 32;
pub const TMR4_OCMRH_OPPKH_POS: u32 = 6;
pub const TMR4_OCMRH_OPPKH: u32 = 192;
pub const TMR4_OCMRH_OPPKH_0: u32 = 64;
pub const TMR4_OCMRH_OPPKH_1: u32 = 128;
pub const TMR4_OCMRH_OPUCH_POS: u32 = 8;
pub const TMR4_OCMRH_OPUCH: u32 = 768;
pub const TMR4_OCMRH_OPUCH_0: u32 = 256;
pub const TMR4_OCMRH_OPUCH_1: u32 = 512;
pub const TMR4_OCMRH_OPZRH_POS: u32 = 10;
pub const TMR4_OCMRH_OPZRH: u32 = 3072;
pub const TMR4_OCMRH_OPZRH_0: u32 = 1024;
pub const TMR4_OCMRH_OPZRH_1: u32 = 2048;
pub const TMR4_OCMRH_OPNPKH_POS: u32 = 12;
pub const TMR4_OCMRH_OPNPKH: u32 = 12288;
pub const TMR4_OCMRH_OPNPKH_0: u32 = 4096;
pub const TMR4_OCMRH_OPNPKH_1: u32 = 8192;
pub const TMR4_OCMRH_OPNZRH_POS: u32 = 14;
pub const TMR4_OCMRH_OPNZRH: u32 = 49152;
pub const TMR4_OCMRH_OPNZRH_0: u32 = 16384;
pub const TMR4_OCMRH_OPNZRH_1: u32 = 32768;
pub const TMR4_OCMRL_OCFDCL_POS: u32 = 0;
pub const TMR4_OCMRL_OCFDCL: u32 = 1;
pub const TMR4_OCMRL_OCFPKL_POS: u32 = 1;
pub const TMR4_OCMRL_OCFPKL: u32 = 2;
pub const TMR4_OCMRL_OCFUCL_POS: u32 = 2;
pub const TMR4_OCMRL_OCFUCL: u32 = 4;
pub const TMR4_OCMRL_OCFZRL_POS: u32 = 3;
pub const TMR4_OCMRL_OCFZRL: u32 = 8;
pub const TMR4_OCMRL_OPDCL_POS: u32 = 4;
pub const TMR4_OCMRL_OPDCL: u32 = 48;
pub const TMR4_OCMRL_OPDCL_0: u32 = 16;
pub const TMR4_OCMRL_OPDCL_1: u32 = 32;
pub const TMR4_OCMRL_OPPKL_POS: u32 = 6;
pub const TMR4_OCMRL_OPPKL: u32 = 192;
pub const TMR4_OCMRL_OPPKL_0: u32 = 64;
pub const TMR4_OCMRL_OPPKL_1: u32 = 128;
pub const TMR4_OCMRL_OPUCL_POS: u32 = 8;
pub const TMR4_OCMRL_OPUCL: u32 = 768;
pub const TMR4_OCMRL_OPUCL_0: u32 = 256;
pub const TMR4_OCMRL_OPUCL_1: u32 = 512;
pub const TMR4_OCMRL_OPZRL_POS: u32 = 10;
pub const TMR4_OCMRL_OPZRL: u32 = 3072;
pub const TMR4_OCMRL_OPZRL_0: u32 = 1024;
pub const TMR4_OCMRL_OPZRL_1: u32 = 2048;
pub const TMR4_OCMRL_OPNPKL_POS: u32 = 12;
pub const TMR4_OCMRL_OPNPKL: u32 = 12288;
pub const TMR4_OCMRL_OPNPKL_0: u32 = 4096;
pub const TMR4_OCMRL_OPNPKL_1: u32 = 8192;
pub const TMR4_OCMRL_OPNZRL_POS: u32 = 14;
pub const TMR4_OCMRL_OPNZRL: u32 = 49152;
pub const TMR4_OCMRL_OPNZRL_0: u32 = 16384;
pub const TMR4_OCMRL_OPNZRL_1: u32 = 32768;
pub const TMR4_OCMRL_EOPNDCL_POS: u32 = 16;
pub const TMR4_OCMRL_EOPNDCL: u32 = 196608;
pub const TMR4_OCMRL_EOPNDCL_0: u32 = 65536;
pub const TMR4_OCMRL_EOPNDCL_1: u32 = 131072;
pub const TMR4_OCMRL_EOPNUCL_POS: u32 = 18;
pub const TMR4_OCMRL_EOPNUCL: u32 = 786432;
pub const TMR4_OCMRL_EOPNUCL_0: u32 = 262144;
pub const TMR4_OCMRL_EOPNUCL_1: u32 = 524288;
pub const TMR4_OCMRL_EOPDCL_POS: u32 = 20;
pub const TMR4_OCMRL_EOPDCL: u32 = 3145728;
pub const TMR4_OCMRL_EOPDCL_0: u32 = 1048576;
pub const TMR4_OCMRL_EOPDCL_1: u32 = 2097152;
pub const TMR4_OCMRL_EOPPKL_POS: u32 = 22;
pub const TMR4_OCMRL_EOPPKL: u32 = 12582912;
pub const TMR4_OCMRL_EOPPKL_0: u32 = 4194304;
pub const TMR4_OCMRL_EOPPKL_1: u32 = 8388608;
pub const TMR4_OCMRL_EOPUCL_POS: u32 = 24;
pub const TMR4_OCMRL_EOPUCL: u32 = 50331648;
pub const TMR4_OCMRL_EOPUCL_0: u32 = 16777216;
pub const TMR4_OCMRL_EOPUCL_1: u32 = 33554432;
pub const TMR4_OCMRL_EOPZRL_POS: u32 = 26;
pub const TMR4_OCMRL_EOPZRL: u32 = 201326592;
pub const TMR4_OCMRL_EOPZRL_0: u32 = 67108864;
pub const TMR4_OCMRL_EOPZRL_1: u32 = 134217728;
pub const TMR4_OCMRL_EOPNPKL_POS: u32 = 28;
pub const TMR4_OCMRL_EOPNPKL: u32 = 805306368;
pub const TMR4_OCMRL_EOPNPKL_0: u32 = 268435456;
pub const TMR4_OCMRL_EOPNPKL_1: u32 = 536870912;
pub const TMR4_OCMRL_EOPNZRL_POS: u32 = 30;
pub const TMR4_OCMRL_EOPNZRL: u32 = 3221225472;
pub const TMR4_OCMRL_EOPNZRL_0: u32 = 1073741824;
pub const TMR4_OCMRL_EOPNZRL_1: u32 = 2147483648;
pub const TMR4_CPSR: u32 = 65535;
pub const TMR4_CNTR: u32 = 65535;
pub const TMR4_CCSR_CKDIV_POS: u32 = 0;
pub const TMR4_CCSR_CKDIV: u32 = 15;
pub const TMR4_CCSR_CLEAR_POS: u32 = 4;
pub const TMR4_CCSR_CLEAR: u32 = 16;
pub const TMR4_CCSR_MODE_POS: u32 = 5;
pub const TMR4_CCSR_MODE: u32 = 32;
pub const TMR4_CCSR_STOP_POS: u32 = 6;
pub const TMR4_CCSR_STOP: u32 = 64;
pub const TMR4_CCSR_BUFEN_POS: u32 = 7;
pub const TMR4_CCSR_BUFEN: u32 = 128;
pub const TMR4_CCSR_IRQPEN_POS: u32 = 8;
pub const TMR4_CCSR_IRQPEN: u32 = 256;
pub const TMR4_CCSR_IRQPF_POS: u32 = 9;
pub const TMR4_CCSR_IRQPF: u32 = 512;
pub const TMR4_CCSR_IRQZEN_POS: u32 = 10;
pub const TMR4_CCSR_IRQZEN: u32 = 1024;
pub const TMR4_CCSR_IRQZF_POS: u32 = 11;
pub const TMR4_CCSR_IRQZF: u32 = 2048;
pub const TMR4_CCSR_SYNST_POS: u32 = 12;
pub const TMR4_CCSR_SYNST: u32 = 4096;
pub const TMR4_CCSR_HST_POS: u32 = 13;
pub const TMR4_CCSR_HST: u32 = 8192;
pub const TMR4_CCSR_ECKEN_POS: u32 = 15;
pub const TMR4_CCSR_ECKEN: u32 = 32768;
pub const TMR4_CVPR_ZIM_POS: u32 = 0;
pub const TMR4_CVPR_ZIM: u32 = 15;
pub const TMR4_CVPR_PIM_POS: u32 = 4;
pub const TMR4_CVPR_PIM: u32 = 240;
pub const TMR4_CVPR_ZIC_POS: u32 = 8;
pub const TMR4_CVPR_ZIC: u32 = 3840;
pub const TMR4_CVPR_PIC_POS: u32 = 12;
pub const TMR4_CVPR_PIC: u32 = 61440;
pub const TMR4_PSCR_OEUH_POS: u32 = 0;
pub const TMR4_PSCR_OEUH: u32 = 1;
pub const TMR4_PSCR_OEUL_POS: u32 = 1;
pub const TMR4_PSCR_OEUL: u32 = 2;
pub const TMR4_PSCR_OEVH_POS: u32 = 2;
pub const TMR4_PSCR_OEVH: u32 = 4;
pub const TMR4_PSCR_OEVL_POS: u32 = 3;
pub const TMR4_PSCR_OEVL: u32 = 8;
pub const TMR4_PSCR_OEWH_POS: u32 = 4;
pub const TMR4_PSCR_OEWH: u32 = 16;
pub const TMR4_PSCR_OEWL_POS: u32 = 5;
pub const TMR4_PSCR_OEWL: u32 = 32;
pub const TMR4_PSCR_OEXH_POS: u32 = 6;
pub const TMR4_PSCR_OEXH: u32 = 64;
pub const TMR4_PSCR_OEXL_POS: u32 = 7;
pub const TMR4_PSCR_OEXL: u32 = 128;
pub const TMR4_PSCR_MOE_POS: u32 = 8;
pub const TMR4_PSCR_MOE: u32 = 256;
pub const TMR4_PSCR_AOE_POS: u32 = 9;
pub const TMR4_PSCR_AOE: u32 = 512;
pub const TMR4_PSCR_ODT_POS: u32 = 10;
pub const TMR4_PSCR_ODT: u32 = 3072;
pub const TMR4_PSCR_ODT_0: u32 = 1024;
pub const TMR4_PSCR_ODT_1: u32 = 2048;
pub const TMR4_PSCR_OSUH_POS: u32 = 16;
pub const TMR4_PSCR_OSUH: u32 = 196608;
pub const TMR4_PSCR_OSUH_0: u32 = 65536;
pub const TMR4_PSCR_OSUH_1: u32 = 131072;
pub const TMR4_PSCR_OSUL_POS: u32 = 18;
pub const TMR4_PSCR_OSUL: u32 = 786432;
pub const TMR4_PSCR_OSUL_0: u32 = 262144;
pub const TMR4_PSCR_OSUL_1: u32 = 524288;
pub const TMR4_PSCR_OSVH_POS: u32 = 20;
pub const TMR4_PSCR_OSVH: u32 = 3145728;
pub const TMR4_PSCR_OSVH_0: u32 = 1048576;
pub const TMR4_PSCR_OSVH_1: u32 = 2097152;
pub const TMR4_PSCR_OSVL_POS: u32 = 22;
pub const TMR4_PSCR_OSVL: u32 = 12582912;
pub const TMR4_PSCR_OSVL_0: u32 = 4194304;
pub const TMR4_PSCR_OSVL_1: u32 = 8388608;
pub const TMR4_PSCR_OSWH_POS: u32 = 24;
pub const TMR4_PSCR_OSWH: u32 = 50331648;
pub const TMR4_PSCR_OSWH_0: u32 = 16777216;
pub const TMR4_PSCR_OSWH_1: u32 = 33554432;
pub const TMR4_PSCR_OSWL_POS: u32 = 26;
pub const TMR4_PSCR_OSWL: u32 = 201326592;
pub const TMR4_PSCR_OSWL_0: u32 = 67108864;
pub const TMR4_PSCR_OSWL_1: u32 = 134217728;
pub const TMR4_PSCR_OSXH_POS: u32 = 28;
pub const TMR4_PSCR_OSXH: u32 = 805306368;
pub const TMR4_PSCR_OSXH_0: u32 = 268435456;
pub const TMR4_PSCR_OSXH_1: u32 = 536870912;
pub const TMR4_PSCR_OSXL_POS: u32 = 30;
pub const TMR4_PSCR_OSXL: u32 = 3221225472;
pub const TMR4_PSCR_OSXL_0: u32 = 1073741824;
pub const TMR4_PSCR_OSXL_1: u32 = 2147483648;
pub const TMR4_PFSRU: u32 = 65535;
pub const TMR4_PDARU: u32 = 65535;
pub const TMR4_PDBRU: u32 = 65535;
pub const TMR4_PFSRV: u32 = 65535;
pub const TMR4_PDARV: u32 = 65535;
pub const TMR4_PDBRV: u32 = 65535;
pub const TMR4_PFSRW: u32 = 65535;
pub const TMR4_PDARW: u32 = 65535;
pub const TMR4_PDBRW: u32 = 65535;
pub const TMR4_PFSRX: u32 = 65535;
pub const TMR4_PDARX: u32 = 65535;
pub const TMR4_PDBRX: u32 = 65535;
pub const TMR4_POCR_DIVCK_POS: u32 = 0;
pub const TMR4_POCR_DIVCK: u32 = 7;
pub const TMR4_POCR_PWMMD_POS: u32 = 4;
pub const TMR4_POCR_PWMMD: u32 = 48;
pub const TMR4_POCR_PWMMD_0: u32 = 16;
pub const TMR4_POCR_PWMMD_1: u32 = 32;
pub const TMR4_POCR_LVLS_POS: u32 = 6;
pub const TMR4_POCR_LVLS: u32 = 192;
pub const TMR4_POCR_LVLS_0: u32 = 64;
pub const TMR4_POCR_LVLS_1: u32 = 128;
pub const TMR4_SCCRUH: u32 = 65535;
pub const TMR4_SCCRUL: u32 = 65535;
pub const TMR4_SCCRVH: u32 = 65535;
pub const TMR4_SCCRVL: u32 = 65535;
pub const TMR4_SCCRWH: u32 = 65535;
pub const TMR4_SCCRWL: u32 = 65535;
pub const TMR4_SCCRXH: u32 = 65535;
pub const TMR4_SCCRXL: u32 = 65535;
pub const TMR4_SCSR_BUFEN_POS: u32 = 0;
pub const TMR4_SCSR_BUFEN: u32 = 3;
pub const TMR4_SCSR_BUFEN_0: u32 = 1;
pub const TMR4_SCSR_BUFEN_1: u32 = 2;
pub const TMR4_SCSR_EVTOS_POS: u32 = 2;
pub const TMR4_SCSR_EVTOS: u32 = 28;
pub const TMR4_SCSR_LMC_POS: u32 = 5;
pub const TMR4_SCSR_LMC: u32 = 32;
pub const TMR4_SCSR_EVTMS_POS: u32 = 8;
pub const TMR4_SCSR_EVTMS: u32 = 256;
pub const TMR4_SCSR_EVTDS_POS: u32 = 9;
pub const TMR4_SCSR_EVTDS: u32 = 512;
pub const TMR4_SCSR_DEN_POS: u32 = 12;
pub const TMR4_SCSR_DEN: u32 = 4096;
pub const TMR4_SCSR_PEN_POS: u32 = 13;
pub const TMR4_SCSR_PEN: u32 = 8192;
pub const TMR4_SCSR_UEN_POS: u32 = 14;
pub const TMR4_SCSR_UEN: u32 = 16384;
pub const TMR4_SCSR_ZEN_POS: u32 = 15;
pub const TMR4_SCSR_ZEN: u32 = 32768;
pub const TMR4_SCMR_AMC_POS: u32 = 0;
pub const TMR4_SCMR_AMC: u32 = 15;
pub const TMR4_SCMR_MZCE_POS: u32 = 6;
pub const TMR4_SCMR_MZCE: u32 = 64;
pub const TMR4_SCMR_MPCE_POS: u32 = 7;
pub const TMR4_SCMR_MPCE: u32 = 128;
pub const TMR4_SCER_EVTRS_POS: u32 = 0;
pub const TMR4_SCER_EVTRS: u32 = 15;
pub const TMR4_SCER_PCTS_POS: u32 = 8;
pub const TMR4_SCER_PCTS: u32 = 256;
pub const TMR4_RCSR_RTIDU_POS: u32 = 0;
pub const TMR4_RCSR_RTIDU: u32 = 1;
pub const TMR4_RCSR_RTIDV_POS: u32 = 1;
pub const TMR4_RCSR_RTIDV: u32 = 2;
pub const TMR4_RCSR_RTIDW_POS: u32 = 2;
pub const TMR4_RCSR_RTIDW: u32 = 4;
pub const TMR4_RCSR_RTIDX_POS: u32 = 3;
pub const TMR4_RCSR_RTIDX: u32 = 8;
pub const TMR4_RCSR_RTIFU_POS: u32 = 4;
pub const TMR4_RCSR_RTIFU: u32 = 16;
pub const TMR4_RCSR_RTICU_POS: u32 = 5;
pub const TMR4_RCSR_RTICU: u32 = 32;
pub const TMR4_RCSR_RTEU_POS: u32 = 6;
pub const TMR4_RCSR_RTEU: u32 = 64;
pub const TMR4_RCSR_RTSU_POS: u32 = 7;
pub const TMR4_RCSR_RTSU: u32 = 128;
pub const TMR4_RCSR_RTIFV_POS: u32 = 8;
pub const TMR4_RCSR_RTIFV: u32 = 256;
pub const TMR4_RCSR_RTICV_POS: u32 = 9;
pub const TMR4_RCSR_RTICV: u32 = 512;
pub const TMR4_RCSR_RTEV_POS: u32 = 10;
pub const TMR4_RCSR_RTEV: u32 = 1024;
pub const TMR4_RCSR_RTSV_POS: u32 = 11;
pub const TMR4_RCSR_RTSV: u32 = 2048;
pub const TMR4_RCSR_RTIFW_POS: u32 = 12;
pub const TMR4_RCSR_RTIFW: u32 = 4096;
pub const TMR4_RCSR_RTICW_POS: u32 = 13;
pub const TMR4_RCSR_RTICW: u32 = 8192;
pub const TMR4_RCSR_RTEW_POS: u32 = 14;
pub const TMR4_RCSR_RTEW: u32 = 16384;
pub const TMR4_RCSR_RTSW_POS: u32 = 15;
pub const TMR4_RCSR_RTSW: u32 = 32768;
pub const TMR4_RCSR_RTIFX_POS: u32 = 16;
pub const TMR4_RCSR_RTIFX: u32 = 65536;
pub const TMR4_RCSR_RTICX_POS: u32 = 17;
pub const TMR4_RCSR_RTICX: u32 = 131072;
pub const TMR4_RCSR_RTEX_POS: u32 = 18;
pub const TMR4_RCSR_RTEX: u32 = 262144;
pub const TMR4_RCSR_RTSX_POS: u32 = 19;
pub const TMR4_RCSR_RTSX: u32 = 524288;
pub const TMR4_SCIR_ITEN0_POS: u32 = 0;
pub const TMR4_SCIR_ITEN0: u32 = 1;
pub const TMR4_SCIR_ITEN1_POS: u32 = 1;
pub const TMR4_SCIR_ITEN1: u32 = 2;
pub const TMR4_SCIR_ITEN2_POS: u32 = 2;
pub const TMR4_SCIR_ITEN2: u32 = 4;
pub const TMR4_SCIR_ITEN3_POS: u32 = 3;
pub const TMR4_SCIR_ITEN3: u32 = 8;
pub const TMR4_SCIR_ITEN4_POS: u32 = 4;
pub const TMR4_SCIR_ITEN4: u32 = 16;
pub const TMR4_SCIR_ITEN5_POS: u32 = 5;
pub const TMR4_SCIR_ITEN5: u32 = 32;
pub const TMR4_SCIR_ITEN6_POS: u32 = 6;
pub const TMR4_SCIR_ITEN6: u32 = 64;
pub const TMR4_SCIR_ITEN7_POS: u32 = 7;
pub const TMR4_SCIR_ITEN7: u32 = 128;
pub const TMR4_SCFR_SF0_POS: u32 = 0;
pub const TMR4_SCFR_SF0: u32 = 1;
pub const TMR4_SCFR_SF1_POS: u32 = 1;
pub const TMR4_SCFR_SF1: u32 = 2;
pub const TMR4_SCFR_SF2_POS: u32 = 2;
pub const TMR4_SCFR_SF2: u32 = 4;
pub const TMR4_SCFR_SF3_POS: u32 = 3;
pub const TMR4_SCFR_SF3: u32 = 8;
pub const TMR4_SCFR_SF4_POS: u32 = 4;
pub const TMR4_SCFR_SF4: u32 = 16;
pub const TMR4_SCFR_SF5_POS: u32 = 5;
pub const TMR4_SCFR_SF5: u32 = 32;
pub const TMR4_SCFR_SF6_POS: u32 = 6;
pub const TMR4_SCFR_SF6: u32 = 64;
pub const TMR4_SCFR_SF7_POS: u32 = 7;
pub const TMR4_SCFR_SF7: u32 = 128;
pub const TMR6_CNTER_CNT: u32 = 65535;
pub const TMR6_UPDAR_UPDA: u32 = 65535;
pub const TMR6_PERAR_PERA: u32 = 65535;
pub const TMR6_PERBR_PERB: u32 = 65535;
pub const TMR6_PERCR_PERC: u32 = 65535;
pub const TMR6_GCMAR_GCMA: u32 = 65535;
pub const TMR6_GCMBR_GCMB: u32 = 65535;
pub const TMR6_GCMCR_GCMC: u32 = 65535;
pub const TMR6_GCMDR_GCMD: u32 = 65535;
pub const TMR6_GCMER_GCME: u32 = 65535;
pub const TMR6_GCMFR_GCMF: u32 = 65535;
pub const TMR6_SCMAR_SCMA: u32 = 65535;
pub const TMR6_SCMBR_SCMB: u32 = 65535;
pub const TMR6_SCMCR_SCMC: u32 = 65535;
pub const TMR6_SCMDR_SCMD: u32 = 65535;
pub const TMR6_SCMER_SCME: u32 = 65535;
pub const TMR6_SCMFR_SCMF: u32 = 65535;
pub const TMR6_DTUAR_DTUA: u32 = 65535;
pub const TMR6_DTDAR_DTDA: u32 = 65535;
pub const TMR6_DTUBR_DTUB: u32 = 65535;
pub const TMR6_DTDBR_DTDB: u32 = 65535;
pub const TMR6_GCONR_START_POS: u32 = 0;
pub const TMR6_GCONR_START: u32 = 1;
pub const TMR6_GCONR_DIR_POS: u32 = 1;
pub const TMR6_GCONR_DIR: u32 = 2;
pub const TMR6_GCONR_MODE_POS: u32 = 2;
pub const TMR6_GCONR_MODE: u32 = 4;
pub const TMR6_GCONR_CKDIV_POS: u32 = 4;
pub const TMR6_GCONR_CKDIV: u32 = 240;
pub const TMR6_GCONR_OVSTP_POS: u32 = 8;
pub const TMR6_GCONR_OVSTP: u32 = 256;
pub const TMR6_GCONR_ZMSKREV_POS: u32 = 16;
pub const TMR6_GCONR_ZMSKREV: u32 = 65536;
pub const TMR6_GCONR_ZMSKPOS_POS: u32 = 17;
pub const TMR6_GCONR_ZMSKPOS: u32 = 131072;
pub const TMR6_GCONR_ZMSKVAL_POS: u32 = 18;
pub const TMR6_GCONR_ZMSKVAL: u32 = 786432;
pub const TMR6_GCONR_ZMSKVAL_0: u32 = 262144;
pub const TMR6_GCONR_ZMSKVAL_1: u32 = 524288;
pub const TMR6_ICONR_INTENA_POS: u32 = 0;
pub const TMR6_ICONR_INTENA: u32 = 1;
pub const TMR6_ICONR_INTENB_POS: u32 = 1;
pub const TMR6_ICONR_INTENB: u32 = 2;
pub const TMR6_ICONR_INTENC_POS: u32 = 2;
pub const TMR6_ICONR_INTENC: u32 = 4;
pub const TMR6_ICONR_INTEND_POS: u32 = 3;
pub const TMR6_ICONR_INTEND: u32 = 8;
pub const TMR6_ICONR_INTENE_POS: u32 = 4;
pub const TMR6_ICONR_INTENE: u32 = 16;
pub const TMR6_ICONR_INTENF_POS: u32 = 5;
pub const TMR6_ICONR_INTENF: u32 = 32;
pub const TMR6_ICONR_INTENOVF_POS: u32 = 6;
pub const TMR6_ICONR_INTENOVF: u32 = 64;
pub const TMR6_ICONR_INTENUDF_POS: u32 = 7;
pub const TMR6_ICONR_INTENUDF: u32 = 128;
pub const TMR6_ICONR_INTENDTE_POS: u32 = 8;
pub const TMR6_ICONR_INTENDTE: u32 = 256;
pub const TMR6_ICONR_INTENSAU_POS: u32 = 16;
pub const TMR6_ICONR_INTENSAU: u32 = 65536;
pub const TMR6_ICONR_INTENSAD_POS: u32 = 17;
pub const TMR6_ICONR_INTENSAD: u32 = 131072;
pub const TMR6_ICONR_INTENSBU_POS: u32 = 18;
pub const TMR6_ICONR_INTENSBU: u32 = 262144;
pub const TMR6_ICONR_INTENSBD_POS: u32 = 19;
pub const TMR6_ICONR_INTENSBD: u32 = 524288;
pub const TMR6_BCONR_BENA_POS: u32 = 0;
pub const TMR6_BCONR_BENA: u32 = 1;
pub const TMR6_BCONR_BSEA_POS: u32 = 1;
pub const TMR6_BCONR_BSEA: u32 = 2;
pub const TMR6_BCONR_BTRUA_POS: u32 = 2;
pub const TMR6_BCONR_BTRUA: u32 = 4;
pub const TMR6_BCONR_BTRDA_POS: u32 = 3;
pub const TMR6_BCONR_BTRDA: u32 = 8;
pub const TMR6_BCONR_BENB_POS: u32 = 4;
pub const TMR6_BCONR_BENB: u32 = 16;
pub const TMR6_BCONR_BSEB_POS: u32 = 5;
pub const TMR6_BCONR_BSEB: u32 = 32;
pub const TMR6_BCONR_BTRUB_POS: u32 = 6;
pub const TMR6_BCONR_BTRUB: u32 = 64;
pub const TMR6_BCONR_BTRDB_POS: u32 = 7;
pub const TMR6_BCONR_BTRDB: u32 = 128;
pub const TMR6_BCONR_BENP_POS: u32 = 8;
pub const TMR6_BCONR_BENP: u32 = 256;
pub const TMR6_BCONR_BSEP_POS: u32 = 9;
pub const TMR6_BCONR_BSEP: u32 = 512;
pub const TMR6_BCONR_BTRUP_POS: u32 = 10;
pub const TMR6_BCONR_BTRUP: u32 = 1024;
pub const TMR6_BCONR_BTRDP_POS: u32 = 11;
pub const TMR6_BCONR_BTRDP: u32 = 2048;
pub const TMR6_BCONR_BENSPA_POS: u32 = 16;
pub const TMR6_BCONR_BENSPA: u32 = 65536;
pub const TMR6_BCONR_BSESPA_POS: u32 = 17;
pub const TMR6_BCONR_BSESPA: u32 = 131072;
pub const TMR6_BCONR_BTRUSPA_POS: u32 = 18;
pub const TMR6_BCONR_BTRUSPA: u32 = 262144;
pub const TMR6_BCONR_BTRDSPA_POS: u32 = 19;
pub const TMR6_BCONR_BTRDSPA: u32 = 524288;
pub const TMR6_BCONR_BENSPB_POS: u32 = 20;
pub const TMR6_BCONR_BENSPB: u32 = 1048576;
pub const TMR6_BCONR_BSESPB_POS: u32 = 21;
pub const TMR6_BCONR_BSESPB: u32 = 2097152;
pub const TMR6_BCONR_BTRUSPB_POS: u32 = 22;
pub const TMR6_BCONR_BTRUSPB: u32 = 4194304;
pub const TMR6_BCONR_BTRDSPB_POS: u32 = 23;
pub const TMR6_BCONR_BTRDSPB: u32 = 8388608;
pub const TMR6_DCONR_DTCEN_POS: u32 = 0;
pub const TMR6_DCONR_DTCEN: u32 = 1;
pub const TMR6_DCONR_SEPA_POS: u32 = 1;
pub const TMR6_DCONR_SEPA: u32 = 2;
pub const TMR6_DCONR_DTBENU_POS: u32 = 4;
pub const TMR6_DCONR_DTBENU: u32 = 16;
pub const TMR6_DCONR_DTBEND_POS: u32 = 5;
pub const TMR6_DCONR_DTBEND: u32 = 32;
pub const TMR6_DCONR_DTBTRU_POS: u32 = 6;
pub const TMR6_DCONR_DTBTRU: u32 = 64;
pub const TMR6_DCONR_DTBTRD_POS: u32 = 7;
pub const TMR6_DCONR_DTBTRD: u32 = 128;
pub const TMR6_PCNAR_STACA_POS: u32 = 0;
pub const TMR6_PCNAR_STACA: u32 = 3;
pub const TMR6_PCNAR_STACA_0: u32 = 1;
pub const TMR6_PCNAR_STACA_1: u32 = 2;
pub const TMR6_PCNAR_STPCA_POS: u32 = 2;
pub const TMR6_PCNAR_STPCA: u32 = 12;
pub const TMR6_PCNAR_STPCA_0: u32 = 4;
pub const TMR6_PCNAR_STPCA_1: u32 = 8;
pub const TMR6_PCNAR_OVFCA_POS: u32 = 4;
pub const TMR6_PCNAR_OVFCA: u32 = 48;
pub const TMR6_PCNAR_OVFCA_0: u32 = 16;
pub const TMR6_PCNAR_OVFCA_1: u32 = 32;
pub const TMR6_PCNAR_UDFCA_POS: u32 = 6;
pub const TMR6_PCNAR_UDFCA: u32 = 192;
pub const TMR6_PCNAR_UDFCA_0: u32 = 64;
pub const TMR6_PCNAR_UDFCA_1: u32 = 128;
pub const TMR6_PCNAR_CMAUCA_POS: u32 = 8;
pub const TMR6_PCNAR_CMAUCA: u32 = 768;
pub const TMR6_PCNAR_CMAUCA_0: u32 = 256;
pub const TMR6_PCNAR_CMAUCA_1: u32 = 512;
pub const TMR6_PCNAR_CMADCA_POS: u32 = 10;
pub const TMR6_PCNAR_CMADCA: u32 = 3072;
pub const TMR6_PCNAR_CMADCA_0: u32 = 1024;
pub const TMR6_PCNAR_CMADCA_1: u32 = 2048;
pub const TMR6_PCNAR_CMBUCA_POS: u32 = 12;
pub const TMR6_PCNAR_CMBUCA: u32 = 12288;
pub const TMR6_PCNAR_CMBUCA_0: u32 = 4096;
pub const TMR6_PCNAR_CMBUCA_1: u32 = 8192;
pub const TMR6_PCNAR_CMBDCA_POS: u32 = 14;
pub const TMR6_PCNAR_CMBDCA: u32 = 49152;
pub const TMR6_PCNAR_CMBDCA_0: u32 = 16384;
pub const TMR6_PCNAR_CMBDCA_1: u32 = 32768;
pub const TMR6_PCNAR_FORCA_POS: u32 = 16;
pub const TMR6_PCNAR_FORCA: u32 = 196608;
pub const TMR6_PCNAR_FORCA_0: u32 = 65536;
pub const TMR6_PCNAR_FORCA_1: u32 = 131072;
pub const TMR6_PCNAR_EMBCA_POS: u32 = 20;
pub const TMR6_PCNAR_EMBCA: u32 = 3145728;
pub const TMR6_PCNAR_EMBCA_0: u32 = 1048576;
pub const TMR6_PCNAR_EMBCA_1: u32 = 2097152;
pub const TMR6_PCNAR_EMBRA_POS: u32 = 22;
pub const TMR6_PCNAR_EMBRA: u32 = 12582912;
pub const TMR6_PCNAR_EMBRA_0: u32 = 4194304;
pub const TMR6_PCNAR_EMBRA_1: u32 = 8388608;
pub const TMR6_PCNAR_EMBSA_POS: u32 = 24;
pub const TMR6_PCNAR_EMBSA: u32 = 50331648;
pub const TMR6_PCNAR_EMBSA_0: u32 = 16777216;
pub const TMR6_PCNAR_EMBSA_1: u32 = 33554432;
pub const TMR6_PCNAR_OUTENA_POS: u32 = 28;
pub const TMR6_PCNAR_OUTENA: u32 = 268435456;
pub const TMR6_PCNAR_CAPMDA_POS: u32 = 31;
pub const TMR6_PCNAR_CAPMDA: u32 = 2147483648;
pub const TMR6_PCNBR_STACB_POS: u32 = 0;
pub const TMR6_PCNBR_STACB: u32 = 3;
pub const TMR6_PCNBR_STACB_0: u32 = 1;
pub const TMR6_PCNBR_STACB_1: u32 = 2;
pub const TMR6_PCNBR_STPCB_POS: u32 = 2;
pub const TMR6_PCNBR_STPCB: u32 = 12;
pub const TMR6_PCNBR_STPCB_0: u32 = 4;
pub const TMR6_PCNBR_STPCB_1: u32 = 8;
pub const TMR6_PCNBR_OVFCB_POS: u32 = 4;
pub const TMR6_PCNBR_OVFCB: u32 = 48;
pub const TMR6_PCNBR_OVFCB_0: u32 = 16;
pub const TMR6_PCNBR_OVFCB_1: u32 = 32;
pub const TMR6_PCNBR_UDFCB_POS: u32 = 6;
pub const TMR6_PCNBR_UDFCB: u32 = 192;
pub const TMR6_PCNBR_UDFCB_0: u32 = 64;
pub const TMR6_PCNBR_UDFCB_1: u32 = 128;
pub const TMR6_PCNBR_CMAUCB_POS: u32 = 8;
pub const TMR6_PCNBR_CMAUCB: u32 = 768;
pub const TMR6_PCNBR_CMAUCB_0: u32 = 256;
pub const TMR6_PCNBR_CMAUCB_1: u32 = 512;
pub const TMR6_PCNBR_CMADCB_POS: u32 = 10;
pub const TMR6_PCNBR_CMADCB: u32 = 3072;
pub const TMR6_PCNBR_CMADCB_0: u32 = 1024;
pub const TMR6_PCNBR_CMADCB_1: u32 = 2048;
pub const TMR6_PCNBR_CMBUCB_POS: u32 = 12;
pub const TMR6_PCNBR_CMBUCB: u32 = 12288;
pub const TMR6_PCNBR_CMBUCB_0: u32 = 4096;
pub const TMR6_PCNBR_CMBUCB_1: u32 = 8192;
pub const TMR6_PCNBR_CMBDCB_POS: u32 = 14;
pub const TMR6_PCNBR_CMBDCB: u32 = 49152;
pub const TMR6_PCNBR_CMBDCB_0: u32 = 16384;
pub const TMR6_PCNBR_CMBDCB_1: u32 = 32768;
pub const TMR6_PCNBR_FORCB_POS: u32 = 16;
pub const TMR6_PCNBR_FORCB: u32 = 196608;
pub const TMR6_PCNBR_FORCB_0: u32 = 65536;
pub const TMR6_PCNBR_FORCB_1: u32 = 131072;
pub const TMR6_PCNBR_EMBCB_POS: u32 = 20;
pub const TMR6_PCNBR_EMBCB: u32 = 3145728;
pub const TMR6_PCNBR_EMBCB_0: u32 = 1048576;
pub const TMR6_PCNBR_EMBCB_1: u32 = 2097152;
pub const TMR6_PCNBR_EMBRB_POS: u32 = 22;
pub const TMR6_PCNBR_EMBRB: u32 = 12582912;
pub const TMR6_PCNBR_EMBRB_0: u32 = 4194304;
pub const TMR6_PCNBR_EMBRB_1: u32 = 8388608;
pub const TMR6_PCNBR_EMBSB_POS: u32 = 24;
pub const TMR6_PCNBR_EMBSB: u32 = 50331648;
pub const TMR6_PCNBR_EMBSB_0: u32 = 16777216;
pub const TMR6_PCNBR_EMBSB_1: u32 = 33554432;
pub const TMR6_PCNBR_OUTENB_POS: u32 = 28;
pub const TMR6_PCNBR_OUTENB: u32 = 268435456;
pub const TMR6_PCNBR_CAPMDB_POS: u32 = 31;
pub const TMR6_PCNBR_CAPMDB: u32 = 2147483648;
pub const TMR6_FCNGR_NOFIENGA_POS: u32 = 0;
pub const TMR6_FCNGR_NOFIENGA: u32 = 1;
pub const TMR6_FCNGR_NOFICKGA_POS: u32 = 1;
pub const TMR6_FCNGR_NOFICKGA: u32 = 6;
pub const TMR6_FCNGR_NOFICKGA_0: u32 = 2;
pub const TMR6_FCNGR_NOFICKGA_1: u32 = 4;
pub const TMR6_FCNGR_NOFIENGB_POS: u32 = 4;
pub const TMR6_FCNGR_NOFIENGB: u32 = 16;
pub const TMR6_FCNGR_NOFICKGB_POS: u32 = 5;
pub const TMR6_FCNGR_NOFICKGB: u32 = 96;
pub const TMR6_FCNGR_NOFICKGB_0: u32 = 32;
pub const TMR6_FCNGR_NOFICKGB_1: u32 = 64;
pub const TMR6_VPERR_SPPERIA_POS: u32 = 8;
pub const TMR6_VPERR_SPPERIA: u32 = 256;
pub const TMR6_VPERR_SPPERIB_POS: u32 = 9;
pub const TMR6_VPERR_SPPERIB: u32 = 512;
pub const TMR6_VPERR_PCNTE_POS: u32 = 16;
pub const TMR6_VPERR_PCNTE: u32 = 196608;
pub const TMR6_VPERR_PCNTE_0: u32 = 65536;
pub const TMR6_VPERR_PCNTE_1: u32 = 131072;
pub const TMR6_VPERR_PCNTS_POS: u32 = 18;
pub const TMR6_VPERR_PCNTS: u32 = 1835008;
pub const TMR6_STFLR_CMAF_POS: u32 = 0;
pub const TMR6_STFLR_CMAF: u32 = 1;
pub const TMR6_STFLR_CMBF_POS: u32 = 1;
pub const TMR6_STFLR_CMBF: u32 = 2;
pub const TMR6_STFLR_CMCF_POS: u32 = 2;
pub const TMR6_STFLR_CMCF: u32 = 4;
pub const TMR6_STFLR_CMDF_POS: u32 = 3;
pub const TMR6_STFLR_CMDF: u32 = 8;
pub const TMR6_STFLR_CMEF_POS: u32 = 4;
pub const TMR6_STFLR_CMEF: u32 = 16;
pub const TMR6_STFLR_CMFF_POS: u32 = 5;
pub const TMR6_STFLR_CMFF: u32 = 32;
pub const TMR6_STFLR_OVFF_POS: u32 = 6;
pub const TMR6_STFLR_OVFF: u32 = 64;
pub const TMR6_STFLR_UDFF_POS: u32 = 7;
pub const TMR6_STFLR_UDFF: u32 = 128;
pub const TMR6_STFLR_DTEF_POS: u32 = 8;
pub const TMR6_STFLR_DTEF: u32 = 256;
pub const TMR6_STFLR_CMSAUF_POS: u32 = 9;
pub const TMR6_STFLR_CMSAUF: u32 = 512;
pub const TMR6_STFLR_CMSADF_POS: u32 = 10;
pub const TMR6_STFLR_CMSADF: u32 = 1024;
pub const TMR6_STFLR_CMSBUF_POS: u32 = 11;
pub const TMR6_STFLR_CMSBUF: u32 = 2048;
pub const TMR6_STFLR_CMSBDF_POS: u32 = 12;
pub const TMR6_STFLR_CMSBDF: u32 = 4096;
pub const TMR6_STFLR_VPERNUM_POS: u32 = 21;
pub const TMR6_STFLR_VPERNUM: u32 = 14680064;
pub const TMR6_STFLR_CMAF2_POS: u32 = 26;
pub const TMR6_STFLR_CMAF2: u32 = 67108864;
pub const TMR6_STFLR_CMBF2_POS: u32 = 27;
pub const TMR6_STFLR_CMBF2: u32 = 134217728;
pub const TMR6_STFLR_DIRF_POS: u32 = 31;
pub const TMR6_STFLR_DIRF: u32 = 2147483648;
pub const TMR6_HSTAR_HSTA0_POS: u32 = 0;
pub const TMR6_HSTAR_HSTA0: u32 = 1;
pub const TMR6_HSTAR_HSTA1_POS: u32 = 1;
pub const TMR6_HSTAR_HSTA1: u32 = 2;
pub const TMR6_HSTAR_HSTA2_POS: u32 = 2;
pub const TMR6_HSTAR_HSTA2: u32 = 4;
pub const TMR6_HSTAR_HSTA3_POS: u32 = 3;
pub const TMR6_HSTAR_HSTA3: u32 = 8;
pub const TMR6_HSTAR_STAS_POS: u32 = 7;
pub const TMR6_HSTAR_STAS: u32 = 128;
pub const TMR6_HSTAR_HSTA8_POS: u32 = 8;
pub const TMR6_HSTAR_HSTA8: u32 = 256;
pub const TMR6_HSTAR_HSTA9_POS: u32 = 9;
pub const TMR6_HSTAR_HSTA9: u32 = 512;
pub const TMR6_HSTAR_HSTA16_POS: u32 = 16;
pub const TMR6_HSTAR_HSTA16: u32 = 65536;
pub const TMR6_HSTAR_HSTA17_POS: u32 = 17;
pub const TMR6_HSTAR_HSTA17: u32 = 131072;
pub const TMR6_HSTAR_HSTA18_POS: u32 = 18;
pub const TMR6_HSTAR_HSTA18: u32 = 262144;
pub const TMR6_HSTAR_HSTA19_POS: u32 = 19;
pub const TMR6_HSTAR_HSTA19: u32 = 524288;
pub const TMR6_HSTPR_HSTP0_POS: u32 = 0;
pub const TMR6_HSTPR_HSTP0: u32 = 1;
pub const TMR6_HSTPR_HSTP1_POS: u32 = 1;
pub const TMR6_HSTPR_HSTP1: u32 = 2;
pub const TMR6_HSTPR_HSTP2_POS: u32 = 2;
pub const TMR6_HSTPR_HSTP2: u32 = 4;
pub const TMR6_HSTPR_HSTP3_POS: u32 = 3;
pub const TMR6_HSTPR_HSTP3: u32 = 8;
pub const TMR6_HSTPR_STPS_POS: u32 = 7;
pub const TMR6_HSTPR_STPS: u32 = 128;
pub const TMR6_HSTPR_HSTP8_POS: u32 = 8;
pub const TMR6_HSTPR_HSTP8: u32 = 256;
pub const TMR6_HSTPR_HSTP9_POS: u32 = 9;
pub const TMR6_HSTPR_HSTP9: u32 = 512;
pub const TMR6_HSTPR_HSTP16_POS: u32 = 16;
pub const TMR6_HSTPR_HSTP16: u32 = 65536;
pub const TMR6_HSTPR_HSTP17_POS: u32 = 17;
pub const TMR6_HSTPR_HSTP17: u32 = 131072;
pub const TMR6_HSTPR_HSTP18_POS: u32 = 18;
pub const TMR6_HSTPR_HSTP18: u32 = 262144;
pub const TMR6_HSTPR_HSTP19_POS: u32 = 19;
pub const TMR6_HSTPR_HSTP19: u32 = 524288;
pub const TMR6_HCLRR_HCLE0_POS: u32 = 0;
pub const TMR6_HCLRR_HCLE0: u32 = 1;
pub const TMR6_HCLRR_HCLE1_POS: u32 = 1;
pub const TMR6_HCLRR_HCLE1: u32 = 2;
pub const TMR6_HCLRR_HCLE2_POS: u32 = 2;
pub const TMR6_HCLRR_HCLE2: u32 = 4;
pub const TMR6_HCLRR_HCLE3_POS: u32 = 3;
pub const TMR6_HCLRR_HCLE3: u32 = 8;
pub const TMR6_HCLRR_CLES_POS: u32 = 7;
pub const TMR6_HCLRR_CLES: u32 = 128;
pub const TMR6_HCLRR_HCLE8_POS: u32 = 8;
pub const TMR6_HCLRR_HCLE8: u32 = 256;
pub const TMR6_HCLRR_HCLE9_POS: u32 = 9;
pub const TMR6_HCLRR_HCLE9: u32 = 512;
pub const TMR6_HCLRR_HCLE16_POS: u32 = 16;
pub const TMR6_HCLRR_HCLE16: u32 = 65536;
pub const TMR6_HCLRR_HCLE17_POS: u32 = 17;
pub const TMR6_HCLRR_HCLE17: u32 = 131072;
pub const TMR6_HCLRR_HCLE18_POS: u32 = 18;
pub const TMR6_HCLRR_HCLE18: u32 = 262144;
pub const TMR6_HCLRR_HCLE19_POS: u32 = 19;
pub const TMR6_HCLRR_HCLE19: u32 = 524288;
pub const TMR6_HUPDR_HUPD0_POS: u32 = 0;
pub const TMR6_HUPDR_HUPD0: u32 = 1;
pub const TMR6_HUPDR_HUPD1_POS: u32 = 1;
pub const TMR6_HUPDR_HUPD1: u32 = 2;
pub const TMR6_HUPDR_HUPD2_POS: u32 = 2;
pub const TMR6_HUPDR_HUPD2: u32 = 4;
pub const TMR6_HUPDR_HUPD3_POS: u32 = 3;
pub const TMR6_HUPDR_HUPD3: u32 = 8;
pub const TMR6_HUPDR_UPDS_POS: u32 = 7;
pub const TMR6_HUPDR_UPDS: u32 = 128;
pub const TMR6_HUPDR_HUPD8_POS: u32 = 8;
pub const TMR6_HUPDR_HUPD8: u32 = 256;
pub const TMR6_HUPDR_HUPD9_POS: u32 = 9;
pub const TMR6_HUPDR_HUPD9: u32 = 512;
pub const TMR6_HUPDR_HUPD16_POS: u32 = 16;
pub const TMR6_HUPDR_HUPD16: u32 = 65536;
pub const TMR6_HUPDR_HUPD17_POS: u32 = 17;
pub const TMR6_HUPDR_HUPD17: u32 = 131072;
pub const TMR6_HUPDR_HUPD18_POS: u32 = 18;
pub const TMR6_HUPDR_HUPD18: u32 = 262144;
pub const TMR6_HUPDR_HUPD19_POS: u32 = 19;
pub const TMR6_HUPDR_HUPD19: u32 = 524288;
pub const TMR6_HCPAR_HCPA0_POS: u32 = 0;
pub const TMR6_HCPAR_HCPA0: u32 = 1;
pub const TMR6_HCPAR_HCPA1_POS: u32 = 1;
pub const TMR6_HCPAR_HCPA1: u32 = 2;
pub const TMR6_HCPAR_HCPA2_POS: u32 = 2;
pub const TMR6_HCPAR_HCPA2: u32 = 4;
pub const TMR6_HCPAR_HCPA3_POS: u32 = 3;
pub const TMR6_HCPAR_HCPA3: u32 = 8;
pub const TMR6_HCPAR_HCPA8_POS: u32 = 8;
pub const TMR6_HCPAR_HCPA8: u32 = 256;
pub const TMR6_HCPAR_HCPA9_POS: u32 = 9;
pub const TMR6_HCPAR_HCPA9: u32 = 512;
pub const TMR6_HCPAR_HCPA16_POS: u32 = 16;
pub const TMR6_HCPAR_HCPA16: u32 = 65536;
pub const TMR6_HCPAR_HCPA17_POS: u32 = 17;
pub const TMR6_HCPAR_HCPA17: u32 = 131072;
pub const TMR6_HCPAR_HCPA18_POS: u32 = 18;
pub const TMR6_HCPAR_HCPA18: u32 = 262144;
pub const TMR6_HCPAR_HCPA19_POS: u32 = 19;
pub const TMR6_HCPAR_HCPA19: u32 = 524288;
pub const TMR6_HCPAR_HCPA24_POS: u32 = 24;
pub const TMR6_HCPAR_HCPA24: u32 = 16777216;
pub const TMR6_HCPAR_HCPA25_POS: u32 = 25;
pub const TMR6_HCPAR_HCPA25: u32 = 33554432;
pub const TMR6_HCPBR_HCPB0_POS: u32 = 0;
pub const TMR6_HCPBR_HCPB0: u32 = 1;
pub const TMR6_HCPBR_HCPB1_POS: u32 = 1;
pub const TMR6_HCPBR_HCPB1: u32 = 2;
pub const TMR6_HCPBR_HCPB2_POS: u32 = 2;
pub const TMR6_HCPBR_HCPB2: u32 = 4;
pub const TMR6_HCPBR_HCPB3_POS: u32 = 3;
pub const TMR6_HCPBR_HCPB3: u32 = 8;
pub const TMR6_HCPBR_HCPB8_POS: u32 = 8;
pub const TMR6_HCPBR_HCPB8: u32 = 256;
pub const TMR6_HCPBR_HCPB9_POS: u32 = 9;
pub const TMR6_HCPBR_HCPB9: u32 = 512;
pub const TMR6_HCPBR_HCPB16_POS: u32 = 16;
pub const TMR6_HCPBR_HCPB16: u32 = 65536;
pub const TMR6_HCPBR_HCPB17_POS: u32 = 17;
pub const TMR6_HCPBR_HCPB17: u32 = 131072;
pub const TMR6_HCPBR_HCPB18_POS: u32 = 18;
pub const TMR6_HCPBR_HCPB18: u32 = 262144;
pub const TMR6_HCPBR_HCPB19_POS: u32 = 19;
pub const TMR6_HCPBR_HCPB19: u32 = 524288;
pub const TMR6_HCPBR_HCPB24_POS: u32 = 24;
pub const TMR6_HCPBR_HCPB24: u32 = 16777216;
pub const TMR6_HCPBR_HCPB25_POS: u32 = 25;
pub const TMR6_HCPBR_HCPB25: u32 = 33554432;
pub const TMR6_HCUPR_HCUP0_POS: u32 = 0;
pub const TMR6_HCUPR_HCUP0: u32 = 1;
pub const TMR6_HCUPR_HCUP1_POS: u32 = 1;
pub const TMR6_HCUPR_HCUP1: u32 = 2;
pub const TMR6_HCUPR_HCUP2_POS: u32 = 2;
pub const TMR6_HCUPR_HCUP2: u32 = 4;
pub const TMR6_HCUPR_HCUP3_POS: u32 = 3;
pub const TMR6_HCUPR_HCUP3: u32 = 8;
pub const TMR6_HCUPR_HCUP4_POS: u32 = 4;
pub const TMR6_HCUPR_HCUP4: u32 = 16;
pub const TMR6_HCUPR_HCUP5_POS: u32 = 5;
pub const TMR6_HCUPR_HCUP5: u32 = 32;
pub const TMR6_HCUPR_HCUP6_POS: u32 = 6;
pub const TMR6_HCUPR_HCUP6: u32 = 64;
pub const TMR6_HCUPR_HCUP7_POS: u32 = 7;
pub const TMR6_HCUPR_HCUP7: u32 = 128;
pub const TMR6_HCUPR_HCUP8_POS: u32 = 8;
pub const TMR6_HCUPR_HCUP8: u32 = 256;
pub const TMR6_HCUPR_HCUP9_POS: u32 = 9;
pub const TMR6_HCUPR_HCUP9: u32 = 512;
pub const TMR6_HCUPR_HCUP16_POS: u32 = 16;
pub const TMR6_HCUPR_HCUP16: u32 = 65536;
pub const TMR6_HCUPR_HCUP17_POS: u32 = 17;
pub const TMR6_HCUPR_HCUP17: u32 = 131072;
pub const TMR6_HCUPR_HCUP18_POS: u32 = 18;
pub const TMR6_HCUPR_HCUP18: u32 = 262144;
pub const TMR6_HCUPR_HCUP19_POS: u32 = 19;
pub const TMR6_HCUPR_HCUP19: u32 = 524288;
pub const TMR6_HCDOR_HCDO0_POS: u32 = 0;
pub const TMR6_HCDOR_HCDO0: u32 = 1;
pub const TMR6_HCDOR_HCDO1_POS: u32 = 1;
pub const TMR6_HCDOR_HCDO1: u32 = 2;
pub const TMR6_HCDOR_HCDO2_POS: u32 = 2;
pub const TMR6_HCDOR_HCDO2: u32 = 4;
pub const TMR6_HCDOR_HCDO3_POS: u32 = 3;
pub const TMR6_HCDOR_HCDO3: u32 = 8;
pub const TMR6_HCDOR_HCDO4_POS: u32 = 4;
pub const TMR6_HCDOR_HCDO4: u32 = 16;
pub const TMR6_HCDOR_HCDO5_POS: u32 = 5;
pub const TMR6_HCDOR_HCDO5: u32 = 32;
pub const TMR6_HCDOR_HCDO6_POS: u32 = 6;
pub const TMR6_HCDOR_HCDO6: u32 = 64;
pub const TMR6_HCDOR_HCDO7_POS: u32 = 7;
pub const TMR6_HCDOR_HCDO7: u32 = 128;
pub const TMR6_HCDOR_HCDO8_POS: u32 = 8;
pub const TMR6_HCDOR_HCDO8: u32 = 256;
pub const TMR6_HCDOR_HCDO9_POS: u32 = 9;
pub const TMR6_HCDOR_HCDO9: u32 = 512;
pub const TMR6_HCDOR_HCDO16_POS: u32 = 16;
pub const TMR6_HCDOR_HCDO16: u32 = 65536;
pub const TMR6_HCDOR_HCDO17_POS: u32 = 17;
pub const TMR6_HCDOR_HCDO17: u32 = 131072;
pub const TMR6_HCDOR_HCDO18_POS: u32 = 18;
pub const TMR6_HCDOR_HCDO18: u32 = 262144;
pub const TMR6_HCDOR_HCDO19_POS: u32 = 19;
pub const TMR6_HCDOR_HCDO19: u32 = 524288;
pub const TMR6_COMMON_FCNTR_NOFIENTA_POS: u32 = 0;
pub const TMR6_COMMON_FCNTR_NOFIENTA: u32 = 1;
pub const TMR6_COMMON_FCNTR_NOFICKTA_POS: u32 = 1;
pub const TMR6_COMMON_FCNTR_NOFICKTA: u32 = 6;
pub const TMR6_COMMON_FCNTR_NOFICKTA_0: u32 = 2;
pub const TMR6_COMMON_FCNTR_NOFICKTA_1: u32 = 4;
pub const TMR6_COMMON_FCNTR_NOFIENTB_POS: u32 = 4;
pub const TMR6_COMMON_FCNTR_NOFIENTB: u32 = 16;
pub const TMR6_COMMON_FCNTR_NOFICKTB_POS: u32 = 5;
pub const TMR6_COMMON_FCNTR_NOFICKTB: u32 = 96;
pub const TMR6_COMMON_FCNTR_NOFICKTB_0: u32 = 32;
pub const TMR6_COMMON_FCNTR_NOFICKTB_1: u32 = 64;
pub const TMR6_COMMON_SSTAR_SSTA1_POS: u32 = 0;
pub const TMR6_COMMON_SSTAR_SSTA1: u32 = 1;
pub const TMR6_COMMON_SSTAR_SSTA2_POS: u32 = 1;
pub const TMR6_COMMON_SSTAR_SSTA2: u32 = 2;
pub const TMR6_COMMON_SSTPR_SSTP1_POS: u32 = 0;
pub const TMR6_COMMON_SSTPR_SSTP1: u32 = 1;
pub const TMR6_COMMON_SSTPR_SSTP2_POS: u32 = 1;
pub const TMR6_COMMON_SSTPR_SSTP2: u32 = 2;
pub const TMR6_COMMON_SCLRR_SCLE1_POS: u32 = 0;
pub const TMR6_COMMON_SCLRR_SCLE1: u32 = 1;
pub const TMR6_COMMON_SCLRR_SCLE2_POS: u32 = 1;
pub const TMR6_COMMON_SCLRR_SCLE2: u32 = 2;
pub const TMR6_COMMON_SUPDR_SUPD1_POS: u32 = 0;
pub const TMR6_COMMON_SUPDR_SUPD1: u32 = 1;
pub const TMR6_COMMON_SUPDR_SUPD2_POS: u32 = 1;
pub const TMR6_COMMON_SUPDR_SUPD2: u32 = 2;
pub const TMRA_CNTER_CNT: u32 = 4294967295;
pub const TMRA_PERAR_PER: u32 = 4294967295;
pub const TMRA_CMPAR_CMP: u32 = 4294967295;
pub const TMRA_BCSTRL_START_POS: u32 = 0;
pub const TMRA_BCSTRL_START: u32 = 1;
pub const TMRA_BCSTRL_DIR_POS: u32 = 1;
pub const TMRA_BCSTRL_DIR: u32 = 2;
pub const TMRA_BCSTRL_MODE_POS: u32 = 2;
pub const TMRA_BCSTRL_MODE: u32 = 4;
pub const TMRA_BCSTRL_SYNST_POS: u32 = 3;
pub const TMRA_BCSTRL_SYNST: u32 = 8;
pub const TMRA_BCSTRL_CKDIV_POS: u32 = 4;
pub const TMRA_BCSTRL_CKDIV: u32 = 240;
pub const TMRA_BCSTRH_OVSTP_POS: u32 = 0;
pub const TMRA_BCSTRH_OVSTP: u32 = 1;
pub const TMRA_BCSTRH_ITENOVF_POS: u32 = 4;
pub const TMRA_BCSTRH_ITENOVF: u32 = 16;
pub const TMRA_BCSTRH_ITENUDF_POS: u32 = 5;
pub const TMRA_BCSTRH_ITENUDF: u32 = 32;
pub const TMRA_BCSTRH_OVFF_POS: u32 = 6;
pub const TMRA_BCSTRH_OVFF: u32 = 64;
pub const TMRA_BCSTRH_UDFF_POS: u32 = 7;
pub const TMRA_BCSTRH_UDFF: u32 = 128;
pub const TMRA_HCONR_HSTA0_POS: u32 = 0;
pub const TMRA_HCONR_HSTA0: u32 = 1;
pub const TMRA_HCONR_HSTA1_POS: u32 = 1;
pub const TMRA_HCONR_HSTA1: u32 = 2;
pub const TMRA_HCONR_HSTA2_POS: u32 = 2;
pub const TMRA_HCONR_HSTA2: u32 = 4;
pub const TMRA_HCONR_HSTP0_POS: u32 = 4;
pub const TMRA_HCONR_HSTP0: u32 = 16;
pub const TMRA_HCONR_HSTP1_POS: u32 = 5;
pub const TMRA_HCONR_HSTP1: u32 = 32;
pub const TMRA_HCONR_HSTP2_POS: u32 = 6;
pub const TMRA_HCONR_HSTP2: u32 = 64;
pub const TMRA_HCONR_HCLE0_POS: u32 = 8;
pub const TMRA_HCONR_HCLE0: u32 = 256;
pub const TMRA_HCONR_HCLE1_POS: u32 = 9;
pub const TMRA_HCONR_HCLE1: u32 = 512;
pub const TMRA_HCONR_HCLE2_POS: u32 = 10;
pub const TMRA_HCONR_HCLE2: u32 = 1024;
pub const TMRA_HCONR_HCLE3_POS: u32 = 12;
pub const TMRA_HCONR_HCLE3: u32 = 4096;
pub const TMRA_HCONR_HCLE4_POS: u32 = 13;
pub const TMRA_HCONR_HCLE4: u32 = 8192;
pub const TMRA_HCONR_HCLE5_POS: u32 = 14;
pub const TMRA_HCONR_HCLE5: u32 = 16384;
pub const TMRA_HCONR_HCLE6_POS: u32 = 15;
pub const TMRA_HCONR_HCLE6: u32 = 32768;
pub const TMRA_HCUPR_HCUP0_POS: u32 = 0;
pub const TMRA_HCUPR_HCUP0: u32 = 1;
pub const TMRA_HCUPR_HCUP1_POS: u32 = 1;
pub const TMRA_HCUPR_HCUP1: u32 = 2;
pub const TMRA_HCUPR_HCUP2_POS: u32 = 2;
pub const TMRA_HCUPR_HCUP2: u32 = 4;
pub const TMRA_HCUPR_HCUP3_POS: u32 = 3;
pub const TMRA_HCUPR_HCUP3: u32 = 8;
pub const TMRA_HCUPR_HCUP4_POS: u32 = 4;
pub const TMRA_HCUPR_HCUP4: u32 = 16;
pub const TMRA_HCUPR_HCUP5_POS: u32 = 5;
pub const TMRA_HCUPR_HCUP5: u32 = 32;
pub const TMRA_HCUPR_HCUP6_POS: u32 = 6;
pub const TMRA_HCUPR_HCUP6: u32 = 64;
pub const TMRA_HCUPR_HCUP7_POS: u32 = 7;
pub const TMRA_HCUPR_HCUP7: u32 = 128;
pub const TMRA_HCUPR_HCUP8_POS: u32 = 8;
pub const TMRA_HCUPR_HCUP8: u32 = 256;
pub const TMRA_HCUPR_HCUP9_POS: u32 = 9;
pub const TMRA_HCUPR_HCUP9: u32 = 512;
pub const TMRA_HCUPR_HCUP10_POS: u32 = 10;
pub const TMRA_HCUPR_HCUP10: u32 = 1024;
pub const TMRA_HCUPR_HCUP11_POS: u32 = 11;
pub const TMRA_HCUPR_HCUP11: u32 = 2048;
pub const TMRA_HCUPR_HCUP12_POS: u32 = 12;
pub const TMRA_HCUPR_HCUP12: u32 = 4096;
pub const TMRA_HCDOR_HCDO0_POS: u32 = 0;
pub const TMRA_HCDOR_HCDO0: u32 = 1;
pub const TMRA_HCDOR_HCDO1_POS: u32 = 1;
pub const TMRA_HCDOR_HCDO1: u32 = 2;
pub const TMRA_HCDOR_HCDO2_POS: u32 = 2;
pub const TMRA_HCDOR_HCDO2: u32 = 4;
pub const TMRA_HCDOR_HCDO3_POS: u32 = 3;
pub const TMRA_HCDOR_HCDO3: u32 = 8;
pub const TMRA_HCDOR_HCDO4_POS: u32 = 4;
pub const TMRA_HCDOR_HCDO4: u32 = 16;
pub const TMRA_HCDOR_HCDO5_POS: u32 = 5;
pub const TMRA_HCDOR_HCDO5: u32 = 32;
pub const TMRA_HCDOR_HCDO6_POS: u32 = 6;
pub const TMRA_HCDOR_HCDO6: u32 = 64;
pub const TMRA_HCDOR_HCDO7_POS: u32 = 7;
pub const TMRA_HCDOR_HCDO7: u32 = 128;
pub const TMRA_HCDOR_HCDO8_POS: u32 = 8;
pub const TMRA_HCDOR_HCDO8: u32 = 256;
pub const TMRA_HCDOR_HCDO9_POS: u32 = 9;
pub const TMRA_HCDOR_HCDO9: u32 = 512;
pub const TMRA_HCDOR_HCDO10_POS: u32 = 10;
pub const TMRA_HCDOR_HCDO10: u32 = 1024;
pub const TMRA_HCDOR_HCDO11_POS: u32 = 11;
pub const TMRA_HCDOR_HCDO11: u32 = 2048;
pub const TMRA_HCDOR_HCDO12_POS: u32 = 12;
pub const TMRA_HCDOR_HCDO12: u32 = 4096;
pub const TMRA_ICONR_ITEN1_POS: u32 = 0;
pub const TMRA_ICONR_ITEN1: u32 = 1;
pub const TMRA_ICONR_ITEN2_POS: u32 = 1;
pub const TMRA_ICONR_ITEN2: u32 = 2;
pub const TMRA_ICONR_ITEN3_POS: u32 = 2;
pub const TMRA_ICONR_ITEN3: u32 = 4;
pub const TMRA_ICONR_ITEN4_POS: u32 = 3;
pub const TMRA_ICONR_ITEN4: u32 = 8;
pub const TMRA_ICONR_ITEN5_POS: u32 = 4;
pub const TMRA_ICONR_ITEN5: u32 = 16;
pub const TMRA_ICONR_ITEN6_POS: u32 = 5;
pub const TMRA_ICONR_ITEN6: u32 = 32;
pub const TMRA_ICONR_ITEN7_POS: u32 = 6;
pub const TMRA_ICONR_ITEN7: u32 = 64;
pub const TMRA_ICONR_ITEN8_POS: u32 = 7;
pub const TMRA_ICONR_ITEN8: u32 = 128;
pub const TMRA_ECONR_ETEN1_POS: u32 = 0;
pub const TMRA_ECONR_ETEN1: u32 = 1;
pub const TMRA_ECONR_ETEN2_POS: u32 = 1;
pub const TMRA_ECONR_ETEN2: u32 = 2;
pub const TMRA_ECONR_ETEN3_POS: u32 = 2;
pub const TMRA_ECONR_ETEN3: u32 = 4;
pub const TMRA_ECONR_ETEN4_POS: u32 = 3;
pub const TMRA_ECONR_ETEN4: u32 = 8;
pub const TMRA_ECONR_ETEN5_POS: u32 = 4;
pub const TMRA_ECONR_ETEN5: u32 = 16;
pub const TMRA_ECONR_ETEN6_POS: u32 = 5;
pub const TMRA_ECONR_ETEN6: u32 = 32;
pub const TMRA_ECONR_ETEN7_POS: u32 = 6;
pub const TMRA_ECONR_ETEN7: u32 = 64;
pub const TMRA_ECONR_ETEN8_POS: u32 = 7;
pub const TMRA_ECONR_ETEN8: u32 = 128;
pub const TMRA_FCONR_NOFIENTG_POS: u32 = 0;
pub const TMRA_FCONR_NOFIENTG: u32 = 1;
pub const TMRA_FCONR_NOFICKTG_POS: u32 = 1;
pub const TMRA_FCONR_NOFICKTG: u32 = 6;
pub const TMRA_FCONR_NOFIENCA_POS: u32 = 8;
pub const TMRA_FCONR_NOFIENCA: u32 = 256;
pub const TMRA_FCONR_NOFICKCA_POS: u32 = 9;
pub const TMRA_FCONR_NOFICKCA: u32 = 1536;
pub const TMRA_FCONR_NOFIENCB_POS: u32 = 12;
pub const TMRA_FCONR_NOFIENCB: u32 = 4096;
pub const TMRA_FCONR_NOFICKCB_POS: u32 = 13;
pub const TMRA_FCONR_NOFICKCB: u32 = 24576;
pub const TMRA_STFLR_CMPF1_POS: u32 = 0;
pub const TMRA_STFLR_CMPF1: u32 = 1;
pub const TMRA_STFLR_CMPF2_POS: u32 = 1;
pub const TMRA_STFLR_CMPF2: u32 = 2;
pub const TMRA_STFLR_CMPF3_POS: u32 = 2;
pub const TMRA_STFLR_CMPF3: u32 = 4;
pub const TMRA_STFLR_CMPF4_POS: u32 = 3;
pub const TMRA_STFLR_CMPF4: u32 = 8;
pub const TMRA_STFLR_CMPF5_POS: u32 = 4;
pub const TMRA_STFLR_CMPF5: u32 = 16;
pub const TMRA_STFLR_CMPF6_POS: u32 = 5;
pub const TMRA_STFLR_CMPF6: u32 = 32;
pub const TMRA_STFLR_CMPF7_POS: u32 = 6;
pub const TMRA_STFLR_CMPF7: u32 = 64;
pub const TMRA_STFLR_CMPF8_POS: u32 = 7;
pub const TMRA_STFLR_CMPF8: u32 = 128;
pub const TMRA_STFLR_ICPF1_POS: u32 = 8;
pub const TMRA_STFLR_ICPF1: u32 = 256;
pub const TMRA_STFLR_ICPF2_POS: u32 = 9;
pub const TMRA_STFLR_ICPF2: u32 = 512;
pub const TMRA_STFLR_ICPF3_POS: u32 = 10;
pub const TMRA_STFLR_ICPF3: u32 = 1024;
pub const TMRA_STFLR_ICPF4_POS: u32 = 11;
pub const TMRA_STFLR_ICPF4: u32 = 2048;
pub const TMRA_STFLR_ICPF5_POS: u32 = 12;
pub const TMRA_STFLR_ICPF5: u32 = 4096;
pub const TMRA_STFLR_ICPF6_POS: u32 = 13;
pub const TMRA_STFLR_ICPF6: u32 = 8192;
pub const TMRA_STFLR_ICPF7_POS: u32 = 14;
pub const TMRA_STFLR_ICPF7: u32 = 16384;
pub const TMRA_STFLR_ICPF8_POS: u32 = 15;
pub const TMRA_STFLR_ICPF8: u32 = 32768;
pub const TMRA_BCONR_BEN_POS: u32 = 0;
pub const TMRA_BCONR_BEN: u32 = 1;
pub const TMRA_BCONR_BSE0_POS: u32 = 1;
pub const TMRA_BCONR_BSE0: u32 = 2;
pub const TMRA_BCONR_BSE1_POS: u32 = 2;
pub const TMRA_BCONR_BSE1: u32 = 4;
pub const TMRA_BCONR_BSEN_POS: u32 = 3;
pub const TMRA_BCONR_BSEN: u32 = 8;
pub const TMRA_CCONR_CAPMD_POS: u32 = 0;
pub const TMRA_CCONR_CAPMD: u32 = 1;
pub const TMRA_CCONR_HICP0_POS: u32 = 4;
pub const TMRA_CCONR_HICP0: u32 = 16;
pub const TMRA_CCONR_HICP1_POS: u32 = 5;
pub const TMRA_CCONR_HICP1: u32 = 32;
pub const TMRA_CCONR_HICP2_POS: u32 = 6;
pub const TMRA_CCONR_HICP2: u32 = 64;
pub const TMRA_CCONR_HICP3_POS: u32 = 8;
pub const TMRA_CCONR_HICP3: u32 = 256;
pub const TMRA_CCONR_HICP4_POS: u32 = 9;
pub const TMRA_CCONR_HICP4: u32 = 512;
pub const TMRA_CCONR_HICP5_POS: u32 = 10;
pub const TMRA_CCONR_HICP5: u32 = 1024;
pub const TMRA_CCONR_HICP6_POS: u32 = 11;
pub const TMRA_CCONR_HICP6: u32 = 2048;
pub const TMRA_CCONR_NOFIENCP_POS: u32 = 12;
pub const TMRA_CCONR_NOFIENCP: u32 = 4096;
pub const TMRA_CCONR_NOFICKCP_POS: u32 = 13;
pub const TMRA_CCONR_NOFICKCP: u32 = 24576;
pub const TMRA_CCONR_NOFICKCP_0: u32 = 8192;
pub const TMRA_CCONR_NOFICKCP_1: u32 = 16384;
pub const TMRA_PCONR_STAC_POS: u32 = 0;
pub const TMRA_PCONR_STAC: u32 = 3;
pub const TMRA_PCONR_STAC_0: u32 = 1;
pub const TMRA_PCONR_STAC_1: u32 = 2;
pub const TMRA_PCONR_STPC_POS: u32 = 2;
pub const TMRA_PCONR_STPC: u32 = 12;
pub const TMRA_PCONR_STPC_0: u32 = 4;
pub const TMRA_PCONR_STPC_1: u32 = 8;
pub const TMRA_PCONR_CMPC_POS: u32 = 4;
pub const TMRA_PCONR_CMPC: u32 = 48;
pub const TMRA_PCONR_CMPC_0: u32 = 16;
pub const TMRA_PCONR_CMPC_1: u32 = 32;
pub const TMRA_PCONR_PERC_POS: u32 = 6;
pub const TMRA_PCONR_PERC: u32 = 192;
pub const TMRA_PCONR_PERC_0: u32 = 64;
pub const TMRA_PCONR_PERC_1: u32 = 128;
pub const TMRA_PCONR_FORC_POS: u32 = 8;
pub const TMRA_PCONR_FORC: u32 = 768;
pub const TMRA_PCONR_FORC_0: u32 = 256;
pub const TMRA_PCONR_FORC_1: u32 = 512;
pub const TMRA_PCONR_OUTEN_POS: u32 = 12;
pub const TMRA_PCONR_OUTEN: u32 = 4096;
pub const TRNG_CR_EN_POS: u32 = 0;
pub const TRNG_CR_EN: u32 = 1;
pub const TRNG_CR_RUN_POS: u32 = 1;
pub const TRNG_CR_RUN: u32 = 2;
pub const TRNG_MR_LOAD_POS: u32 = 0;
pub const TRNG_MR_LOAD: u32 = 1;
pub const TRNG_MR_CNT_POS: u32 = 2;
pub const TRNG_MR_CNT: u32 = 28;
pub const TRNG_DR0: u32 = 4294967295;
pub const TRNG_DR1: u32 = 4294967295;
pub const USART_SR_PE_POS: u32 = 0;
pub const USART_SR_PE: u32 = 1;
pub const USART_SR_FE_POS: u32 = 1;
pub const USART_SR_FE: u32 = 2;
pub const USART_SR_ORE_POS: u32 = 3;
pub const USART_SR_ORE: u32 = 8;
pub const USART_SR_BE_POS: u32 = 4;
pub const USART_SR_BE: u32 = 16;
pub const USART_SR_RXNE_POS: u32 = 5;
pub const USART_SR_RXNE: u32 = 32;
pub const USART_SR_TC_POS: u32 = 6;
pub const USART_SR_TC: u32 = 64;
pub const USART_SR_TXE_POS: u32 = 7;
pub const USART_SR_TXE: u32 = 128;
pub const USART_SR_RTOF_POS: u32 = 8;
pub const USART_SR_RTOF: u32 = 256;
pub const USART_SR_WKUP_POS: u32 = 9;
pub const USART_SR_WKUP: u32 = 512;
pub const USART_SR_LBD_POS: u32 = 10;
pub const USART_SR_LBD: u32 = 1024;
pub const USART_SR_TEND_POS: u32 = 11;
pub const USART_SR_TEND: u32 = 2048;
pub const USART_SR_MPB_POS: u32 = 16;
pub const USART_SR_MPB: u32 = 65536;
pub const USART_TDR_TDR_POS: u32 = 0;
pub const USART_TDR_TDR: u32 = 511;
pub const USART_TDR_MPID_POS: u32 = 9;
pub const USART_TDR_MPID: u32 = 512;
pub const USART_RDR_RDR: u32 = 511;
pub const USART_BRR_DIV_FRACTION_POS: u32 = 0;
pub const USART_BRR_DIV_FRACTION: u32 = 127;
pub const USART_BRR_DIV_INTEGER_POS: u32 = 8;
pub const USART_BRR_DIV_INTEGER: u32 = 65280;
pub const USART_CR1_RTOE_POS: u32 = 0;
pub const USART_CR1_RTOE: u32 = 1;
pub const USART_CR1_RTOIE_POS: u32 = 1;
pub const USART_CR1_RTOIE: u32 = 2;
pub const USART_CR1_RE_POS: u32 = 2;
pub const USART_CR1_RE: u32 = 4;
pub const USART_CR1_TE_POS: u32 = 3;
pub const USART_CR1_TE: u32 = 8;
pub const USART_CR1_SLME_POS: u32 = 4;
pub const USART_CR1_SLME: u32 = 16;
pub const USART_CR1_RIE_POS: u32 = 5;
pub const USART_CR1_RIE: u32 = 32;
pub const USART_CR1_TCIE_POS: u32 = 6;
pub const USART_CR1_TCIE: u32 = 64;
pub const USART_CR1_TXEIE_POS: u32 = 7;
pub const USART_CR1_TXEIE: u32 = 128;
pub const USART_CR1_TENDIE_POS: u32 = 8;
pub const USART_CR1_TENDIE: u32 = 256;
pub const USART_CR1_PS_POS: u32 = 9;
pub const USART_CR1_PS: u32 = 512;
pub const USART_CR1_PCE_POS: u32 = 10;
pub const USART_CR1_PCE: u32 = 1024;
pub const USART_CR1_M_POS: u32 = 12;
pub const USART_CR1_M: u32 = 4096;
pub const USART_CR1_OVER8_POS: u32 = 15;
pub const USART_CR1_OVER8: u32 = 32768;
pub const USART_CR1_CPE_POS: u32 = 16;
pub const USART_CR1_CPE: u32 = 65536;
pub const USART_CR1_CFE_POS: u32 = 17;
pub const USART_CR1_CFE: u32 = 131072;
pub const USART_CR1_CORE_POS: u32 = 19;
pub const USART_CR1_CORE: u32 = 524288;
pub const USART_CR1_CRTOF_POS: u32 = 20;
pub const USART_CR1_CRTOF: u32 = 1048576;
pub const USART_CR1_CBE_POS: u32 = 21;
pub const USART_CR1_CBE: u32 = 2097152;
pub const USART_CR1_CWKUP_POS: u32 = 22;
pub const USART_CR1_CWKUP: u32 = 4194304;
pub const USART_CR1_CLBD_POS: u32 = 23;
pub const USART_CR1_CLBD: u32 = 8388608;
pub const USART_CR1_MS_POS: u32 = 24;
pub const USART_CR1_MS: u32 = 16777216;
pub const USART_CR1_CTEND_POS: u32 = 25;
pub const USART_CR1_CTEND: u32 = 33554432;
pub const USART_CR1_ML_POS: u32 = 28;
pub const USART_CR1_ML: u32 = 268435456;
pub const USART_CR1_FBME_POS: u32 = 29;
pub const USART_CR1_FBME: u32 = 536870912;
pub const USART_CR1_NFE_POS: u32 = 30;
pub const USART_CR1_NFE: u32 = 1073741824;
pub const USART_CR1_SBS_POS: u32 = 31;
pub const USART_CR1_SBS: u32 = 2147483648;
pub const USART_CR2_MPE_POS: u32 = 0;
pub const USART_CR2_MPE: u32 = 1;
pub const USART_CR2_WKUPIE_POS: u32 = 1;
pub const USART_CR2_WKUPIE: u32 = 2;
pub const USART_CR2_BEIE_POS: u32 = 2;
pub const USART_CR2_BEIE: u32 = 4;
pub const USART_CR2_BEE_POS: u32 = 3;
pub const USART_CR2_BEE: u32 = 8;
pub const USART_CR2_LBDIE_POS: u32 = 4;
pub const USART_CR2_LBDIE: u32 = 16;
pub const USART_CR2_LBDL_POS: u32 = 5;
pub const USART_CR2_LBDL: u32 = 32;
pub const USART_CR2_SBKL_POS: u32 = 6;
pub const USART_CR2_SBKL: u32 = 192;
pub const USART_CR2_SBKL_0: u32 = 64;
pub const USART_CR2_SBKL_1: u32 = 128;
pub const USART_CR2_WKUPE_POS: u32 = 8;
pub const USART_CR2_WKUPE: u32 = 256;
pub const USART_CR2_CLKC_POS: u32 = 11;
pub const USART_CR2_CLKC: u32 = 6144;
pub const USART_CR2_CLKC_0: u32 = 2048;
pub const USART_CR2_CLKC_1: u32 = 4096;
pub const USART_CR2_STOP_POS: u32 = 13;
pub const USART_CR2_STOP: u32 = 8192;
pub const USART_CR2_LINEN_POS: u32 = 14;
pub const USART_CR2_LINEN: u32 = 16384;
pub const USART_CR2_SBK_POS: u32 = 16;
pub const USART_CR2_SBK: u32 = 65536;
pub const USART_CR2_SBKM_POS: u32 = 17;
pub const USART_CR2_SBKM: u32 = 131072;
pub const USART_CR3_HDSEL_POS: u32 = 3;
pub const USART_CR3_HDSEL: u32 = 8;
pub const USART_CR3_LOOP_POS: u32 = 4;
pub const USART_CR3_LOOP: u32 = 16;
pub const USART_CR3_SCEN_POS: u32 = 5;
pub const USART_CR3_SCEN: u32 = 32;
pub const USART_CR3_RTSE_POS: u32 = 8;
pub const USART_CR3_RTSE: u32 = 256;
pub const USART_CR3_CTSE_POS: u32 = 9;
pub const USART_CR3_CTSE: u32 = 512;
pub const USART_CR3_BCN_POS: u32 = 21;
pub const USART_CR3_BCN: u32 = 14680064;
pub const USART_PR_PSC_POS: u32 = 0;
pub const USART_PR_PSC: u32 = 3;
pub const USART_PR_PSC_0: u32 = 1;
pub const USART_PR_PSC_1: u32 = 2;
pub const USART_PR_LBMPSC_POS: u32 = 2;
pub const USART_PR_LBMPSC: u32 = 12;
pub const USART_PR_LBMPSC_0: u32 = 4;
pub const USART_PR_LBMPSC_1: u32 = 8;
pub const USART_PR_ULBREN_POS: u32 = 4;
pub const USART_PR_ULBREN: u32 = 16;
pub const USART_LBMC_LBMC: u32 = 65535;
pub const USART_LBMC_LBMC_0: u32 = 1;
pub const USART_LBMC_LBMC_1: u32 = 2;
pub const USART_LBMC_LBMC_2: u32 = 4;
pub const USART_LBMC_LBMC_3: u32 = 8;
pub const USART_LBMC_LBMC_4: u32 = 16;
pub const USART_LBMC_LBMC_5: u32 = 32;
pub const USART_LBMC_LBMC_6: u32 = 64;
pub const USART_LBMC_LBMC_7: u32 = 128;
pub const USART_LBMC_LBMC_8: u32 = 256;
pub const USART_LBMC_LBMC_9: u32 = 512;
pub const USART_LBMC_LBMC_10: u32 = 1024;
pub const USART_LBMC_LBMC_11: u32 = 2048;
pub const USART_LBMC_LBMC_12: u32 = 4096;
pub const USART_LBMC_LBMC_13: u32 = 8192;
pub const USART_LBMC_LBMC_14: u32 = 16384;
pub const USART_LBMC_LBMC_15: u32 = 32768;
pub const WDT_CR_PERI_POS: u32 = 0;
pub const WDT_CR_PERI: u32 = 3;
pub const WDT_CR_PERI_0: u32 = 1;
pub const WDT_CR_PERI_1: u32 = 2;
pub const WDT_CR_CKS_POS: u32 = 4;
pub const WDT_CR_CKS: u32 = 240;
pub const WDT_CR_WDPT_POS: u32 = 8;
pub const WDT_CR_WDPT: u32 = 3840;
pub const WDT_CR_SLPOFF_POS: u32 = 16;
pub const WDT_CR_SLPOFF: u32 = 65536;
pub const WDT_CR_ITS_POS: u32 = 31;
pub const WDT_CR_ITS: u32 = 2147483648;
pub const WDT_SR_CNT_POS: u32 = 0;
pub const WDT_SR_CNT: u32 = 65535;
pub const WDT_SR_UDF_POS: u32 = 16;
pub const WDT_SR_UDF: u32 = 65536;
pub const WDT_SR_REF_POS: u32 = 17;
pub const WDT_SR_REF: u32 = 131072;
pub const WDT_RR_RF: u32 = 65535;
pub const LL_ICG_ENABLE: u32 = 1;
pub const LL_UTILITY_ENABLE: u32 = 1;
pub const LL_PRINT_ENABLE: u32 = 0;
pub const LL_ADC_ENABLE: u32 = 1;
pub const LL_AES_ENABLE: u32 = 1;
pub const LL_AOS_ENABLE: u32 = 1;
pub const LL_CLK_ENABLE: u32 = 1;
pub const LL_CMP_ENABLE: u32 = 1;
pub const LL_CRC_ENABLE: u32 = 1;
pub const LL_CTC_ENABLE: u32 = 1;
pub const LL_DAC_ENABLE: u32 = 1;
pub const LL_DBGC_ENABLE: u32 = 1;
pub const LL_DCU_ENABLE: u32 = 1;
pub const LL_DMA_ENABLE: u32 = 1;
pub const LL_EFM_ENABLE: u32 = 1;
pub const LL_EMB_ENABLE: u32 = 1;
pub const LL_EVENT_PORT_ENABLE: u32 = 1;
pub const LL_FCG_ENABLE: u32 = 1;
pub const LL_FCM_ENABLE: u32 = 1;
pub const LL_GPIO_ENABLE: u32 = 1;
pub const LL_HASH_ENABLE: u32 = 1;
pub const LL_I2C_ENABLE: u32 = 1;
pub const LL_INTERRUPTS_ENABLE: u32 = 1;
pub const LL_KEYSCAN_ENABLE: u32 = 1;
pub const LL_MCAN_ENABLE: u32 = 1;
pub const LL_MPU_ENABLE: u32 = 1;
pub const LL_PWC_ENABLE: u32 = 1;
pub const LL_QSPI_ENABLE: u32 = 1;
pub const LL_RMU_ENABLE: u32 = 1;
pub const LL_RTC_ENABLE: u32 = 1;
pub const LL_SMC_ENABLE: u32 = 1;
pub const LL_SPI_ENABLE: u32 = 1;
pub const LL_SRAM_ENABLE: u32 = 1;
pub const LL_SWDT_ENABLE: u32 = 1;
pub const LL_TMR0_ENABLE: u32 = 1;
pub const LL_TMR4_ENABLE: u32 = 1;
pub const LL_TMR6_ENABLE: u32 = 1;
pub const LL_TMRA_ENABLE: u32 = 1;
pub const LL_TRNG_ENABLE: u32 = 1;
pub const LL_USART_ENABLE: u32 = 1;
pub const LL_WDT_ENABLE: u32 = 1;
pub const BSP_EV_HC32F448_LQFP80: u32 = 9;
pub const BSP_EV_HC32F4XX: u32 = 0;
pub const BSP_24CXX_ENABLE: u32 = 0;
pub const BSP_GT9XX_ENABLE: u32 = 0;
pub const BSP_IS61LV6416_ENABLE: u32 = 0;
pub const BSP_NT35510_ENABLE: u32 = 0;
pub const BSP_TCA9539_ENABLE: u32 = 0;
pub const BSP_W25QXX_ENABLE: u32 = 0;
pub const BSP_INT_KEY_ENABLE: u32 = 0;
pub const MRC_VALUE: u32 = 8000000;
pub const LRC_VALUE: u32 = 32768;
pub const SWDTLRC_VALUE: u32 = 10000;
pub const IRQn_Type_NMI_IRQn: IRQn_Type = -14;
pub const IRQn_Type_HardFault_IRQn: IRQn_Type = -13;
pub const IRQn_Type_MemManageFault_IRQn: IRQn_Type = -12;
pub const IRQn_Type_BusFault_IRQn: IRQn_Type = -11;
pub const IRQn_Type_UsageFault_IRQn: IRQn_Type = -10;
pub const IRQn_Type_SVC_IRQn: IRQn_Type = -5;
pub const IRQn_Type_DebugMonitor_IRQn: IRQn_Type = -4;
pub const IRQn_Type_PendSV_IRQn: IRQn_Type = -2;
pub const IRQn_Type_SysTick_IRQn: IRQn_Type = -1;
pub const IRQn_Type_INT000_IRQn: IRQn_Type = 0;
pub const IRQn_Type_INT001_IRQn: IRQn_Type = 1;
pub const IRQn_Type_INT002_IRQn: IRQn_Type = 2;
pub const IRQn_Type_INT003_IRQn: IRQn_Type = 3;
pub const IRQn_Type_INT004_IRQn: IRQn_Type = 4;
pub const IRQn_Type_INT005_IRQn: IRQn_Type = 5;
pub const IRQn_Type_INT006_IRQn: IRQn_Type = 6;
pub const IRQn_Type_INT007_IRQn: IRQn_Type = 7;
pub const IRQn_Type_INT008_IRQn: IRQn_Type = 8;
pub const IRQn_Type_INT009_IRQn: IRQn_Type = 9;
pub const IRQn_Type_INT010_IRQn: IRQn_Type = 10;
pub const IRQn_Type_INT011_IRQn: IRQn_Type = 11;
pub const IRQn_Type_INT012_IRQn: IRQn_Type = 12;
pub const IRQn_Type_INT013_IRQn: IRQn_Type = 13;
pub const IRQn_Type_INT014_IRQn: IRQn_Type = 14;
pub const IRQn_Type_INT015_IRQn: IRQn_Type = 15;
pub const IRQn_Type_EXTINT_PORT_EIRQ0_IRQn: IRQn_Type = 16;
pub const IRQn_Type_EXTINT_PORT_EIRQ1_IRQn: IRQn_Type = 17;
pub const IRQn_Type_EXTINT_PORT_EIRQ2_IRQn: IRQn_Type = 18;
pub const IRQn_Type_EXTINT_PORT_EIRQ3_IRQn: IRQn_Type = 19;
pub const IRQn_Type_EXTINT_PORT_EIRQ4_IRQn: IRQn_Type = 20;
pub const IRQn_Type_EXTINT_PORT_EIRQ5_IRQn: IRQn_Type = 21;
pub const IRQn_Type_EXTINT_PORT_EIRQ6_IRQn: IRQn_Type = 22;
pub const IRQn_Type_EXTINT_PORT_EIRQ7_IRQn: IRQn_Type = 23;
pub const IRQn_Type_EXTINT_PORT_EIRQ8_IRQn: IRQn_Type = 24;
pub const IRQn_Type_EXTINT_PORT_EIRQ9_IRQn: IRQn_Type = 25;
pub const IRQn_Type_EXTINT_PORT_EIRQ10_IRQn: IRQn_Type = 26;
pub const IRQn_Type_EXTINT_PORT_EIRQ11_IRQn: IRQn_Type = 27;
pub const IRQn_Type_EXTINT_PORT_EIRQ12_IRQn: IRQn_Type = 28;
pub const IRQn_Type_EXTINT_PORT_EIRQ13_IRQn: IRQn_Type = 29;
pub const IRQn_Type_EXTINT_PORT_EIRQ14_IRQn: IRQn_Type = 30;
pub const IRQn_Type_EXTINT_PORT_EIRQ15_IRQn: IRQn_Type = 31;
pub const IRQn_Type_SWINT0_IRQn: IRQn_Type = 0;
pub const IRQn_Type_SWINT1_IRQn: IRQn_Type = 1;
pub const IRQn_Type_SWINT2_IRQn: IRQn_Type = 2;
pub const IRQn_Type_SWINT3_IRQn: IRQn_Type = 3;
pub const IRQn_Type_SWINT4_IRQn: IRQn_Type = 4;
pub const IRQn_Type_SWINT5_IRQn: IRQn_Type = 5;
pub const IRQn_Type_SWINT6_IRQn: IRQn_Type = 6;
pub const IRQn_Type_SWINT7_IRQn: IRQn_Type = 7;
pub const IRQn_Type_SWINT8_IRQn: IRQn_Type = 8;
pub const IRQn_Type_SWINT9_IRQn: IRQn_Type = 9;
pub const IRQn_Type_SWINT10_IRQn: IRQn_Type = 10;
pub const IRQn_Type_SWINT11_IRQn: IRQn_Type = 11;
pub const IRQn_Type_SWINT12_IRQn: IRQn_Type = 12;
pub const IRQn_Type_SWINT13_IRQn: IRQn_Type = 13;
pub const IRQn_Type_SWINT14_IRQn: IRQn_Type = 14;
pub const IRQn_Type_SWINT15_IRQn: IRQn_Type = 15;
pub const IRQn_Type_SWINT16_IRQn: IRQn_Type = 16;
pub const IRQn_Type_SWINT17_IRQn: IRQn_Type = 17;
pub const IRQn_Type_SWINT18_IRQn: IRQn_Type = 18;
pub const IRQn_Type_SWINT19_IRQn: IRQn_Type = 19;
pub const IRQn_Type_SWINT20_IRQn: IRQn_Type = 20;
pub const IRQn_Type_SWINT21_IRQn: IRQn_Type = 21;
pub const IRQn_Type_SWINT22_IRQn: IRQn_Type = 22;
pub const IRQn_Type_SWINT23_IRQn: IRQn_Type = 23;
pub const IRQn_Type_SWINT24_IRQn: IRQn_Type = 24;
pub const IRQn_Type_SWINT25_IRQn: IRQn_Type = 25;
pub const IRQn_Type_SWINT26_IRQn: IRQn_Type = 26;
pub const IRQn_Type_SWINT27_IRQn: IRQn_Type = 27;
pub const IRQn_Type_SWINT28_IRQn: IRQn_Type = 28;
pub const IRQn_Type_SWINT29_IRQn: IRQn_Type = 29;
pub const IRQn_Type_SWINT30_IRQn: IRQn_Type = 30;
pub const IRQn_Type_SWINT31_IRQn: IRQn_Type = 31;
pub const IRQn_Type_DMA1_ERR_IRQn: IRQn_Type = 32;
pub const IRQn_Type_DMA1_TC0_BTC0_IRQn: IRQn_Type = 33;
pub const IRQn_Type_DMA1_TC1_BTC1_IRQn: IRQn_Type = 34;
pub const IRQn_Type_DMA1_TC2_BTC2_IRQn: IRQn_Type = 35;
pub const IRQn_Type_DMA1_TC3_BTC3_IRQn: IRQn_Type = 36;
pub const IRQn_Type_DMA1_TC4_BTC4_IRQn: IRQn_Type = 37;
pub const IRQn_Type_DMA1_TC5_BTC5_IRQn: IRQn_Type = 38;
pub const IRQn_Type_EFM_PEERR_RDCOL_IRQn: IRQn_Type = 39;
pub const IRQn_Type_EFM_OPTEND_IRQn: IRQn_Type = 40;
pub const IRQn_Type_QSPI_IRQn: IRQn_Type = 41;
pub const IRQn_Type_DCU1_IRQn: IRQn_Type = 42;
pub const IRQn_Type_DCU2_IRQn: IRQn_Type = 43;
pub const IRQn_Type_DCU3_IRQn: IRQn_Type = 44;
pub const IRQn_Type_DCU4_IRQn: IRQn_Type = 45;
pub const IRQn_Type_DMA2_ERR_IRQn: IRQn_Type = 46;
pub const IRQn_Type_DMA2_TC0_BTC0_IRQn: IRQn_Type = 47;
pub const IRQn_Type_DMA2_TC1_BTC1_IRQn: IRQn_Type = 48;
pub const IRQn_Type_DMA2_TC2_BTC2_IRQn: IRQn_Type = 49;
pub const IRQn_Type_DMA2_TC3_BTC3_IRQn: IRQn_Type = 50;
pub const IRQn_Type_DMA2_TC4_BTC4_IRQn: IRQn_Type = 51;
pub const IRQn_Type_DMA2_TC5_BTC5_IRQn: IRQn_Type = 52;
pub const IRQn_Type_TMR0_1_IRQn: IRQn_Type = 53;
pub const IRQn_Type_TMR0_2_IRQn: IRQn_Type = 54;
pub const IRQn_Type_RTC_IRQn: IRQn_Type = 55;
pub const IRQn_Type_XTAL_IRQn: IRQn_Type = 56;
pub const IRQn_Type_WKTM_IRQn: IRQn_Type = 57;
pub const IRQn_Type_SWDT_IRQn: IRQn_Type = 58;
pub const IRQn_Type_TMR6_1_GCMP_IRQn: IRQn_Type = 59;
pub const IRQn_Type_TMR6_1_OVF_UDF_IRQn: IRQn_Type = 60;
pub const IRQn_Type_TMR6_1_DTE_IRQn: IRQn_Type = 61;
pub const IRQn_Type_TMR6_1_SCMP_IRQn: IRQn_Type = 62;
pub const IRQn_Type_TMRA_1_OVF_UDF_IRQn: IRQn_Type = 63;
pub const IRQn_Type_TMRA_1_CMP_IRQn: IRQn_Type = 64;
pub const IRQn_Type_TMR6_2_GCMP_IRQn: IRQn_Type = 65;
pub const IRQn_Type_TMR6_2_OVF_UDF_IRQn: IRQn_Type = 66;
pub const IRQn_Type_TMR6_2_DTE_IRQn: IRQn_Type = 67;
pub const IRQn_Type_TMR6_2_SCMP_IRQn: IRQn_Type = 68;
pub const IRQn_Type_TMRA_2_OVF_UDF_IRQn: IRQn_Type = 69;
pub const IRQn_Type_TMRA_2_CMP_IRQn: IRQn_Type = 70;
pub const IRQn_Type_TMRA_3_OVF_UDF_IRQn: IRQn_Type = 71;
pub const IRQn_Type_TMRA_3_CMP_IRQn: IRQn_Type = 72;
pub const IRQn_Type_TMRA_4_OVF_UDF_IRQn: IRQn_Type = 73;
pub const IRQn_Type_TMRA_4_CMP_IRQn: IRQn_Type = 74;
pub const IRQn_Type_TMR4_1_GCMP_IRQn: IRQn_Type = 75;
pub const IRQn_Type_TMR4_1_OVF_UDF_IRQn: IRQn_Type = 76;
pub const IRQn_Type_TMR4_1_RELOAD_IRQn: IRQn_Type = 77;
pub const IRQn_Type_TMR4_1_SCMP_IRQn: IRQn_Type = 78;
pub const IRQn_Type_TMR4_2_GCMP_IRQn: IRQn_Type = 79;
pub const IRQn_Type_TMR4_2_OVF_UDF_IRQn: IRQn_Type = 80;
pub const IRQn_Type_TMR4_2_RELOAD_IRQn: IRQn_Type = 81;
pub const IRQn_Type_TMR4_2_SCMP_IRQn: IRQn_Type = 82;
pub const IRQn_Type_TMR4_3_GCMP_IRQn: IRQn_Type = 83;
pub const IRQn_Type_TMR4_3_OVF_UDF_IRQn: IRQn_Type = 84;
pub const IRQn_Type_TMR4_3_RELOAD_IRQn: IRQn_Type = 85;
pub const IRQn_Type_TMR4_3_SCMP_IRQn: IRQn_Type = 86;
pub const IRQn_Type_I2C1_IRQn: IRQn_Type = 87;
pub const IRQn_Type_I2C2_IRQn: IRQn_Type = 88;
pub const IRQn_Type_CMP1_IRQn: IRQn_Type = 89;
pub const IRQn_Type_CMP2_IRQn: IRQn_Type = 90;
pub const IRQn_Type_CMP3_IRQn: IRQn_Type = 91;
pub const IRQn_Type_CMP4_IRQn: IRQn_Type = 92;
pub const IRQn_Type_USART1_IRQn: IRQn_Type = 93;
pub const IRQn_Type_USART1_TCI_IRQn: IRQn_Type = 94;
pub const IRQn_Type_USART2_IRQn: IRQn_Type = 95;
pub const IRQn_Type_USART2_TCI_IRQn: IRQn_Type = 96;
pub const IRQn_Type_SPI1_IRQn: IRQn_Type = 97;
pub const IRQn_Type_TMRA_5_OVF_UDF_IRQn: IRQn_Type = 98;
pub const IRQn_Type_TMRA_5_CMP_IRQn: IRQn_Type = 99;
pub const IRQn_Type_EVENT_PORT1_IRQn: IRQn_Type = 100;
pub const IRQn_Type_EVENT_PORT2_IRQn: IRQn_Type = 101;
pub const IRQn_Type_EVENT_PORT3_IRQn: IRQn_Type = 102;
pub const IRQn_Type_EVENT_PORT4_IRQn: IRQn_Type = 103;
pub const IRQn_Type_USART3_IRQn: IRQn_Type = 104;
pub const IRQn_Type_USART3_TCI_IRQn: IRQn_Type = 105;
pub const IRQn_Type_USART4_IRQn: IRQn_Type = 106;
pub const IRQn_Type_USART4_TCI_IRQn: IRQn_Type = 107;
pub const IRQn_Type_SPI2_IRQn: IRQn_Type = 108;
pub const IRQn_Type_SPI3_IRQn: IRQn_Type = 109;
pub const IRQn_Type_EMB_GR0_IRQn: IRQn_Type = 110;
pub const IRQn_Type_EMB_GR1_IRQn: IRQn_Type = 111;
pub const IRQn_Type_EMB_GR2_IRQn: IRQn_Type = 112;
pub const IRQn_Type_EMB_GR3_IRQn: IRQn_Type = 113;
pub const IRQn_Type_USART5_IRQn: IRQn_Type = 114;
pub const IRQn_Type_USART5_TCI_IRQn: IRQn_Type = 115;
pub const IRQn_Type_USART6_IRQn: IRQn_Type = 116;
pub const IRQn_Type_USART6_TCI_IRQn: IRQn_Type = 117;
pub const IRQn_Type_MCAN1_INT0_IRQn: IRQn_Type = 118;
pub const IRQn_Type_MCAN1_INT1_IRQn: IRQn_Type = 119;
pub const IRQn_Type_MCAN2_INT0_IRQn: IRQn_Type = 120;
pub const IRQn_Type_MCAN2_INT1_IRQn: IRQn_Type = 121;
pub const IRQn_Type_USART1_WUPI_IRQn: IRQn_Type = 122;
pub const IRQn_Type_FCM_IRQn: IRQn_Type = 125;
pub const IRQn_Type_WDT_IRQn: IRQn_Type = 126;
pub const IRQn_Type_CTC_IRQn: IRQn_Type = 127;
pub const IRQn_Type_ADC1_IRQn: IRQn_Type = 128;
pub const IRQn_Type_ADC2_IRQn: IRQn_Type = 129;
pub const IRQn_Type_ADC3_IRQn: IRQn_Type = 130;
pub const IRQn_Type_TRNG_IRQn: IRQn_Type = 131;
#[doc = " Interrupt Number Definition"]
pub type IRQn_Type = ::core::ffi::c_int;
pub const en_event_src_t_EVT_SRC_SWI_IRQ0: en_event_src_t = 0;
pub const en_event_src_t_EVT_SRC_SWI_IRQ1: en_event_src_t = 1;
pub const en_event_src_t_EVT_SRC_SWI_IRQ2: en_event_src_t = 2;
pub const en_event_src_t_EVT_SRC_SWI_IRQ3: en_event_src_t = 3;
pub const en_event_src_t_EVT_SRC_SWI_IRQ4: en_event_src_t = 4;
pub const en_event_src_t_EVT_SRC_SWI_IRQ5: en_event_src_t = 5;
pub const en_event_src_t_EVT_SRC_SWI_IRQ6: en_event_src_t = 6;
pub const en_event_src_t_EVT_SRC_SWI_IRQ7: en_event_src_t = 7;
pub const en_event_src_t_EVT_SRC_SWI_IRQ8: en_event_src_t = 8;
pub const en_event_src_t_EVT_SRC_SWI_IRQ9: en_event_src_t = 9;
pub const en_event_src_t_EVT_SRC_SWI_IRQ10: en_event_src_t = 10;
pub const en_event_src_t_EVT_SRC_SWI_IRQ11: en_event_src_t = 11;
pub const en_event_src_t_EVT_SRC_SWI_IRQ12: en_event_src_t = 12;
pub const en_event_src_t_EVT_SRC_SWI_IRQ13: en_event_src_t = 13;
pub const en_event_src_t_EVT_SRC_SWI_IRQ14: en_event_src_t = 14;
pub const en_event_src_t_EVT_SRC_SWI_IRQ15: en_event_src_t = 15;
pub const en_event_src_t_EVT_SRC_SWI_IRQ16: en_event_src_t = 16;
pub const en_event_src_t_EVT_SRC_SWI_IRQ17: en_event_src_t = 17;
pub const en_event_src_t_EVT_SRC_SWI_IRQ18: en_event_src_t = 18;
pub const en_event_src_t_EVT_SRC_SWI_IRQ19: en_event_src_t = 19;
pub const en_event_src_t_EVT_SRC_SWI_IRQ20: en_event_src_t = 20;
pub const en_event_src_t_EVT_SRC_SWI_IRQ21: en_event_src_t = 21;
pub const en_event_src_t_EVT_SRC_SWI_IRQ22: en_event_src_t = 22;
pub const en_event_src_t_EVT_SRC_SWI_IRQ23: en_event_src_t = 23;
pub const en_event_src_t_EVT_SRC_SWI_IRQ24: en_event_src_t = 24;
pub const en_event_src_t_EVT_SRC_SWI_IRQ25: en_event_src_t = 25;
pub const en_event_src_t_EVT_SRC_SWI_IRQ26: en_event_src_t = 26;
pub const en_event_src_t_EVT_SRC_SWI_IRQ27: en_event_src_t = 27;
pub const en_event_src_t_EVT_SRC_SWI_IRQ28: en_event_src_t = 28;
pub const en_event_src_t_EVT_SRC_SWI_IRQ29: en_event_src_t = 29;
pub const en_event_src_t_EVT_SRC_SWI_IRQ30: en_event_src_t = 30;
pub const en_event_src_t_EVT_SRC_SWI_IRQ31: en_event_src_t = 31;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ0: en_event_src_t = 0;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ1: en_event_src_t = 1;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ2: en_event_src_t = 2;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ3: en_event_src_t = 3;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ4: en_event_src_t = 4;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ5: en_event_src_t = 5;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ6: en_event_src_t = 6;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ7: en_event_src_t = 7;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ8: en_event_src_t = 8;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ9: en_event_src_t = 9;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ10: en_event_src_t = 10;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ11: en_event_src_t = 11;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ12: en_event_src_t = 12;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ13: en_event_src_t = 13;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ14: en_event_src_t = 14;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ15: en_event_src_t = 15;
pub const en_event_src_t_EVT_SRC_DMA1_TC0: en_event_src_t = 33;
pub const en_event_src_t_EVT_SRC_DMA1_BTC0: en_event_src_t = 34;
pub const en_event_src_t_EVT_SRC_DMA1_TC1: en_event_src_t = 35;
pub const en_event_src_t_EVT_SRC_DMA1_BTC1: en_event_src_t = 36;
pub const en_event_src_t_EVT_SRC_DMA1_TC2: en_event_src_t = 37;
pub const en_event_src_t_EVT_SRC_DMA1_BTC2: en_event_src_t = 38;
pub const en_event_src_t_EVT_SRC_DMA1_TC3: en_event_src_t = 39;
pub const en_event_src_t_EVT_SRC_DMA1_BTC3: en_event_src_t = 40;
pub const en_event_src_t_EVT_SRC_DMA1_TC4: en_event_src_t = 41;
pub const en_event_src_t_EVT_SRC_DMA1_BTC4: en_event_src_t = 42;
pub const en_event_src_t_EVT_SRC_DMA1_TC5: en_event_src_t = 43;
pub const en_event_src_t_EVT_SRC_DMA1_BTC5: en_event_src_t = 44;
pub const en_event_src_t_EVT_SRC_EFM_OPTEND: en_event_src_t = 51;
pub const en_event_src_t_EVT_SRC_DCU1: en_event_src_t = 55;
pub const en_event_src_t_EVT_SRC_DCU2: en_event_src_t = 56;
pub const en_event_src_t_EVT_SRC_DCU3: en_event_src_t = 57;
pub const en_event_src_t_EVT_SRC_DCU4: en_event_src_t = 58;
pub const en_event_src_t_EVT_SRC_DMA2_TC0: en_event_src_t = 65;
pub const en_event_src_t_EVT_SRC_DMA2_BTC0: en_event_src_t = 66;
pub const en_event_src_t_EVT_SRC_DMA2_TC1: en_event_src_t = 67;
pub const en_event_src_t_EVT_SRC_DMA2_BTC1: en_event_src_t = 68;
pub const en_event_src_t_EVT_SRC_DMA2_TC2: en_event_src_t = 69;
pub const en_event_src_t_EVT_SRC_DMA2_BTC2: en_event_src_t = 70;
pub const en_event_src_t_EVT_SRC_DMA2_TC3: en_event_src_t = 71;
pub const en_event_src_t_EVT_SRC_DMA2_BTC3: en_event_src_t = 72;
pub const en_event_src_t_EVT_SRC_DMA2_TC4: en_event_src_t = 73;
pub const en_event_src_t_EVT_SRC_DMA2_BTC4: en_event_src_t = 74;
pub const en_event_src_t_EVT_SRC_DMA2_TC5: en_event_src_t = 75;
pub const en_event_src_t_EVT_SRC_DMA2_BTC5: en_event_src_t = 76;
pub const en_event_src_t_EVT_SRC_TMR0_1_CMP_A: en_event_src_t = 96;
pub const en_event_src_t_EVT_SRC_TMR0_1_CMP_B: en_event_src_t = 97;
pub const en_event_src_t_EVT_SRC_TMR0_1_OVF_A: en_event_src_t = 98;
pub const en_event_src_t_EVT_SRC_TMR0_1_OVF_B: en_event_src_t = 99;
pub const en_event_src_t_EVT_SRC_TMR0_2_CMP_A: en_event_src_t = 100;
pub const en_event_src_t_EVT_SRC_TMR0_2_CMP_B: en_event_src_t = 101;
pub const en_event_src_t_EVT_SRC_TMR0_2_OVF_A: en_event_src_t = 102;
pub const en_event_src_t_EVT_SRC_TMR0_2_OVF_B: en_event_src_t = 103;
pub const en_event_src_t_EVT_SRC_RTC_ALM: en_event_src_t = 121;
pub const en_event_src_t_EVT_SRC_RTC_PRD: en_event_src_t = 122;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_A: en_event_src_t = 128;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_B: en_event_src_t = 129;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_C: en_event_src_t = 130;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_D: en_event_src_t = 131;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_E: en_event_src_t = 132;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_F: en_event_src_t = 133;
pub const en_event_src_t_EVT_SRC_TMR6_1_OVF: en_event_src_t = 134;
pub const en_event_src_t_EVT_SRC_TMR6_1_UDF: en_event_src_t = 135;
pub const en_event_src_t_EVT_SRC_TMR6_1_SCMP_A: en_event_src_t = 137;
pub const en_event_src_t_EVT_SRC_TMR6_1_SCMP_B: en_event_src_t = 138;
pub const en_event_src_t_EVT_SRC_TMRA_1_OVF: en_event_src_t = 139;
pub const en_event_src_t_EVT_SRC_TMRA_1_UDF: en_event_src_t = 140;
pub const en_event_src_t_EVT_SRC_TMRA_1_CMP: en_event_src_t = 141;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_A: en_event_src_t = 144;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_B: en_event_src_t = 145;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_C: en_event_src_t = 146;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_D: en_event_src_t = 147;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_E: en_event_src_t = 148;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_F: en_event_src_t = 149;
pub const en_event_src_t_EVT_SRC_TMR6_2_OVF: en_event_src_t = 150;
pub const en_event_src_t_EVT_SRC_TMR6_2_UDF: en_event_src_t = 151;
pub const en_event_src_t_EVT_SRC_TMR6_2_SCMP_A: en_event_src_t = 153;
pub const en_event_src_t_EVT_SRC_TMR6_2_SCMP_B: en_event_src_t = 154;
pub const en_event_src_t_EVT_SRC_TMRA_2_OVF: en_event_src_t = 155;
pub const en_event_src_t_EVT_SRC_TMRA_2_UDF: en_event_src_t = 156;
pub const en_event_src_t_EVT_SRC_TMRA_2_CMP: en_event_src_t = 157;
pub const en_event_src_t_EVT_SRC_TMRA_3_OVF: en_event_src_t = 171;
pub const en_event_src_t_EVT_SRC_TMRA_3_UDF: en_event_src_t = 172;
pub const en_event_src_t_EVT_SRC_TMRA_3_CMP: en_event_src_t = 173;
pub const en_event_src_t_EVT_SRC_TMRA_4_OVF: en_event_src_t = 187;
pub const en_event_src_t_EVT_SRC_TMRA_4_UDF: en_event_src_t = 188;
pub const en_event_src_t_EVT_SRC_TMRA_4_CMP: en_event_src_t = 189;
pub const en_event_src_t_EVT_SRC_TMR4_1_GCMP_UH: en_event_src_t = 192;
pub const en_event_src_t_EVT_SRC_TMR4_1_GCMP_UL: en_event_src_t = 193;
pub const en_event_src_t_EVT_SRC_TMR4_1_GCMP_VH: en_event_src_t = 194;
pub const en_event_src_t_EVT_SRC_TMR4_1_GCMP_VL: en_event_src_t = 195;
pub const en_event_src_t_EVT_SRC_TMR4_1_GCMP_WH: en_event_src_t = 196;
pub const en_event_src_t_EVT_SRC_TMR4_1_GCMP_WL: en_event_src_t = 197;
pub const en_event_src_t_EVT_SRC_TMR4_1_GCMP_XH: en_event_src_t = 198;
pub const en_event_src_t_EVT_SRC_TMR4_1_GCMP_XL: en_event_src_t = 199;
pub const en_event_src_t_EVT_SRC_TMR4_1_OVF: en_event_src_t = 200;
pub const en_event_src_t_EVT_SRC_TMR4_1_UDF: en_event_src_t = 201;
pub const en_event_src_t_EVT_SRC_TMR4_1_RELOAD_U: en_event_src_t = 202;
pub const en_event_src_t_EVT_SRC_TMR4_1_RELOAD_V: en_event_src_t = 203;
pub const en_event_src_t_EVT_SRC_TMR4_1_RELOAD_W: en_event_src_t = 204;
pub const en_event_src_t_EVT_SRC_TMR4_1_RELOAD_X: en_event_src_t = 205;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP0: en_event_src_t = 206;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP1: en_event_src_t = 207;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP2: en_event_src_t = 208;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP3: en_event_src_t = 209;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP4: en_event_src_t = 210;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP5: en_event_src_t = 211;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP6: en_event_src_t = 212;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP7: en_event_src_t = 213;
pub const en_event_src_t_EVT_SRC_TMR4_2_GCMP_UH: en_event_src_t = 224;
pub const en_event_src_t_EVT_SRC_TMR4_2_GCMP_UL: en_event_src_t = 225;
pub const en_event_src_t_EVT_SRC_TMR4_2_GCMP_VH: en_event_src_t = 226;
pub const en_event_src_t_EVT_SRC_TMR4_2_GCMP_VL: en_event_src_t = 227;
pub const en_event_src_t_EVT_SRC_TMR4_2_GCMP_WH: en_event_src_t = 228;
pub const en_event_src_t_EVT_SRC_TMR4_2_GCMP_WL: en_event_src_t = 229;
pub const en_event_src_t_EVT_SRC_TMR4_2_GCMP_XH: en_event_src_t = 230;
pub const en_event_src_t_EVT_SRC_TMR4_2_GCMP_XL: en_event_src_t = 231;
pub const en_event_src_t_EVT_SRC_TMR4_2_OVF: en_event_src_t = 232;
pub const en_event_src_t_EVT_SRC_TMR4_2_UDF: en_event_src_t = 233;
pub const en_event_src_t_EVT_SRC_TMR4_2_RELOAD_U: en_event_src_t = 234;
pub const en_event_src_t_EVT_SRC_TMR4_2_RELOAD_V: en_event_src_t = 235;
pub const en_event_src_t_EVT_SRC_TMR4_2_RELOAD_W: en_event_src_t = 236;
pub const en_event_src_t_EVT_SRC_TMR4_2_RELOAD_X: en_event_src_t = 237;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP0: en_event_src_t = 238;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP1: en_event_src_t = 239;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP2: en_event_src_t = 240;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP3: en_event_src_t = 241;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP4: en_event_src_t = 242;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP5: en_event_src_t = 243;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP6: en_event_src_t = 244;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP7: en_event_src_t = 245;
pub const en_event_src_t_EVT_SRC_TMR4_3_GCMP_UH: en_event_src_t = 256;
pub const en_event_src_t_EVT_SRC_TMR4_3_GCMP_UL: en_event_src_t = 257;
pub const en_event_src_t_EVT_SRC_TMR4_3_GCMP_VH: en_event_src_t = 258;
pub const en_event_src_t_EVT_SRC_TMR4_3_GCMP_VL: en_event_src_t = 259;
pub const en_event_src_t_EVT_SRC_TMR4_3_GCMP_WH: en_event_src_t = 260;
pub const en_event_src_t_EVT_SRC_TMR4_3_GCMP_WL: en_event_src_t = 261;
pub const en_event_src_t_EVT_SRC_TMR4_3_GCMP_XH: en_event_src_t = 262;
pub const en_event_src_t_EVT_SRC_TMR4_3_GCMP_XL: en_event_src_t = 263;
pub const en_event_src_t_EVT_SRC_TMR4_3_OVF: en_event_src_t = 264;
pub const en_event_src_t_EVT_SRC_TMR4_3_UDF: en_event_src_t = 265;
pub const en_event_src_t_EVT_SRC_TMR4_3_RELOAD_U: en_event_src_t = 266;
pub const en_event_src_t_EVT_SRC_TMR4_3_RELOAD_V: en_event_src_t = 267;
pub const en_event_src_t_EVT_SRC_TMR4_3_RELOAD_W: en_event_src_t = 268;
pub const en_event_src_t_EVT_SRC_TMR4_3_RELOAD_X: en_event_src_t = 269;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP0: en_event_src_t = 270;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP1: en_event_src_t = 271;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP2: en_event_src_t = 272;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP3: en_event_src_t = 273;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP4: en_event_src_t = 274;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP5: en_event_src_t = 275;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP6: en_event_src_t = 276;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP7: en_event_src_t = 277;
pub const en_event_src_t_EVT_SRC_I2C1_RXI: en_event_src_t = 288;
pub const en_event_src_t_EVT_SRC_I2C1_TXI: en_event_src_t = 289;
pub const en_event_src_t_EVT_SRC_I2C1_TEI: en_event_src_t = 290;
pub const en_event_src_t_EVT_SRC_I2C1_EEI: en_event_src_t = 291;
pub const en_event_src_t_EVT_SRC_I2C2_RXI: en_event_src_t = 292;
pub const en_event_src_t_EVT_SRC_I2C2_TXI: en_event_src_t = 293;
pub const en_event_src_t_EVT_SRC_I2C2_TEI: en_event_src_t = 294;
pub const en_event_src_t_EVT_SRC_I2C2_EEI: en_event_src_t = 295;
pub const en_event_src_t_EVT_SRC_CMP1: en_event_src_t = 312;
pub const en_event_src_t_EVT_SRC_CMP2: en_event_src_t = 313;
pub const en_event_src_t_EVT_SRC_CMP3: en_event_src_t = 314;
pub const en_event_src_t_EVT_SRC_CMP4: en_event_src_t = 315;
pub const en_event_src_t_EVT_SRC_USART1_EI: en_event_src_t = 321;
pub const en_event_src_t_EVT_SRC_USART1_RI: en_event_src_t = 322;
pub const en_event_src_t_EVT_SRC_USART1_TI: en_event_src_t = 323;
pub const en_event_src_t_EVT_SRC_USART1_RTO: en_event_src_t = 324;
pub const en_event_src_t_EVT_SRC_USART1_TCI: en_event_src_t = 326;
pub const en_event_src_t_EVT_SRC_USART2_EI: en_event_src_t = 328;
pub const en_event_src_t_EVT_SRC_USART2_RI: en_event_src_t = 329;
pub const en_event_src_t_EVT_SRC_USART2_TI: en_event_src_t = 330;
pub const en_event_src_t_EVT_SRC_USART2_RTO: en_event_src_t = 331;
pub const en_event_src_t_EVT_SRC_USART2_TCI: en_event_src_t = 333;
pub const en_event_src_t_EVT_SRC_SPI1_SPRI: en_event_src_t = 334;
pub const en_event_src_t_EVT_SRC_SPI1_SPTI: en_event_src_t = 335;
pub const en_event_src_t_EVT_SRC_SPI1_SPII: en_event_src_t = 336;
pub const en_event_src_t_EVT_SRC_SPI1_SPEI: en_event_src_t = 337;
pub const en_event_src_t_EVT_SRC_SPI1_SPEND: en_event_src_t = 338;
pub const en_event_src_t_EVT_SRC_TMRA_5_OVF: en_event_src_t = 340;
pub const en_event_src_t_EVT_SRC_TMRA_5_UDF: en_event_src_t = 341;
pub const en_event_src_t_EVT_SRC_TMRA_5_CMP: en_event_src_t = 342;
pub const en_event_src_t_EVT_SRC_EVENT_PORT1: en_event_src_t = 348;
pub const en_event_src_t_EVT_SRC_EVENT_PORT2: en_event_src_t = 349;
pub const en_event_src_t_EVT_SRC_EVENT_PORT3: en_event_src_t = 350;
pub const en_event_src_t_EVT_SRC_EVENT_PORT4: en_event_src_t = 351;
pub const en_event_src_t_EVT_SRC_USART3_BRKWKPI: en_event_src_t = 352;
pub const en_event_src_t_EVT_SRC_USART3_EI: en_event_src_t = 353;
pub const en_event_src_t_EVT_SRC_USART3_RI: en_event_src_t = 354;
pub const en_event_src_t_EVT_SRC_USART3_TI: en_event_src_t = 355;
pub const en_event_src_t_EVT_SRC_USART3_TCI: en_event_src_t = 358;
pub const en_event_src_t_EVT_SRC_USART4_EI: en_event_src_t = 360;
pub const en_event_src_t_EVT_SRC_USART4_RI: en_event_src_t = 361;
pub const en_event_src_t_EVT_SRC_USART4_TI: en_event_src_t = 362;
pub const en_event_src_t_EVT_SRC_USART4_RTO: en_event_src_t = 363;
pub const en_event_src_t_EVT_SRC_USART4_TCI: en_event_src_t = 365;
pub const en_event_src_t_EVT_SRC_SPI2_SPRI: en_event_src_t = 366;
pub const en_event_src_t_EVT_SRC_SPI2_SPTI: en_event_src_t = 367;
pub const en_event_src_t_EVT_SRC_SPI2_SPII: en_event_src_t = 368;
pub const en_event_src_t_EVT_SRC_SPI2_SPEI: en_event_src_t = 369;
pub const en_event_src_t_EVT_SRC_SPI2_SPEND: en_event_src_t = 370;
pub const en_event_src_t_EVT_SRC_SPI3_SPRI: en_event_src_t = 371;
pub const en_event_src_t_EVT_SRC_SPI3_SPTI: en_event_src_t = 372;
pub const en_event_src_t_EVT_SRC_SPI3_SPII: en_event_src_t = 373;
pub const en_event_src_t_EVT_SRC_SPI3_SPEI: en_event_src_t = 374;
pub const en_event_src_t_EVT_SRC_SPI3_SPEND: en_event_src_t = 375;
pub const en_event_src_t_EVT_SRC_USART5_EI: en_event_src_t = 385;
pub const en_event_src_t_EVT_SRC_USART5_RI: en_event_src_t = 386;
pub const en_event_src_t_EVT_SRC_USART5_TI: en_event_src_t = 387;
pub const en_event_src_t_EVT_SRC_USART5_RTO: en_event_src_t = 388;
pub const en_event_src_t_EVT_SRC_USART5_TCI: en_event_src_t = 390;
pub const en_event_src_t_EVT_SRC_USART6_BRKWKPI: en_event_src_t = 391;
pub const en_event_src_t_EVT_SRC_USART6_EI: en_event_src_t = 392;
pub const en_event_src_t_EVT_SRC_USART6_RI: en_event_src_t = 393;
pub const en_event_src_t_EVT_SRC_USART6_TI: en_event_src_t = 394;
pub const en_event_src_t_EVT_SRC_USART6_TCI: en_event_src_t = 396;
pub const en_event_src_t_EVT_SRC_AOS_STRG: en_event_src_t = 415;
pub const en_event_src_t_EVT_SRC_LVD1: en_event_src_t = 465;
pub const en_event_src_t_EVT_SRC_LVD2: en_event_src_t = 466;
pub const en_event_src_t_EVT_SRC_WDT_REFUDF: en_event_src_t = 471;
pub const en_event_src_t_EVT_SRC_ADC1_EOCA: en_event_src_t = 480;
pub const en_event_src_t_EVT_SRC_ADC1_EOCB: en_event_src_t = 481;
pub const en_event_src_t_EVT_SRC_ADC1_CMP0: en_event_src_t = 482;
pub const en_event_src_t_EVT_SRC_ADC1_CMP1: en_event_src_t = 483;
pub const en_event_src_t_EVT_SRC_ADC2_EOCA: en_event_src_t = 484;
pub const en_event_src_t_EVT_SRC_ADC2_EOCB: en_event_src_t = 485;
pub const en_event_src_t_EVT_SRC_ADC2_CMP0: en_event_src_t = 486;
pub const en_event_src_t_EVT_SRC_ADC2_CMP1: en_event_src_t = 487;
pub const en_event_src_t_EVT_SRC_ADC3_EOCA: en_event_src_t = 488;
pub const en_event_src_t_EVT_SRC_ADC3_EOCB: en_event_src_t = 489;
pub const en_event_src_t_EVT_SRC_ADC3_CMP0: en_event_src_t = 490;
pub const en_event_src_t_EVT_SRC_ADC3_CMP1: en_event_src_t = 491;
pub const en_event_src_t_EVT_SRC_TRNG_END: en_event_src_t = 492;
pub const en_event_src_t_EVT_SRC_MAX: en_event_src_t = 511;
#[doc = " \\brief Event number enumeration"]
pub type en_event_src_t = ::core::ffi::c_uint;
pub const en_int_src_t_INT_SRC_SWI_IRQ0: en_int_src_t = 0;
pub const en_int_src_t_INT_SRC_SWI_IRQ1: en_int_src_t = 1;
pub const en_int_src_t_INT_SRC_SWI_IRQ2: en_int_src_t = 2;
pub const en_int_src_t_INT_SRC_SWI_IRQ3: en_int_src_t = 3;
pub const en_int_src_t_INT_SRC_SWI_IRQ4: en_int_src_t = 4;
pub const en_int_src_t_INT_SRC_SWI_IRQ5: en_int_src_t = 5;
pub const en_int_src_t_INT_SRC_SWI_IRQ6: en_int_src_t = 6;
pub const en_int_src_t_INT_SRC_SWI_IRQ7: en_int_src_t = 7;
pub const en_int_src_t_INT_SRC_SWI_IRQ8: en_int_src_t = 8;
pub const en_int_src_t_INT_SRC_SWI_IRQ9: en_int_src_t = 9;
pub const en_int_src_t_INT_SRC_SWI_IRQ10: en_int_src_t = 10;
pub const en_int_src_t_INT_SRC_SWI_IRQ11: en_int_src_t = 11;
pub const en_int_src_t_INT_SRC_SWI_IRQ12: en_int_src_t = 12;
pub const en_int_src_t_INT_SRC_SWI_IRQ13: en_int_src_t = 13;
pub const en_int_src_t_INT_SRC_SWI_IRQ14: en_int_src_t = 14;
pub const en_int_src_t_INT_SRC_SWI_IRQ15: en_int_src_t = 15;
pub const en_int_src_t_INT_SRC_SWI_IRQ16: en_int_src_t = 16;
pub const en_int_src_t_INT_SRC_SWI_IRQ17: en_int_src_t = 17;
pub const en_int_src_t_INT_SRC_SWI_IRQ18: en_int_src_t = 18;
pub const en_int_src_t_INT_SRC_SWI_IRQ19: en_int_src_t = 19;
pub const en_int_src_t_INT_SRC_SWI_IRQ20: en_int_src_t = 20;
pub const en_int_src_t_INT_SRC_SWI_IRQ21: en_int_src_t = 21;
pub const en_int_src_t_INT_SRC_SWI_IRQ22: en_int_src_t = 22;
pub const en_int_src_t_INT_SRC_SWI_IRQ23: en_int_src_t = 23;
pub const en_int_src_t_INT_SRC_SWI_IRQ24: en_int_src_t = 24;
pub const en_int_src_t_INT_SRC_SWI_IRQ25: en_int_src_t = 25;
pub const en_int_src_t_INT_SRC_SWI_IRQ26: en_int_src_t = 26;
pub const en_int_src_t_INT_SRC_SWI_IRQ27: en_int_src_t = 27;
pub const en_int_src_t_INT_SRC_SWI_IRQ28: en_int_src_t = 28;
pub const en_int_src_t_INT_SRC_SWI_IRQ29: en_int_src_t = 29;
pub const en_int_src_t_INT_SRC_SWI_IRQ30: en_int_src_t = 30;
pub const en_int_src_t_INT_SRC_SWI_IRQ31: en_int_src_t = 31;
pub const en_int_src_t_INT_SRC_PORT_EIRQ0: en_int_src_t = 0;
pub const en_int_src_t_INT_SRC_PORT_EIRQ1: en_int_src_t = 1;
pub const en_int_src_t_INT_SRC_PORT_EIRQ2: en_int_src_t = 2;
pub const en_int_src_t_INT_SRC_PORT_EIRQ3: en_int_src_t = 3;
pub const en_int_src_t_INT_SRC_PORT_EIRQ4: en_int_src_t = 4;
pub const en_int_src_t_INT_SRC_PORT_EIRQ5: en_int_src_t = 5;
pub const en_int_src_t_INT_SRC_PORT_EIRQ6: en_int_src_t = 6;
pub const en_int_src_t_INT_SRC_PORT_EIRQ7: en_int_src_t = 7;
pub const en_int_src_t_INT_SRC_PORT_EIRQ8: en_int_src_t = 8;
pub const en_int_src_t_INT_SRC_PORT_EIRQ9: en_int_src_t = 9;
pub const en_int_src_t_INT_SRC_PORT_EIRQ10: en_int_src_t = 10;
pub const en_int_src_t_INT_SRC_PORT_EIRQ11: en_int_src_t = 11;
pub const en_int_src_t_INT_SRC_PORT_EIRQ12: en_int_src_t = 12;
pub const en_int_src_t_INT_SRC_PORT_EIRQ13: en_int_src_t = 13;
pub const en_int_src_t_INT_SRC_PORT_EIRQ14: en_int_src_t = 14;
pub const en_int_src_t_INT_SRC_PORT_EIRQ15: en_int_src_t = 15;
pub const en_int_src_t_INT_SRC_DMA1_ERR: en_int_src_t = 32;
pub const en_int_src_t_INT_SRC_DMA1_TC0: en_int_src_t = 33;
pub const en_int_src_t_INT_SRC_DMA1_BTC0: en_int_src_t = 34;
pub const en_int_src_t_INT_SRC_DMA1_TC1: en_int_src_t = 35;
pub const en_int_src_t_INT_SRC_DMA1_BTC1: en_int_src_t = 36;
pub const en_int_src_t_INT_SRC_DMA1_TC2: en_int_src_t = 37;
pub const en_int_src_t_INT_SRC_DMA1_BTC2: en_int_src_t = 38;
pub const en_int_src_t_INT_SRC_DMA1_TC3: en_int_src_t = 39;
pub const en_int_src_t_INT_SRC_DMA1_BTC3: en_int_src_t = 40;
pub const en_int_src_t_INT_SRC_DMA1_TC4: en_int_src_t = 41;
pub const en_int_src_t_INT_SRC_DMA1_BTC4: en_int_src_t = 42;
pub const en_int_src_t_INT_SRC_DMA1_TC5: en_int_src_t = 43;
pub const en_int_src_t_INT_SRC_DMA1_BTC5: en_int_src_t = 44;
pub const en_int_src_t_INT_SRC_EFM_PEERR: en_int_src_t = 49;
pub const en_int_src_t_INT_SRC_EFM_RDCOL: en_int_src_t = 50;
pub const en_int_src_t_INT_SRC_EFM_OPTEND: en_int_src_t = 51;
pub const en_int_src_t_INT_SRC_QSPI_INTR: en_int_src_t = 54;
pub const en_int_src_t_INT_SRC_DCU1: en_int_src_t = 55;
pub const en_int_src_t_INT_SRC_DCU2: en_int_src_t = 56;
pub const en_int_src_t_INT_SRC_DCU3: en_int_src_t = 57;
pub const en_int_src_t_INT_SRC_DCU4: en_int_src_t = 58;
pub const en_int_src_t_INT_SRC_DMA2_ERR: en_int_src_t = 64;
pub const en_int_src_t_INT_SRC_DMA2_TC0: en_int_src_t = 65;
pub const en_int_src_t_INT_SRC_DMA2_BTC0: en_int_src_t = 66;
pub const en_int_src_t_INT_SRC_DMA2_TC1: en_int_src_t = 67;
pub const en_int_src_t_INT_SRC_DMA2_BTC1: en_int_src_t = 68;
pub const en_int_src_t_INT_SRC_DMA2_TC2: en_int_src_t = 69;
pub const en_int_src_t_INT_SRC_DMA2_BTC2: en_int_src_t = 70;
pub const en_int_src_t_INT_SRC_DMA2_TC3: en_int_src_t = 71;
pub const en_int_src_t_INT_SRC_DMA2_BTC3: en_int_src_t = 72;
pub const en_int_src_t_INT_SRC_DMA2_TC4: en_int_src_t = 73;
pub const en_int_src_t_INT_SRC_DMA2_BTC4: en_int_src_t = 74;
pub const en_int_src_t_INT_SRC_DMA2_TC5: en_int_src_t = 75;
pub const en_int_src_t_INT_SRC_DMA2_BTC5: en_int_src_t = 76;
pub const en_int_src_t_INT_SRC_TMR0_1_CMP_A: en_int_src_t = 96;
pub const en_int_src_t_INT_SRC_TMR0_1_CMP_B: en_int_src_t = 97;
pub const en_int_src_t_INT_SRC_TMR0_1_OVF_A: en_int_src_t = 98;
pub const en_int_src_t_INT_SRC_TMR0_1_OVF_B: en_int_src_t = 99;
pub const en_int_src_t_INT_SRC_TMR0_2_CMP_A: en_int_src_t = 100;
pub const en_int_src_t_INT_SRC_TMR0_2_CMP_B: en_int_src_t = 101;
pub const en_int_src_t_INT_SRC_TMR0_2_OVF_A: en_int_src_t = 102;
pub const en_int_src_t_INT_SRC_TMR0_2_OVF_B: en_int_src_t = 103;
pub const en_int_src_t_INT_SRC_RTC_ALM: en_int_src_t = 121;
pub const en_int_src_t_INT_SRC_RTC_PRD: en_int_src_t = 122;
pub const en_int_src_t_INT_SRC_XTAL_STOP: en_int_src_t = 125;
pub const en_int_src_t_INT_SRC_WKTM_PRD: en_int_src_t = 126;
pub const en_int_src_t_INT_SRC_SWDT_REFUDF: en_int_src_t = 127;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_A: en_int_src_t = 128;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_B: en_int_src_t = 129;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_C: en_int_src_t = 130;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_D: en_int_src_t = 131;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_E: en_int_src_t = 132;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_F: en_int_src_t = 133;
pub const en_int_src_t_INT_SRC_TMR6_1_OVF: en_int_src_t = 134;
pub const en_int_src_t_INT_SRC_TMR6_1_UDF: en_int_src_t = 135;
pub const en_int_src_t_INT_SRC_TMR6_1_DTE: en_int_src_t = 136;
pub const en_int_src_t_INT_SRC_TMR6_1_SCMP_A: en_int_src_t = 137;
pub const en_int_src_t_INT_SRC_TMR6_1_SCMP_B: en_int_src_t = 138;
pub const en_int_src_t_INT_SRC_TMRA_1_OVF: en_int_src_t = 139;
pub const en_int_src_t_INT_SRC_TMRA_1_UDF: en_int_src_t = 140;
pub const en_int_src_t_INT_SRC_TMRA_1_CMP: en_int_src_t = 141;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_A: en_int_src_t = 144;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_B: en_int_src_t = 145;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_C: en_int_src_t = 146;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_D: en_int_src_t = 147;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_E: en_int_src_t = 148;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_F: en_int_src_t = 149;
pub const en_int_src_t_INT_SRC_TMR6_2_OVF: en_int_src_t = 150;
pub const en_int_src_t_INT_SRC_TMR6_2_UDF: en_int_src_t = 151;
pub const en_int_src_t_INT_SRC_TMR6_2_DTE: en_int_src_t = 152;
pub const en_int_src_t_INT_SRC_TMR6_2_SCMP_A: en_int_src_t = 153;
pub const en_int_src_t_INT_SRC_TMR6_2_SCMP_B: en_int_src_t = 154;
pub const en_int_src_t_INT_SRC_TMRA_2_OVF: en_int_src_t = 155;
pub const en_int_src_t_INT_SRC_TMRA_2_UDF: en_int_src_t = 156;
pub const en_int_src_t_INT_SRC_TMRA_2_CMP: en_int_src_t = 157;
pub const en_int_src_t_INT_SRC_TMRA_3_OVF: en_int_src_t = 171;
pub const en_int_src_t_INT_SRC_TMRA_3_UDF: en_int_src_t = 172;
pub const en_int_src_t_INT_SRC_TMRA_3_CMP: en_int_src_t = 173;
pub const en_int_src_t_INT_SRC_TMRA_4_OVF: en_int_src_t = 187;
pub const en_int_src_t_INT_SRC_TMRA_4_UDF: en_int_src_t = 188;
pub const en_int_src_t_INT_SRC_TMRA_4_CMP: en_int_src_t = 189;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_UH: en_int_src_t = 192;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_UL: en_int_src_t = 193;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_VH: en_int_src_t = 194;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_VL: en_int_src_t = 195;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_WH: en_int_src_t = 196;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_WL: en_int_src_t = 197;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_XH: en_int_src_t = 198;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_XL: en_int_src_t = 199;
pub const en_int_src_t_INT_SRC_TMR4_1_OVF: en_int_src_t = 200;
pub const en_int_src_t_INT_SRC_TMR4_1_UDF: en_int_src_t = 201;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_U: en_int_src_t = 202;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_V: en_int_src_t = 203;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_W: en_int_src_t = 204;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_X: en_int_src_t = 205;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP0: en_int_src_t = 206;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP1: en_int_src_t = 207;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP2: en_int_src_t = 208;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP3: en_int_src_t = 209;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP4: en_int_src_t = 210;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP5: en_int_src_t = 211;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP6: en_int_src_t = 212;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP7: en_int_src_t = 213;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_UH: en_int_src_t = 224;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_UL: en_int_src_t = 225;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_VH: en_int_src_t = 226;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_VL: en_int_src_t = 227;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_WH: en_int_src_t = 228;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_WL: en_int_src_t = 229;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_XH: en_int_src_t = 230;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_XL: en_int_src_t = 231;
pub const en_int_src_t_INT_SRC_TMR4_2_OVF: en_int_src_t = 232;
pub const en_int_src_t_INT_SRC_TMR4_2_UDF: en_int_src_t = 233;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_U: en_int_src_t = 234;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_V: en_int_src_t = 235;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_W: en_int_src_t = 236;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_X: en_int_src_t = 237;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP0: en_int_src_t = 238;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP1: en_int_src_t = 239;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP2: en_int_src_t = 240;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP3: en_int_src_t = 241;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP4: en_int_src_t = 242;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP5: en_int_src_t = 243;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP6: en_int_src_t = 244;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP7: en_int_src_t = 245;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_UH: en_int_src_t = 256;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_UL: en_int_src_t = 257;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_VH: en_int_src_t = 258;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_VL: en_int_src_t = 259;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_WH: en_int_src_t = 260;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_WL: en_int_src_t = 261;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_XH: en_int_src_t = 262;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_XL: en_int_src_t = 263;
pub const en_int_src_t_INT_SRC_TMR4_3_OVF: en_int_src_t = 264;
pub const en_int_src_t_INT_SRC_TMR4_3_UDF: en_int_src_t = 265;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_U: en_int_src_t = 266;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_V: en_int_src_t = 267;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_W: en_int_src_t = 268;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_X: en_int_src_t = 269;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP0: en_int_src_t = 270;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP1: en_int_src_t = 271;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP2: en_int_src_t = 272;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP3: en_int_src_t = 273;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP4: en_int_src_t = 274;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP5: en_int_src_t = 275;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP6: en_int_src_t = 276;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP7: en_int_src_t = 277;
pub const en_int_src_t_INT_SRC_I2C1_RXI: en_int_src_t = 288;
pub const en_int_src_t_INT_SRC_I2C1_TXI: en_int_src_t = 289;
pub const en_int_src_t_INT_SRC_I2C1_TEI: en_int_src_t = 290;
pub const en_int_src_t_INT_SRC_I2C1_EEI: en_int_src_t = 291;
pub const en_int_src_t_INT_SRC_I2C2_RXI: en_int_src_t = 292;
pub const en_int_src_t_INT_SRC_I2C2_TXI: en_int_src_t = 293;
pub const en_int_src_t_INT_SRC_I2C2_TEI: en_int_src_t = 294;
pub const en_int_src_t_INT_SRC_I2C2_EEI: en_int_src_t = 295;
pub const en_int_src_t_INT_SRC_CMP1: en_int_src_t = 312;
pub const en_int_src_t_INT_SRC_CMP2: en_int_src_t = 313;
pub const en_int_src_t_INT_SRC_CMP3: en_int_src_t = 314;
pub const en_int_src_t_INT_SRC_CMP4: en_int_src_t = 315;
pub const en_int_src_t_INT_SRC_USART1_EI: en_int_src_t = 321;
pub const en_int_src_t_INT_SRC_USART1_RI: en_int_src_t = 322;
pub const en_int_src_t_INT_SRC_USART1_TI: en_int_src_t = 323;
pub const en_int_src_t_INT_SRC_USART1_RTO: en_int_src_t = 324;
pub const en_int_src_t_INT_SRC_USART1_TENDI: en_int_src_t = 325;
pub const en_int_src_t_INT_SRC_USART1_TCI: en_int_src_t = 326;
pub const en_int_src_t_INT_SRC_USART2_EI: en_int_src_t = 328;
pub const en_int_src_t_INT_SRC_USART2_RI: en_int_src_t = 329;
pub const en_int_src_t_INT_SRC_USART2_TI: en_int_src_t = 330;
pub const en_int_src_t_INT_SRC_USART2_RTO: en_int_src_t = 331;
pub const en_int_src_t_INT_SRC_USART2_TENDI: en_int_src_t = 332;
pub const en_int_src_t_INT_SRC_USART2_TCI: en_int_src_t = 333;
pub const en_int_src_t_INT_SRC_SPI1_SPRI: en_int_src_t = 334;
pub const en_int_src_t_INT_SRC_SPI1_SPTI: en_int_src_t = 335;
pub const en_int_src_t_INT_SRC_SPI1_SPII: en_int_src_t = 336;
pub const en_int_src_t_INT_SRC_SPI1_SPEI: en_int_src_t = 337;
pub const en_int_src_t_INT_SRC_TMRA_5_OVF: en_int_src_t = 340;
pub const en_int_src_t_INT_SRC_TMRA_5_UDF: en_int_src_t = 341;
pub const en_int_src_t_INT_SRC_TMRA_5_CMP: en_int_src_t = 342;
pub const en_int_src_t_INT_SRC_EVENT_PORT1: en_int_src_t = 348;
pub const en_int_src_t_INT_SRC_EVENT_PORT2: en_int_src_t = 349;
pub const en_int_src_t_INT_SRC_EVENT_PORT3: en_int_src_t = 350;
pub const en_int_src_t_INT_SRC_EVENT_PORT4: en_int_src_t = 351;
pub const en_int_src_t_INT_SRC_USART3_BRKWKPI: en_int_src_t = 352;
pub const en_int_src_t_INT_SRC_USART3_EI: en_int_src_t = 353;
pub const en_int_src_t_INT_SRC_USART3_RI: en_int_src_t = 354;
pub const en_int_src_t_INT_SRC_USART3_TI: en_int_src_t = 355;
pub const en_int_src_t_INT_SRC_USART3_TENDI: en_int_src_t = 357;
pub const en_int_src_t_INT_SRC_USART3_TCI: en_int_src_t = 358;
pub const en_int_src_t_INT_SRC_USART4_EI: en_int_src_t = 360;
pub const en_int_src_t_INT_SRC_USART4_RI: en_int_src_t = 361;
pub const en_int_src_t_INT_SRC_USART4_TI: en_int_src_t = 362;
pub const en_int_src_t_INT_SRC_USART4_RTO: en_int_src_t = 363;
pub const en_int_src_t_INT_SRC_USART4_TENDI: en_int_src_t = 364;
pub const en_int_src_t_INT_SRC_USART4_TCI: en_int_src_t = 365;
pub const en_int_src_t_INT_SRC_SPI2_SPRI: en_int_src_t = 366;
pub const en_int_src_t_INT_SRC_SPI2_SPTI: en_int_src_t = 367;
pub const en_int_src_t_INT_SRC_SPI2_SPII: en_int_src_t = 368;
pub const en_int_src_t_INT_SRC_SPI2_SPEI: en_int_src_t = 369;
pub const en_int_src_t_INT_SRC_SPI3_SPRI: en_int_src_t = 371;
pub const en_int_src_t_INT_SRC_SPI3_SPTI: en_int_src_t = 372;
pub const en_int_src_t_INT_SRC_SPI3_SPII: en_int_src_t = 373;
pub const en_int_src_t_INT_SRC_SPI3_SPEI: en_int_src_t = 374;
pub const en_int_src_t_INT_SRC_EMB_GR0: en_int_src_t = 376;
pub const en_int_src_t_INT_SRC_EMB_GR1: en_int_src_t = 377;
pub const en_int_src_t_INT_SRC_EMB_GR2: en_int_src_t = 378;
pub const en_int_src_t_INT_SRC_EMB_GR3: en_int_src_t = 379;
pub const en_int_src_t_INT_SRC_USART5_EI: en_int_src_t = 385;
pub const en_int_src_t_INT_SRC_USART5_RI: en_int_src_t = 386;
pub const en_int_src_t_INT_SRC_USART5_TI: en_int_src_t = 387;
pub const en_int_src_t_INT_SRC_USART5_RTO: en_int_src_t = 388;
pub const en_int_src_t_INT_SRC_USART5_TENDI: en_int_src_t = 389;
pub const en_int_src_t_INT_SRC_USART5_TCI: en_int_src_t = 390;
pub const en_int_src_t_INT_SRC_USART6_BRKWKPI: en_int_src_t = 391;
pub const en_int_src_t_INT_SRC_USART6_EI: en_int_src_t = 392;
pub const en_int_src_t_INT_SRC_USART6_RI: en_int_src_t = 393;
pub const en_int_src_t_INT_SRC_USART6_TI: en_int_src_t = 394;
pub const en_int_src_t_INT_SRC_USART6_TENDI: en_int_src_t = 395;
pub const en_int_src_t_INT_SRC_USART6_TCI: en_int_src_t = 396;
pub const en_int_src_t_INT_SRC_MCAN1_INT0: en_int_src_t = 408;
pub const en_int_src_t_INT_SRC_MCAN1_INT1: en_int_src_t = 409;
pub const en_int_src_t_INT_SRC_MCAN2_INT0: en_int_src_t = 410;
pub const en_int_src_t_INT_SRC_MCAN2_INT1: en_int_src_t = 411;
pub const en_int_src_t_INT_SRC_USART1_WUPI: en_int_src_t = 464;
pub const en_int_src_t_INT_SRC_FCMFERRI: en_int_src_t = 468;
pub const en_int_src_t_INT_SRC_FCMMENDI: en_int_src_t = 469;
pub const en_int_src_t_INT_SRC_FCMCOVFI: en_int_src_t = 470;
pub const en_int_src_t_INT_SRC_WDT_REFUDF: en_int_src_t = 471;
pub const en_int_src_t_INT_SRC_CTC_ERR: en_int_src_t = 472;
pub const en_int_src_t_INT_SRC_ADC1_EOCA: en_int_src_t = 480;
pub const en_int_src_t_INT_SRC_ADC1_EOCB: en_int_src_t = 481;
pub const en_int_src_t_INT_SRC_ADC1_CMP0: en_int_src_t = 482;
pub const en_int_src_t_INT_SRC_ADC1_CMP1: en_int_src_t = 483;
pub const en_int_src_t_INT_SRC_ADC2_EOCA: en_int_src_t = 484;
pub const en_int_src_t_INT_SRC_ADC2_EOCB: en_int_src_t = 485;
pub const en_int_src_t_INT_SRC_ADC2_CMP0: en_int_src_t = 486;
pub const en_int_src_t_INT_SRC_ADC2_CMP1: en_int_src_t = 487;
pub const en_int_src_t_INT_SRC_ADC3_EOCA: en_int_src_t = 488;
pub const en_int_src_t_INT_SRC_ADC3_EOCB: en_int_src_t = 489;
pub const en_int_src_t_INT_SRC_ADC3_CMP0: en_int_src_t = 490;
pub const en_int_src_t_INT_SRC_ADC3_CMP1: en_int_src_t = 491;
pub const en_int_src_t_INT_SRC_TRNG_END: en_int_src_t = 492;
pub const en_int_src_t_INT_SRC_MAX: en_int_src_t = 511;
#[doc = " \\brief Interrupt number enumeration"]
pub type en_int_src_t = ::core::ffi::c_uint;
#[doc = " @brief ADC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_ADC_TypeDef {
    pub STR: u8,
    pub RESERVED0: [u8; 1usize],
    pub CR0: u16,
    pub CR1: u16,
    pub CR2: u16,
    pub RESERVED1: [u8; 2usize],
    pub TRGSR: u16,
    pub CHSELRA: u32,
    pub CHSELRB: u32,
    pub AVCHSELR: u32,
    pub EXCHSELR: u8,
    pub RESERVED2: [u8; 7usize],
    pub SSTR0: u8,
    pub SSTR1: u8,
    pub SSTR2: u8,
    pub SSTR3: u8,
    pub SSTR4: u8,
    pub SSTR5: u8,
    pub SSTR6: u8,
    pub SSTR7: u8,
    pub SSTR8: u8,
    pub SSTR9: u8,
    pub SSTR10: u8,
    pub SSTR11: u8,
    pub SSTR12: u8,
    pub SSTR13: u8,
    pub SSTR14: u8,
    pub SSTR15: u8,
    pub RESERVED3: [u8; 8usize],
    pub CHMUXR0: u16,
    pub CHMUXR1: u16,
    pub CHMUXR2: u16,
    pub CHMUXR3: u16,
    pub RESERVED4: [u8; 4usize],
    pub ISR: u8,
    pub ICR: u8,
    pub ISCLRR: u8,
    pub RESERVED5: [u8; 5usize],
    pub SYNCCR: u16,
    pub RESERVED6: [u8; 2usize],
    pub DR0: u16,
    pub DR1: u16,
    pub DR2: u16,
    pub DR3: u16,
    pub DR4: u16,
    pub DR5: u16,
    pub DR6: u16,
    pub DR7: u16,
    pub DR8: u16,
    pub DR9: u16,
    pub DR10: u16,
    pub DR11: u16,
    pub DR12: u16,
    pub DR13: u16,
    pub DR14: u16,
    pub DR15: u16,
    pub RESERVED7: [u8; 48usize],
    pub AWDCR: u16,
    pub AWDSR: u8,
    pub AWDSCLRR: u8,
    pub AWD0DR0: u16,
    pub AWD0DR1: u16,
    pub AWD0CHSR: u8,
    pub RESERVED8: [u8; 3usize],
    pub AWD1DR0: u16,
    pub AWD1DR1: u16,
    pub AWD1CHSR: u8,
}
#[doc = " @brief AES"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_AES_TypeDef {
    pub CR: u32,
    pub RESERVED0: [u8; 12usize],
    pub DR0: u32,
    pub DR1: u32,
    pub DR2: u32,
    pub DR3: u32,
    pub KR0: u32,
    pub KR1: u32,
    pub KR2: u32,
    pub KR3: u32,
    pub KR4: u32,
    pub KR5: u32,
    pub KR6: u32,
    pub KR7: u32,
}
#[doc = " @brief AOS"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_AOS_TypeDef {
    pub INTSFTTRG: u32,
    pub DCU_TRGSEL1: u32,
    pub DCU_TRGSEL2: u32,
    pub DCU_TRGSEL3: u32,
    pub DCU_TRGSEL4: u32,
    pub DMA1_TRGSEL0: u32,
    pub DMA1_TRGSEL1: u32,
    pub DMA1_TRGSEL2: u32,
    pub DMA1_TRGSEL3: u32,
    pub DMA1_TRGSEL4: u32,
    pub DMA1_TRGSEL5: u32,
    pub DMA2_TRGSEL0: u32,
    pub DMA2_TRGSEL1: u32,
    pub DMA2_TRGSEL2: u32,
    pub DMA2_TRGSEL3: u32,
    pub DMA2_TRGSEL4: u32,
    pub DMA2_TRGSEL5: u32,
    pub DMA_RC_TRGSEL: u32,
    pub TMR6_TRGSEL0: u32,
    pub TMR6_TRGSEL1: u32,
    pub TMR4_TRGSEL0: u32,
    pub TMR4_TRGSEL1: u32,
    pub TMR4_TRGSEL2: u32,
    pub PEVNT_TRGSEL12: u32,
    pub PEVNT_TRGSEL34: u32,
    pub TMR0_TRGSEL: u32,
    pub TMRA_TRGSEL0: u32,
    pub TMRA_TRGSEL1: u32,
    pub TMRA_TRGSEL2: u32,
    pub TMRA_TRGSEL3: u32,
    pub ADC1_TRGSEL0: u32,
    pub ADC1_TRGSEL1: u32,
    pub ADC2_TRGSEL0: u32,
    pub ADC2_TRGSEL1: u32,
    pub ADC3_TRGSEL0: u32,
    pub ADC3_TRGSEL1: u32,
    pub COMTRGSEL1: u32,
    pub COMTRGSEL2: u32,
    pub RESERVED0: [u8; 104usize],
    pub PEVNTDIRR1: u32,
    pub PEVNTIDR1: u32,
    pub PEVNTODR1: u32,
    pub PEVNTORR1: u32,
    pub PEVNTOSR1: u32,
    pub PEVNTRISR1: u32,
    pub PEVNTFALR1: u32,
    pub PEVNTDIRR2: u32,
    pub PEVNTIDR2: u32,
    pub PEVNTODR2: u32,
    pub PEVNTORR2: u32,
    pub PEVNTOSR2: u32,
    pub PEVNTRISR2: u32,
    pub PEVNTFALR2: u32,
    pub PEVNTDIRR3: u32,
    pub PEVNTIDR3: u32,
    pub PEVNTODR3: u32,
    pub PEVNTORR3: u32,
    pub PEVNTOSR3: u32,
    pub PEVNTRISR3: u32,
    pub PEVNTFALR3: u32,
    pub PEVNTDIRR4: u32,
    pub PEVNTIDR4: u32,
    pub PEVNTODR4: u32,
    pub PEVNTORR4: u32,
    pub PEVNTOSR4: u32,
    pub PEVNTRISR4: u32,
    pub PEVNTFALR4: u32,
    pub PEVNTNFCR: u32,
    pub RESERVED1: [u8; 140usize],
    pub PLU0_CR: u32,
    pub PLU1_CR: u32,
    pub PLU2_CR: u32,
    pub PLU3_CR: u32,
    pub PLU0_TRGSELA: u32,
    pub PLU0_TRGSELB: u32,
    pub PLU0_TRGSELC: u32,
    pub PLU0_TRGSELD: u32,
    pub PLU1_TRGSELA: u32,
    pub PLU1_TRGSELB: u32,
    pub PLU1_TRGSELC: u32,
    pub PLU1_TRGSELD: u32,
    pub PLU2_TRGSELA: u32,
    pub PLU2_TRGSELB: u32,
    pub PLU2_TRGSELC: u32,
    pub PLU2_TRGSELD: u32,
    pub PLU3_TRGSELA: u32,
    pub PLU3_TRGSELB: u32,
    pub PLU3_TRGSELC: u32,
    pub PLU3_TRGSELD: u32,
}
#[doc = " @brief CMP"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_CMP_TypeDef {
    pub MDR: u8,
    pub FIR: u8,
    pub OCR: u8,
    pub RESERVED0: [u8; 1usize],
    pub PMSR: u32,
    pub RESERVED1: [u8; 8usize],
    pub BWSR1: u32,
    pub BWSR2: u16,
    pub RESERVED2: [u8; 2usize],
    pub SCCR: u32,
    pub SCMR: u32,
}
#[doc = " @brief CMU"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_CMU_TypeDef {
    pub RESERVED0: [u8; 24usize],
    pub XTALDIVR: u32,
    pub XTALDIVCR: u32,
    pub RESERVED1: [u8; 19504usize],
    pub XTALCFGR: u8,
    pub RESERVED2: [u8; 3usize],
    pub XTAL32CR: u8,
    pub RESERVED3: [u8; 3usize],
    pub XTAL32CFGR: u8,
    pub RESERVED4: [u8; 15usize],
    pub XTAL32NFR: u8,
    pub RESERVED5: [u8; 3usize],
    pub LRCCR: u8,
    pub RESERVED6: [u8; 7usize],
    pub LRCTRM: u8,
    pub RESERVED7: [u8; 29595usize],
    pub PERICKSEL: u16,
    pub RESERVED8: [u8; 6usize],
    pub CANCKCFGR: u16,
    pub RESERVED9: [u8; 6usize],
    pub SCFGR: u32,
    pub RESERVED10: [u8; 2usize],
    pub CKSWR: u8,
    pub RESERVED11: [u8; 3usize],
    pub PLLHCR: u8,
    pub RESERVED12: [u8; 7usize],
    pub XTALCR: u8,
    pub RESERVED13: [u8; 3usize],
    pub HRCCR: u8,
    pub RESERVED14: [u8; 1usize],
    pub MRCCR: u8,
    pub RESERVED15: [u8; 3usize],
    pub OSCSTBSR: u8,
    pub MCO1CFGR: u8,
    pub MCO2CFGR: u8,
    pub TPIUCKCFGR: u8,
    pub XTALSTDCR: u8,
    pub XTALSTDSR: u8,
    pub RESERVED16: [u8; 31usize],
    pub MRCTRM: u8,
    pub HRCTRM: u8,
    pub RESERVED17: [u8; 63usize],
    pub XTALSTBCR: u8,
    pub RESERVED18: [u8; 93usize],
    pub PLLHCFGR: u32,
}
#[doc = " @brief CRC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_CRC_TypeDef {
    pub CR: u32,
    pub RESLT: u32,
    pub RESERVED0: [u8; 120usize],
    pub DAT0: u32,
    pub DAT1: u32,
    pub DAT2: u32,
    pub DAT3: u32,
    pub DAT4: u32,
    pub DAT5: u32,
    pub DAT6: u32,
    pub DAT7: u32,
    pub DAT8: u32,
    pub DAT9: u32,
    pub DAT10: u32,
    pub DAT11: u32,
    pub DAT12: u32,
    pub DAT13: u32,
    pub DAT14: u32,
    pub DAT15: u32,
    pub DAT16: u32,
    pub DAT17: u32,
    pub DAT18: u32,
    pub DAT19: u32,
    pub DAT20: u32,
    pub DAT21: u32,
    pub DAT22: u32,
    pub DAT23: u32,
    pub DAT24: u32,
    pub DAT25: u32,
    pub DAT26: u32,
    pub DAT27: u32,
    pub DAT28: u32,
    pub DAT29: u32,
    pub DAT30: u32,
    pub DAT31: u32,
}
#[doc = " @brief CTC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_CTC_TypeDef {
    pub CR1: u32,
    pub CR2: u32,
    pub STR: u32,
    pub CNT: u16,
}
#[doc = " @brief DAC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_DAC_TypeDef {
    pub DADR1: u16,
    pub DADR2: u16,
    pub DACR: u16,
    pub DAADPCR: u16,
    pub RESERVED0: [u8; 20usize],
    pub DAOCR: u16,
}
#[doc = " @brief DBGC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_DBGC_TypeDef {
    pub RESERVED0: [u8; 12usize],
    pub CHIPID: u32,
    pub RESERVED1: [u8; 12usize],
    pub MCUDBGCSTAT: u32,
    pub MCUSTPCTL: u32,
    pub MCUTRACECTL: u32,
    pub MCUSTPCTL2: u32,
}
#[doc = " @brief DCU"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_DCU_TypeDef {
    pub CTL: u32,
    pub FLAG: u32,
    pub DATA0: u32,
    pub DATA1: u32,
    pub DATA2: u32,
    pub FLAGCLR: u32,
    pub INTEVTSEL: u32,
}
#[doc = " @brief DMA"]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct CM_DMA_TypeDef {
    pub EN: u32,
    pub INTSTAT0: u32,
    pub INTSTAT1: u32,
    pub INTMASK0: u32,
    pub INTMASK1: u32,
    pub INTCLR0: u32,
    pub INTCLR1: u32,
    pub CHEN: u32,
    pub REQSTAT: u32,
    pub CHSTAT: u32,
    pub RESERVED0: [u8; 4usize],
    pub RCFGCTL: u32,
    pub SWREQ: u32,
    pub CHENCLR: u32,
    pub RESERVED1: [u8; 8usize],
    pub SAR0: u32,
    pub DAR0: u32,
    pub DTCTL0: u32,
    pub __bindgen_anon_1: CM_DMA_TypeDef__bindgen_ty_1,
    pub __bindgen_anon_2: CM_DMA_TypeDef__bindgen_ty_2,
    pub __bindgen_anon_3: CM_DMA_TypeDef__bindgen_ty_3,
    pub LLP0: u32,
    pub CHCTL0: u32,
    pub MONSAR0: u32,
    pub MONDAR0: u32,
    pub MONDTCTL0: u32,
    pub MONRPT0: u32,
    pub MONSNSEQCTL0: u32,
    pub MONDNSEQCTL0: u32,
    pub RESERVED2: [u8; 8usize],
    pub SAR1: u32,
    pub DAR1: u32,
    pub DTCTL1: u32,
    pub __bindgen_anon_4: CM_DMA_TypeDef__bindgen_ty_4,
    pub __bindgen_anon_5: CM_DMA_TypeDef__bindgen_ty_5,
    pub __bindgen_anon_6: CM_DMA_TypeDef__bindgen_ty_6,
    pub LLP1: u32,
    pub CHCTL1: u32,
    pub MONSAR1: u32,
    pub MONDAR1: u32,
    pub MONDTCTL1: u32,
    pub MONRPT1: u32,
    pub MONSNSEQCTL1: u32,
    pub MONDNSEQCTL1: u32,
    pub RESERVED3: [u8; 8usize],
    pub SAR2: u32,
    pub DAR2: u32,
    pub DTCTL2: u32,
    pub __bindgen_anon_7: CM_DMA_TypeDef__bindgen_ty_7,
    pub __bindgen_anon_8: CM_DMA_TypeDef__bindgen_ty_8,
    pub __bindgen_anon_9: CM_DMA_TypeDef__bindgen_ty_9,
    pub LLP2: u32,
    pub CHCTL2: u32,
    pub MONSAR2: u32,
    pub MONDAR2: u32,
    pub MONDTCTL2: u32,
    pub MONRPT2: u32,
    pub MONSNSEQCTL2: u32,
    pub MONDNSEQCTL2: u32,
    pub RESERVED4: [u8; 8usize],
    pub SAR3: u32,
    pub DAR3: u32,
    pub DTCTL3: u32,
    pub __bindgen_anon_10: CM_DMA_TypeDef__bindgen_ty_10,
    pub __bindgen_anon_11: CM_DMA_TypeDef__bindgen_ty_11,
    pub __bindgen_anon_12: CM_DMA_TypeDef__bindgen_ty_12,
    pub LLP3: u32,
    pub CHCTL3: u32,
    pub MONSAR3: u32,
    pub MONDAR3: u32,
    pub MONDTCTL3: u32,
    pub MONRPT3: u32,
    pub MONSNSEQCTL3: u32,
    pub MONDNSEQCTL3: u32,
    pub RESERVED5: [u8; 8usize],
    pub SAR4: u32,
    pub DAR4: u32,
    pub DTCTL4: u32,
    pub __bindgen_anon_13: CM_DMA_TypeDef__bindgen_ty_13,
    pub __bindgen_anon_14: CM_DMA_TypeDef__bindgen_ty_14,
    pub __bindgen_anon_15: CM_DMA_TypeDef__bindgen_ty_15,
    pub LLP4: u32,
    pub CHCTL4: u32,
    pub MONSAR4: u32,
    pub MONDAR4: u32,
    pub MONDTCTL4: u32,
    pub MONRPT4: u32,
    pub MONSNSEQCTL4: u32,
    pub MONDNSEQCTL4: u32,
    pub RESERVED6: [u8; 8usize],
    pub SAR5: u32,
    pub DAR5: u32,
    pub DTCTL5: u32,
    pub __bindgen_anon_16: CM_DMA_TypeDef__bindgen_ty_16,
    pub __bindgen_anon_17: CM_DMA_TypeDef__bindgen_ty_17,
    pub __bindgen_anon_18: CM_DMA_TypeDef__bindgen_ty_18,
    pub LLP5: u32,
    pub CHCTL5: u32,
    pub MONSAR5: u32,
    pub MONDAR5: u32,
    pub MONDTCTL5: u32,
    pub MONRPT5: u32,
    pub MONSNSEQCTL5: u32,
    pub MONDNSEQCTL5: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_1 {
    pub RPT0: u32,
    pub RPTB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_2 {
    pub SNSEQCTL0: u32,
    pub SNSEQCTLB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_3 {
    pub DNSEQCTL0: u32,
    pub DNSEQCTLB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_4 {
    pub RPT1: u32,
    pub RPTB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_5 {
    pub SNSEQCTL1: u32,
    pub SNSEQCTLB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_6 {
    pub DNSEQCTL1: u32,
    pub DNSEQCTLB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_7 {
    pub RPT2: u32,
    pub RPTB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_8 {
    pub SNSEQCTL2: u32,
    pub SNSEQCTLB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_9 {
    pub DNSEQCTL2: u32,
    pub DNSEQCTLB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_10 {
    pub RPT3: u32,
    pub RPTB3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_11 {
    pub SNSEQCTL3: u32,
    pub SNSEQCTLB3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_12 {
    pub DNSEQCTL3: u32,
    pub DNSEQCTLB3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_13 {
    pub RPT4: u32,
    pub RPTB4: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_14 {
    pub SNSEQCTL4: u32,
    pub SNSEQCTLB4: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_15 {
    pub DNSEQCTL4: u32,
    pub DNSEQCTLB4: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_16 {
    pub RPT5: u32,
    pub RPTB5: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_17 {
    pub SNSEQCTL5: u32,
    pub SNSEQCTLB5: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_18 {
    pub DNSEQCTL5: u32,
    pub DNSEQCTLB5: u32,
}
#[doc = " @brief EFM"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_EFM_TypeDef {
    pub FAPRT: u32,
    pub KEY1: u32,
    pub KEY2: u32,
    pub RESERVED0: [u8; 8usize],
    pub FSTP: u32,
    pub FRMC: u32,
    pub FWMC: u32,
    pub FSR: u32,
    pub FSCLR: u32,
    pub FITE: u32,
    pub FSWP: u32,
    pub RESERVED1: [u8; 16usize],
    pub CHIPID: u32,
    pub RESERVED2: [u8; 12usize],
    pub UQID0: u32,
    pub UQID1: u32,
    pub UQID2: u32,
    pub RESERVED3: [u8; 164usize],
    pub MMF_REMPRT: u32,
    pub MMF_REMCR0: u32,
    pub MMF_REMCR1: u32,
    pub RESERVED4: [u8; 116usize],
    pub WLOCK: u32,
    pub RESERVED5: [u8; 12usize],
    pub F0NWPRT: u32,
}
#[doc = " @brief EMB"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_EMB_TypeDef {
    pub CTL1: u32,
    pub CTL2: u32,
    pub SOE: u32,
    pub STAT: u32,
    pub STATCLR: u32,
    pub INTEN: u32,
    pub RLSSEL: u32,
}
#[doc = " @brief FCM"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_FCM_TypeDef {
    pub LVR: u32,
    pub UVR: u32,
    pub CNTR: u32,
    pub STR: u32,
    pub MCCR: u32,
    pub RCCR: u32,
    pub RIER: u32,
    pub SR: u32,
    pub CLR: u32,
}
#[doc = " @brief GPIO"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_GPIO_TypeDef {
    pub PIDRA: u16,
    pub RESERVED0: [u8; 2usize],
    pub PODRA: u16,
    pub POERA: u16,
    pub POSRA: u16,
    pub PORRA: u16,
    pub POTRA: u16,
    pub RESERVED1: [u8; 2usize],
    pub PIDRB: u16,
    pub RESERVED2: [u8; 2usize],
    pub PODRB: u16,
    pub POERB: u16,
    pub POSRB: u16,
    pub PORRB: u16,
    pub POTRB: u16,
    pub RESERVED3: [u8; 2usize],
    pub PIDRC: u16,
    pub RESERVED4: [u8; 2usize],
    pub PODRC: u16,
    pub POERC: u16,
    pub POSRC: u16,
    pub PORRC: u16,
    pub POTRC: u16,
    pub RESERVED5: [u8; 2usize],
    pub PIDRD: u16,
    pub RESERVED6: [u8; 2usize],
    pub PODRD: u16,
    pub POERD: u16,
    pub POSRD: u16,
    pub PORRD: u16,
    pub POTRD: u16,
    pub RESERVED7: [u8; 2usize],
    pub PIDRE: u16,
    pub RESERVED8: [u8; 2usize],
    pub PODRE: u16,
    pub POERE: u16,
    pub POSRE: u16,
    pub PORRE: u16,
    pub POTRE: u16,
    pub RESERVED9: [u8; 2usize],
    pub PIDRH: u16,
    pub RESERVED10: [u8; 2usize],
    pub PODRH: u16,
    pub POERH: u16,
    pub POSRH: u16,
    pub PORRH: u16,
    pub POTRH: u16,
    pub RESERVED11: [u8; 918usize],
    pub PSPCR: u16,
    pub RESERVED12: [u8; 2usize],
    pub PCCR: u16,
    pub RESERVED13: [u8; 2usize],
    pub PWPR: u16,
    pub RESERVED14: [u8; 2usize],
    pub PCRA0: u16,
    pub PFSRA0: u16,
    pub PCRA1: u16,
    pub PFSRA1: u16,
    pub PCRA2: u16,
    pub PFSRA2: u16,
    pub PCRA3: u16,
    pub PFSRA3: u16,
    pub PCRA4: u16,
    pub PFSRA4: u16,
    pub PCRA5: u16,
    pub PFSRA5: u16,
    pub PCRA6: u16,
    pub PFSRA6: u16,
    pub PCRA7: u16,
    pub PFSRA7: u16,
    pub PCRA8: u16,
    pub PFSRA8: u16,
    pub PCRA9: u16,
    pub PFSRA9: u16,
    pub PCRA10: u16,
    pub PFSRA10: u16,
    pub PCRA11: u16,
    pub PFSRA11: u16,
    pub PCRA12: u16,
    pub PFSRA12: u16,
    pub PCRA13: u16,
    pub PFSRA13: u16,
    pub PCRA14: u16,
    pub PFSRA14: u16,
    pub PCRA15: u16,
    pub PFSRA15: u16,
    pub PCRB0: u16,
    pub PFSRB0: u16,
    pub PCRB1: u16,
    pub PFSRB1: u16,
    pub PCRB2: u16,
    pub PFSRB2: u16,
    pub PCRB3: u16,
    pub PFSRB3: u16,
    pub PCRB4: u16,
    pub PFSRB4: u16,
    pub PCRB5: u16,
    pub PFSRB5: u16,
    pub PCRB6: u16,
    pub PFSRB6: u16,
    pub PCRB7: u16,
    pub PFSRB7: u16,
    pub PCRB8: u16,
    pub PFSRB8: u16,
    pub PCRB9: u16,
    pub PFSRB9: u16,
    pub PCRB10: u16,
    pub PFSRB10: u16,
    pub PCRB11: u16,
    pub PFSRB11: u16,
    pub PCRB12: u16,
    pub PFSRB12: u16,
    pub PCRB13: u16,
    pub PFSRB13: u16,
    pub PCRB14: u16,
    pub PFSRB14: u16,
    pub PCRB15: u16,
    pub PFSRB15: u16,
    pub PCRC0: u16,
    pub PFSRC0: u16,
    pub PCRC1: u16,
    pub PFSRC1: u16,
    pub PCRC2: u16,
    pub PFSRC2: u16,
    pub PCRC3: u16,
    pub PFSRC3: u16,
    pub PCRC4: u16,
    pub PFSRC4: u16,
    pub PCRC5: u16,
    pub PFSRC5: u16,
    pub PCRC6: u16,
    pub PFSRC6: u16,
    pub PCRC7: u16,
    pub PFSRC7: u16,
    pub PCRC8: u16,
    pub PFSRC8: u16,
    pub PCRC9: u16,
    pub PFSRC9: u16,
    pub PCRC10: u16,
    pub PFSRC10: u16,
    pub PCRC11: u16,
    pub PFSRC11: u16,
    pub PCRC12: u16,
    pub PFSRC12: u16,
    pub PCRC13: u16,
    pub PFSRC13: u16,
    pub PCRC14: u16,
    pub PFSRC14: u16,
    pub PCRC15: u16,
    pub PFSRC15: u16,
    pub PCRD0: u16,
    pub PFSRD0: u16,
    pub PCRD1: u16,
    pub PFSRD1: u16,
    pub PCRD2: u16,
    pub PFSRD2: u16,
    pub RESERVED15: [u8; 20usize],
    pub PCRD8: u16,
    pub PFSRD8: u16,
    pub PCRD9: u16,
    pub PFSRD9: u16,
    pub PCRD10: u16,
    pub PFSRD10: u16,
    pub PCRD11: u16,
    pub PFSRD11: u16,
    pub RESERVED16: [u8; 16usize],
    pub PCRE0: u16,
    pub PFSRE0: u16,
    pub PCRE1: u16,
    pub PFSRE1: u16,
    pub PCRE2: u16,
    pub PFSRE2: u16,
    pub PCRE3: u16,
    pub PFSRE3: u16,
    pub PCRE4: u16,
    pub PFSRE4: u16,
    pub RESERVED17: [u8; 28usize],
    pub PCRE12: u16,
    pub PFSRE12: u16,
    pub PCRE13: u16,
    pub PFSRE13: u16,
    pub PCRE14: u16,
    pub PFSRE14: u16,
    pub PCRE15: u16,
    pub PFSRE15: u16,
    pub PCRH0: u16,
    pub PFSRH0: u16,
    pub PCRH1: u16,
    pub PFSRH1: u16,
    pub PCRH2: u16,
    pub PFSRH2: u16,
}
#[doc = " @brief HASH"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_HASH_TypeDef {
    pub CR: u32,
    pub RESERVED0: [u8; 12usize],
    pub HR7: u32,
    pub HR6: u32,
    pub HR5: u32,
    pub HR4: u32,
    pub HR3: u32,
    pub HR2: u32,
    pub HR1: u32,
    pub HR0: u32,
    pub RESERVED1: [u8; 16usize],
    pub DR15: u32,
    pub DR14: u32,
    pub DR13: u32,
    pub DR12: u32,
    pub DR11: u32,
    pub DR10: u32,
    pub DR9: u32,
    pub DR8: u32,
    pub DR7: u32,
    pub DR6: u32,
    pub DR5: u32,
    pub DR4: u32,
    pub DR3: u32,
    pub DR2: u32,
    pub DR1: u32,
    pub DR0: u32,
}
#[doc = " @brief I2C"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_I2C_TypeDef {
    pub CR1: u32,
    pub CR2: u32,
    pub CR3: u32,
    pub CR4: u32,
    pub SLR0: u32,
    pub SLR1: u32,
    pub SLTR: u32,
    pub SR: u32,
    pub CLR: u32,
    pub DTR: u8,
    pub RESERVED0: [u8; 3usize],
    pub DRR: u8,
    pub RESERVED1: [u8; 3usize],
    pub CCR: u32,
    pub FLTR: u32,
    pub FSTR: u32,
    pub SLVADDR: u32,
}
#[doc = " @brief ICG"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_ICG_TypeDef {
    pub ICG0: u32,
    pub ICG1: u32,
    pub RESERVED0: [u8; 4usize],
    pub ICG3: u32,
}
#[doc = " @brief INTC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_INTC_TypeDef {
    pub RESERVED0: [u8; 4usize],
    pub NMIER: u32,
    pub NMIFR: u32,
    pub NMIFCR: u32,
    pub EIRQCR0: u32,
    pub EIRQCR1: u32,
    pub EIRQCR2: u32,
    pub EIRQCR3: u32,
    pub EIRQCR4: u32,
    pub EIRQCR5: u32,
    pub EIRQCR6: u32,
    pub EIRQCR7: u32,
    pub EIRQCR8: u32,
    pub EIRQCR9: u32,
    pub EIRQCR10: u32,
    pub EIRQCR11: u32,
    pub EIRQCR12: u32,
    pub EIRQCR13: u32,
    pub EIRQCR14: u32,
    pub EIRQCR15: u32,
    pub WKEN: u32,
    pub EIFR: u32,
    pub EIFCR: u32,
    pub INTSEL0: u32,
    pub INTSEL1: u32,
    pub INTSEL2: u32,
    pub INTSEL3: u32,
    pub INTSEL4: u32,
    pub INTSEL5: u32,
    pub INTSEL6: u32,
    pub INTSEL7: u32,
    pub INTSEL8: u32,
    pub INTSEL9: u32,
    pub INTSEL10: u32,
    pub INTSEL11: u32,
    pub INTSEL12: u32,
    pub INTSEL13: u32,
    pub INTSEL14: u32,
    pub INTSEL15: u32,
    pub INTEN0: u32,
    pub INTEN1: u32,
    pub INTEN2: u32,
    pub INTEN3: u32,
    pub INTEN4: u32,
    pub INTEN5: u32,
    pub INTEN6: u32,
    pub INTEN7: u32,
    pub INTEN8: u32,
    pub INTEN9: u32,
    pub INTEN10: u32,
    pub INTEN11: u32,
    pub INTEN12: u32,
    pub INTEN13: u32,
    pub INTEN14: u32,
    pub INTEN15: u32,
    pub SWIER: u32,
    pub EVTER: u32,
    pub IER: u32,
}
#[doc = " @brief KEYSCAN"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_KEYSCAN_TypeDef {
    pub SCR: u32,
    pub SER: u32,
    pub SSR: u32,
}
#[doc = " @brief MCAN"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_MCAN_TypeDef {
    pub RESERVED0: [u8; 4usize],
    pub ENDN: u32,
    pub RESERVED1: [u8; 4usize],
    pub DBTP: u32,
    pub TEST: u32,
    pub RWD: u32,
    pub CCCR: u32,
    pub NBTP: u32,
    pub TSCC: u32,
    pub TSCV: u32,
    pub TOCC: u32,
    pub TOCV: u32,
    pub RESERVED2: [u8; 16usize],
    pub ECR: u32,
    pub PSR: u32,
    pub TDCR: u32,
    pub RESERVED3: [u8; 4usize],
    pub IR: u32,
    pub IE: u32,
    pub ILS: u32,
    pub ILE: u32,
    pub RESERVED4: [u8; 32usize],
    pub GFC: u32,
    pub SIDFC: u32,
    pub XIDFC: u32,
    pub RESERVED5: [u8; 4usize],
    pub XIDAM: u32,
    pub HPMS: u32,
    pub NDAT1: u32,
    pub NDAT2: u32,
    pub RXF0C: u32,
    pub RXF0S: u32,
    pub RXF0A: u32,
    pub RXBC: u32,
    pub RXF1C: u32,
    pub RXF1S: u32,
    pub RXF1A: u32,
    pub RXESC: u32,
    pub TXBC: u32,
    pub TXFQS: u32,
    pub TXESC: u32,
    pub TXBRP: u32,
    pub TXBAR: u32,
    pub TXBCR: u32,
    pub TXBTO: u32,
    pub TXBCF: u32,
    pub TXBTIE: u32,
    pub TXBCIE: u32,
    pub RESERVED6: [u8; 8usize],
    pub TXEFC: u32,
    pub TXEFS: u32,
    pub TXEFA: u32,
}
#[doc = " @brief MPU"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_MPU_TypeDef {
    pub RGD0: u32,
    pub RGD1: u32,
    pub RGD2: u32,
    pub RGD3: u32,
    pub RGD4: u32,
    pub RGD5: u32,
    pub RGD6: u32,
    pub RGD7: u32,
    pub RGD8: u32,
    pub RGD9: u32,
    pub RGD10: u32,
    pub RGD11: u32,
    pub RGD12: u32,
    pub RGD13: u32,
    pub RGD14: u32,
    pub RGD15: u32,
    pub SR: u32,
    pub ECLR: u32,
    pub WP: u32,
    pub IPPR: u32,
    pub MSPPBA: u32,
    pub MSPPCTL: u32,
    pub PSPPBA: u32,
    pub PSPPCTL: u32,
    pub S1RGE: u32,
    pub S1RGWP: u32,
    pub S1RGRP: u32,
    pub S1CR: u32,
    pub S2RGE: u32,
    pub S2RGWP: u32,
    pub S2RGRP: u32,
    pub S2CR: u32,
}
#[doc = " @brief PERIC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_PERIC_TypeDef {
    pub RESERVED0: [u8; 12usize],
    pub SMC_ENAR: u32,
    pub RESERVED1: [u8; 4usize],
    pub TMR_SYNENR: u32,
    pub RESERVED2: [u8; 4usize],
    pub USART1_NFC: u32,
}
#[doc = " @brief PWC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_PWC_TypeDef {
    pub FCG0: u32,
    pub FCG1: u32,
    pub FCG2: u32,
    pub FCG3: u32,
    pub FCG0PC: u32,
    pub RESERVED0: [u8; 17388usize],
    pub WKTCR: u16,
    pub RESERVED1: [u8; 2046usize],
    pub PWRC0: u8,
    pub RESERVED2: [u8; 3usize],
    pub PWRC1: u8,
    pub RESERVED3: [u8; 3usize],
    pub PWRC2: u8,
    pub RESERVED4: [u8; 3usize],
    pub PWRC3: u8,
    pub RESERVED5: [u8; 3usize],
    pub PWRC4: u8,
    pub RESERVED6: [u8; 3usize],
    pub PVDCR0: u8,
    pub RESERVED7: [u8; 3usize],
    pub PVDCR1: u8,
    pub RESERVED8: [u8; 3usize],
    pub PVDFCR: u8,
    pub RESERVED9: [u8; 3usize],
    pub PVDLCR: u8,
    pub RESERVED10: [u8; 7usize],
    pub PDWKE0: u8,
    pub RESERVED11: [u8; 3usize],
    pub PDWKE1: u8,
    pub RESERVED12: [u8; 3usize],
    pub PDWKE2: u8,
    pub RESERVED13: [u8; 3usize],
    pub PDWKES: u8,
    pub RESERVED14: [u8; 3usize],
    pub PDWKF0: u8,
    pub RESERVED15: [u8; 3usize],
    pub PDWKF1: u8,
    pub RESERVED16: [u8; 3usize],
    pub PWRC5: u8,
    pub RESERVED17: [u8; 3usize],
    pub PWRC6: u8,
    pub RESERVED18: [u8; 123usize],
    pub PVDICR: u8,
    pub RESERVED19: [u8; 3usize],
    pub PVDDSR: u8,
    pub RESERVED20: [u8; 3usize],
    pub RAMPC0: u32,
    pub RAMOPM: u32,
    pub PRAMLPC: u32,
    pub RESERVED21: [u8; 29496usize],
    pub STPMCR: u16,
    pub RESERVED22: [u8; 1008usize],
    pub FPRC: u16,
}
#[doc = " @brief QSPI"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_QSPI_TypeDef {
    pub CR: u32,
    pub CSCR: u32,
    pub FCR: u32,
    pub SR: u32,
    pub DCOM: u32,
    pub CCMD: u32,
    pub XCMD: u32,
    pub RESERVED0: [u8; 8usize],
    pub CLR: u32,
    pub RESERVED1: [u8; 2012usize],
    pub EXAR: u32,
}
#[doc = " @brief RMU"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_RMU_TypeDef {
    pub FRST0: u32,
    pub FRST1: u32,
    pub FRST2: u32,
    pub FRST3: u32,
    pub PRSTCR0: u8,
    pub RESERVED0: [u8; 3usize],
    pub RSTF0: u32,
}
#[doc = " @brief RTC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_RTC_TypeDef {
    pub CR0: u8,
    pub RESERVED0: [u8; 3usize],
    pub CR1: u8,
    pub RESERVED1: [u8; 3usize],
    pub CR2: u8,
    pub RESERVED2: [u8; 3usize],
    pub CR3: u8,
    pub RESERVED3: [u8; 3usize],
    pub SEC: u8,
    pub RESERVED4: [u8; 3usize],
    pub MIN: u8,
    pub RESERVED5: [u8; 3usize],
    pub HOUR: u8,
    pub RESERVED6: [u8; 3usize],
    pub WEEK: u8,
    pub RESERVED7: [u8; 3usize],
    pub DAY: u8,
    pub RESERVED8: [u8; 3usize],
    pub MON: u8,
    pub RESERVED9: [u8; 3usize],
    pub YEAR: u8,
    pub RESERVED10: [u8; 3usize],
    pub ALMMIN: u8,
    pub RESERVED11: [u8; 3usize],
    pub ALMHOUR: u8,
    pub RESERVED12: [u8; 3usize],
    pub ALMWEEK: u8,
    pub RESERVED13: [u8; 3usize],
    pub ERRCRH: u8,
    pub RESERVED14: [u8; 3usize],
    pub ERRCRL: u8,
}
#[doc = " @brief SMC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_SMC_TypeDef {
    pub STSR: u32,
    pub RESERVED0: [u8; 4usize],
    pub STCR0: u32,
    pub STCR1: u32,
    pub CMDR: u32,
    pub TMCR: u32,
    pub CPCR: u32,
    pub RESERVED1: [u8; 4usize],
    pub RFTR: u32,
    pub RESERVED2: [u8; 220usize],
    pub TMSR0: u32,
    pub CPSR0: u32,
    pub RESERVED3: [u8; 248usize],
    pub BACR: u32,
    pub RESERVED4: [u8; 4usize],
    pub CSCR0: u32,
    pub CSCR1: u32,
}
#[doc = " @brief SPI"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_SPI_TypeDef {
    pub DR: u32,
    pub CR: u32,
    pub RESERVED0: [u8; 4usize],
    pub CFG1: u32,
    pub RESERVED1: [u8; 4usize],
    pub SR: u32,
    pub CFG2: u32,
}
#[doc = " @brief SRAMC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_SRAMC_TypeDef {
    pub RESERVED0: [u8; 8usize],
    pub CKCR: u32,
    pub CKPR: u32,
    pub CKSR: u32,
    pub SRAM0_EIEN: u32,
    pub SRAM0_EIBIT0: u32,
    pub SRAM0_EIBIT1: u32,
    pub SRAM0_ECCERRADDR: u32,
    pub SRAMB_EIEN: u32,
    pub SRAMB_EIBIT0: u32,
    pub SRAMB_EIBIT1: u32,
    pub SRAMB_ECCERRADDR: u32,
}
#[doc = " @brief SWDT"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_SWDT_TypeDef {
    pub CR: u32,
    pub SR: u32,
    pub RR: u32,
}
#[doc = " @brief TMR0"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR0_TypeDef {
    pub CNTAR: u32,
    pub CNTBR: u32,
    pub CMPAR: u32,
    pub CMPBR: u32,
    pub BCONR: u32,
    pub STFLR: u32,
}
#[doc = " @brief TMR4"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR4_TypeDef {
    pub OCCRUH: u16,
    pub RESERVED0: [u8; 2usize],
    pub OCCRUL: u16,
    pub RESERVED1: [u8; 2usize],
    pub OCCRVH: u16,
    pub RESERVED2: [u8; 2usize],
    pub OCCRVL: u16,
    pub RESERVED3: [u8; 2usize],
    pub OCCRWH: u16,
    pub RESERVED4: [u8; 2usize],
    pub OCCRWL: u16,
    pub RESERVED5: [u8; 2usize],
    pub OCCRXH: u16,
    pub RESERVED6: [u8; 2usize],
    pub OCCRXL: u16,
    pub RESERVED7: [u8; 2usize],
    pub OCSRU: u16,
    pub OCERU: u16,
    pub OCSRV: u16,
    pub OCERV: u16,
    pub OCSRW: u16,
    pub OCERW: u16,
    pub OCSRX: u16,
    pub OCERX: u16,
    pub OCMRUH: u16,
    pub RESERVED8: [u8; 2usize],
    pub OCMRUL: u32,
    pub OCMRVH: u16,
    pub RESERVED9: [u8; 2usize],
    pub OCMRVL: u32,
    pub OCMRWH: u16,
    pub RESERVED10: [u8; 2usize],
    pub OCMRWL: u32,
    pub OCMRXH: u16,
    pub RESERVED11: [u8; 2usize],
    pub OCMRXL: u32,
    pub CPSR: u16,
    pub RESERVED12: [u8; 2usize],
    pub CNTR: u16,
    pub RESERVED13: [u8; 2usize],
    pub CCSR: u16,
    pub CVPR: u16,
    pub PSCR: u32,
    pub RESERVED14: [u8; 34usize],
    pub PFSRU: u16,
    pub PDARU: u16,
    pub PDBRU: u16,
    pub RESERVED15: [u8; 2usize],
    pub PFSRV: u16,
    pub PDARV: u16,
    pub PDBRV: u16,
    pub RESERVED16: [u8; 2usize],
    pub PFSRW: u16,
    pub PDARW: u16,
    pub PDBRW: u16,
    pub RESERVED17: [u8; 2usize],
    pub PFSRX: u16,
    pub PDARX: u16,
    pub PDBRX: u16,
    pub POCRU: u16,
    pub RESERVED18: [u8; 2usize],
    pub POCRV: u16,
    pub RESERVED19: [u8; 2usize],
    pub POCRW: u16,
    pub RESERVED20: [u8; 2usize],
    pub POCRX: u16,
    pub RESERVED21: [u8; 2usize],
    pub SCCRUH: u16,
    pub RESERVED22: [u8; 2usize],
    pub SCCRUL: u16,
    pub RESERVED23: [u8; 2usize],
    pub SCCRVH: u16,
    pub RESERVED24: [u8; 2usize],
    pub SCCRVL: u16,
    pub RESERVED25: [u8; 2usize],
    pub SCCRWH: u16,
    pub RESERVED26: [u8; 2usize],
    pub SCCRWL: u16,
    pub RESERVED27: [u8; 2usize],
    pub SCCRXH: u16,
    pub RESERVED28: [u8; 2usize],
    pub SCCRXL: u16,
    pub RESERVED29: [u8; 2usize],
    pub SCSRUH: u16,
    pub SCMRUH: u16,
    pub SCSRUL: u16,
    pub SCMRUL: u16,
    pub SCSRVH: u16,
    pub SCMRVH: u16,
    pub SCSRVL: u16,
    pub SCMRVL: u16,
    pub SCSRWH: u16,
    pub SCMRWH: u16,
    pub SCSRWL: u16,
    pub SCMRWL: u16,
    pub SCSRXH: u16,
    pub SCMRXH: u16,
    pub SCSRXL: u16,
    pub SCMRXL: u16,
    pub SCER: u16,
    pub RESERVED30: [u8; 2usize],
    pub RCSR: u32,
    pub SCIR: u16,
    pub RESERVED31: [u8; 2usize],
    pub SCFR: u16,
}
#[doc = " @brief TMR6"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR6_TypeDef {
    pub CNTER: u32,
    pub UPDAR: u32,
    pub RESERVED0: [u8; 56usize],
    pub PERAR: u32,
    pub PERBR: u32,
    pub PERCR: u32,
    pub RESERVED1: [u8; 52usize],
    pub GCMAR: u32,
    pub GCMBR: u32,
    pub GCMCR: u32,
    pub GCMDR: u32,
    pub GCMER: u32,
    pub GCMFR: u32,
    pub RESERVED2: [u8; 40usize],
    pub SCMAR: u32,
    pub SCMBR: u32,
    pub SCMCR: u32,
    pub SCMDR: u32,
    pub SCMER: u32,
    pub SCMFR: u32,
    pub RESERVED3: [u8; 40usize],
    pub DTUAR: u32,
    pub DTDAR: u32,
    pub DTUBR: u32,
    pub DTDBR: u32,
    pub RESERVED4: [u8; 48usize],
    pub GCONR: u32,
    pub ICONR: u32,
    pub BCONR: u32,
    pub DCONR: u32,
    pub RESERVED5: [u8; 4usize],
    pub PCNAR: u32,
    pub PCNBR: u32,
    pub FCNGR: u32,
    pub VPERR: u32,
    pub STFLR: u32,
    pub RESERVED6: [u8; 24usize],
    pub HSTAR: u32,
    pub HSTPR: u32,
    pub HCLRR: u32,
    pub HUPDR: u32,
    pub HCPAR: u32,
    pub HCPBR: u32,
    pub HCUPR: u32,
    pub HCDOR: u32,
}
#[doc = " @brief TMR6_COMMON"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR6_COMMON_TypeDef {
    pub RESERVED0: [u8; 236usize],
    pub FCNTR: u32,
    pub SSTAR: u32,
    pub SSTPR: u32,
    pub SCLRR: u32,
    pub SUPDR: u32,
}
#[doc = " @brief TMRA"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMRA_TypeDef {
    pub CNTER: u32,
    pub PERAR: u32,
    pub RESERVED0: [u8; 56usize],
    pub CMPAR1: u32,
    pub CMPAR2: u32,
    pub CMPAR3: u32,
    pub CMPAR4: u32,
    pub CMPAR5: u32,
    pub CMPAR6: u32,
    pub CMPAR7: u32,
    pub CMPAR8: u32,
    pub RESERVED1: [u8; 32usize],
    pub BCSTRL: u8,
    pub BCSTRH: u8,
    pub RESERVED2: [u8; 2usize],
    pub HCONR: u16,
    pub RESERVED3: [u8; 2usize],
    pub HCUPR: u16,
    pub RESERVED4: [u8; 2usize],
    pub HCDOR: u16,
    pub RESERVED5: [u8; 2usize],
    pub ICONR: u16,
    pub RESERVED6: [u8; 2usize],
    pub ECONR: u16,
    pub RESERVED7: [u8; 2usize],
    pub FCONR: u16,
    pub RESERVED8: [u8; 2usize],
    pub STFLR: u16,
    pub RESERVED9: [u8; 34usize],
    pub BCONR1: u16,
    pub RESERVED10: [u8; 6usize],
    pub BCONR2: u16,
    pub RESERVED11: [u8; 6usize],
    pub BCONR3: u16,
    pub RESERVED12: [u8; 6usize],
    pub BCONR4: u16,
    pub RESERVED13: [u8; 38usize],
    pub CCONR1: u16,
    pub RESERVED14: [u8; 2usize],
    pub CCONR2: u16,
    pub RESERVED15: [u8; 2usize],
    pub CCONR3: u16,
    pub RESERVED16: [u8; 2usize],
    pub CCONR4: u16,
    pub RESERVED17: [u8; 2usize],
    pub CCONR5: u16,
    pub RESERVED18: [u8; 2usize],
    pub CCONR6: u16,
    pub RESERVED19: [u8; 2usize],
    pub CCONR7: u16,
    pub RESERVED20: [u8; 2usize],
    pub CCONR8: u16,
    pub RESERVED21: [u8; 34usize],
    pub PCONR1: u16,
    pub RESERVED22: [u8; 2usize],
    pub PCONR2: u16,
    pub RESERVED23: [u8; 2usize],
    pub PCONR3: u16,
    pub RESERVED24: [u8; 2usize],
    pub PCONR4: u16,
    pub RESERVED25: [u8; 2usize],
    pub PCONR5: u16,
    pub RESERVED26: [u8; 2usize],
    pub PCONR6: u16,
    pub RESERVED27: [u8; 2usize],
    pub PCONR7: u16,
    pub RESERVED28: [u8; 2usize],
    pub PCONR8: u16,
}
#[doc = " @brief TRNG"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TRNG_TypeDef {
    pub CR: u32,
    pub MR: u32,
    pub RESERVED0: [u8; 4usize],
    pub DR0: u32,
    pub DR1: u32,
}
#[doc = " @brief USART"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_USART_TypeDef {
    pub SR: u32,
    pub TDR: u16,
    pub RDR: u16,
    pub BRR: u32,
    pub CR1: u32,
    pub CR2: u32,
    pub CR3: u32,
    pub PR: u32,
    pub LBMC: u32,
}
#[doc = " @brief WDT"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_WDT_TypeDef {
    pub CR: u32,
    pub SR: u32,
    pub RR: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_str_bit_t {
    pub STRT: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_cr0_bit_t {
    pub RESERVED0: [u32; 6usize],
    pub CLREN: u32,
    pub DFMT: u32,
    pub RESERVED1: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_cr1_bit_t {
    pub RESERVED0: [u32; 2usize],
    pub RSCHSEL: u32,
    pub RESERVED1: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_cr2_bit_t {
    pub RESERVED0: [u32; 12usize],
    pub OVSMOD: u32,
    pub RESERVED1: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_trgsr_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub TRGENA: u32,
    pub RESERVED1: [u32; 7usize],
    pub TRGENB: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_exchselr_bit_t {
    pub EXCHSEL: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_isr_bit_t {
    pub EOCAF: u32,
    pub EOCBF: u32,
    pub RESERVED0: [u32; 2usize],
    pub SASTPDF: u32,
    pub RESERVED1: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_icr_bit_t {
    pub EOCAIEN: u32,
    pub EOCBIEN: u32,
    pub RESERVED0: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_isclrr_bit_t {
    pub CLREOCAF: u32,
    pub CLREOCBF: u32,
    pub RESERVED0: [u32; 2usize],
    pub CLRSASTPDF: u32,
    pub RESERVED1: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_synccr_bit_t {
    pub SYNCEN: u32,
    pub RESERVED0: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_awdcr_bit_t {
    pub AWD0EN: u32,
    pub AWD0IEN: u32,
    pub AWD0MD: u32,
    pub RESERVED0: [u32; 1usize],
    pub AWD1EN: u32,
    pub AWD1IEN: u32,
    pub AWD1MD: u32,
    pub RESERVED1: [u32; 9usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_awdsr_bit_t {
    pub AWD0F: u32,
    pub AWD1F: u32,
    pub RESERVED0: [u32; 2usize],
    pub AWDCMF: u32,
    pub RESERVED1: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_awdsclrr_bit_t {
    pub CLRAWD0F: u32,
    pub CLRAWD1F: u32,
    pub RESERVED0: [u32; 2usize],
    pub CLRAWDCMF: u32,
    pub RESERVED1: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_aes_cr_bit_t {
    pub START: u32,
    pub MODE: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_aos_intsfttrg_bit_t {
    pub STRG: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_aos_pevntnfcr_bit_t {
    pub NFEN1: u32,
    pub RESERVED0: [u32; 7usize],
    pub NFEN2: u32,
    pub RESERVED1: [u32; 7usize],
    pub NFEN3: u32,
    pub RESERVED2: [u32; 7usize],
    pub NFEN4: u32,
    pub RESERVED3: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmp_mdr_bit_t {
    pub CENA: u32,
    pub CWDE: u32,
    pub RESERVED0: [u32; 2usize],
    pub CSST: u32,
    pub RESERVED1: [u32; 2usize],
    pub CMON: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmp_fir_bit_t {
    pub RESERVED0: [u32; 3usize],
    pub CIEN: u32,
    pub RESERVED1: [u32; 2usize],
    pub CFF: u32,
    pub CRF: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmp_ocr_bit_t {
    pub COEN: u32,
    pub COPS: u32,
    pub CPOE: u32,
    pub RESERVED0: [u32; 1usize],
    pub BWEN: u32,
    pub BWMD: u32,
    pub RESERVED1: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmp_bwsr1_bit_t {
    pub CTWS0: u32,
    pub CTWS1: u32,
    pub CTWS2: u32,
    pub CTWS3: u32,
    pub CTWS4: u32,
    pub CTWS5: u32,
    pub CTWS6: u32,
    pub CTWS7: u32,
    pub CTWS8: u32,
    pub CTWS9: u32,
    pub CTWS10: u32,
    pub CTWS11: u32,
    pub CTWS12: u32,
    pub CTWS13: u32,
    pub CTWS14: u32,
    pub CTWS15: u32,
    pub CTWP0: u32,
    pub CTWP1: u32,
    pub CTWP2: u32,
    pub CTWP3: u32,
    pub CTWP4: u32,
    pub CTWP5: u32,
    pub CTWP6: u32,
    pub CTWP7: u32,
    pub CTWP8: u32,
    pub CTWP9: u32,
    pub CTWP10: u32,
    pub CTWP11: u32,
    pub CTWP12: u32,
    pub CTWP13: u32,
    pub CTWP14: u32,
    pub CTWP15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_xtaldivcr_bit_t {
    pub FRADIVEN: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_xtalcfgr_bit_t {
    pub RESERVED0: [u32; 6usize],
    pub XTALMS: u32,
    pub RESERVED1: [u32; 1usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_xtal32cr_bit_t {
    pub XTAL32STP: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_lrccr_bit_t {
    pub LRCSTP: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_pllhcr_bit_t {
    pub PLLHOFF: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_xtalcr_bit_t {
    pub XTALSTP: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_hrccr_bit_t {
    pub HRCSTP: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_mrccr_bit_t {
    pub MRCSTP: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_oscstbsr_bit_t {
    pub HRCSTBF: u32,
    pub RESERVED0: [u32; 2usize],
    pub XTALSTBF: u32,
    pub RESERVED1: [u32; 1usize],
    pub PLLHSTBF: u32,
    pub RESERVED2: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_mcocfgr_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub MCOEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_tpiuckcfgr_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub TPIUCKOE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_xtalstdcr_bit_t {
    pub XTALSTDIE: u32,
    pub XTALSTDRE: u32,
    pub XTALSTDRIS: u32,
    pub RESERVED0: [u32; 4usize],
    pub XTALSTDE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_xtalstdsr_bit_t {
    pub XTALSTDF: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmu_pllhcfgr_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub PLLSRC: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_crc_cr_bit_t {
    pub CR: u32,
    pub FLAG: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_ctc_cr1_bit_t {
    pub RESERVED0: [u32; 6usize],
    pub ERRIE: u32,
    pub CTCEN: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_ctc_str_bit_t {
    pub TRIMOK: u32,
    pub TRMOVF: u32,
    pub TRMUDF: u32,
    pub CTCBSY: u32,
    pub RESERVED0: [u32; 28usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dac_dadr1_bit_t {
    pub DR0: u32,
    pub DR1: u32,
    pub DR2: u32,
    pub DR3: u32,
    pub DL0R4: u32,
    pub DL1R5: u32,
    pub DL2R6: u32,
    pub DL3R7: u32,
    pub DL4R8: u32,
    pub DL5R9: u32,
    pub DL6R10: u32,
    pub DL7R11: u32,
    pub DL8: u32,
    pub DL9: u32,
    pub DL10: u32,
    pub DL11: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dac_dadr2_bit_t {
    pub DR0: u32,
    pub DR1: u32,
    pub DR2: u32,
    pub DR3: u32,
    pub DL0R4: u32,
    pub DL1R5: u32,
    pub DL2R6: u32,
    pub DL3R7: u32,
    pub DL4R8: u32,
    pub DL5R9: u32,
    pub DL6R10: u32,
    pub DL7R11: u32,
    pub DL8: u32,
    pub DL9: u32,
    pub DL10: u32,
    pub DL11: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dac_dacr_bit_t {
    pub DAE: u32,
    pub DA1E: u32,
    pub DA2E: u32,
    pub RESERVED0: [u32; 5usize],
    pub DPSEL: u32,
    pub DAAMP1: u32,
    pub DAAMP2: u32,
    pub EXTDSL1: u32,
    pub EXTDSL2: u32,
    pub RESERVED1: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dac_daadpcr_bit_t {
    pub ADCSL1: u32,
    pub ADCSL2: u32,
    pub ADCSL3: u32,
    pub RESERVED0: [u32; 5usize],
    pub DA1SF: u32,
    pub DA2SF: u32,
    pub RESERVED1: [u32; 5usize],
    pub ADPEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dac_daocr_bit_t {
    pub RESERVED0: [u32; 14usize],
    pub DAODIS1: u32,
    pub DAODIS2: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dcu_ctl_bit_t {
    pub RESERVED0: [u32; 8usize],
    pub COMPTRG: u32,
    pub RESERVED1: [u32; 22usize],
    pub INTEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dcu_flag_bit_t {
    pub FLAG_OP: u32,
    pub FLAG_LS2: u32,
    pub FLAG_EQ2: u32,
    pub FLAG_GT2: u32,
    pub FLAG_LS1: u32,
    pub FLAG_EQ1: u32,
    pub FLAG_GT1: u32,
    pub RESERVED0: [u32; 2usize],
    pub FLAG_RLD: u32,
    pub FLAG_BTM: u32,
    pub FLAG_TOP: u32,
    pub RESERVED1: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dcu_flagclr_bit_t {
    pub CLR_OP: u32,
    pub CLR_LS2: u32,
    pub CLR_EQ2: u32,
    pub CLR_GT2: u32,
    pub CLR_LS1: u32,
    pub CLR_EQ1: u32,
    pub CLR_GT1: u32,
    pub RESERVED0: [u32; 2usize],
    pub CLR_RLD: u32,
    pub CLR_BTM: u32,
    pub CLR_TOP: u32,
    pub RESERVED1: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dcu_intevtsel_bit_t {
    pub SEL_OP: u32,
    pub SEL_LS2: u32,
    pub SEL_EQ2: u32,
    pub SEL_GT2: u32,
    pub SEL_LS1: u32,
    pub SEL_EQ1: u32,
    pub SEL_GT1: u32,
    pub RESERVED0: [u32; 3usize],
    pub SEL_BTM: u32,
    pub SEL_TOP: u32,
    pub RESERVED1: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_en_bit_t {
    pub EN: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intstat0_bit_t {
    pub TRNERR0: u32,
    pub TRNERR1: u32,
    pub TRNERR2: u32,
    pub TRNERR3: u32,
    pub TRNERR4: u32,
    pub TRNERR5: u32,
    pub RESERVED0: [u32; 10usize],
    pub REQERR0: u32,
    pub REQERR1: u32,
    pub REQERR2: u32,
    pub REQERR3: u32,
    pub REQERR4: u32,
    pub REQERR5: u32,
    pub RESERVED1: [u32; 10usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intstat1_bit_t {
    pub TC0: u32,
    pub TC1: u32,
    pub TC2: u32,
    pub TC3: u32,
    pub TC4: u32,
    pub TC5: u32,
    pub RESERVED0: [u32; 10usize],
    pub BTC0: u32,
    pub BTC1: u32,
    pub BTC2: u32,
    pub BTC3: u32,
    pub BTC4: u32,
    pub BTC5: u32,
    pub RESERVED1: [u32; 10usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intmask0_bit_t {
    pub MSKTRNERR0: u32,
    pub MSKTRNERR1: u32,
    pub MSKTRNERR2: u32,
    pub MSKTRNERR3: u32,
    pub MSKTRNERR4: u32,
    pub MSKTRNERR5: u32,
    pub RESERVED0: [u32; 10usize],
    pub MSKREQERR0: u32,
    pub MSKREQERR1: u32,
    pub MSKREQERR2: u32,
    pub MSKREQERR3: u32,
    pub MSKREQERR4: u32,
    pub MSKREQERR5: u32,
    pub RESERVED1: [u32; 10usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intmask1_bit_t {
    pub MSKTC0: u32,
    pub MSKTC1: u32,
    pub MSKTC2: u32,
    pub MSKTC3: u32,
    pub MSKTC4: u32,
    pub MSKTC5: u32,
    pub RESERVED0: [u32; 10usize],
    pub MSKBTC0: u32,
    pub MSKBTC1: u32,
    pub MSKBTC2: u32,
    pub MSKBTC3: u32,
    pub MSKBTC4: u32,
    pub MSKBTC5: u32,
    pub RESERVED1: [u32; 10usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intclr0_bit_t {
    pub CLRTRNERR0: u32,
    pub CLRTRNERR1: u32,
    pub CLRTRNERR2: u32,
    pub CLRTRNERR3: u32,
    pub CLRTRNERR4: u32,
    pub CLRTRNERR5: u32,
    pub RESERVED0: [u32; 10usize],
    pub CLRREQERR0: u32,
    pub CLRREQERR1: u32,
    pub CLRREQERR2: u32,
    pub CLRREQERR3: u32,
    pub CLRREQERR4: u32,
    pub CLRREQERR5: u32,
    pub RESERVED1: [u32; 10usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_intclr1_bit_t {
    pub CLRTC0: u32,
    pub CLRTC1: u32,
    pub CLRTC2: u32,
    pub CLRTC3: u32,
    pub CLRTC4: u32,
    pub CLRTC5: u32,
    pub RESERVED0: [u32; 10usize],
    pub CLRBTC0: u32,
    pub CLRBTC1: u32,
    pub CLRBTC2: u32,
    pub CLRBTC3: u32,
    pub CLRBTC4: u32,
    pub CLRBTC5: u32,
    pub RESERVED1: [u32; 10usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_reqstat_bit_t {
    pub RESERVED0: [u32; 15usize],
    pub RCFGREQ: u32,
    pub RESERVED1: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_chstat_bit_t {
    pub DMAACT: u32,
    pub RCFGACT: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_rcfgctl_bit_t {
    pub RCFGEN: u32,
    pub RCFGLLP: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_swreq_bit_t {
    pub SWREQ0: u32,
    pub SWREQ1: u32,
    pub SWREQ2: u32,
    pub SWREQ3: u32,
    pub SWREQ4: u32,
    pub SWREQ5: u32,
    pub SWREQ6: u32,
    pub SWREQ7: u32,
    pub RESERVED0: [u32; 7usize],
    pub SWRCFGREQ: u32,
    pub RESERVED1: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_chctl_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub SRPTEN: u32,
    pub DRPTEN: u32,
    pub SNSEQEN: u32,
    pub DNSEQEN: u32,
    pub RESERVED1: [u32; 2usize],
    pub LLPEN: u32,
    pub LLPRUN: u32,
    pub IE: u32,
    pub RESERVED2: [u32; 19usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fstp_bit_t {
    pub FSTP: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_frmc_bit_t {
    pub RESERVED0: [u32; 8usize],
    pub LVM: u32,
    pub RESERVED1: [u32; 7usize],
    pub ICACHE: u32,
    pub DCACHE: u32,
    pub PREFETE: u32,
    pub CRST: u32,
    pub RESERVED2: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fwmc_bit_t {
    pub RESERVED0: [u32; 8usize],
    pub BUSHLDCTL: u32,
    pub RESERVED1: [u32; 7usize],
    pub KEY1LOCK: u32,
    pub KEY2LOCK: u32,
    pub RESERVED2: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fsr_bit_t {
    pub OTPWERR: u32,
    pub PRTWERR: u32,
    pub PGSZERR: u32,
    pub MISMTCH: u32,
    pub OPTEND: u32,
    pub COLERR: u32,
    pub RESERVED0: [u32; 2usize],
    pub RDY: u32,
    pub RESERVED1: [u32; 23usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fsclr_bit_t {
    pub OTPWERRCLR: u32,
    pub PRTWERRCLR: u32,
    pub PGSZERRCLR: u32,
    pub MISMTCHCLR: u32,
    pub OPTENDCLR: u32,
    pub COLERRCLR: u32,
    pub RESERVED0: [u32; 26usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fite_bit_t {
    pub PEERRITE: u32,
    pub OPTENDITE: u32,
    pub COLERRITE: u32,
    pub RESERVED0: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_fswp_bit_t {
    pub FSWP: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_mmf_remcr_bit_t {
    pub RESERVED0: [u32; 31usize],
    pub EN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_wlock_bit_t {
    pub WLOCK0: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_f0nwprt_bit_t {
    pub F0NWPRT0: u32,
    pub F0NWPRT1: u32,
    pub F0NWPRT2: u32,
    pub F0NWPRT3: u32,
    pub F0NWPRT4: u32,
    pub F0NWPRT5: u32,
    pub F0NWPRT6: u32,
    pub F0NWPRT7: u32,
    pub F0NWPRT8: u32,
    pub F0NWPRT9: u32,
    pub F0NWPRT10: u32,
    pub F0NWPRT11: u32,
    pub F0NWPRT12: u32,
    pub F0NWPRT13: u32,
    pub F0NWPRT14: u32,
    pub F0NWPRT15: u32,
    pub F0NWPRT16: u32,
    pub F0NWPRT17: u32,
    pub F0NWPRT18: u32,
    pub F0NWPRT19: u32,
    pub F0NWPRT20: u32,
    pub F0NWPRT21: u32,
    pub F0NWPRT22: u32,
    pub F0NWPRT23: u32,
    pub F0NWPRT24: u32,
    pub F0NWPRT25: u32,
    pub F0NWPRT26: u32,
    pub F0NWPRT27: u32,
    pub F0NWPRT28: u32,
    pub F0NWPRT29: u32,
    pub F0NWPRT30: u32,
    pub F0NWPRT31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_ctl1_bit_t {
    pub CMPEN1: u32,
    pub CMPEN2: u32,
    pub CMPEN3: u32,
    pub CMPEN4: u32,
    pub SYSEN: u32,
    pub PWMSEN0: u32,
    pub PWMSEN1: u32,
    pub PWMSEN2: u32,
    pub PWMSEN3: u32,
    pub RESERVED0: [u32; 7usize],
    pub PORTINEN1: u32,
    pub PORTINEN2: u32,
    pub PORTINEN3: u32,
    pub PORTINEN4: u32,
    pub RESERVED1: [u32; 2usize],
    pub INVSEL1: u32,
    pub INVSEL2: u32,
    pub INVSEL3: u32,
    pub INVSEL4: u32,
    pub RESERVED2: [u32; 1usize],
    pub OSCSTPEN: u32,
    pub SRAMECCERREN: u32,
    pub SRAMPYERREN: u32,
    pub LOCKUPEN: u32,
    pub PVDEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_ctl2_bit_t {
    pub PWMLV0: u32,
    pub PWMLV1: u32,
    pub PWMLV2: u32,
    pub PWMLV3: u32,
    pub RESERVED0: [u32; 14usize],
    pub NFEN1: u32,
    pub RESERVED1: [u32; 2usize],
    pub NFEN2: u32,
    pub RESERVED2: [u32; 2usize],
    pub NFEN3: u32,
    pub RESERVED3: [u32; 2usize],
    pub NFEN4: u32,
    pub RESERVED4: [u32; 4usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_soe_bit_t {
    pub SOE: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_stat_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub PWMSF: u32,
    pub CMPF: u32,
    pub SYSF: u32,
    pub RESERVED1: [u32; 1usize],
    pub PWMST: u32,
    pub CMPST: u32,
    pub SYSST: u32,
    pub PORTINF1: u32,
    pub PORTINF2: u32,
    pub PORTINF3: u32,
    pub PORTINF4: u32,
    pub RESERVED2: [u32; 2usize],
    pub PORTINST1: u32,
    pub PORTINST2: u32,
    pub PORTINST3: u32,
    pub PORTINST4: u32,
    pub RESERVED3: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_statclr_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub PWMSFCLR: u32,
    pub CMPFCLR: u32,
    pub SYSFCLR: u32,
    pub RESERVED1: [u32; 4usize],
    pub PORTINFCLR1: u32,
    pub PORTINFCLR2: u32,
    pub PORTINFCLR3: u32,
    pub PORTINFCLR4: u32,
    pub RESERVED2: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_inten_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub PWMSINTEN: u32,
    pub CMPINTEN: u32,
    pub SYSINTEN: u32,
    pub RESERVED1: [u32; 4usize],
    pub PORTININTEN1: u32,
    pub PORTININTEN2: u32,
    pub PORTININTEN3: u32,
    pub PORTININTEN4: u32,
    pub RESERVED2: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_rlssel_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub PWMRSEL: u32,
    pub CMPRSEL: u32,
    pub SYSRSEL: u32,
    pub RESERVED1: [u32; 4usize],
    pub PORTINRSEL1: u32,
    pub PORTINRSEL2: u32,
    pub PORTINRSEL3: u32,
    pub PORTINRSEL4: u32,
    pub RESERVED2: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_fcm_str_bit_t {
    pub START: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_fcm_rccr_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub INEXS: u32,
    pub RESERVED1: [u32; 7usize],
    pub EXREFE: u32,
    pub RESERVED2: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_fcm_rier_bit_t {
    pub ERRIE: u32,
    pub MENDIE: u32,
    pub OVFIE: u32,
    pub RESERVED0: [u32; 1usize],
    pub ERRINTRS: u32,
    pub RESERVED1: [u32; 2usize],
    pub ERRE: u32,
    pub RESERVED2: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_fcm_sr_bit_t {
    pub ERRF: u32,
    pub MENDF: u32,
    pub OVF: u32,
    pub RESERVED0: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_fcm_clr_bit_t {
    pub ERRFCLR: u32,
    pub MENDFCLR: u32,
    pub OVFCLR: u32,
    pub RESERVED0: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_pidr_bit_t {
    pub PIN00: u32,
    pub PIN01: u32,
    pub PIN02: u32,
    pub PIN03: u32,
    pub PIN04: u32,
    pub PIN05: u32,
    pub PIN06: u32,
    pub PIN07: u32,
    pub PIN08: u32,
    pub PIN09: u32,
    pub PIN10: u32,
    pub PIN11: u32,
    pub PIN12: u32,
    pub PIN13: u32,
    pub PIN14: u32,
    pub PIN15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_podr_bit_t {
    pub POUT00: u32,
    pub POUT01: u32,
    pub POUT02: u32,
    pub POUT03: u32,
    pub POUT04: u32,
    pub POUT05: u32,
    pub POUT06: u32,
    pub POUT07: u32,
    pub POUT08: u32,
    pub POUT09: u32,
    pub POUT10: u32,
    pub POUT11: u32,
    pub POUT12: u32,
    pub POUT13: u32,
    pub POUT14: u32,
    pub POUT15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_poer_bit_t {
    pub POUTE00: u32,
    pub POUTE01: u32,
    pub POUTE02: u32,
    pub POUTE03: u32,
    pub POUTE04: u32,
    pub POUTE05: u32,
    pub POUTE06: u32,
    pub POUTE07: u32,
    pub POUTE08: u32,
    pub POUTE09: u32,
    pub POUTE10: u32,
    pub POUTE11: u32,
    pub POUTE12: u32,
    pub POUTE13: u32,
    pub POUTE14: u32,
    pub POUTE15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_posr_bit_t {
    pub POS00: u32,
    pub POS01: u32,
    pub POS02: u32,
    pub POS03: u32,
    pub POS04: u32,
    pub POS05: u32,
    pub POS06: u32,
    pub POS07: u32,
    pub POS08: u32,
    pub POS09: u32,
    pub POS10: u32,
    pub POS11: u32,
    pub POS12: u32,
    pub POS13: u32,
    pub POS14: u32,
    pub POS15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_porr_bit_t {
    pub POR00: u32,
    pub POR01: u32,
    pub POR02: u32,
    pub POR03: u32,
    pub POR04: u32,
    pub POR05: u32,
    pub POR06: u32,
    pub POR07: u32,
    pub POR08: u32,
    pub POR09: u32,
    pub POR10: u32,
    pub POR11: u32,
    pub POR12: u32,
    pub POR13: u32,
    pub POR14: u32,
    pub POR15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_potr_bit_t {
    pub POT00: u32,
    pub POT01: u32,
    pub POT02: u32,
    pub POT03: u32,
    pub POT04: u32,
    pub POT05: u32,
    pub POT06: u32,
    pub POT07: u32,
    pub POT08: u32,
    pub POT09: u32,
    pub POT10: u32,
    pub POT11: u32,
    pub POT12: u32,
    pub POT13: u32,
    pub POT14: u32,
    pub POT15: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_pwpr_bit_t {
    pub WE: u32,
    pub RESERVED0: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_pcr_bit_t {
    pub POUT: u32,
    pub POUTE: u32,
    pub NOD: u32,
    pub RESERVED0: [u32; 3usize],
    pub PUU: u32,
    pub PUD: u32,
    pub PIN: u32,
    pub INVE: u32,
    pub CINSEL: u32,
    pub RESERVED1: [u32; 1usize],
    pub INTE: u32,
    pub PINAE: u32,
    pub LTE: u32,
    pub DDIS: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_pfsr_bit_t {
    pub RESERVED0: [u32; 8usize],
    pub BFE: u32,
    pub RESERVED1: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_hash_cr_bit_t {
    pub START: u32,
    pub FST_GRP: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_cr1_bit_t {
    pub PE: u32,
    pub SMBUS: u32,
    pub SMBALRTEN: u32,
    pub SMBDEFAULTEN: u32,
    pub SMBHOSTEN: u32,
    pub RESERVED0: [u32; 1usize],
    pub GCEN: u32,
    pub RESTART: u32,
    pub START: u32,
    pub STOP: u32,
    pub ACK: u32,
    pub RESERVED1: [u32; 4usize],
    pub SWRST: u32,
    pub RESERVED2: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_cr2_bit_t {
    pub STARTIE: u32,
    pub SLADDR0IE: u32,
    pub SLADDR1IE: u32,
    pub TENDIE: u32,
    pub STOPIE: u32,
    pub RESERVED0: [u32; 1usize],
    pub RFULLIE: u32,
    pub TEMPTYIE: u32,
    pub RESERVED1: [u32; 1usize],
    pub ARLOIE: u32,
    pub RESERVED2: [u32; 1usize],
    pub RFREQIE: u32,
    pub NACKIE: u32,
    pub RESERVED3: [u32; 1usize],
    pub TMOUTIE: u32,
    pub RESERVED4: [u32; 5usize],
    pub GENCALLIE: u32,
    pub SMBDEFAULTIE: u32,
    pub SMBHOSTIE: u32,
    pub SMBALRTIE: u32,
    pub RESERVED5: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_cr3_bit_t {
    pub TMOUTEN: u32,
    pub LTMOUT: u32,
    pub HTMOUT: u32,
    pub RESERVED0: [u32; 4usize],
    pub FACKEN: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_cr4_bit_t {
    pub RESERVED0: [u32; 10usize],
    pub BUSWAIT: u32,
    pub RESERVED1: [u32; 1usize],
    pub BUSFREE_CLREN: u32,
    pub RESERVED2: [u32; 19usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_slr0_bit_t {
    pub RESERVED0: [u32; 12usize],
    pub SLADDR0EN: u32,
    pub RESERVED1: [u32; 2usize],
    pub ADDRMOD0: u32,
    pub RESERVED2: [u32; 10usize],
    pub MASK0EN: u32,
    pub RESERVED3: [u32; 5usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_slr1_bit_t {
    pub RESERVED0: [u32; 12usize],
    pub SLADDR1EN: u32,
    pub RESERVED1: [u32; 2usize],
    pub ADDRMOD1: u32,
    pub RESERVED2: [u32; 10usize],
    pub MASK1EN: u32,
    pub RESERVED3: [u32; 5usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_sr_bit_t {
    pub STARTF: u32,
    pub SLADDR0F: u32,
    pub SLADDR1F: u32,
    pub TENDF: u32,
    pub STOPF: u32,
    pub RESERVED0: [u32; 1usize],
    pub RFULLF: u32,
    pub TEMPTYF: u32,
    pub RESERVED1: [u32; 1usize],
    pub ARLOF: u32,
    pub ACKRF: u32,
    pub RESERVED2: [u32; 1usize],
    pub NACKF: u32,
    pub RESERVED3: [u32; 1usize],
    pub TMOUTF: u32,
    pub RESERVED4: [u32; 1usize],
    pub MSL: u32,
    pub BUSY: u32,
    pub TRA: u32,
    pub RESERVED5: [u32; 1usize],
    pub GENCALLF: u32,
    pub SMBDEFAULTF: u32,
    pub SMBHOSTF: u32,
    pub SMBALRTF: u32,
    pub TFEMPTY: u32,
    pub TFFULL: u32,
    pub RFEMPTY: u32,
    pub RFFULL: u32,
    pub RESERVED6: [u32; 3usize],
    pub RFREQ: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_clr_bit_t {
    pub STARTFCLR: u32,
    pub SLADDR0FCLR: u32,
    pub SLADDR1FCLR: u32,
    pub TENDFCLR: u32,
    pub STOPFCLR: u32,
    pub RESERVED0: [u32; 1usize],
    pub RFULLFCLR: u32,
    pub RESERVED1: [u32; 2usize],
    pub ARLOFCLR: u32,
    pub RFREQCLR: u32,
    pub RESERVED2: [u32; 1usize],
    pub NACKFCLR: u32,
    pub RESERVED3: [u32; 1usize],
    pub TMOUTFCLR: u32,
    pub RESERVED4: [u32; 5usize],
    pub GENCALLFCLR: u32,
    pub SMBDEFAULTFCLR: u32,
    pub SMBHOSTFCLR: u32,
    pub SMBALRTFCLR: u32,
    pub RESERVED5: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_fltr_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub DNFEN: u32,
    pub ANFEN: u32,
    pub RESERVED1: [u32; 26usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_fstr_bit_t {
    pub FEN: u32,
    pub TFFLUSH: u32,
    pub RFFLUSH: u32,
    pub NACKTFFLUSH: u32,
    pub RESERVED0: [u32; 28usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_icg_icg0_bit_t {
    pub SWDTAUTS: u32,
    pub SWDTITS: u32,
    pub RESERVED0: [u32; 10usize],
    pub SWDTSLPOFF: u32,
    pub RESERVED1: [u32; 3usize],
    pub WDTAUTS: u32,
    pub WDTITS: u32,
    pub RESERVED2: [u32; 10usize],
    pub WDTSLPOFF: u32,
    pub RESERVED3: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_icg_icg1_bit_t {
    pub HRCFREQSEL: u32,
    pub RESERVED0: [u32; 7usize],
    pub HRCSTOP: u32,
    pub RESERVED1: [u32; 9usize],
    pub BORDIS: u32,
    pub RESERVED2: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_nmier_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub SWDTEN: u32,
    pub PVD1EN: u32,
    pub PVD2EN: u32,
    pub RESERVED1: [u32; 1usize],
    pub XTALSTPEN: u32,
    pub RESERVED2: [u32; 2usize],
    pub RPARERREN: u32,
    pub RECCERREN: u32,
    pub BUSERREN: u32,
    pub WDTEN: u32,
    pub RESERVED3: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_nmifr_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub SWDTF: u32,
    pub PVD1F: u32,
    pub PVD2F: u32,
    pub RESERVED1: [u32; 1usize],
    pub XTALSTPF: u32,
    pub RESERVED2: [u32; 2usize],
    pub RPARERRF: u32,
    pub RECCERRF: u32,
    pub BUSERRF: u32,
    pub WDTF: u32,
    pub RESERVED3: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_nmifcr_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub SWDTFCLR: u32,
    pub PVD1FCLR: u32,
    pub PVD2FCLR: u32,
    pub RESERVED1: [u32; 1usize],
    pub XTALSTPFCLR: u32,
    pub RESERVED2: [u32; 2usize],
    pub RPARERRFCLR: u32,
    pub RECCERRFCLR: u32,
    pub BUSERRFCLR: u32,
    pub WDTFCLR: u32,
    pub RESERVED3: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_eirqcr_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub EFEN: u32,
    pub RESERVED1: [u32; 7usize],
    pub NOCEN: u32,
    pub RESERVED2: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_wken_bit_t {
    pub RESERVED0: [u32; 16usize],
    pub SWDTWKEN: u32,
    pub RESERVED1: [u32; 2usize],
    pub CMP1WKEN: u32,
    pub WKTMWKEN: u32,
    pub RTCALMWKEN: u32,
    pub RTCPRDWKEN: u32,
    pub TMR0CMPWKEN: u32,
    pub RESERVED2: [u32; 2usize],
    pub RXWKEN: u32,
    pub RESERVED3: [u32; 2usize],
    pub CMP2WKEN: u32,
    pub CMP3WKEN: u32,
    pub CMP4WKEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_eifr_bit_t {
    pub EIF0: u32,
    pub EIF1: u32,
    pub EIF2: u32,
    pub EIF3: u32,
    pub EIF4: u32,
    pub EIF5: u32,
    pub EIF6: u32,
    pub EIF7: u32,
    pub EIF8: u32,
    pub EIF9: u32,
    pub EIF10: u32,
    pub EIF11: u32,
    pub EIF12: u32,
    pub EIF13: u32,
    pub EIF14: u32,
    pub EIF15: u32,
    pub RESERVED0: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_eifcr_bit_t {
    pub EIFCLR0: u32,
    pub EIFCLR1: u32,
    pub EIFCLR2: u32,
    pub EIFCLR3: u32,
    pub EIFCLR4: u32,
    pub EIFCLR5: u32,
    pub EIFCLR6: u32,
    pub EIFCLR7: u32,
    pub EIFCLR8: u32,
    pub EIFCLR9: u32,
    pub EIFCLR10: u32,
    pub EIFCLR11: u32,
    pub EIFCLR12: u32,
    pub EIFCLR13: u32,
    pub EIFCLR14: u32,
    pub EIFCLR15: u32,
    pub RESERVED0: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_swier_bit_t {
    pub SWIE0: u32,
    pub SWIE1: u32,
    pub SWIE2: u32,
    pub SWIE3: u32,
    pub SWIE4: u32,
    pub SWIE5: u32,
    pub SWIE6: u32,
    pub SWIE7: u32,
    pub SWIE8: u32,
    pub SWIE9: u32,
    pub SWIE10: u32,
    pub SWIE11: u32,
    pub SWIE12: u32,
    pub SWIE13: u32,
    pub SWIE14: u32,
    pub SWIE15: u32,
    pub SWIE16: u32,
    pub SWIE17: u32,
    pub SWIE18: u32,
    pub SWIE19: u32,
    pub SWIE20: u32,
    pub SWIE21: u32,
    pub SWIE22: u32,
    pub SWIE23: u32,
    pub SWIE24: u32,
    pub SWIE25: u32,
    pub SWIE26: u32,
    pub SWIE27: u32,
    pub SWIE28: u32,
    pub SWIE29: u32,
    pub SWIE30: u32,
    pub SWIE31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_evter_bit_t {
    pub EVTE0: u32,
    pub EVTE1: u32,
    pub EVTE2: u32,
    pub EVTE3: u32,
    pub EVTE4: u32,
    pub EVTE5: u32,
    pub EVTE6: u32,
    pub EVTE7: u32,
    pub EVTE8: u32,
    pub EVTE9: u32,
    pub EVTE10: u32,
    pub EVTE11: u32,
    pub EVTE12: u32,
    pub EVTE13: u32,
    pub EVTE14: u32,
    pub EVTE15: u32,
    pub EVTE16: u32,
    pub EVTE17: u32,
    pub EVTE18: u32,
    pub EVTE19: u32,
    pub EVTE20: u32,
    pub EVTE21: u32,
    pub EVTE22: u32,
    pub EVTE23: u32,
    pub EVTE24: u32,
    pub EVTE25: u32,
    pub EVTE26: u32,
    pub EVTE27: u32,
    pub EVTE28: u32,
    pub EVTE29: u32,
    pub EVTE30: u32,
    pub EVTE31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_intc_ier_bit_t {
    pub IEN0: u32,
    pub IEN1: u32,
    pub IEN2: u32,
    pub IEN3: u32,
    pub IEN4: u32,
    pub IEN5: u32,
    pub IEN6: u32,
    pub IEN7: u32,
    pub IEN8: u32,
    pub IEN9: u32,
    pub IEN10: u32,
    pub IEN11: u32,
    pub IEN12: u32,
    pub IEN13: u32,
    pub IEN14: u32,
    pub IEN15: u32,
    pub IEN16: u32,
    pub IEN17: u32,
    pub IEN18: u32,
    pub IEN19: u32,
    pub IEN20: u32,
    pub IEN21: u32,
    pub IEN22: u32,
    pub IEN23: u32,
    pub IEN24: u32,
    pub IEN25: u32,
    pub IEN26: u32,
    pub IEN27: u32,
    pub IEN28: u32,
    pub IEN29: u32,
    pub IEN30: u32,
    pub IEN31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_keyscan_ser_bit_t {
    pub SEN: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_dbtp_bit_t {
    pub RESERVED0: [u32; 23usize],
    pub TDC: u32,
    pub RESERVED1: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_test_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub LBCK: u32,
    pub RESERVED1: [u32; 2usize],
    pub RX: u32,
    pub RESERVED2: [u32; 5usize],
    pub PVAL: u32,
    pub RESERVED3: [u32; 7usize],
    pub SVAL: u32,
    pub RESERVED4: [u32; 10usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_cccr_bit_t {
    pub INIT: u32,
    pub CCE: u32,
    pub ASM: u32,
    pub CSA: u32,
    pub CSR: u32,
    pub MON: u32,
    pub DAR: u32,
    pub TEST: u32,
    pub FDOE: u32,
    pub BRSE: u32,
    pub UTSU: u32,
    pub WMM: u32,
    pub PXHD: u32,
    pub EFBI: u32,
    pub TXP: u32,
    pub NISO: u32,
    pub RESERVED0: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_tocc_bit_t {
    pub ETOC: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_ecr_bit_t {
    pub RESERVED0: [u32; 15usize],
    pub RP: u32,
    pub RESERVED1: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_psr_bit_t {
    pub RESERVED0: [u32; 5usize],
    pub EP: u32,
    pub EW: u32,
    pub BO: u32,
    pub RESERVED1: [u32; 3usize],
    pub RESI: u32,
    pub RBRS: u32,
    pub RFDF: u32,
    pub PXE: u32,
    pub RESERVED2: [u32; 17usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_ir_bit_t {
    pub RF0N: u32,
    pub RF0W: u32,
    pub RF0F: u32,
    pub RF0L: u32,
    pub RF1N: u32,
    pub RF1W: u32,
    pub RF1F: u32,
    pub RF1L: u32,
    pub HPM: u32,
    pub TC: u32,
    pub TCF: u32,
    pub TFE: u32,
    pub TEFN: u32,
    pub TEFW: u32,
    pub TEFF: u32,
    pub TEFL: u32,
    pub TSW: u32,
    pub MRAF: u32,
    pub TOO: u32,
    pub DRX: u32,
    pub BEC: u32,
    pub BEU: u32,
    pub ELO: u32,
    pub EP: u32,
    pub EW: u32,
    pub BO: u32,
    pub WDI: u32,
    pub PEA: u32,
    pub PED: u32,
    pub ARA: u32,
    pub RESERVED0: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_ie_bit_t {
    pub RF0NE: u32,
    pub RF0WE: u32,
    pub RF0FE: u32,
    pub RF0LE: u32,
    pub RF1NE: u32,
    pub RF1WE: u32,
    pub RF1FE: u32,
    pub RF1LE: u32,
    pub HPME: u32,
    pub TCE: u32,
    pub TCFE: u32,
    pub TFEE: u32,
    pub TEFNE: u32,
    pub TEFWE: u32,
    pub TEFFE: u32,
    pub TEFLE: u32,
    pub TSWE: u32,
    pub MRAFE: u32,
    pub TOOE: u32,
    pub DRXE: u32,
    pub BECE: u32,
    pub BEUE: u32,
    pub ELOE: u32,
    pub EPE: u32,
    pub EWE: u32,
    pub BOE: u32,
    pub WDIE: u32,
    pub PEAE: u32,
    pub PEDE: u32,
    pub ARAE: u32,
    pub RESERVED0: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_ils_bit_t {
    pub RF0NL: u32,
    pub RF0WL: u32,
    pub RF0FL: u32,
    pub RF0LL: u32,
    pub RF1NL: u32,
    pub RF1WL: u32,
    pub RF1FL: u32,
    pub RF1LL: u32,
    pub HPML: u32,
    pub TCL: u32,
    pub TCFL: u32,
    pub TFEL: u32,
    pub TEFNL: u32,
    pub TEFWL: u32,
    pub TEFFL: u32,
    pub TEFLL: u32,
    pub TSWL: u32,
    pub MRAFL: u32,
    pub TOOL: u32,
    pub DRXL: u32,
    pub BECL: u32,
    pub BEUL: u32,
    pub ELOL: u32,
    pub EPL: u32,
    pub EWL: u32,
    pub BOL: u32,
    pub WDIL: u32,
    pub PEAL: u32,
    pub PEDL: u32,
    pub ARAL: u32,
    pub RESERVED0: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_ile_bit_t {
    pub EINT0: u32,
    pub EINT1: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_gfc_bit_t {
    pub RRFE: u32,
    pub RRFS: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_hpms_bit_t {
    pub RESERVED0: [u32; 15usize],
    pub FLST: u32,
    pub RESERVED1: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_ndat1_bit_t {
    pub ND0: u32,
    pub ND1: u32,
    pub ND2: u32,
    pub ND3: u32,
    pub ND4: u32,
    pub ND5: u32,
    pub ND6: u32,
    pub ND7: u32,
    pub ND8: u32,
    pub ND9: u32,
    pub ND10: u32,
    pub ND11: u32,
    pub ND12: u32,
    pub ND13: u32,
    pub ND14: u32,
    pub ND15: u32,
    pub ND16: u32,
    pub ND17: u32,
    pub ND18: u32,
    pub ND19: u32,
    pub ND20: u32,
    pub ND21: u32,
    pub ND22: u32,
    pub ND23: u32,
    pub ND24: u32,
    pub ND25: u32,
    pub ND26: u32,
    pub ND27: u32,
    pub ND28: u32,
    pub ND29: u32,
    pub ND30: u32,
    pub ND31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_ndat2_bit_t {
    pub ND32: u32,
    pub ND33: u32,
    pub ND34: u32,
    pub ND35: u32,
    pub ND36: u32,
    pub ND37: u32,
    pub ND38: u32,
    pub ND39: u32,
    pub ND40: u32,
    pub ND41: u32,
    pub ND42: u32,
    pub ND43: u32,
    pub ND44: u32,
    pub ND45: u32,
    pub ND46: u32,
    pub ND47: u32,
    pub ND48: u32,
    pub ND49: u32,
    pub ND50: u32,
    pub ND51: u32,
    pub ND52: u32,
    pub ND53: u32,
    pub ND54: u32,
    pub ND55: u32,
    pub ND56: u32,
    pub ND57: u32,
    pub ND58: u32,
    pub ND59: u32,
    pub ND60: u32,
    pub ND61: u32,
    pub ND62: u32,
    pub ND63: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_rxf0c_bit_t {
    pub RESERVED0: [u32; 31usize],
    pub F0OM: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_rxf0s_bit_t {
    pub RESERVED0: [u32; 24usize],
    pub F0F: u32,
    pub RF0L: u32,
    pub RESERVED1: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_rxf1c_bit_t {
    pub RESERVED0: [u32; 31usize],
    pub F1OM: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_rxf1s_bit_t {
    pub RESERVED0: [u32; 24usize],
    pub F1F: u32,
    pub RF1L: u32,
    pub RESERVED1: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_txbc_bit_t {
    pub RESERVED0: [u32; 30usize],
    pub TFQM: u32,
    pub RESERVED1: [u32; 1usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_txfqs_bit_t {
    pub RESERVED0: [u32; 21usize],
    pub TFQF: u32,
    pub RESERVED1: [u32; 10usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_txbrp_bit_t {
    pub TRP0: u32,
    pub TRP1: u32,
    pub TRP2: u32,
    pub TRP3: u32,
    pub TRP4: u32,
    pub TRP5: u32,
    pub TRP6: u32,
    pub TRP7: u32,
    pub TRP8: u32,
    pub TRP9: u32,
    pub TRP10: u32,
    pub TRP11: u32,
    pub TRP12: u32,
    pub TRP13: u32,
    pub TRP14: u32,
    pub TRP15: u32,
    pub TRP16: u32,
    pub TRP17: u32,
    pub TRP18: u32,
    pub TRP19: u32,
    pub TRP20: u32,
    pub TRP21: u32,
    pub TRP22: u32,
    pub TRP23: u32,
    pub TRP24: u32,
    pub TRP25: u32,
    pub TRP26: u32,
    pub TRP27: u32,
    pub TRP28: u32,
    pub TRP29: u32,
    pub TRP30: u32,
    pub TRP31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_txbar_bit_t {
    pub AR0: u32,
    pub AR1: u32,
    pub AR2: u32,
    pub AR3: u32,
    pub AR4: u32,
    pub AR5: u32,
    pub AR6: u32,
    pub AR7: u32,
    pub AR8: u32,
    pub AR9: u32,
    pub AR10: u32,
    pub AR11: u32,
    pub AR12: u32,
    pub AR13: u32,
    pub AR14: u32,
    pub AR15: u32,
    pub AR16: u32,
    pub AR17: u32,
    pub AR18: u32,
    pub AR19: u32,
    pub AR20: u32,
    pub AR21: u32,
    pub AR22: u32,
    pub AR23: u32,
    pub AR24: u32,
    pub AR25: u32,
    pub AR26: u32,
    pub AR27: u32,
    pub AR28: u32,
    pub AR29: u32,
    pub AR30: u32,
    pub AR31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_txbcr_bit_t {
    pub CR0: u32,
    pub CR1: u32,
    pub CR2: u32,
    pub CR3: u32,
    pub CR4: u32,
    pub CR5: u32,
    pub CR6: u32,
    pub CR7: u32,
    pub CR8: u32,
    pub CR9: u32,
    pub CR10: u32,
    pub CR11: u32,
    pub CR12: u32,
    pub CR13: u32,
    pub CR14: u32,
    pub CR15: u32,
    pub CR16: u32,
    pub CR17: u32,
    pub CR18: u32,
    pub CR19: u32,
    pub CR20: u32,
    pub CR21: u32,
    pub CR22: u32,
    pub CR23: u32,
    pub CR24: u32,
    pub CR25: u32,
    pub CR26: u32,
    pub CR27: u32,
    pub CR28: u32,
    pub CR29: u32,
    pub CR30: u32,
    pub CR31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_txbto_bit_t {
    pub TO0: u32,
    pub TO1: u32,
    pub TO2: u32,
    pub TO3: u32,
    pub TO4: u32,
    pub TO5: u32,
    pub TO6: u32,
    pub TO7: u32,
    pub TO8: u32,
    pub TO9: u32,
    pub TO10: u32,
    pub TO11: u32,
    pub TO12: u32,
    pub TO13: u32,
    pub TO14: u32,
    pub TO15: u32,
    pub TO16: u32,
    pub TO17: u32,
    pub TO18: u32,
    pub TO19: u32,
    pub TO20: u32,
    pub TO21: u32,
    pub TO22: u32,
    pub TO23: u32,
    pub TO24: u32,
    pub TO25: u32,
    pub TO26: u32,
    pub TO27: u32,
    pub TO28: u32,
    pub TO29: u32,
    pub TO30: u32,
    pub TO31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_txbcf_bit_t {
    pub CF0: u32,
    pub CF1: u32,
    pub CF2: u32,
    pub CF3: u32,
    pub CF4: u32,
    pub CF5: u32,
    pub CF6: u32,
    pub CF7: u32,
    pub CF8: u32,
    pub CF9: u32,
    pub CF10: u32,
    pub CF11: u32,
    pub CF12: u32,
    pub CF13: u32,
    pub CF14: u32,
    pub CF15: u32,
    pub CF16: u32,
    pub CF17: u32,
    pub CF18: u32,
    pub CF19: u32,
    pub CF20: u32,
    pub CF21: u32,
    pub CF22: u32,
    pub CF23: u32,
    pub CF24: u32,
    pub CF25: u32,
    pub CF26: u32,
    pub CF27: u32,
    pub CF28: u32,
    pub CF29: u32,
    pub CF30: u32,
    pub CF31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_txbtie_bit_t {
    pub TIE0: u32,
    pub TIE1: u32,
    pub TIE2: u32,
    pub TIE3: u32,
    pub TIE4: u32,
    pub TIE5: u32,
    pub TIE6: u32,
    pub TIE7: u32,
    pub TIE8: u32,
    pub TIE9: u32,
    pub TIE10: u32,
    pub TIE11: u32,
    pub TIE12: u32,
    pub TIE13: u32,
    pub TIE14: u32,
    pub TIE15: u32,
    pub TIE16: u32,
    pub TIE17: u32,
    pub TIE18: u32,
    pub TIE19: u32,
    pub TIE20: u32,
    pub TIE21: u32,
    pub TIE22: u32,
    pub TIE23: u32,
    pub TIE24: u32,
    pub TIE25: u32,
    pub TIE26: u32,
    pub TIE27: u32,
    pub TIE28: u32,
    pub TIE29: u32,
    pub TIE30: u32,
    pub TIE31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_txbcie_bit_t {
    pub CFIE0: u32,
    pub CFIE1: u32,
    pub CFIE2: u32,
    pub CFIE3: u32,
    pub CFIE4: u32,
    pub CFIE5: u32,
    pub CFIE6: u32,
    pub CFIE7: u32,
    pub CFIE8: u32,
    pub CFIE9: u32,
    pub CFIE10: u32,
    pub CFIE11: u32,
    pub CFIE12: u32,
    pub CFIE13: u32,
    pub CFIE14: u32,
    pub CFIE15: u32,
    pub CFIE16: u32,
    pub CFIE17: u32,
    pub CFIE18: u32,
    pub CFIE19: u32,
    pub CFIE20: u32,
    pub CFIE21: u32,
    pub CFIE22: u32,
    pub CFIE23: u32,
    pub CFIE24: u32,
    pub CFIE25: u32,
    pub CFIE26: u32,
    pub CFIE27: u32,
    pub CFIE28: u32,
    pub CFIE29: u32,
    pub CFIE30: u32,
    pub CFIE31: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mcan_txefs_bit_t {
    pub RESERVED0: [u32; 24usize],
    pub EFF: u32,
    pub TEFL: u32,
    pub RESERVED1: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_sr_bit_t {
    pub SMPU1EAF: u32,
    pub SMPU2EAF: u32,
    pub PSPEF: u32,
    pub MSPEF: u32,
    pub RESERVED0: [u32; 28usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_eclr_bit_t {
    pub SMPU1ECLR: u32,
    pub SMPU2ECLR: u32,
    pub PSPECLR: u32,
    pub MSPECLR: u32,
    pub RESERVED0: [u32; 28usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_wp_bit_t {
    pub MPUWE: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_ippr_bit_t {
    pub AESRDP: u32,
    pub AESWRP: u32,
    pub HASHRDP: u32,
    pub HASHWRP: u32,
    pub TRNGRDP: u32,
    pub TRNGWRP: u32,
    pub CRCRDP: u32,
    pub CRCWRP: u32,
    pub EFMRDP: u32,
    pub EFMWRP: u32,
    pub RESERVED0: [u32; 2usize],
    pub WDTRDP: u32,
    pub WDTWRP: u32,
    pub SWDTRDP: u32,
    pub SWDTWRP: u32,
    pub BKSRAMRDP: u32,
    pub BKSRAMWRP: u32,
    pub RTCRDP: u32,
    pub RTCWRP: u32,
    pub DMPURDP: u32,
    pub DMPUWRP: u32,
    pub SRAMCRDP: u32,
    pub SRAMCWRP: u32,
    pub INTCRDP: u32,
    pub INTCWRP: u32,
    pub SYSCRDP: u32,
    pub SYSCWRP: u32,
    pub MSTPRDP: u32,
    pub MSPTWRP: u32,
    pub RESERVED1: [u32; 1usize],
    pub BUSERRE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_msppctl_bit_t {
    pub RESERVED0: [u32; 30usize],
    pub MSPPACT: u32,
    pub MSPPE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_psppctl_bit_t {
    pub RESERVED0: [u32; 30usize],
    pub PSPPACT: u32,
    pub PSPPE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_srge_bit_t {
    pub RG0E: u32,
    pub RG1E: u32,
    pub RG2E: u32,
    pub RG3E: u32,
    pub RG4E: u32,
    pub RG5E: u32,
    pub RG6E: u32,
    pub RG7E: u32,
    pub RG8E: u32,
    pub RG9E: u32,
    pub RG10E: u32,
    pub RG11E: u32,
    pub RG12E: u32,
    pub RG13E: u32,
    pub RG14E: u32,
    pub RG15E: u32,
    pub RESERVED0: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_srgwp_bit_t {
    pub RG0WP: u32,
    pub RG1WP: u32,
    pub RG2WP: u32,
    pub RG3WP: u32,
    pub RG4WP: u32,
    pub RG5WP: u32,
    pub RG6WP: u32,
    pub RG7WP: u32,
    pub RG8WP: u32,
    pub RG9WP: u32,
    pub RG10WP: u32,
    pub RG11WP: u32,
    pub RG12WP: u32,
    pub RG13WP: u32,
    pub RG14WP: u32,
    pub RG15WP: u32,
    pub RESERVED0: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_srgrp_bit_t {
    pub RG0RP: u32,
    pub RG1RP: u32,
    pub RG2RP: u32,
    pub RG3RP: u32,
    pub RG4RP: u32,
    pub RG5RP: u32,
    pub RG6RP: u32,
    pub RG7RP: u32,
    pub RG8RP: u32,
    pub RG9RP: u32,
    pub RG10RP: u32,
    pub RG11RP: u32,
    pub RG12RP: u32,
    pub RG13RP: u32,
    pub RG14RP: u32,
    pub RG15RP: u32,
    pub RESERVED0: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_scr_bit_t {
    pub SMPUBRP: u32,
    pub SMPUBWP: u32,
    pub RESERVED0: [u32; 5usize],
    pub SMPUE: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_peric_smc_enar_bit_t {
    pub RESERVED0: [u32; 1usize],
    pub SMCEN: u32,
    pub RESERVED1: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_peric_tmr_synenr_bit_t {
    pub TMR0U1A: u32,
    pub TMR0U1B: u32,
    pub TMR0U2A: u32,
    pub TMR0U2B: u32,
    pub TMR4U1: u32,
    pub TMR4U2: u32,
    pub TMR4U3: u32,
    pub RESERVED0: [u32; 1usize],
    pub TMR6U1: u32,
    pub TMR6U2: u32,
    pub TMRAU1: u32,
    pub TMRAU2: u32,
    pub TMRAU3: u32,
    pub TMRAU4: u32,
    pub TMRAU5: u32,
    pub RESERVED1: [u32; 17usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_peric_usart1_nfc_bit_t {
    pub RESERVED0: [u32; 2usize],
    pub USART1_NFE: u32,
    pub RESERVED1: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_fcg0_bit_t {
    pub SRAMH: u32,
    pub RESERVED0: [u32; 3usize],
    pub SRAM0: u32,
    pub RESERVED1: [u32; 5usize],
    pub SRAMB: u32,
    pub RESERVED2: [u32; 2usize],
    pub KEY: u32,
    pub DMA1: u32,
    pub DMA2: u32,
    pub FCM: u32,
    pub AOS: u32,
    pub CTC: u32,
    pub RESERVED3: [u32; 1usize],
    pub AES: u32,
    pub HASH: u32,
    pub TRNG: u32,
    pub CRC: u32,
    pub DCU1: u32,
    pub DCU2: u32,
    pub DCU3: u32,
    pub DCU4: u32,
    pub RESERVED4: [u32; 4usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_fcg1_bit_t {
    pub MCAN1: u32,
    pub MCAN2: u32,
    pub RESERVED0: [u32; 1usize],
    pub QSPI: u32,
    pub I2C1: u32,
    pub I2C2: u32,
    pub RESERVED1: [u32; 10usize],
    pub SPI1: u32,
    pub SPI2: u32,
    pub SPI3: u32,
    pub RESERVED2: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_fcg2_bit_t {
    pub TMR6_1: u32,
    pub TMR6_2: u32,
    pub RESERVED0: [u32; 7usize],
    pub TMR4_1: u32,
    pub TMR4_2: u32,
    pub TMR4_3: u32,
    pub TMR0_1: u32,
    pub TMR0_2: u32,
    pub RESERVED1: [u32; 1usize],
    pub EMB: u32,
    pub RESERVED2: [u32; 4usize],
    pub TMRA_1: u32,
    pub TMRA_2: u32,
    pub TMRA_3: u32,
    pub TMRA_4: u32,
    pub TMRA_5: u32,
    pub RESERVED3: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_fcg3_bit_t {
    pub ADC1: u32,
    pub ADC2: u32,
    pub ADC3: u32,
    pub RESERVED0: [u32; 1usize],
    pub DAC: u32,
    pub RESERVED1: [u32; 3usize],
    pub CMP12: u32,
    pub CMP34: u32,
    pub RESERVED2: [u32; 6usize],
    pub SMC: u32,
    pub RESERVED3: [u32; 3usize],
    pub USART1: u32,
    pub USART2: u32,
    pub USART3: u32,
    pub USART4: u32,
    pub USART5: u32,
    pub USART6: u32,
    pub RESERVED4: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_fcg0pc_bit_t {
    pub PRT0: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_wktcr_bit_t {
    pub RESERVED0: [u32; 12usize],
    pub WKOVF: u32,
    pub RESERVED1: [u32; 2usize],
    pub WKTCE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pwrc0_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub PWDN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pwrc1_bit_t {
    pub RESERVED0: [u32; 2usize],
    pub VHRCSD: u32,
    pub PDTS: u32,
    pub RESERVED1: [u32; 4usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pwrc4_bit_t {
    pub RESERVED0: [u32; 7usize],
    pub ADBUFE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pvdcr0_bit_t {
    pub EXVCCINEN: u32,
    pub RESERVED0: [u32; 4usize],
    pub PVD1EN: u32,
    pub PVD2EN: u32,
    pub RESERVED1: [u32; 1usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pvdcr1_bit_t {
    pub PVD1IRE: u32,
    pub PVD1IRS: u32,
    pub PVD1CMPOE: u32,
    pub RESERVED0: [u32; 1usize],
    pub PVD2IRE: u32,
    pub PVD2IRS: u32,
    pub PVD2CMPOE: u32,
    pub RESERVED1: [u32; 1usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pvdfcr_bit_t {
    pub PVD1NFDIS: u32,
    pub RESERVED0: [u32; 3usize],
    pub PVD2NFDIS: u32,
    pub RESERVED1: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pdwke0_bit_t {
    pub WKE00: u32,
    pub WKE01: u32,
    pub WKE02: u32,
    pub WKE03: u32,
    pub WKE10: u32,
    pub WKE11: u32,
    pub WKE12: u32,
    pub WKE13: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pdwke1_bit_t {
    pub WKE20: u32,
    pub WKE21: u32,
    pub WKE22: u32,
    pub WKE23: u32,
    pub WKE30: u32,
    pub WKE31: u32,
    pub WKE32: u32,
    pub WKE33: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pdwke2_bit_t {
    pub VD1WKE: u32,
    pub VD2WKE: u32,
    pub RESERVED0: [u32; 2usize],
    pub RTCPRDWKE: u32,
    pub RTCALMWKE: u32,
    pub RESERVED1: [u32; 1usize],
    pub WKTMWKE: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pdwkes_bit_t {
    pub WK0EGS: u32,
    pub WK1EGS: u32,
    pub WK2EGS: u32,
    pub WK3EGS: u32,
    pub VD1EGS: u32,
    pub VD2EGS: u32,
    pub RESERVED0: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pdwkf0_bit_t {
    pub PTWK0F: u32,
    pub PTWK1F: u32,
    pub PTWK2F: u32,
    pub PTWK3F: u32,
    pub VD1WKF: u32,
    pub VD2WKF: u32,
    pub RESERVED0: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pdwkf1_bit_t {
    pub RESERVED0: [u32; 3usize],
    pub RXD0WKF: u32,
    pub RTCPRDWKF: u32,
    pub RTCALMWKF: u32,
    pub RESERVED1: [u32; 1usize],
    pub WKTMWKF: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pwrc5_bit_t {
    pub VVDRSD: u32,
    pub SRAMBSD: u32,
    pub RESERVED0: [u32; 5usize],
    pub CSDIS: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pvddsr_bit_t {
    pub PVD1MON: u32,
    pub PVD1DETFLG: u32,
    pub RESERVED0: [u32; 2usize],
    pub PVD2MON: u32,
    pub PVD2DETFLG: u32,
    pub RESERVED1: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_rampc0_bit_t {
    pub RAMPDC0: u32,
    pub RESERVED0: [u32; 9usize],
    pub RAMPDC10: u32,
    pub RESERVED1: [u32; 21usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pramlpc_bit_t {
    pub PRAMPDC0: u32,
    pub RESERVED0: [u32; 1usize],
    pub PRAMPDC2: u32,
    pub RESERVED1: [u32; 29usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_stpmcr_bit_t {
    pub FLNWT: u32,
    pub CKSMRC: u32,
    pub RESERVED0: [u32; 12usize],
    pub EXBUSOE: u32,
    pub STOP: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_fprc_bit_t {
    pub FPRCB0: u32,
    pub FPRCB1: u32,
    pub RESERVED0: [u32; 1usize],
    pub FPRCB3: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rmu_frst0_bit_t {
    pub RESERVED0: [u32; 13usize],
    pub KEY: u32,
    pub DMA1: u32,
    pub DMA2: u32,
    pub FCM: u32,
    pub AOS: u32,
    pub CTC: u32,
    pub RESERVED1: [u32; 1usize],
    pub AES: u32,
    pub HASH: u32,
    pub TRNG: u32,
    pub CRC: u32,
    pub DCU1: u32,
    pub DCU2: u32,
    pub DCU3: u32,
    pub DCU4: u32,
    pub RESERVED2: [u32; 4usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rmu_frst1_bit_t {
    pub RESERVED0: [u32; 3usize],
    pub QSPI: u32,
    pub RESERVED1: [u32; 12usize],
    pub SPI1: u32,
    pub SPI2: u32,
    pub SPI3: u32,
    pub RESERVED2: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rmu_frst2_bit_t {
    pub TMR6: u32,
    pub RESERVED0: [u32; 9usize],
    pub TMR4: u32,
    pub RESERVED1: [u32; 1usize],
    pub TMR0: u32,
    pub RESERVED2: [u32; 2usize],
    pub EMB: u32,
    pub RESERVED3: [u32; 4usize],
    pub TMRA: u32,
    pub RESERVED4: [u32; 11usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rmu_frst3_bit_t {
    pub ADC1: u32,
    pub ADC2: u32,
    pub ADC3: u32,
    pub RESERVED0: [u32; 1usize],
    pub DAC: u32,
    pub RESERVED1: [u32; 3usize],
    pub CMP12: u32,
    pub CMP34: u32,
    pub RESERVED2: [u32; 6usize],
    pub SMC: u32,
    pub RESERVED3: [u32; 3usize],
    pub USART1: u32,
    pub USART2: u32,
    pub USART3: u32,
    pub USART4: u32,
    pub USART5: u32,
    pub USART6: u32,
    pub RESERVED4: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rmu_prstcr0_bit_t {
    pub RESERVED0: [u32; 5usize],
    pub LKUPREN: u32,
    pub RESERVED1: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rmu_rstf0_bit_t {
    pub PORF: u32,
    pub PINRF: u32,
    pub BORF: u32,
    pub PVD1RF: u32,
    pub PVD2RF: u32,
    pub WDRF: u32,
    pub SWDRF: u32,
    pub PDRF: u32,
    pub SWRF: u32,
    pub MPUERF: u32,
    pub RAPERF: u32,
    pub RAECRF: u32,
    pub CKFERF: u32,
    pub XTALERF: u32,
    pub LKUPRF: u32,
    pub RESERVED0: [u32; 15usize],
    pub MULTIRF: u32,
    pub CLRF: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_cr0_bit_t {
    pub RESET: u32,
    pub RESERVED0: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_cr1_bit_t {
    pub RESERVED0: [u32; 3usize],
    pub AMPM: u32,
    pub RESERVED1: [u32; 1usize],
    pub ONEHZOE: u32,
    pub ONEHZSEL: u32,
    pub START: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_cr2_bit_t {
    pub RWREQ: u32,
    pub RWEN: u32,
    pub PRDF: u32,
    pub ALMF: u32,
    pub RESERVED0: [u32; 1usize],
    pub PRDIE: u32,
    pub ALMIE: u32,
    pub ALME: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_cr3_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub LRCEN: u32,
    pub RESERVED1: [u32; 2usize],
    pub RCKSEL: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_errcrh_bit_t {
    pub COMP8: u32,
    pub RESERVED0: [u32; 6usize],
    pub COMPEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_cr_bit_t {
    pub SPIMDS: u32,
    pub TXMDS: u32,
    pub RESERVED0: [u32; 1usize],
    pub MSTR: u32,
    pub SPLPBK: u32,
    pub SPLPBK2: u32,
    pub SPE: u32,
    pub CSUSPE: u32,
    pub EIE: u32,
    pub TXIE: u32,
    pub RXIE: u32,
    pub IDIE: u32,
    pub MODFE: u32,
    pub PATE: u32,
    pub PAOE: u32,
    pub PAE: u32,
    pub RESERVED1: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_cfg1_bit_t {
    pub RESERVED0: [u32; 2usize],
    pub CTMDS: u32,
    pub RESERVED1: [u32; 3usize],
    pub SPRDTD: u32,
    pub RESERVED2: [u32; 1usize],
    pub SS0PV: u32,
    pub SS1PV: u32,
    pub SS2PV: u32,
    pub SS3PV: u32,
    pub RESERVED3: [u32; 20usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_sr_bit_t {
    pub OVRERF: u32,
    pub IDLNF: u32,
    pub MODFERF: u32,
    pub PERF: u32,
    pub UDRERF: u32,
    pub TDEF: u32,
    pub RESERVED0: [u32; 1usize],
    pub RDFF: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_cfg2_bit_t {
    pub CPHA: u32,
    pub CPOL: u32,
    pub RESERVED0: [u32; 10usize],
    pub LSBF: u32,
    pub MIDIE: u32,
    pub MSSDLE: u32,
    pub MSSIE: u32,
    pub RESERVED1: [u32; 16usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sramc_ckcr_bit_t {
    pub PYOAD: u32,
    pub RESERVED0: [u32; 15usize],
    pub ECCOAD: u32,
    pub BECCOAD: u32,
    pub RESERVED1: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sramc_ckpr_bit_t {
    pub CKPRC: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sramc_cksr_bit_t {
    pub RESERVED0: [u32; 3usize],
    pub SRAMH_PYERR: u32,
    pub SRAM0_1ERR: u32,
    pub SRAM0_2ERR: u32,
    pub SRAMB_1ERR: u32,
    pub SRAMB_2ERR: u32,
    pub CACHE_PYERR: u32,
    pub RESERVED1: [u32; 23usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sramc_sram0_eien_bit_t {
    pub EIEN: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sramc_sramb_eien_bit_t {
    pub EIEN: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_swdt_cr_bit_t {
    pub RESERVED0: [u32; 16usize],
    pub SLPOFF: u32,
    pub RESERVED1: [u32; 14usize],
    pub ITS: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_swdt_sr_bit_t {
    pub RESERVED0: [u32; 16usize],
    pub UDF: u32,
    pub REF: u32,
    pub RESERVED1: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr0_bconr_bit_t {
    pub CSTA: u32,
    pub CAPMDA: u32,
    pub CMENA: u32,
    pub OVENA: u32,
    pub RESERVED0: [u32; 4usize],
    pub SYNSA: u32,
    pub SYNCLKA: u32,
    pub ASYNCLKA: u32,
    pub RESERVED1: [u32; 1usize],
    pub HSTAA: u32,
    pub HSTPA: u32,
    pub HCLEA: u32,
    pub HICPA: u32,
    pub CSTB: u32,
    pub CAPMDB: u32,
    pub CMENB: u32,
    pub OVENB: u32,
    pub RESERVED2: [u32; 4usize],
    pub SYNSB: u32,
    pub SYNCLKB: u32,
    pub ASYNCLKB: u32,
    pub RESERVED3: [u32; 1usize],
    pub HSTAB: u32,
    pub HSTPB: u32,
    pub HCLEB: u32,
    pub HICPB: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr0_stflr_bit_t {
    pub CMFA: u32,
    pub OVFA: u32,
    pub ICPA: u32,
    pub RESERVED0: [u32; 13usize],
    pub CMFB: u32,
    pub OVFB: u32,
    pub ICPB: u32,
    pub RESERVED1: [u32; 13usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_ocsr_bit_t {
    pub OCEH: u32,
    pub OCEL: u32,
    pub OCPH: u32,
    pub OCPL: u32,
    pub OCIEH: u32,
    pub OCIEL: u32,
    pub OCFH: u32,
    pub OCFL: u32,
    pub RESERVED0: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_ocer_bit_t {
    pub RESERVED0: [u32; 8usize],
    pub LMCH: u32,
    pub LMCL: u32,
    pub LMMH: u32,
    pub LMML: u32,
    pub MCECH: u32,
    pub MCECL: u32,
    pub RESERVED1: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_ocmrh_bit_t {
    pub OCFDCH: u32,
    pub OCFPKH: u32,
    pub OCFUCH: u32,
    pub OCFZRH: u32,
    pub RESERVED0: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_ocmrl_bit_t {
    pub OCFDCL: u32,
    pub OCFPKL: u32,
    pub OCFUCL: u32,
    pub OCFZRL: u32,
    pub RESERVED0: [u32; 28usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_ccsr_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub CLEAR: u32,
    pub MODE: u32,
    pub STOP: u32,
    pub BUFEN: u32,
    pub IRQPEN: u32,
    pub IRQPF: u32,
    pub IRQZEN: u32,
    pub IRQZF: u32,
    pub SYNST: u32,
    pub HST: u32,
    pub RESERVED1: [u32; 1usize],
    pub ECKEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_pscr_bit_t {
    pub OEUH: u32,
    pub OEUL: u32,
    pub OEVH: u32,
    pub OEVL: u32,
    pub OEWH: u32,
    pub OEWL: u32,
    pub OEXH: u32,
    pub OEXL: u32,
    pub MOE: u32,
    pub AOE: u32,
    pub RESERVED0: [u32; 22usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_scsr_bit_t {
    pub RESERVED0: [u32; 5usize],
    pub LMC: u32,
    pub RESERVED1: [u32; 2usize],
    pub EVTMS: u32,
    pub EVTDS: u32,
    pub RESERVED2: [u32; 2usize],
    pub DEN: u32,
    pub PEN: u32,
    pub UEN: u32,
    pub ZEN: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_scmr_bit_t {
    pub RESERVED0: [u32; 6usize],
    pub MZCE: u32,
    pub MPCE: u32,
    pub RESERVED1: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_scer_bit_t {
    pub RESERVED0: [u32; 8usize],
    pub PCTS: u32,
    pub RESERVED1: [u32; 7usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_rcsr_bit_t {
    pub RTIDU: u32,
    pub RTIDV: u32,
    pub RTIDW: u32,
    pub RTIDX: u32,
    pub RTIFU: u32,
    pub RTICU: u32,
    pub RTEU: u32,
    pub RTSU: u32,
    pub RTIFV: u32,
    pub RTICV: u32,
    pub RTEV: u32,
    pub RTSV: u32,
    pub RTIFW: u32,
    pub RTICW: u32,
    pub RTEW: u32,
    pub RTSW: u32,
    pub RTIFX: u32,
    pub RTICX: u32,
    pub RTEX: u32,
    pub RTSX: u32,
    pub RESERVED0: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_scir_bit_t {
    pub ITEN0: u32,
    pub ITEN1: u32,
    pub ITEN2: u32,
    pub ITEN3: u32,
    pub ITEN4: u32,
    pub ITEN5: u32,
    pub ITEN6: u32,
    pub ITEN7: u32,
    pub RESERVED0: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_scfr_bit_t {
    pub SF0: u32,
    pub SF1: u32,
    pub SF2: u32,
    pub SF3: u32,
    pub SF4: u32,
    pub SF5: u32,
    pub SF6: u32,
    pub SF7: u32,
    pub RESERVED0: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_gconr_bit_t {
    pub START: u32,
    pub DIR: u32,
    pub MODE: u32,
    pub RESERVED0: [u32; 5usize],
    pub OVSTP: u32,
    pub RESERVED1: [u32; 7usize],
    pub ZMSKREV: u32,
    pub ZMSKPOS: u32,
    pub RESERVED2: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_iconr_bit_t {
    pub INTENA: u32,
    pub INTENB: u32,
    pub INTENC: u32,
    pub INTEND: u32,
    pub INTENE: u32,
    pub INTENF: u32,
    pub INTENOVF: u32,
    pub INTENUDF: u32,
    pub INTENDTE: u32,
    pub RESERVED0: [u32; 7usize],
    pub INTENSAU: u32,
    pub INTENSAD: u32,
    pub INTENSBU: u32,
    pub INTENSBD: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_bconr_bit_t {
    pub BENA: u32,
    pub BSEA: u32,
    pub BTRUA: u32,
    pub BTRDA: u32,
    pub BENB: u32,
    pub BSEB: u32,
    pub BTRUB: u32,
    pub BTRDB: u32,
    pub BENP: u32,
    pub BSEP: u32,
    pub BTRUP: u32,
    pub BTRDP: u32,
    pub RESERVED0: [u32; 4usize],
    pub BENSPA: u32,
    pub BSESPA: u32,
    pub BTRUSPA: u32,
    pub BTRDSPA: u32,
    pub BENSPB: u32,
    pub BSESPB: u32,
    pub BTRUSPB: u32,
    pub BTRDSPB: u32,
    pub RESERVED1: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_dconr_bit_t {
    pub DTCEN: u32,
    pub SEPA: u32,
    pub RESERVED0: [u32; 2usize],
    pub DTBENU: u32,
    pub DTBEND: u32,
    pub DTBTRU: u32,
    pub DTBTRD: u32,
    pub RESERVED1: [u32; 24usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_pcnar_bit_t {
    pub RESERVED0: [u32; 28usize],
    pub OUTENA: u32,
    pub RESERVED1: [u32; 2usize],
    pub CAPMDA: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_pcnbr_bit_t {
    pub RESERVED0: [u32; 28usize],
    pub OUTENB: u32,
    pub RESERVED1: [u32; 2usize],
    pub CAPMDB: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_fcngr_bit_t {
    pub NOFIENGA: u32,
    pub RESERVED0: [u32; 3usize],
    pub NOFIENGB: u32,
    pub RESERVED1: [u32; 27usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_vperr_bit_t {
    pub RESERVED0: [u32; 8usize],
    pub SPPERIA: u32,
    pub SPPERIB: u32,
    pub RESERVED1: [u32; 22usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_stflr_bit_t {
    pub CMAF: u32,
    pub CMBF: u32,
    pub CMCF: u32,
    pub CMDF: u32,
    pub CMEF: u32,
    pub CMFF: u32,
    pub OVFF: u32,
    pub UDFF: u32,
    pub DTEF: u32,
    pub CMSAUF: u32,
    pub CMSADF: u32,
    pub CMSBUF: u32,
    pub CMSBDF: u32,
    pub RESERVED0: [u32; 13usize],
    pub CMAF2: u32,
    pub CMBF2: u32,
    pub RESERVED1: [u32; 3usize],
    pub DIRF: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hstar_bit_t {
    pub HSTA0: u32,
    pub HSTA1: u32,
    pub HSTA2: u32,
    pub HSTA3: u32,
    pub RESERVED0: [u32; 3usize],
    pub STAS: u32,
    pub HSTA8: u32,
    pub HSTA9: u32,
    pub RESERVED1: [u32; 6usize],
    pub HSTA16: u32,
    pub HSTA17: u32,
    pub HSTA18: u32,
    pub HSTA19: u32,
    pub RESERVED2: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hstpr_bit_t {
    pub HSTP0: u32,
    pub HSTP1: u32,
    pub HSTP2: u32,
    pub HSTP3: u32,
    pub RESERVED0: [u32; 3usize],
    pub STPS: u32,
    pub HSTP8: u32,
    pub HSTP9: u32,
    pub RESERVED1: [u32; 6usize],
    pub HSTP16: u32,
    pub HSTP17: u32,
    pub HSTP18: u32,
    pub HSTP19: u32,
    pub RESERVED2: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hclrr_bit_t {
    pub HCLE0: u32,
    pub HCLE1: u32,
    pub HCLE2: u32,
    pub HCLE3: u32,
    pub RESERVED0: [u32; 3usize],
    pub CLES: u32,
    pub HCLE8: u32,
    pub HCLE9: u32,
    pub RESERVED1: [u32; 6usize],
    pub HCLE16: u32,
    pub HCLE17: u32,
    pub HCLE18: u32,
    pub HCLE19: u32,
    pub RESERVED2: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hupdr_bit_t {
    pub HUPD0: u32,
    pub HUPD1: u32,
    pub HUPD2: u32,
    pub HUPD3: u32,
    pub RESERVED0: [u32; 3usize],
    pub UPDS: u32,
    pub HUPD8: u32,
    pub HUPD9: u32,
    pub RESERVED1: [u32; 6usize],
    pub HUPD16: u32,
    pub HUPD17: u32,
    pub HUPD18: u32,
    pub HUPD19: u32,
    pub RESERVED2: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hcpar_bit_t {
    pub HCPA0: u32,
    pub HCPA1: u32,
    pub HCPA2: u32,
    pub HCPA3: u32,
    pub RESERVED0: [u32; 4usize],
    pub HCPA8: u32,
    pub HCPA9: u32,
    pub RESERVED1: [u32; 6usize],
    pub HCPA16: u32,
    pub HCPA17: u32,
    pub HCPA18: u32,
    pub HCPA19: u32,
    pub RESERVED2: [u32; 4usize],
    pub HCPA24: u32,
    pub HCPA25: u32,
    pub RESERVED3: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hcpbr_bit_t {
    pub HCPB0: u32,
    pub HCPB1: u32,
    pub HCPB2: u32,
    pub HCPB3: u32,
    pub RESERVED0: [u32; 4usize],
    pub HCPB8: u32,
    pub HCPB9: u32,
    pub RESERVED1: [u32; 6usize],
    pub HCPB16: u32,
    pub HCPB17: u32,
    pub HCPB18: u32,
    pub HCPB19: u32,
    pub RESERVED2: [u32; 4usize],
    pub HCPB24: u32,
    pub HCPB25: u32,
    pub RESERVED3: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hcupr_bit_t {
    pub HCUP0: u32,
    pub HCUP1: u32,
    pub HCUP2: u32,
    pub HCUP3: u32,
    pub HCUP4: u32,
    pub HCUP5: u32,
    pub HCUP6: u32,
    pub HCUP7: u32,
    pub HCUP8: u32,
    pub HCUP9: u32,
    pub RESERVED0: [u32; 6usize],
    pub HCUP16: u32,
    pub HCUP17: u32,
    pub HCUP18: u32,
    pub HCUP19: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_hcdor_bit_t {
    pub HCDO0: u32,
    pub HCDO1: u32,
    pub HCDO2: u32,
    pub HCDO3: u32,
    pub HCDO4: u32,
    pub HCDO5: u32,
    pub HCDO6: u32,
    pub HCDO7: u32,
    pub HCDO8: u32,
    pub HCDO9: u32,
    pub RESERVED0: [u32; 6usize],
    pub HCDO16: u32,
    pub HCDO17: u32,
    pub HCDO18: u32,
    pub HCDO19: u32,
    pub RESERVED1: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_common_fcntr_bit_t {
    pub NOFIENTA: u32,
    pub RESERVED0: [u32; 3usize],
    pub NOFIENTB: u32,
    pub RESERVED1: [u32; 27usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_common_sstar_bit_t {
    pub SSTA1: u32,
    pub SSTA2: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_common_sstpr_bit_t {
    pub SSTP1: u32,
    pub SSTP2: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_common_sclrr_bit_t {
    pub SCLE1: u32,
    pub SCLE2: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_common_supdr_bit_t {
    pub SUPD1: u32,
    pub SUPD2: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_bcstrl_bit_t {
    pub START: u32,
    pub DIR: u32,
    pub MODE: u32,
    pub SYNST: u32,
    pub RESERVED0: [u32; 4usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_bcstrh_bit_t {
    pub OVSTP: u32,
    pub RESERVED0: [u32; 3usize],
    pub ITENOVF: u32,
    pub ITENUDF: u32,
    pub OVFF: u32,
    pub UDFF: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_hconr_bit_t {
    pub HSTA0: u32,
    pub HSTA1: u32,
    pub HSTA2: u32,
    pub RESERVED0: [u32; 1usize],
    pub HSTP0: u32,
    pub HSTP1: u32,
    pub HSTP2: u32,
    pub RESERVED1: [u32; 1usize],
    pub HCLE0: u32,
    pub HCLE1: u32,
    pub HCLE2: u32,
    pub RESERVED2: [u32; 1usize],
    pub HCLE3: u32,
    pub HCLE4: u32,
    pub HCLE5: u32,
    pub HCLE6: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_hcupr_bit_t {
    pub HCUP0: u32,
    pub HCUP1: u32,
    pub HCUP2: u32,
    pub HCUP3: u32,
    pub HCUP4: u32,
    pub HCUP5: u32,
    pub HCUP6: u32,
    pub HCUP7: u32,
    pub HCUP8: u32,
    pub HCUP9: u32,
    pub HCUP10: u32,
    pub HCUP11: u32,
    pub HCUP12: u32,
    pub RESERVED0: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_hcdor_bit_t {
    pub HCDO0: u32,
    pub HCDO1: u32,
    pub HCDO2: u32,
    pub HCDO3: u32,
    pub HCDO4: u32,
    pub HCDO5: u32,
    pub HCDO6: u32,
    pub HCDO7: u32,
    pub HCDO8: u32,
    pub HCDO9: u32,
    pub HCDO10: u32,
    pub HCDO11: u32,
    pub HCDO12: u32,
    pub RESERVED0: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_iconr_bit_t {
    pub ITEN1: u32,
    pub ITEN2: u32,
    pub ITEN3: u32,
    pub ITEN4: u32,
    pub ITEN5: u32,
    pub ITEN6: u32,
    pub ITEN7: u32,
    pub ITEN8: u32,
    pub RESERVED0: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_econr_bit_t {
    pub ETEN1: u32,
    pub ETEN2: u32,
    pub ETEN3: u32,
    pub ETEN4: u32,
    pub ETEN5: u32,
    pub ETEN6: u32,
    pub ETEN7: u32,
    pub ETEN8: u32,
    pub RESERVED0: [u32; 8usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_fconr_bit_t {
    pub NOFIENTG: u32,
    pub RESERVED0: [u32; 7usize],
    pub NOFIENCA: u32,
    pub RESERVED1: [u32; 3usize],
    pub NOFIENCB: u32,
    pub RESERVED2: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_stflr_bit_t {
    pub CMPF1: u32,
    pub CMPF2: u32,
    pub CMPF3: u32,
    pub CMPF4: u32,
    pub CMPF5: u32,
    pub CMPF6: u32,
    pub CMPF7: u32,
    pub CMPF8: u32,
    pub ICPF1: u32,
    pub ICPF2: u32,
    pub ICPF3: u32,
    pub ICPF4: u32,
    pub ICPF5: u32,
    pub ICPF6: u32,
    pub ICPF7: u32,
    pub ICPF8: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_bconr_bit_t {
    pub BEN: u32,
    pub BSE0: u32,
    pub BSE1: u32,
    pub BSEN: u32,
    pub RESERVED0: [u32; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_cconr_bit_t {
    pub CAPMD: u32,
    pub RESERVED0: [u32; 3usize],
    pub HICP0: u32,
    pub HICP1: u32,
    pub HICP2: u32,
    pub RESERVED1: [u32; 1usize],
    pub HICP3: u32,
    pub HICP4: u32,
    pub HICP5: u32,
    pub HICP6: u32,
    pub NOFIENCP: u32,
    pub RESERVED2: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_pconr_bit_t {
    pub RESERVED0: [u32; 12usize],
    pub OUTEN: u32,
    pub RESERVED1: [u32; 3usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_trng_cr_bit_t {
    pub EN: u32,
    pub RUN: u32,
    pub RESERVED0: [u32; 30usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_trng_mr_bit_t {
    pub LOAD: u32,
    pub RESERVED0: [u32; 31usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_sr_bit_t {
    pub PE: u32,
    pub FE: u32,
    pub RESERVED0: [u32; 1usize],
    pub ORE: u32,
    pub BE: u32,
    pub RXNE: u32,
    pub TC: u32,
    pub TXE: u32,
    pub RTOF: u32,
    pub WKUP: u32,
    pub LBD: u32,
    pub TEND: u32,
    pub RESERVED1: [u32; 4usize],
    pub MPB: u32,
    pub RESERVED2: [u32; 15usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_tdr_bit_t {
    pub RESERVED0: [u32; 9usize],
    pub MPID: u32,
    pub RESERVED1: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_cr1_bit_t {
    pub RTOE: u32,
    pub RTOIE: u32,
    pub RE: u32,
    pub TE: u32,
    pub SLME: u32,
    pub RIE: u32,
    pub TCIE: u32,
    pub TXEIE: u32,
    pub TENDIE: u32,
    pub PS: u32,
    pub PCE: u32,
    pub RESERVED0: [u32; 1usize],
    pub M: u32,
    pub RESERVED1: [u32; 2usize],
    pub OVER8: u32,
    pub CPE: u32,
    pub CFE: u32,
    pub RESERVED2: [u32; 1usize],
    pub CORE: u32,
    pub CRTOF: u32,
    pub CBE: u32,
    pub CWKUP: u32,
    pub CLBD: u32,
    pub MS: u32,
    pub CTEND: u32,
    pub RESERVED3: [u32; 2usize],
    pub ML: u32,
    pub FBME: u32,
    pub NFE: u32,
    pub SBS: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_cr2_bit_t {
    pub MPE: u32,
    pub WKUPIE: u32,
    pub BEIE: u32,
    pub BEE: u32,
    pub LBDIE: u32,
    pub LBDL: u32,
    pub RESERVED0: [u32; 2usize],
    pub WKUPE: u32,
    pub RESERVED1: [u32; 4usize],
    pub STOP: u32,
    pub LINEN: u32,
    pub RESERVED2: [u32; 1usize],
    pub SBK: u32,
    pub SBKM: u32,
    pub RESERVED3: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_cr3_bit_t {
    pub RESERVED0: [u32; 3usize],
    pub HDSEL: u32,
    pub LOOP: u32,
    pub SCEN: u32,
    pub RESERVED1: [u32; 2usize],
    pub RTSE: u32,
    pub CTSE: u32,
    pub RESERVED2: [u32; 22usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_pr_bit_t {
    pub RESERVED0: [u32; 4usize],
    pub ULBREN: u32,
    pub RESERVED1: [u32; 27usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_wdt_cr_bit_t {
    pub RESERVED0: [u32; 16usize],
    pub SLPOFF: u32,
    pub RESERVED1: [u32; 14usize],
    pub ITS: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_wdt_sr_bit_t {
    pub RESERVED0: [u32; 16usize],
    pub UDF: u32,
    pub REF: u32,
    pub RESERVED1: [u32; 14usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_ADC_TypeDef {
    pub STR_b: stc_adc_str_bit_t,
    pub RESERVED0: [u32; 8usize],
    pub CR0_b: stc_adc_cr0_bit_t,
    pub CR1_b: stc_adc_cr1_bit_t,
    pub CR2_b: stc_adc_cr2_bit_t,
    pub RESERVED1: [u32; 16usize],
    pub TRGSR_b: stc_adc_trgsr_bit_t,
    pub RESERVED2: [u32; 96usize],
    pub EXCHSELR_b: stc_adc_exchselr_bit_t,
    pub RESERVED3: [u32; 344usize],
    pub ISR_b: stc_adc_isr_bit_t,
    pub ICR_b: stc_adc_icr_bit_t,
    pub ISCLRR_b: stc_adc_isclrr_bit_t,
    pub RESERVED4: [u32; 40usize],
    pub SYNCCR_b: stc_adc_synccr_bit_t,
    pub RESERVED5: [u32; 656usize],
    pub AWDCR_b: stc_adc_awdcr_bit_t,
    pub AWDSR_b: stc_adc_awdsr_bit_t,
    pub AWDSCLRR_b: stc_adc_awdsclrr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_AES_TypeDef {
    pub CR_b: stc_aes_cr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_AOS_TypeDef {
    pub INTSFTTRG_b: stc_aos_intsfttrg_bit_t,
    pub RESERVED0: [u32; 2912usize],
    pub PEVNTNFCR_b: stc_aos_pevntnfcr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_CMP_TypeDef {
    pub MDR_b: stc_cmp_mdr_bit_t,
    pub FIR_b: stc_cmp_fir_bit_t,
    pub OCR_b: stc_cmp_ocr_bit_t,
    pub RESERVED0: [u32; 104usize],
    pub BWSR1_b: stc_cmp_bwsr1_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_CMU_TypeDef {
    pub RESERVED0: [u32; 224usize],
    pub XTALDIVCR_b: stc_cmu_xtaldivcr_bit_t,
    pub RESERVED1: [u32; 156032usize],
    pub XTALCFGR_b: stc_cmu_xtalcfgr_bit_t,
    pub RESERVED2: [u32; 24usize],
    pub XTAL32CR_b: stc_cmu_xtal32cr_bit_t,
    pub RESERVED3: [u32; 184usize],
    pub LRCCR_b: stc_cmu_lrccr_bit_t,
    pub RESERVED4: [u32; 237032usize],
    pub PLLHCR_b: stc_cmu_pllhcr_bit_t,
    pub RESERVED5: [u32; 56usize],
    pub XTALCR_b: stc_cmu_xtalcr_bit_t,
    pub RESERVED6: [u32; 24usize],
    pub HRCCR_b: stc_cmu_hrccr_bit_t,
    pub RESERVED7: [u32; 8usize],
    pub MRCCR_b: stc_cmu_mrccr_bit_t,
    pub RESERVED8: [u32; 24usize],
    pub OSCSTBSR_b: stc_cmu_oscstbsr_bit_t,
    pub MCO1CFGR_b: stc_cmu_mcocfgr_bit_t,
    pub MCO2CFGR_b: stc_cmu_mcocfgr_bit_t,
    pub TPIUCKCFGR_b: stc_cmu_tpiuckcfgr_bit_t,
    pub XTALSTDCR_b: stc_cmu_xtalstdcr_bit_t,
    pub XTALSTDSR_b: stc_cmu_xtalstdsr_bit_t,
    pub RESERVED9: [u32; 1520usize],
    pub PLLHCFGR_b: stc_cmu_pllhcfgr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_CRC_TypeDef {
    pub CR_b: stc_crc_cr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_CTC_TypeDef {
    pub CR1_b: stc_ctc_cr1_bit_t,
    pub RESERVED0: [u32; 32usize],
    pub STR_b: stc_ctc_str_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_DAC_TypeDef {
    pub DADR1_b: stc_dac_dadr1_bit_t,
    pub DADR2_b: stc_dac_dadr2_bit_t,
    pub DACR_b: stc_dac_dacr_bit_t,
    pub DAADPCR_b: stc_dac_daadpcr_bit_t,
    pub RESERVED0: [u32; 160usize],
    pub DAOCR_b: stc_dac_daocr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_DCU_TypeDef {
    pub CTL_b: stc_dcu_ctl_bit_t,
    pub FLAG_b: stc_dcu_flag_bit_t,
    pub RESERVED0: [u32; 96usize],
    pub FLAGCLR_b: stc_dcu_flagclr_bit_t,
    pub INTEVTSEL_b: stc_dcu_intevtsel_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_DMA_TypeDef {
    pub EN_b: stc_dma_en_bit_t,
    pub INTSTAT0_b: stc_dma_intstat0_bit_t,
    pub INTSTAT1_b: stc_dma_intstat1_bit_t,
    pub INTMASK0_b: stc_dma_intmask0_bit_t,
    pub INTMASK1_b: stc_dma_intmask1_bit_t,
    pub INTCLR0_b: stc_dma_intclr0_bit_t,
    pub INTCLR1_b: stc_dma_intclr1_bit_t,
    pub RESERVED0: [u32; 32usize],
    pub REQSTAT_b: stc_dma_reqstat_bit_t,
    pub CHSTAT_b: stc_dma_chstat_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub RCFGCTL_b: stc_dma_rcfgctl_bit_t,
    pub SWREQ_b: stc_dma_swreq_bit_t,
    pub RESERVED2: [u32; 320usize],
    pub CHCTL0_b: stc_dma_chctl_bit_t,
    pub RESERVED3: [u32; 480usize],
    pub CHCTL1_b: stc_dma_chctl_bit_t,
    pub RESERVED4: [u32; 480usize],
    pub CHCTL2_b: stc_dma_chctl_bit_t,
    pub RESERVED5: [u32; 480usize],
    pub CHCTL3_b: stc_dma_chctl_bit_t,
    pub RESERVED6: [u32; 480usize],
    pub CHCTL4_b: stc_dma_chctl_bit_t,
    pub RESERVED7: [u32; 480usize],
    pub CHCTL5_b: stc_dma_chctl_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_EFM_TypeDef {
    pub RESERVED0: [u32; 160usize],
    pub FSTP_b: stc_efm_fstp_bit_t,
    pub FRMC_b: stc_efm_frmc_bit_t,
    pub FWMC_b: stc_efm_fwmc_bit_t,
    pub FSR_b: stc_efm_fsr_bit_t,
    pub FSCLR_b: stc_efm_fsclr_bit_t,
    pub FITE_b: stc_efm_fite_bit_t,
    pub FSWP_b: stc_efm_fswp_bit_t,
    pub RESERVED1: [u32; 1696usize],
    pub MMF_REMCR0_b: stc_efm_mmf_remcr_bit_t,
    pub MMF_REMCR1_b: stc_efm_mmf_remcr_bit_t,
    pub RESERVED2: [u32; 928usize],
    pub WLOCK_b: stc_efm_wlock_bit_t,
    pub RESERVED3: [u32; 96usize],
    pub F0NWPRT_b: stc_efm_f0nwprt_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_EMB_TypeDef {
    pub CTL1_b: stc_emb_ctl1_bit_t,
    pub CTL2_b: stc_emb_ctl2_bit_t,
    pub SOE_b: stc_emb_soe_bit_t,
    pub STAT_b: stc_emb_stat_bit_t,
    pub STATCLR_b: stc_emb_statclr_bit_t,
    pub INTEN_b: stc_emb_inten_bit_t,
    pub RLSSEL_b: stc_emb_rlssel_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_FCM_TypeDef {
    pub RESERVED0: [u32; 96usize],
    pub STR_b: stc_fcm_str_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub RCCR_b: stc_fcm_rccr_bit_t,
    pub RIER_b: stc_fcm_rier_bit_t,
    pub SR_b: stc_fcm_sr_bit_t,
    pub CLR_b: stc_fcm_clr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_GPIO_TypeDef {
    pub PIDRA_b: stc_gpio_pidr_bit_t,
    pub RESERVED0: [u32; 16usize],
    pub PODRA_b: stc_gpio_podr_bit_t,
    pub POERA_b: stc_gpio_poer_bit_t,
    pub POSRA_b: stc_gpio_posr_bit_t,
    pub PORRA_b: stc_gpio_porr_bit_t,
    pub POTRA_b: stc_gpio_potr_bit_t,
    pub RESERVED1: [u32; 16usize],
    pub PIDRB_b: stc_gpio_pidr_bit_t,
    pub RESERVED2: [u32; 16usize],
    pub PODRB_b: stc_gpio_podr_bit_t,
    pub POERB_b: stc_gpio_poer_bit_t,
    pub POSRB_b: stc_gpio_posr_bit_t,
    pub PORRB_b: stc_gpio_porr_bit_t,
    pub POTRB_b: stc_gpio_potr_bit_t,
    pub RESERVED3: [u32; 16usize],
    pub PIDRC_b: stc_gpio_pidr_bit_t,
    pub RESERVED4: [u32; 16usize],
    pub PODRC_b: stc_gpio_podr_bit_t,
    pub POERC_b: stc_gpio_poer_bit_t,
    pub POSRC_b: stc_gpio_posr_bit_t,
    pub PORRC_b: stc_gpio_porr_bit_t,
    pub POTRC_b: stc_gpio_potr_bit_t,
    pub RESERVED5: [u32; 16usize],
    pub PIDRD_b: stc_gpio_pidr_bit_t,
    pub RESERVED6: [u32; 16usize],
    pub PODRD_b: stc_gpio_podr_bit_t,
    pub POERD_b: stc_gpio_poer_bit_t,
    pub POSRD_b: stc_gpio_posr_bit_t,
    pub PORRD_b: stc_gpio_porr_bit_t,
    pub POTRD_b: stc_gpio_potr_bit_t,
    pub RESERVED7: [u32; 16usize],
    pub PIDRE_b: stc_gpio_pidr_bit_t,
    pub RESERVED8: [u32; 16usize],
    pub PODRE_b: stc_gpio_podr_bit_t,
    pub POERE_b: stc_gpio_poer_bit_t,
    pub POSRE_b: stc_gpio_posr_bit_t,
    pub PORRE_b: stc_gpio_porr_bit_t,
    pub POTRE_b: stc_gpio_potr_bit_t,
    pub RESERVED9: [u32; 16usize],
    pub PIDRH_b: stc_gpio_pidr_bit_t,
    pub RESERVED10: [u32; 16usize],
    pub PODRH_b: stc_gpio_podr_bit_t,
    pub POERH_b: stc_gpio_poer_bit_t,
    pub POSRH_b: stc_gpio_posr_bit_t,
    pub PORRH_b: stc_gpio_porr_bit_t,
    pub POTRH_b: stc_gpio_potr_bit_t,
    pub RESERVED11: [u32; 7408usize],
    pub PWPR_b: stc_gpio_pwpr_bit_t,
    pub RESERVED12: [u32; 16usize],
    pub PCRA0_b: stc_gpio_pcr_bit_t,
    pub PFSRA0_b: stc_gpio_pfsr_bit_t,
    pub PCRA1_b: stc_gpio_pcr_bit_t,
    pub PFSRA1_b: stc_gpio_pfsr_bit_t,
    pub PCRA2_b: stc_gpio_pcr_bit_t,
    pub PFSRA2_b: stc_gpio_pfsr_bit_t,
    pub PCRA3_b: stc_gpio_pcr_bit_t,
    pub PFSRA3_b: stc_gpio_pfsr_bit_t,
    pub PCRA4_b: stc_gpio_pcr_bit_t,
    pub PFSRA4_b: stc_gpio_pfsr_bit_t,
    pub PCRA5_b: stc_gpio_pcr_bit_t,
    pub PFSRA5_b: stc_gpio_pfsr_bit_t,
    pub PCRA6_b: stc_gpio_pcr_bit_t,
    pub PFSRA6_b: stc_gpio_pfsr_bit_t,
    pub PCRA7_b: stc_gpio_pcr_bit_t,
    pub PFSRA7_b: stc_gpio_pfsr_bit_t,
    pub PCRA8_b: stc_gpio_pcr_bit_t,
    pub PFSRA8_b: stc_gpio_pfsr_bit_t,
    pub PCRA9_b: stc_gpio_pcr_bit_t,
    pub PFSRA9_b: stc_gpio_pfsr_bit_t,
    pub PCRA10_b: stc_gpio_pcr_bit_t,
    pub PFSRA10_b: stc_gpio_pfsr_bit_t,
    pub PCRA11_b: stc_gpio_pcr_bit_t,
    pub PFSRA11_b: stc_gpio_pfsr_bit_t,
    pub PCRA12_b: stc_gpio_pcr_bit_t,
    pub PFSRA12_b: stc_gpio_pfsr_bit_t,
    pub PCRA13_b: stc_gpio_pcr_bit_t,
    pub PFSRA13_b: stc_gpio_pfsr_bit_t,
    pub PCRA14_b: stc_gpio_pcr_bit_t,
    pub PFSRA14_b: stc_gpio_pfsr_bit_t,
    pub PCRA15_b: stc_gpio_pcr_bit_t,
    pub PFSRA15_b: stc_gpio_pfsr_bit_t,
    pub PCRB0_b: stc_gpio_pcr_bit_t,
    pub PFSRB0_b: stc_gpio_pfsr_bit_t,
    pub PCRB1_b: stc_gpio_pcr_bit_t,
    pub PFSRB1_b: stc_gpio_pfsr_bit_t,
    pub PCRB2_b: stc_gpio_pcr_bit_t,
    pub PFSRB2_b: stc_gpio_pfsr_bit_t,
    pub PCRB3_b: stc_gpio_pcr_bit_t,
    pub PFSRB3_b: stc_gpio_pfsr_bit_t,
    pub PCRB4_b: stc_gpio_pcr_bit_t,
    pub PFSRB4_b: stc_gpio_pfsr_bit_t,
    pub PCRB5_b: stc_gpio_pcr_bit_t,
    pub PFSRB5_b: stc_gpio_pfsr_bit_t,
    pub PCRB6_b: stc_gpio_pcr_bit_t,
    pub PFSRB6_b: stc_gpio_pfsr_bit_t,
    pub PCRB7_b: stc_gpio_pcr_bit_t,
    pub PFSRB7_b: stc_gpio_pfsr_bit_t,
    pub PCRB8_b: stc_gpio_pcr_bit_t,
    pub PFSRB8_b: stc_gpio_pfsr_bit_t,
    pub PCRB9_b: stc_gpio_pcr_bit_t,
    pub PFSRB9_b: stc_gpio_pfsr_bit_t,
    pub PCRB10_b: stc_gpio_pcr_bit_t,
    pub PFSRB10_b: stc_gpio_pfsr_bit_t,
    pub PCRB11_b: stc_gpio_pcr_bit_t,
    pub PFSRB11_b: stc_gpio_pfsr_bit_t,
    pub PCRB12_b: stc_gpio_pcr_bit_t,
    pub PFSRB12_b: stc_gpio_pfsr_bit_t,
    pub PCRB13_b: stc_gpio_pcr_bit_t,
    pub PFSRB13_b: stc_gpio_pfsr_bit_t,
    pub PCRB14_b: stc_gpio_pcr_bit_t,
    pub PFSRB14_b: stc_gpio_pfsr_bit_t,
    pub PCRB15_b: stc_gpio_pcr_bit_t,
    pub PFSRB15_b: stc_gpio_pfsr_bit_t,
    pub PCRC0_b: stc_gpio_pcr_bit_t,
    pub PFSRC0_b: stc_gpio_pfsr_bit_t,
    pub PCRC1_b: stc_gpio_pcr_bit_t,
    pub PFSRC1_b: stc_gpio_pfsr_bit_t,
    pub PCRC2_b: stc_gpio_pcr_bit_t,
    pub PFSRC2_b: stc_gpio_pfsr_bit_t,
    pub PCRC3_b: stc_gpio_pcr_bit_t,
    pub PFSRC3_b: stc_gpio_pfsr_bit_t,
    pub PCRC4_b: stc_gpio_pcr_bit_t,
    pub PFSRC4_b: stc_gpio_pfsr_bit_t,
    pub PCRC5_b: stc_gpio_pcr_bit_t,
    pub PFSRC5_b: stc_gpio_pfsr_bit_t,
    pub PCRC6_b: stc_gpio_pcr_bit_t,
    pub PFSRC6_b: stc_gpio_pfsr_bit_t,
    pub PCRC7_b: stc_gpio_pcr_bit_t,
    pub PFSRC7_b: stc_gpio_pfsr_bit_t,
    pub PCRC8_b: stc_gpio_pcr_bit_t,
    pub PFSRC8_b: stc_gpio_pfsr_bit_t,
    pub PCRC9_b: stc_gpio_pcr_bit_t,
    pub PFSRC9_b: stc_gpio_pfsr_bit_t,
    pub PCRC10_b: stc_gpio_pcr_bit_t,
    pub PFSRC10_b: stc_gpio_pfsr_bit_t,
    pub PCRC11_b: stc_gpio_pcr_bit_t,
    pub PFSRC11_b: stc_gpio_pfsr_bit_t,
    pub PCRC12_b: stc_gpio_pcr_bit_t,
    pub PFSRC12_b: stc_gpio_pfsr_bit_t,
    pub PCRC13_b: stc_gpio_pcr_bit_t,
    pub PFSRC13_b: stc_gpio_pfsr_bit_t,
    pub PCRC14_b: stc_gpio_pcr_bit_t,
    pub PFSRC14_b: stc_gpio_pfsr_bit_t,
    pub PCRC15_b: stc_gpio_pcr_bit_t,
    pub PFSRC15_b: stc_gpio_pfsr_bit_t,
    pub PCRD0_b: stc_gpio_pcr_bit_t,
    pub PFSRD0_b: stc_gpio_pfsr_bit_t,
    pub PCRD1_b: stc_gpio_pcr_bit_t,
    pub PFSRD1_b: stc_gpio_pfsr_bit_t,
    pub PCRD2_b: stc_gpio_pcr_bit_t,
    pub PFSRD2_b: stc_gpio_pfsr_bit_t,
    pub RESERVED13: [u32; 160usize],
    pub PCRD8_b: stc_gpio_pcr_bit_t,
    pub PFSRD8_b: stc_gpio_pfsr_bit_t,
    pub PCRD9_b: stc_gpio_pcr_bit_t,
    pub PFSRD9_b: stc_gpio_pfsr_bit_t,
    pub PCRD10_b: stc_gpio_pcr_bit_t,
    pub PFSRD10_b: stc_gpio_pfsr_bit_t,
    pub PCRD11_b: stc_gpio_pcr_bit_t,
    pub PFSRD11_b: stc_gpio_pfsr_bit_t,
    pub RESERVED14: [u32; 128usize],
    pub PCRE0_b: stc_gpio_pcr_bit_t,
    pub PFSRE0_b: stc_gpio_pfsr_bit_t,
    pub PCRE1_b: stc_gpio_pcr_bit_t,
    pub PFSRE1_b: stc_gpio_pfsr_bit_t,
    pub PCRE2_b: stc_gpio_pcr_bit_t,
    pub PFSRE2_b: stc_gpio_pfsr_bit_t,
    pub PCRE3_b: stc_gpio_pcr_bit_t,
    pub PFSRE3_b: stc_gpio_pfsr_bit_t,
    pub PCRE4_b: stc_gpio_pcr_bit_t,
    pub PFSRE4_b: stc_gpio_pfsr_bit_t,
    pub RESERVED15: [u32; 224usize],
    pub PCRE12_b: stc_gpio_pcr_bit_t,
    pub PFSRE12_b: stc_gpio_pfsr_bit_t,
    pub PCRE13_b: stc_gpio_pcr_bit_t,
    pub PFSRE13_b: stc_gpio_pfsr_bit_t,
    pub PCRE14_b: stc_gpio_pcr_bit_t,
    pub PFSRE14_b: stc_gpio_pfsr_bit_t,
    pub PCRE15_b: stc_gpio_pcr_bit_t,
    pub PFSRE15_b: stc_gpio_pfsr_bit_t,
    pub PCRH0_b: stc_gpio_pcr_bit_t,
    pub PFSRH0_b: stc_gpio_pfsr_bit_t,
    pub PCRH1_b: stc_gpio_pcr_bit_t,
    pub PFSRH1_b: stc_gpio_pfsr_bit_t,
    pub PCRH2_b: stc_gpio_pcr_bit_t,
    pub PFSRH2_b: stc_gpio_pfsr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_HASH_TypeDef {
    pub CR_b: stc_hash_cr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_I2C_TypeDef {
    pub CR1_b: stc_i2c_cr1_bit_t,
    pub CR2_b: stc_i2c_cr2_bit_t,
    pub CR3_b: stc_i2c_cr3_bit_t,
    pub CR4_b: stc_i2c_cr4_bit_t,
    pub SLR0_b: stc_i2c_slr0_bit_t,
    pub SLR1_b: stc_i2c_slr1_bit_t,
    pub RESERVED0: [u32; 32usize],
    pub SR_b: stc_i2c_sr_bit_t,
    pub CLR_b: stc_i2c_clr_bit_t,
    pub RESERVED1: [u32; 96usize],
    pub FLTR_b: stc_i2c_fltr_bit_t,
    pub FSTR_b: stc_i2c_fstr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_ICG_TypeDef {
    pub ICG0_b: stc_icg_icg0_bit_t,
    pub ICG1_b: stc_icg_icg1_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_INTC_TypeDef {
    pub RESERVED0: [u32; 32usize],
    pub NMIER_b: stc_intc_nmier_bit_t,
    pub NMIFR_b: stc_intc_nmifr_bit_t,
    pub NMIFCR_b: stc_intc_nmifcr_bit_t,
    pub EIRQCR0_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR1_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR2_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR3_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR4_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR5_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR6_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR7_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR8_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR9_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR10_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR11_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR12_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR13_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR14_b: stc_intc_eirqcr_bit_t,
    pub EIRQCR15_b: stc_intc_eirqcr_bit_t,
    pub WKEN_b: stc_intc_wken_bit_t,
    pub EIFR_b: stc_intc_eifr_bit_t,
    pub EIFCR_b: stc_intc_eifcr_bit_t,
    pub RESERVED1: [u32; 1024usize],
    pub SWIER_b: stc_intc_swier_bit_t,
    pub EVTER_b: stc_intc_evter_bit_t,
    pub IER_b: stc_intc_ier_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_KEYSCAN_TypeDef {
    pub RESERVED0: [u32; 32usize],
    pub SER_b: stc_keyscan_ser_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_MCAN_TypeDef {
    pub RESERVED0: [u32; 96usize],
    pub DBTP_b: stc_mcan_dbtp_bit_t,
    pub TEST_b: stc_mcan_test_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub CCCR_b: stc_mcan_cccr_bit_t,
    pub RESERVED2: [u32; 96usize],
    pub TOCC_b: stc_mcan_tocc_bit_t,
    pub RESERVED3: [u32; 160usize],
    pub ECR_b: stc_mcan_ecr_bit_t,
    pub PSR_b: stc_mcan_psr_bit_t,
    pub RESERVED4: [u32; 64usize],
    pub IR_b: stc_mcan_ir_bit_t,
    pub IE_b: stc_mcan_ie_bit_t,
    pub ILS_b: stc_mcan_ils_bit_t,
    pub ILE_b: stc_mcan_ile_bit_t,
    pub RESERVED5: [u32; 256usize],
    pub GFC_b: stc_mcan_gfc_bit_t,
    pub RESERVED6: [u32; 128usize],
    pub HPMS_b: stc_mcan_hpms_bit_t,
    pub NDAT1_b: stc_mcan_ndat1_bit_t,
    pub NDAT2_b: stc_mcan_ndat2_bit_t,
    pub RXF0C_b: stc_mcan_rxf0c_bit_t,
    pub RXF0S_b: stc_mcan_rxf0s_bit_t,
    pub RESERVED7: [u32; 64usize],
    pub RXF1C_b: stc_mcan_rxf1c_bit_t,
    pub RXF1S_b: stc_mcan_rxf1s_bit_t,
    pub RESERVED8: [u32; 64usize],
    pub TXBC_b: stc_mcan_txbc_bit_t,
    pub TXFQS_b: stc_mcan_txfqs_bit_t,
    pub RESERVED9: [u32; 32usize],
    pub TXBRP_b: stc_mcan_txbrp_bit_t,
    pub TXBAR_b: stc_mcan_txbar_bit_t,
    pub TXBCR_b: stc_mcan_txbcr_bit_t,
    pub TXBTO_b: stc_mcan_txbto_bit_t,
    pub TXBCF_b: stc_mcan_txbcf_bit_t,
    pub TXBTIE_b: stc_mcan_txbtie_bit_t,
    pub TXBCIE_b: stc_mcan_txbcie_bit_t,
    pub RESERVED10: [u32; 96usize],
    pub TXEFS_b: stc_mcan_txefs_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_MPU_TypeDef {
    pub RESERVED0: [u32; 512usize],
    pub SR_b: stc_mpu_sr_bit_t,
    pub ECLR_b: stc_mpu_eclr_bit_t,
    pub WP_b: stc_mpu_wp_bit_t,
    pub IPPR_b: stc_mpu_ippr_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub MSPPCTL_b: stc_mpu_msppctl_bit_t,
    pub RESERVED2: [u32; 32usize],
    pub PSPPCTL_b: stc_mpu_psppctl_bit_t,
    pub S1RGE_b: stc_mpu_srge_bit_t,
    pub S1RGWP_b: stc_mpu_srgwp_bit_t,
    pub S1RGRP_b: stc_mpu_srgrp_bit_t,
    pub S1CR_b: stc_mpu_scr_bit_t,
    pub S2RGE_b: stc_mpu_srge_bit_t,
    pub S2RGWP_b: stc_mpu_srgwp_bit_t,
    pub S2RGRP_b: stc_mpu_srgrp_bit_t,
    pub S2CR_b: stc_mpu_scr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_PERIC_TypeDef {
    pub RESERVED0: [u32; 96usize],
    pub SMC_ENAR_b: stc_peric_smc_enar_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub TMR_SYNENR_b: stc_peric_tmr_synenr_bit_t,
    pub RESERVED2: [u32; 32usize],
    pub USART1_NFC_b: stc_peric_usart1_nfc_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_PWC_TypeDef {
    pub FCG0_b: stc_pwc_fcg0_bit_t,
    pub FCG1_b: stc_pwc_fcg1_bit_t,
    pub FCG2_b: stc_pwc_fcg2_bit_t,
    pub FCG3_b: stc_pwc_fcg3_bit_t,
    pub FCG0PC_b: stc_pwc_fcg0pc_bit_t,
    pub RESERVED0: [u32; 139104usize],
    pub WKTCR_b: stc_pwc_wktcr_bit_t,
    pub RESERVED1: [u32; 16368usize],
    pub PWRC0_b: stc_pwc_pwrc0_bit_t,
    pub RESERVED2: [u32; 24usize],
    pub PWRC1_b: stc_pwc_pwrc1_bit_t,
    pub RESERVED3: [u32; 88usize],
    pub PWRC4_b: stc_pwc_pwrc4_bit_t,
    pub RESERVED4: [u32; 24usize],
    pub PVDCR0_b: stc_pwc_pvdcr0_bit_t,
    pub RESERVED5: [u32; 24usize],
    pub PVDCR1_b: stc_pwc_pvdcr1_bit_t,
    pub RESERVED6: [u32; 24usize],
    pub PVDFCR_b: stc_pwc_pvdfcr_bit_t,
    pub RESERVED7: [u32; 88usize],
    pub PDWKE0_b: stc_pwc_pdwke0_bit_t,
    pub RESERVED8: [u32; 24usize],
    pub PDWKE1_b: stc_pwc_pdwke1_bit_t,
    pub RESERVED9: [u32; 24usize],
    pub PDWKE2_b: stc_pwc_pdwke2_bit_t,
    pub RESERVED10: [u32; 24usize],
    pub PDWKES_b: stc_pwc_pdwkes_bit_t,
    pub RESERVED11: [u32; 24usize],
    pub PDWKF0_b: stc_pwc_pdwkf0_bit_t,
    pub RESERVED12: [u32; 24usize],
    pub PDWKF1_b: stc_pwc_pdwkf1_bit_t,
    pub RESERVED13: [u32; 24usize],
    pub PWRC5_b: stc_pwc_pwrc5_bit_t,
    pub RESERVED14: [u32; 1048usize],
    pub PVDDSR_b: stc_pwc_pvddsr_bit_t,
    pub RESERVED15: [u32; 24usize],
    pub RAMPC0_b: stc_pwc_rampc0_bit_t,
    pub RESERVED16: [u32; 32usize],
    pub PRAMLPC_b: stc_pwc_pramlpc_bit_t,
    pub RESERVED17: [u32; 235968usize],
    pub STPMCR_b: stc_pwc_stpmcr_bit_t,
    pub RESERVED18: [u32; 8064usize],
    pub FPRC_b: stc_pwc_fprc_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_RMU_TypeDef {
    pub FRST0_b: stc_rmu_frst0_bit_t,
    pub FRST1_b: stc_rmu_frst1_bit_t,
    pub FRST2_b: stc_rmu_frst2_bit_t,
    pub FRST3_b: stc_rmu_frst3_bit_t,
    pub PRSTCR0_b: stc_rmu_prstcr0_bit_t,
    pub RESERVED0: [u32; 24usize],
    pub RSTF0_b: stc_rmu_rstf0_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_RTC_TypeDef {
    pub CR0_b: stc_rtc_cr0_bit_t,
    pub RESERVED0: [u32; 24usize],
    pub CR1_b: stc_rtc_cr1_bit_t,
    pub RESERVED1: [u32; 24usize],
    pub CR2_b: stc_rtc_cr2_bit_t,
    pub RESERVED2: [u32; 24usize],
    pub CR3_b: stc_rtc_cr3_bit_t,
    pub RESERVED3: [u32; 344usize],
    pub ERRCRH_b: stc_rtc_errcrh_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_SPI_TypeDef {
    pub RESERVED0: [u32; 32usize],
    pub CR_b: stc_spi_cr_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub CFG1_b: stc_spi_cfg1_bit_t,
    pub RESERVED2: [u32; 32usize],
    pub SR_b: stc_spi_sr_bit_t,
    pub CFG2_b: stc_spi_cfg2_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_SRAMC_TypeDef {
    pub RESERVED0: [u32; 64usize],
    pub CKCR_b: stc_sramc_ckcr_bit_t,
    pub CKPR_b: stc_sramc_ckpr_bit_t,
    pub CKSR_b: stc_sramc_cksr_bit_t,
    pub SRAM0_EIEN_b: stc_sramc_sram0_eien_bit_t,
    pub RESERVED1: [u32; 96usize],
    pub SRAMB_EIEN_b: stc_sramc_sramb_eien_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_SWDT_TypeDef {
    pub CR_b: stc_swdt_cr_bit_t,
    pub SR_b: stc_swdt_sr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TMR0_TypeDef {
    pub RESERVED0: [u32; 128usize],
    pub BCONR_b: stc_tmr0_bconr_bit_t,
    pub STFLR_b: stc_tmr0_stflr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TMR4_TypeDef {
    pub RESERVED0: [u32; 256usize],
    pub OCSRU_b: stc_tmr4_ocsr_bit_t,
    pub OCERU_b: stc_tmr4_ocer_bit_t,
    pub OCSRV_b: stc_tmr4_ocsr_bit_t,
    pub OCERV_b: stc_tmr4_ocer_bit_t,
    pub OCSRW_b: stc_tmr4_ocsr_bit_t,
    pub OCERW_b: stc_tmr4_ocer_bit_t,
    pub OCSRX_b: stc_tmr4_ocsr_bit_t,
    pub OCERX_b: stc_tmr4_ocer_bit_t,
    pub OCMRUH_b: stc_tmr4_ocmrh_bit_t,
    pub RESERVED1: [u32; 16usize],
    pub OCMRUL_b: stc_tmr4_ocmrl_bit_t,
    pub OCMRVH_b: stc_tmr4_ocmrh_bit_t,
    pub RESERVED2: [u32; 16usize],
    pub OCMRVL_b: stc_tmr4_ocmrl_bit_t,
    pub OCMRWH_b: stc_tmr4_ocmrh_bit_t,
    pub RESERVED3: [u32; 16usize],
    pub OCMRWL_b: stc_tmr4_ocmrl_bit_t,
    pub OCMRXH_b: stc_tmr4_ocmrh_bit_t,
    pub RESERVED4: [u32; 16usize],
    pub OCMRXL_b: stc_tmr4_ocmrl_bit_t,
    pub RESERVED5: [u32; 64usize],
    pub CCSR_b: stc_tmr4_ccsr_bit_t,
    pub RESERVED6: [u32; 16usize],
    pub PSCR_b: stc_tmr4_pscr_bit_t,
    pub RESERVED7: [u32; 896usize],
    pub SCSRUH_b: stc_tmr4_scsr_bit_t,
    pub SCMRUH_b: stc_tmr4_scmr_bit_t,
    pub SCSRUL_b: stc_tmr4_scsr_bit_t,
    pub SCMRUL_b: stc_tmr4_scmr_bit_t,
    pub SCSRVH_b: stc_tmr4_scsr_bit_t,
    pub SCMRVH_b: stc_tmr4_scmr_bit_t,
    pub SCSRVL_b: stc_tmr4_scsr_bit_t,
    pub SCMRVL_b: stc_tmr4_scmr_bit_t,
    pub SCSRWH_b: stc_tmr4_scsr_bit_t,
    pub SCMRWH_b: stc_tmr4_scmr_bit_t,
    pub SCSRWL_b: stc_tmr4_scsr_bit_t,
    pub SCMRWL_b: stc_tmr4_scmr_bit_t,
    pub SCSRXH_b: stc_tmr4_scsr_bit_t,
    pub SCMRXH_b: stc_tmr4_scmr_bit_t,
    pub SCSRXL_b: stc_tmr4_scsr_bit_t,
    pub SCMRXL_b: stc_tmr4_scmr_bit_t,
    pub SCER_b: stc_tmr4_scer_bit_t,
    pub RESERVED8: [u32; 16usize],
    pub RCSR_b: stc_tmr4_rcsr_bit_t,
    pub SCIR_b: stc_tmr4_scir_bit_t,
    pub RESERVED9: [u32; 16usize],
    pub SCFR_b: stc_tmr4_scfr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TMR6_TypeDef {
    pub RESERVED0: [u32; 2560usize],
    pub GCONR_b: stc_tmr6_gconr_bit_t,
    pub ICONR_b: stc_tmr6_iconr_bit_t,
    pub BCONR_b: stc_tmr6_bconr_bit_t,
    pub DCONR_b: stc_tmr6_dconr_bit_t,
    pub RESERVED1: [u32; 32usize],
    pub PCNAR_b: stc_tmr6_pcnar_bit_t,
    pub PCNBR_b: stc_tmr6_pcnbr_bit_t,
    pub FCNGR_b: stc_tmr6_fcngr_bit_t,
    pub VPERR_b: stc_tmr6_vperr_bit_t,
    pub STFLR_b: stc_tmr6_stflr_bit_t,
    pub RESERVED2: [u32; 192usize],
    pub HSTAR_b: stc_tmr6_hstar_bit_t,
    pub HSTPR_b: stc_tmr6_hstpr_bit_t,
    pub HCLRR_b: stc_tmr6_hclrr_bit_t,
    pub HUPDR_b: stc_tmr6_hupdr_bit_t,
    pub HCPAR_b: stc_tmr6_hcpar_bit_t,
    pub HCPBR_b: stc_tmr6_hcpbr_bit_t,
    pub HCUPR_b: stc_tmr6_hcupr_bit_t,
    pub HCDOR_b: stc_tmr6_hcdor_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TMR6_COMMON_TypeDef {
    pub RESERVED0: [u32; 1888usize],
    pub FCNTR_b: stc_tmr6_common_fcntr_bit_t,
    pub SSTAR_b: stc_tmr6_common_sstar_bit_t,
    pub SSTPR_b: stc_tmr6_common_sstpr_bit_t,
    pub SCLRR_b: stc_tmr6_common_sclrr_bit_t,
    pub SUPDR_b: stc_tmr6_common_supdr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TMRA_TypeDef {
    pub RESERVED0: [u32; 1024usize],
    pub BCSTRL_b: stc_tmra_bcstrl_bit_t,
    pub BCSTRH_b: stc_tmra_bcstrh_bit_t,
    pub RESERVED1: [u32; 16usize],
    pub HCONR_b: stc_tmra_hconr_bit_t,
    pub RESERVED2: [u32; 16usize],
    pub HCUPR_b: stc_tmra_hcupr_bit_t,
    pub RESERVED3: [u32; 16usize],
    pub HCDOR_b: stc_tmra_hcdor_bit_t,
    pub RESERVED4: [u32; 16usize],
    pub ICONR_b: stc_tmra_iconr_bit_t,
    pub RESERVED5: [u32; 16usize],
    pub ECONR_b: stc_tmra_econr_bit_t,
    pub RESERVED6: [u32; 16usize],
    pub FCONR_b: stc_tmra_fconr_bit_t,
    pub RESERVED7: [u32; 16usize],
    pub STFLR_b: stc_tmra_stflr_bit_t,
    pub RESERVED8: [u32; 272usize],
    pub BCONR1_b: stc_tmra_bconr_bit_t,
    pub RESERVED9: [u32; 48usize],
    pub BCONR2_b: stc_tmra_bconr_bit_t,
    pub RESERVED10: [u32; 48usize],
    pub BCONR3_b: stc_tmra_bconr_bit_t,
    pub RESERVED11: [u32; 48usize],
    pub BCONR4_b: stc_tmra_bconr_bit_t,
    pub RESERVED12: [u32; 304usize],
    pub CCONR1_b: stc_tmra_cconr_bit_t,
    pub RESERVED13: [u32; 16usize],
    pub CCONR2_b: stc_tmra_cconr_bit_t,
    pub RESERVED14: [u32; 16usize],
    pub CCONR3_b: stc_tmra_cconr_bit_t,
    pub RESERVED15: [u32; 16usize],
    pub CCONR4_b: stc_tmra_cconr_bit_t,
    pub RESERVED16: [u32; 16usize],
    pub CCONR5_b: stc_tmra_cconr_bit_t,
    pub RESERVED17: [u32; 16usize],
    pub CCONR6_b: stc_tmra_cconr_bit_t,
    pub RESERVED18: [u32; 16usize],
    pub CCONR7_b: stc_tmra_cconr_bit_t,
    pub RESERVED19: [u32; 16usize],
    pub CCONR8_b: stc_tmra_cconr_bit_t,
    pub RESERVED20: [u32; 272usize],
    pub PCONR1_b: stc_tmra_pconr_bit_t,
    pub RESERVED21: [u32; 16usize],
    pub PCONR2_b: stc_tmra_pconr_bit_t,
    pub RESERVED22: [u32; 16usize],
    pub PCONR3_b: stc_tmra_pconr_bit_t,
    pub RESERVED23: [u32; 16usize],
    pub PCONR4_b: stc_tmra_pconr_bit_t,
    pub RESERVED24: [u32; 16usize],
    pub PCONR5_b: stc_tmra_pconr_bit_t,
    pub RESERVED25: [u32; 16usize],
    pub PCONR6_b: stc_tmra_pconr_bit_t,
    pub RESERVED26: [u32; 16usize],
    pub PCONR7_b: stc_tmra_pconr_bit_t,
    pub RESERVED27: [u32; 16usize],
    pub PCONR8_b: stc_tmra_pconr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_TRNG_TypeDef {
    pub CR_b: stc_trng_cr_bit_t,
    pub MR_b: stc_trng_mr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_USART_TypeDef {
    pub SR_b: stc_usart_sr_bit_t,
    pub TDR_b: stc_usart_tdr_bit_t,
    pub RESERVED0: [u32; 48usize],
    pub CR1_b: stc_usart_cr1_bit_t,
    pub CR2_b: stc_usart_cr2_bit_t,
    pub CR3_b: stc_usart_cr3_bit_t,
    pub PR_b: stc_usart_pr_bit_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct bCM_WDT_TypeDef {
    pub CR_b: stc_wdt_cr_bit_t,
    pub SR_b: stc_wdt_sr_bit_t,
}
unsafe extern "C" {
    #[doc = "< External high speed OSC freq."]
    pub static mut XTAL_VALUE: u32;
    #[doc = "< External low speed OSC freq."]
    pub static mut XTAL32_VALUE: u32;
    #[doc = "< System clock frequency"]
    pub static mut SystemCoreClock: u32;
    #[doc = "< HRC frequency"]
    pub static mut HRC_VALUE: u32;
    #[doc = " Global function prototypes (definition in C source)\n/\n/**\n @addtogroup HC32F448_System_Global_Functions\n @{"]
    pub fn SystemInit();
    pub fn SystemCoreClockUpdate();
}