hc32f448_driver_sys 0.1.1

/* automatically generated by rust-bindgen 0.72.1 */

pub const I2C_WIDTH_MAX_IMME: u32 = 516;
pub const I2C_DIR_TX: u32 = 0;
pub const I2C_DIR_RX: u32 = 1;
pub const I2C_ADDR_DISABLE: u32 = 0;
pub const I2C_ADDR_7BIT: u32 = 4096;
pub const I2C_ADDR_10BIT: u32 = 36864;
pub const I2C_CLK_DIV1: u32 = 0;
pub const I2C_CLK_DIV2: u32 = 1;
pub const I2C_CLK_DIV4: u32 = 2;
pub const I2C_CLK_DIV8: u32 = 3;
pub const I2C_CLK_DIV16: u32 = 4;
pub const I2C_CLK_DIV32: u32 = 5;
pub const I2C_CLK_DIV64: u32 = 6;
pub const I2C_CLK_DIV128: u32 = 7;
pub const I2C_ADDR0: u32 = 0;
pub const I2C_ADDR1: u32 = 1;
pub const I2C_ACK: u32 = 0;
pub const I2C_NACK: u32 = 1024;
pub const I2C_SMBUS_MATCH_ALERT: u32 = 4;
pub const I2C_SMBUS_MATCH_DEFAULT: u32 = 8;
pub const I2C_SMBUS_MATCH_HOST: u32 = 16;
pub const I2C_SMBUS_MATCH_ALL: u32 = 28;
pub const I2C_DIG_FILTER_CLK_DIV1: u32 = 0;
pub const I2C_DIG_FILTER_CLK_DIV2: u32 = 1;
pub const I2C_DIG_FILTER_CLK_DIV3: u32 = 2;
pub const I2C_DIG_FILTER_CLK_DIV4: u32 = 3;
pub const I2C_FLAG_START: u32 = 1;
pub const I2C_FLAG_MATCH_ADDR0: u32 = 2;
pub const I2C_FLAG_MATCH_ADDR1: u32 = 4;
pub const I2C_FLAG_TX_CPLT: u32 = 8;
pub const I2C_FLAG_STOP: u32 = 16;
pub const I2C_FLAG_RX_FULL: u32 = 64;
pub const I2C_FLAG_TX_EMPTY: u32 = 128;
pub const I2C_FLAG_ARBITRATE_FAIL: u32 = 512;
pub const I2C_FLAG_ACKR: u32 = 1024;
pub const I2C_FLAG_NACKF: u32 = 4096;
pub const I2C_FLAG_TMOUTF: u32 = 16384;
pub const I2C_FLAG_MASTER: u32 = 65536;
pub const I2C_FLAG_BUSY: u32 = 131072;
pub const I2C_FLAG_TRA: u32 = 262144;
pub const I2C_FLAG_GENERAL_CALL: u32 = 1048576;
pub const I2C_FLAG_SMBUS_DEFAULT_MATCH: u32 = 2097152;
pub const I2C_FLAG_SMBUS_HOST_MATCH: u32 = 4194304;
pub const I2C_FLAG_SMBUS_ALERT_MATCH: u32 = 8388608;
pub const I2C_FLAG_RX_FIFO_REQ: u32 = 2147483648;
pub const I2C_FLAG_RX_FIFO_FULL: u32 = 134217728;
pub const I2C_FLAG_RX_FIFO_EMPTY: u32 = 67108864;
pub const I2C_FLAG_TX_FIFO_FULL: u32 = 33554432;
pub const I2C_FLAG_TX_FIFO_EMPTY: u32 = 16777216;
pub const I2C_FLAG_ALL: u32 = 2415351519;
pub const I2C_FLAG_CLR_START: u32 = 1;
pub const I2C_FLAG_CLR_MATCH_ADDR0: u32 = 2;
pub const I2C_FLAG_CLR_MATCH_ADDR1: u32 = 4;
pub const I2C_FLAG_CLR_TX_CPLT: u32 = 8;
pub const I2C_FLAG_CLR_STOP: u32 = 16;
pub const I2C_FLAG_CLR_RX_FULL: u32 = 64;
pub const I2C_FLAG_CLR_ARBITRATE_FAIL: u32 = 512;
pub const I2C_FLAG_CLR_NACK: u32 = 4096;
pub const I2C_FLAG_CLR_TMOUTF: u32 = 16384;
pub const I2C_FLAG_CLR_GENERAL_CALL: u32 = 1048576;
pub const I2C_FLAG_CLR_SMBUS_DEFAULT_MATCH: u32 = 2097152;
pub const I2C_FLAG_CLR_SMBUS_HOST_MATCH: u32 = 4194304;
pub const I2C_FLAG_CLR_SMBUS_ALERT_MATCH: u32 = 8388608;
pub const I2C_FLAG_CLR_RX_FIFO_REQ: u32 = 1024;
pub const I2C_FLAG_CLR_ALL: u32 = 15750751;
pub const I2C_FIFO_EMPTY: u32 = 0;
pub const I2C_FIFO_HALFFULL: u32 = 1;
pub const I2C_FIFO_FULL: u32 = 2;
pub const I2C_INT_START: u32 = 1;
pub const I2C_INT_MATCH_ADDR0: u32 = 2;
pub const I2C_INT_MATCH_ADDR1: u32 = 4;
pub const I2C_INT_TX_CPLT: u32 = 8;
pub const I2C_INT_STOP: u32 = 16;
pub const I2C_INT_RX_FULL: u32 = 64;
pub const I2C_INT_TX_EMPTY: u32 = 128;
pub const I2C_INT_ARBITRATE_FAIL: u32 = 512;
pub const I2C_INT_NACK: u32 = 4096;
pub const I2C_INT_TMOUTIE: u32 = 16384;
pub const I2C_INT_GENERAL_CALL: u32 = 1048576;
pub const I2C_INT_SMBUS_DEFAULT_MATCH: u32 = 2097152;
pub const I2C_INT_SMBUS_HOST_MATCH: u32 = 4194304;
pub const I2C_INT_SMBUS_ALERT_MATCH: u32 = 8388608;
pub const I2C_INT_RX_FIFO_REQ: u32 = 2048;
pub const I2C_INT_ALL: u32 = 15751903;
#[doc = " @brief Single precision floating point number (4 byte)"]
pub type float32_t = f32;
pub const en_functional_state_t_DISABLE: en_functional_state_t = 0;
pub const en_functional_state_t_ENABLE: en_functional_state_t = 1;
#[doc = " @brief Functional state"]
pub type en_functional_state_t = ::core::ffi::c_uint;
pub const en_flag_status_t_RESET: en_flag_status_t = 0;
pub const en_flag_status_t_SET: en_flag_status_t = 1;
#[doc = " @brief Flag status"]
pub type en_flag_status_t = ::core::ffi::c_uint;
#[doc = " @brief I2C"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_I2C_TypeDef {
    pub CR1: u32,
    pub CR2: u32,
    pub CR3: u32,
    pub CR4: u32,
    pub SLR0: u32,
    pub SLR1: u32,
    pub SLTR: u32,
    pub SR: u32,
    pub CLR: u32,
    pub DTR: u8,
    pub RESERVED0: [u8; 3usize],
    pub DRR: u8,
    pub RESERVED1: [u8; 3usize],
    pub CCR: u32,
    pub FLTR: u32,
    pub FSTR: u32,
    pub SLVADDR: u32,
}
#[doc = " @brief I2c configuration structure"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_init_t {
    #[doc = "< I2C clock division for i2c source clock"]
    pub u32ClockDiv: u32,
    #[doc = "< I2C baudrate config"]
    pub u32Baudrate: u32,
    #[doc = "< The SCL rising and falling time, count of T(i2c source clock after frequency divider)"]
    pub u32SclTime: u32,
}
unsafe extern "C" {
    #[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup I2C_Global_Functions\n @{"]
    pub fn I2C_StructInit(pstcI2cInit: *mut stc_i2c_init_t) -> i32;
    pub fn I2C_BaudrateConfig(
        I2Cx: *mut CM_I2C_TypeDef,
        pstcI2cInit: *const stc_i2c_init_t,
        pf32Error: *mut float32_t,
    ) -> i32;
    pub fn I2C_DeInit(I2Cx: *mut CM_I2C_TypeDef) -> i32;
    pub fn I2C_Init(
        I2Cx: *mut CM_I2C_TypeDef,
        pstcI2cInit: *const stc_i2c_init_t,
        pf32Error: *mut float32_t,
    ) -> i32;
    pub fn I2C_SlaveAddrConfig(
        I2Cx: *mut CM_I2C_TypeDef,
        u32AddrNum: u32,
        u32AddrMode: u32,
        u32Addr: u32,
    );
    pub fn I2C_SlaveAddrCmd(
        I2Cx: *mut CM_I2C_TypeDef,
        u32AddrNum: u32,
        enNewState: en_functional_state_t,
    );
    pub fn I2C_Cmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_FastAckCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_BusWaitCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_SmbusConfig(
        I2Cx: *mut CM_I2C_TypeDef,
        u32SmbusConfig: u32,
        enNewState: en_functional_state_t,
    );
    pub fn I2C_SmbusCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_DigitalFilterConfig(I2Cx: *mut CM_I2C_TypeDef, u32FilterClock: u32);
    pub fn I2C_DigitalFilterCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_AnalogFilterCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_GeneralCallCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_SWResetCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_IntCmd(
        I2Cx: *mut CM_I2C_TypeDef,
        u32IntType: u32,
        enNewState: en_functional_state_t,
    );
    pub fn I2C_SlaveMaskAddrConfig(
        I2Cx: *mut CM_I2C_TypeDef,
        u32AddrNum: u32,
        u32AddrMode: u32,
        u32MaskAddr: u32,
    );
    pub fn I2C_SlaveMaskAddrCmd(
        I2Cx: *mut CM_I2C_TypeDef,
        u32AddrNum: u32,
        enNewState: en_functional_state_t,
    );
    pub fn I2C_BusFreeClearCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_SetSDAOutDelay(I2Cx: *mut CM_I2C_TypeDef, u8DelayCycle: u8);
    pub fn I2C_GenerateStart(I2Cx: *mut CM_I2C_TypeDef);
    pub fn I2C_GenerateRestart(I2Cx: *mut CM_I2C_TypeDef);
    pub fn I2C_GenerateStop(I2Cx: *mut CM_I2C_TypeDef);
    pub fn I2C_GetStatus(I2Cx: *const CM_I2C_TypeDef, u32Flag: u32) -> en_flag_status_t;
    pub fn I2C_ClearStatus(I2Cx: *mut CM_I2C_TypeDef, u32Flag: u32);
    pub fn I2C_FIFO_Cmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_FIFO_GetTxDataNum(I2Cx: *const CM_I2C_TypeDef) -> u32;
    pub fn I2C_FIFO_GetRxDataStatus(I2Cx: *const CM_I2C_TypeDef) -> u32;
    pub fn I2C_FIFO_GetTxDataStatus(I2Cx: *const CM_I2C_TypeDef) -> u32;
    pub fn I2C_FIFO_NackResetFIFOCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_FIFO_TxFlush(I2Cx: *mut CM_I2C_TypeDef);
    pub fn I2C_FIFO_RxFlush(I2Cx: *mut CM_I2C_TypeDef);
    pub fn I2C_GetMatchAddr(I2Cx: *const CM_I2C_TypeDef) -> u32;
    pub fn I2C_WriteData(I2Cx: *mut CM_I2C_TypeDef, u8Data: u8);
    pub fn I2C_ReadData(I2Cx: *const CM_I2C_TypeDef) -> u8;
    pub fn I2C_AckConfig(I2Cx: *mut CM_I2C_TypeDef, u32AckConfig: u32);
    pub fn I2C_SCLHighTimeoutConfig(I2Cx: *mut CM_I2C_TypeDef, u16TimeoutH: u16);
    pub fn I2C_SCLLowTimeoutConfig(I2Cx: *mut CM_I2C_TypeDef, u16TimeoutL: u16);
    pub fn I2C_SCLHighTimeoutCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_SCLLowTimeoutCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_SCLTimeoutCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
    pub fn I2C_Start(I2Cx: *mut CM_I2C_TypeDef, u32Timeout: u32) -> i32;
    pub fn I2C_Restart(I2Cx: *mut CM_I2C_TypeDef, u32Timeout: u32) -> i32;
    pub fn I2C_TransAddr(
        I2Cx: *mut CM_I2C_TypeDef,
        u16Addr: u16,
        u8Dir: u8,
        u32Timeout: u32,
    ) -> i32;
    pub fn I2C_Trans10BitAddr(
        I2Cx: *mut CM_I2C_TypeDef,
        u16Addr: u16,
        u8Dir: u8,
        u32Timeout: u32,
    ) -> i32;
    pub fn I2C_TransData(
        I2Cx: *mut CM_I2C_TypeDef,
        au8TxData: *const u8,
        u32Size: u32,
        u32Timeout: u32,
    ) -> i32;
    pub fn I2C_ReceiveData(
        I2Cx: *mut CM_I2C_TypeDef,
        au8RxData: *mut u8,
        u32Size: u32,
        u32Timeout: u32,
    ) -> i32;
    pub fn I2C_MasterReceiveDataAndStop(
        I2Cx: *mut CM_I2C_TypeDef,
        au8RxData: *mut u8,
        u32Size: u32,
        u32Timeout: u32,
    ) -> i32;
    pub fn I2C_Stop(I2Cx: *mut CM_I2C_TypeDef, u32Timeout: u32) -> i32;
    pub fn I2C_WaitStatus(
        I2Cx: *const CM_I2C_TypeDef,
        u32Flag: u32,
        enStatus: en_flag_status_t,
        u32Timeout: u32,
    ) -> i32;
}