hc32f448_driver_sys 0.1.1

Provide driver function binding for HDSC's HC32F448 MCU.
Documentation 
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/* automatically generated by rust-bindgen 0.72.1 */

pub const ICG_SWDT_RST_START: u32 = 0;
pub const ICG_SWDT_RST_STOP: u32 = 1;
pub const ICG_SWDT_EXP_TYPE_INT: u32 = 0;
pub const ICG_SWDT_EXP_TYPE_RST: u32 = 2;
pub const ICG_SWDT_CNT_PERIOD256: u32 = 0;
pub const ICG_SWDT_CNT_PERIOD4096: u32 = 4;
pub const ICG_SWDT_CNT_PERIOD16384: u32 = 8;
pub const ICG_SWDT_CNT_PERIOD65536: u32 = 12;
pub const ICG_SWDT_CLK_DIV1: u32 = 0;
pub const ICG_SWDT_CLK_DIV16: u32 = 64;
pub const ICG_SWDT_CLK_DIV32: u32 = 80;
pub const ICG_SWDT_CLK_DIV64: u32 = 96;
pub const ICG_SWDT_CLK_DIV128: u32 = 112;
pub const ICG_SWDT_CLK_DIV256: u32 = 128;
pub const ICG_SWDT_CLK_DIV2048: u32 = 176;
pub const ICG_SWDT_RANGE_0TO25PCT: u32 = 256;
pub const ICG_SWDT_RANGE_25TO50PCT: u32 = 512;
pub const ICG_SWDT_RANGE_0TO50PCT: u32 = 768;
pub const ICG_SWDT_RANGE_50TO75PCT: u32 = 1024;
pub const ICG_SWDT_RANGE_0TO25PCT_50TO75PCT: u32 = 1280;
pub const ICG_SWDT_RANGE_25TO75PCT: u32 = 1536;
pub const ICG_SWDT_RANGE_0TO75PCT: u32 = 1792;
pub const ICG_SWDT_RANGE_75TO100PCT: u32 = 2048;
pub const ICG_SWDT_RANGE_0TO25PCT_75TO100PCT: u32 = 2304;
pub const ICG_SWDT_RANGE_25TO50PCT_75TO100PCT: u32 = 2560;
pub const ICG_SWDT_RANGE_0TO50PCT_75TO100PCT: u32 = 2816;
pub const ICG_SWDT_RANGE_50TO100PCT: u32 = 3072;
pub const ICG_SWDT_RANGE_0TO25PCT_50TO100PCT: u32 = 3328;
pub const ICG_SWDT_RANGE_25TO100PCT: u32 = 3584;
pub const ICG_SWDT_RANGE_0TO100PCT: u32 = 3840;
pub const ICG_SWDT_LPM_CNT_CONT: u32 = 0;
pub const ICG_SWDT_LPM_CNT_STOP: u32 = 4096;
pub const ICG_WDT_RST_START: u32 = 0;
pub const ICG_WDT_RST_STOP: u32 = 65536;
pub const ICG_WDT_EXP_TYPE_INT: u32 = 0;
pub const ICG_WDT_EXP_TYPE_RST: u32 = 131072;
pub const REDEF_ICG_WDTPERI_POS: u32 = 18;
pub const ICG_WDT_CNT_PERIOD256: u32 = 0;
pub const ICG_WDT_CNT_PERIOD4096: u32 = 262144;
pub const ICG_WDT_CNT_PERIOD16384: u32 = 524288;
pub const ICG_WDT_CNT_PERIOD65536: u32 = 786432;
pub const REDEF_ICG_WDTCKS_POS: u32 = 20;
pub const ICG_WDT_CLK_DIV4: u32 = 2097152;
pub const ICG_WDT_CLK_DIV64: u32 = 6291456;
pub const ICG_WDT_CLK_DIV128: u32 = 7340032;
pub const ICG_WDT_CLK_DIV256: u32 = 8388608;
pub const ICG_WDT_CLK_DIV512: u32 = 9437184;
pub const ICG_WDT_CLK_DIV1024: u32 = 10485760;
pub const ICG_WDT_CLK_DIV2048: u32 = 11534336;
pub const ICG_WDT_CLK_DIV8192: u32 = 13631488;
pub const REDEF_ICG_WDTWDPT_POS: u32 = 24;
pub const ICG_WDT_RANGE_0TO25PCT: u32 = 16777216;
pub const ICG_WDT_RANGE_25TO50PCT: u32 = 33554432;
pub const ICG_WDT_RANGE_0TO50PCT: u32 = 50331648;
pub const ICG_WDT_RANGE_50TO75PCT: u32 = 67108864;
pub const ICG_WDT_RANGE_0TO25PCT_50TO75PCT: u32 = 83886080;
pub const ICG_WDT_RANGE_25TO75PCT: u32 = 100663296;
pub const ICG_WDT_RANGE_0TO75PCT: u32 = 117440512;
pub const ICG_WDT_RANGE_75TO100PCT: u32 = 134217728;
pub const ICG_WDT_RANGE_0TO25PCT_75TO100PCT: u32 = 150994944;
pub const ICG_WDT_RANGE_25TO50PCT_75TO100PCT: u32 = 167772160;
pub const ICG_WDT_RANGE_0TO50PCT_75TO100PCT: u32 = 184549376;
pub const ICG_WDT_RANGE_50TO100PCT: u32 = 201326592;
pub const ICG_WDT_RANGE_0TO25PCT_50TO100PCT: u32 = 218103808;
pub const ICG_WDT_RANGE_25TO100PCT: u32 = 234881024;
pub const ICG_WDT_RANGE_0TO100PCT: u32 = 251658240;
pub const ICG_WDT_LPM_CNT_CONT: u32 = 0;
pub const ICG_WDT_LPM_CNT_STOP: u32 = 268435456;
pub const ICG_BOR_VOL_THRESHOLD_LVL0: u32 = 0;
pub const ICG_BOR_VOL_THRESHOLD_LVL1: u32 = 65536;
pub const ICG_BOR_VOL_THRESHOLD_LVL2: u32 = 131072;
pub const ICG_BOR_VOL_THRESHOLD_LVL3: u32 = 196608;
pub const ICG_BOR_RST_ENABLE: u32 = 0;
pub const ICG_BOR_RST_DISABLE: u32 = 262144;
pub const ICG_HRC_20M: u32 = 0;
pub const ICG_HRC_16M: u32 = 1;
pub const ICG_HRC_RST_OSCILLATION: u32 = 0;
pub const ICG_HRC_RST_STOP: u32 = 256;
pub const ICG_FLASH_PROTECT_RST_DISABLE: u32 = 4294967295;
pub const ICG_FLASH_PROTECT_RST_ENABLE: u32 = 4294919248;
pub const ICG_RB_SWDT_AUTS: u32 = 1;
pub const ICG_RB_SWDT_ITS: u32 = 2;
pub const ICG_RB_SWDT_PERI: u32 = 12;
pub const ICG_RB_SWDT_CKS: u32 = 176;
pub const ICG_RB_SWDT_WDPT: u32 = 3840;
pub const ICG_RB_SWDT_SLTPOFF: u32 = 4096;
pub const ICG_REG_SWDT_CONFIG: u32 = 8127;
pub const ICG_RB_WDT_AUTS: u32 = 65536;
pub const ICG_RB_WDT_ITS: u32 = 131072;
pub const ICG_RB_WDT_PERI: u32 = 786432;
pub const ICG_RB_WDT_CKS: u32 = 13631488;
pub const ICG_RB_WDT_WDPT: u32 = 251658240;
pub const ICG_RB_WDT_SLTPOFF: u32 = 268435456;
pub const ICG_REG_WDT_CONFIG: u32 = 534708224;
pub const ICG_RB_BOR_LEV: u32 = 196608;
pub const ICG_RB_BOR_DIS: u32 = 262144;
pub const ICG_REG_BOR_CONFIG: u32 = 458752;
pub const ICG_RB_HRC_FREQSEL: u32 = 1;
pub const ICG_RB_HRC_STOP: u32 = 256;
pub const ICG_REG_HRC_CONFIG: u32 = 257;
pub const ICG_REG_FLASH_PROTECT_CONFIG: u32 = 4294967295;
pub const ICG_REG_CFG0_CONST: u32 = 4292870079;
pub const ICG_REG_CFG1_CONST: u32 = 4294967295;
pub const ICG_REG_CFG3_CONST: u32 = 4294967295;
pub const ICG_REG_RESV_CONST: u32 = 4294967295;