; BTOR description generated by Yosys 0.33+65 (git sha1 90124dce5, clang 15.0.0 -fPIC -Os) for module std_sub.
1 sort bitvec 32
2 input 1 left ; core.sv:127.35-127.39
3 input 1 right ; core.sv:128.35-128.40
4 sub 1 2 3
5 output 4 out ; core.sv:129.35-129.38
; end of yosys output