; BTOR description generated by Yosys 0.33+65 (git sha1 90124dce5, clang 15.0.0 -fPIC -Os) for module std_cat.
1 sort bitvec 32
2 input 1 left ; core.sv:63.39-63.43
3 input 1 right ; core.sv:64.40-64.45
4 sort bitvec 64
5 concat 4 2 3
6 output 5 out ; core.sv:65.34-65.37
; end of yosys output