; BTOR description generated by Yosys 0.33+65 (git sha1 90124dce5, clang 15.0.0 -fPIC -Os) for module std_lt.
1 sort bitvec 32
2 input 1 left ; core.sv:147.34-147.38
3 input 1 right ; core.sv:148.34-148.39
4 sort bitvec 1
5 ult 4 2 3
6 output 5 out ; core.sv:149.18-149.21
; end of yosys output