; BTOR description generated by Yosys 0.33+65 (git sha1 90124dce5, clang 15.0.0 -fPIC -Os) for module std_eq.
1 sort bitvec 32
2 input 1 left ; core.sv:157.34-157.38
3 input 1 right ; core.sv:158.34-158.39
4 sort bitvec 1
5 eq 4 2 3
6 output 5 out ; core.sv:159.18-159.21
; end of yosys output