calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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; BTOR description generated by Yosys 0.33+65 (git sha1 90124dce5, clang 15.0.0 -fPIC -Os) for module std_slice.
1 sort bitvec 32
2 input 1 in ; core.sv:15.39-15.41
3 output 2 out ; core.sv:16.39-16.42
; end of yosys output