; BTOR description generated by Yosys 0.33+65 (git sha1 90124dce5, clang 15.0.0 -fPIC -Os) for module std_reg.
1 sort bitvec 1
2 input 1 clk ; temp.sv:7.31-7.34
3 sort bitvec 32
4 input 3 in ; temp.sv:5.31-5.33
5 input 1 reset ; temp.sv:8.31-8.36
6 input 1 write_en ; temp.sv:6.31-6.39
7 state 1
8 output 7 done ; temp.sv:11.31-11.35
9 state 3
10 output 9 out ; temp.sv:10.31-10.34
11 const 1 0
12 const 1 1
13 ite 1 6 12 11
14 ite 1 5 11 13
15 next 1 7 14
16 ite 3 6 4 9 ; input if write_en else existing 9 state val
17 const 3 00000000000000000000000000000000
18 ite 3 5 17 16 ; 32 bit 0 if reset else 16
19 next 3 9 18
; end of yosys output