; BTOR description generated by Yosys 0.33+65 (git sha1 90124dce5, clang 15.0.0 -fPIC -Os) for module std_le.
1 sort bitvec 32
2 input 1 left ; core.sv:187.34-187.38
3 input 1 right ; core.sv:188.34-188.39
4 sort bitvec 1
5 ulte 4 2 3
6 output 5 out ; core.sv:189.18-189.21
; end of yosys output