stm32f4xx_hal::dma::traits

Trait DMASet

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pub unsafe trait DMASet<STREAM, const CHANNEL: u8, DIRECTION> { }
Expand description

Trait to mark a set of Stream, Channel and Direction for a Peripheral as correct together.

§Safety

Memory corruption might occur if this trait is implemented for an invalid combination.

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impl<SPI, MS, TR, STD, STREAM, const CHANNEL: u8, DIR> DMASet<STREAM, CHANNEL, DIR> for I2sDriver<I2s<SPI>, MS, TR, STD>
where SPI: DMASet<STREAM, CHANNEL, DIR> + Instance,

DMA is available for I2S based on the underlying implementations for SPI

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impl DMASet<StreamX<DMA1, 0>, 0, PeripheralToMemory> for SPI3

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impl DMASet<StreamX<DMA1, 0>, 1, PeripheralToMemory> for I2C1

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impl DMASet<StreamX<DMA1, 0>, 2, MemoryToPeripheral> for CCR1<TIM4>

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impl DMASet<StreamX<DMA1, 0>, 2, PeripheralToMemory> for CCR1<TIM4>

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impl DMASet<StreamX<DMA1, 0>, 4, PeripheralToMemory> for UART5

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impl DMASet<StreamX<DMA1, 0>, 5, MemoryToPeripheral> for UART8

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impl DMASet<StreamX<DMA1, 0>, 6, MemoryToPeripheral> for DMAR<TIM5>

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impl DMASet<StreamX<DMA1, 0>, 6, MemoryToPeripheral> for CCR3<TIM5>

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impl DMASet<StreamX<DMA1, 0>, 6, PeripheralToMemory> for DMAR<TIM5>

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impl DMASet<StreamX<DMA1, 0>, 6, PeripheralToMemory> for CCR3<TIM5>

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impl DMASet<StreamX<DMA1, 1>, 3, MemoryToPeripheral> for DMAR<TIM2>

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impl DMASet<StreamX<DMA1, 1>, 3, MemoryToPeripheral> for CCR3<TIM2>

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impl DMASet<StreamX<DMA1, 1>, 3, PeripheralToMemory> for DMAR<TIM2>

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impl DMASet<StreamX<DMA1, 1>, 3, PeripheralToMemory> for CCR3<TIM2>

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impl DMASet<StreamX<DMA1, 1>, 4, PeripheralToMemory> for USART3

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impl DMASet<StreamX<DMA1, 1>, 5, MemoryToPeripheral> for UART7

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impl DMASet<StreamX<DMA1, 1>, 6, MemoryToPeripheral> for DMAR<TIM5>

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impl DMASet<StreamX<DMA1, 1>, 6, MemoryToPeripheral> for CCR4<TIM5>

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impl DMASet<StreamX<DMA1, 1>, 6, PeripheralToMemory> for DMAR<TIM5>

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impl DMASet<StreamX<DMA1, 1>, 6, PeripheralToMemory> for CCR4<TIM5>

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impl DMASet<StreamX<DMA1, 2>, 0, PeripheralToMemory> for SPI3

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impl DMASet<StreamX<DMA1, 2>, 3, PeripheralToMemory> for I2C3

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impl DMASet<StreamX<DMA1, 2>, 4, PeripheralToMemory> for UART4

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impl DMASet<StreamX<DMA1, 2>, 5, MemoryToPeripheral> for DMAR<TIM3>

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impl DMASet<StreamX<DMA1, 2>, 5, MemoryToPeripheral> for CCR4<TIM3>

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impl DMASet<StreamX<DMA1, 2>, 5, PeripheralToMemory> for DMAR<TIM3>

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impl DMASet<StreamX<DMA1, 2>, 5, PeripheralToMemory> for CCR4<TIM3>

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impl DMASet<StreamX<DMA1, 2>, 6, MemoryToPeripheral> for CCR1<TIM5>

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impl DMASet<StreamX<DMA1, 2>, 6, PeripheralToMemory> for CCR1<TIM5>

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impl DMASet<StreamX<DMA1, 2>, 7, PeripheralToMemory> for I2C2

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impl DMASet<StreamX<DMA1, 3>, 0, PeripheralToMemory> for SPI2

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impl DMASet<StreamX<DMA1, 3>, 2, MemoryToPeripheral> for CCR2<TIM4>

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impl DMASet<StreamX<DMA1, 3>, 2, PeripheralToMemory> for CCR2<TIM4>

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impl DMASet<StreamX<DMA1, 3>, 4, MemoryToPeripheral> for USART3

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impl DMASet<StreamX<DMA1, 3>, 5, PeripheralToMemory> for UART7

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impl DMASet<StreamX<DMA1, 3>, 6, MemoryToPeripheral> for DMAR<TIM5>

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impl DMASet<StreamX<DMA1, 3>, 6, MemoryToPeripheral> for CCR4<TIM5>

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impl DMASet<StreamX<DMA1, 3>, 6, PeripheralToMemory> for DMAR<TIM5>

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impl DMASet<StreamX<DMA1, 3>, 6, PeripheralToMemory> for CCR4<TIM5>

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impl DMASet<StreamX<DMA1, 3>, 7, PeripheralToMemory> for I2C2

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impl DMASet<StreamX<DMA1, 4>, 0, MemoryToPeripheral> for SPI2

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impl DMASet<StreamX<DMA1, 4>, 3, MemoryToPeripheral> for I2C3

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impl DMASet<StreamX<DMA1, 4>, 4, MemoryToPeripheral> for UART4

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impl DMASet<StreamX<DMA1, 4>, 5, MemoryToPeripheral> for DMAR<TIM3>

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impl DMASet<StreamX<DMA1, 4>, 5, MemoryToPeripheral> for CCR1<TIM3>

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impl DMASet<StreamX<DMA1, 4>, 5, PeripheralToMemory> for DMAR<TIM3>

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impl DMASet<StreamX<DMA1, 4>, 5, PeripheralToMemory> for CCR1<TIM3>

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impl DMASet<StreamX<DMA1, 4>, 6, MemoryToPeripheral> for CCR2<TIM5>

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impl DMASet<StreamX<DMA1, 4>, 6, PeripheralToMemory> for CCR2<TIM5>

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impl DMASet<StreamX<DMA1, 4>, 7, MemoryToPeripheral> for USART3

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impl DMASet<StreamX<DMA1, 5>, 0, MemoryToPeripheral> for SPI3

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impl DMASet<StreamX<DMA1, 5>, 1, PeripheralToMemory> for I2C1

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impl DMASet<StreamX<DMA1, 5>, 3, MemoryToPeripheral> for CCR1<TIM2>

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impl DMASet<StreamX<DMA1, 5>, 3, PeripheralToMemory> for CCR1<TIM2>

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impl DMASet<StreamX<DMA1, 5>, 4, PeripheralToMemory> for USART2

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impl DMASet<StreamX<DMA1, 5>, 5, MemoryToPeripheral> for CCR2<TIM3>

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impl DMASet<StreamX<DMA1, 5>, 5, PeripheralToMemory> for CCR2<TIM3>

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impl DMASet<StreamX<DMA1, 6>, 1, MemoryToPeripheral> for I2C1

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impl DMASet<StreamX<DMA1, 6>, 2, MemoryToPeripheral> for DMAR<TIM4>

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impl DMASet<StreamX<DMA1, 6>, 2, PeripheralToMemory> for DMAR<TIM4>

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impl DMASet<StreamX<DMA1, 6>, 3, MemoryToPeripheral> for CCR2<TIM2>

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impl DMASet<StreamX<DMA1, 6>, 3, MemoryToPeripheral> for CCR4<TIM2>

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impl DMASet<StreamX<DMA1, 6>, 3, PeripheralToMemory> for CCR2<TIM2>

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impl DMASet<StreamX<DMA1, 6>, 3, PeripheralToMemory> for CCR4<TIM2>

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impl DMASet<StreamX<DMA1, 6>, 4, MemoryToPeripheral> for USART2

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impl DMASet<StreamX<DMA1, 6>, 5, PeripheralToMemory> for UART8

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impl DMASet<StreamX<DMA1, 6>, 6, MemoryToPeripheral> for DMAR<TIM5>

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impl DMASet<StreamX<DMA1, 6>, 6, PeripheralToMemory> for DMAR<TIM5>

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impl DMASet<StreamX<DMA1, 7>, 0, MemoryToPeripheral> for SPI3

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impl DMASet<StreamX<DMA1, 7>, 1, MemoryToPeripheral> for I2C1

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impl DMASet<StreamX<DMA1, 7>, 2, MemoryToPeripheral> for CCR3<TIM4>

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impl DMASet<StreamX<DMA1, 7>, 2, PeripheralToMemory> for CCR3<TIM4>

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impl DMASet<StreamX<DMA1, 7>, 3, MemoryToPeripheral> for DMAR<TIM2>

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impl DMASet<StreamX<DMA1, 7>, 3, MemoryToPeripheral> for CCR4<TIM2>

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impl DMASet<StreamX<DMA1, 7>, 3, PeripheralToMemory> for DMAR<TIM2>

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impl DMASet<StreamX<DMA1, 7>, 3, PeripheralToMemory> for CCR4<TIM2>

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impl DMASet<StreamX<DMA1, 7>, 4, MemoryToPeripheral> for UART5

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impl DMASet<StreamX<DMA1, 7>, 5, MemoryToPeripheral> for CCR3<TIM3>

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impl DMASet<StreamX<DMA1, 7>, 5, PeripheralToMemory> for CCR3<TIM3>

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impl DMASet<StreamX<DMA1, 7>, 7, MemoryToPeripheral> for I2C2

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impl DMASet<StreamX<DMA2, 0>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 0>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 0>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 0>, 0, PeripheralToMemory> for ADC1

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impl DMASet<StreamX<DMA2, 0>, 2, PeripheralToMemory> for ADC3

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impl DMASet<StreamX<DMA2, 0>, 3, PeripheralToMemory> for SPI1

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impl DMASet<StreamX<DMA2, 0>, 4, PeripheralToMemory> for SPI4

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impl DMASet<StreamX<DMA2, 0>, 6, MemoryToPeripheral> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 0>, 6, PeripheralToMemory> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 1>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 1>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 1>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 1>, 0, MemoryToPeripheral> for SAICH<SAI, false>

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impl DMASet<StreamX<DMA2, 1>, 0, PeripheralToMemory> for SAICH<SAI, false>

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impl DMASet<StreamX<DMA2, 1>, 1, PeripheralToMemory> for DCMI

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impl DMASet<StreamX<DMA2, 1>, 2, PeripheralToMemory> for ADC3

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impl DMASet<StreamX<DMA2, 1>, 4, MemoryToPeripheral> for SPI4

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impl DMASet<StreamX<DMA2, 1>, 5, PeripheralToMemory> for USART6

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impl DMASet<StreamX<DMA2, 1>, 6, MemoryToPeripheral> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 1>, 6, PeripheralToMemory> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 1>, 7, MemoryToPeripheral> for DMAR<TIM8>

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impl DMASet<StreamX<DMA2, 1>, 7, PeripheralToMemory> for DMAR<TIM8>

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impl DMASet<StreamX<DMA2, 2>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 2>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 2>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 2>, 0, MemoryToPeripheral> for CCR1<TIM8>

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impl DMASet<StreamX<DMA2, 2>, 0, MemoryToPeripheral> for CCR2<TIM8>

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impl DMASet<StreamX<DMA2, 2>, 0, MemoryToPeripheral> for CCR3<TIM8>

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impl DMASet<StreamX<DMA2, 2>, 0, PeripheralToMemory> for CCR1<TIM8>

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impl DMASet<StreamX<DMA2, 2>, 0, PeripheralToMemory> for CCR2<TIM8>

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impl DMASet<StreamX<DMA2, 2>, 0, PeripheralToMemory> for CCR3<TIM8>

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impl DMASet<StreamX<DMA2, 2>, 1, PeripheralToMemory> for ADC2

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impl DMASet<StreamX<DMA2, 2>, 3, PeripheralToMemory> for SPI1

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impl DMASet<StreamX<DMA2, 2>, 4, PeripheralToMemory> for USART1

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impl DMASet<StreamX<DMA2, 2>, 5, PeripheralToMemory> for USART6

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impl DMASet<StreamX<DMA2, 2>, 6, MemoryToPeripheral> for CCR2<TIM1>

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impl DMASet<StreamX<DMA2, 2>, 6, PeripheralToMemory> for CCR2<TIM1>

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impl DMASet<StreamX<DMA2, 2>, 7, MemoryToPeripheral> for CCR1<TIM8>

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impl DMASet<StreamX<DMA2, 2>, 7, PeripheralToMemory> for CCR1<TIM8>

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impl DMASet<StreamX<DMA2, 3>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 3>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 3>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 3>, 0, MemoryToPeripheral> for SAICH<SAI, false>

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impl DMASet<StreamX<DMA2, 3>, 0, PeripheralToMemory> for SAICH<SAI, false>

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impl DMASet<StreamX<DMA2, 3>, 1, PeripheralToMemory> for ADC2

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impl DMASet<StreamX<DMA2, 3>, 2, PeripheralToMemory> for SPI5

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impl DMASet<StreamX<DMA2, 3>, 3, MemoryToPeripheral> for SPI1

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impl DMASet<StreamX<DMA2, 3>, 4, MemoryToPeripheral> for SDIO

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impl DMASet<StreamX<DMA2, 3>, 4, PeripheralToMemory> for SDIO

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impl DMASet<StreamX<DMA2, 3>, 5, PeripheralToMemory> for SPI4

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impl DMASet<StreamX<DMA2, 3>, 6, MemoryToPeripheral> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 3>, 6, PeripheralToMemory> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 3>, 7, MemoryToPeripheral> for CCR2<TIM8>

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impl DMASet<StreamX<DMA2, 3>, 7, PeripheralToMemory> for CCR2<TIM8>

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impl DMASet<StreamX<DMA2, 4>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 4>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 4>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 4>, 0, PeripheralToMemory> for ADC1

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impl DMASet<StreamX<DMA2, 4>, 1, MemoryToPeripheral> for SAICH<SAI, true>

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impl DMASet<StreamX<DMA2, 4>, 1, PeripheralToMemory> for SAICH<SAI, true>

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impl DMASet<StreamX<DMA2, 4>, 2, MemoryToPeripheral> for SPI5

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impl DMASet<StreamX<DMA2, 4>, 5, MemoryToPeripheral> for SPI4

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impl DMASet<StreamX<DMA2, 4>, 6, MemoryToPeripheral> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 4>, 6, MemoryToPeripheral> for CCR4<TIM1>

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impl DMASet<StreamX<DMA2, 4>, 6, PeripheralToMemory> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 4>, 6, PeripheralToMemory> for CCR4<TIM1>

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impl DMASet<StreamX<DMA2, 4>, 7, MemoryToPeripheral> for CCR3<TIM8>

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impl DMASet<StreamX<DMA2, 4>, 7, PeripheralToMemory> for CCR3<TIM8>

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impl DMASet<StreamX<DMA2, 5>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 5>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 5>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 5>, 0, MemoryToPeripheral> for SAICH<SAI, true>

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impl DMASet<StreamX<DMA2, 5>, 0, PeripheralToMemory> for SAICH<SAI, true>

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impl DMASet<StreamX<DMA2, 5>, 1, MemoryToPeripheral> for SPI6

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impl DMASet<StreamX<DMA2, 5>, 2, PeripheralToMemory> for CRYP

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impl DMASet<StreamX<DMA2, 5>, 3, MemoryToPeripheral> for SPI1

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impl DMASet<StreamX<DMA2, 5>, 4, PeripheralToMemory> for USART1

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impl DMASet<StreamX<DMA2, 5>, 6, MemoryToPeripheral> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 5>, 6, PeripheralToMemory> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 5>, 7, PeripheralToMemory> for SPI5

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impl DMASet<StreamX<DMA2, 6>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 6>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 6>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR2<TIM1>

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impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR3<TIM1>

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impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR2<TIM1>

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impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR3<TIM1>

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impl DMASet<StreamX<DMA2, 6>, 1, PeripheralToMemory> for SPI6

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impl DMASet<StreamX<DMA2, 6>, 2, MemoryToPeripheral> for CRYP

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impl DMASet<StreamX<DMA2, 6>, 4, MemoryToPeripheral> for SDIO

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impl DMASet<StreamX<DMA2, 6>, 4, PeripheralToMemory> for SDIO

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impl DMASet<StreamX<DMA2, 6>, 5, MemoryToPeripheral> for USART6

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impl DMASet<StreamX<DMA2, 6>, 6, MemoryToPeripheral> for CCR3<TIM1>

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impl DMASet<StreamX<DMA2, 6>, 6, PeripheralToMemory> for CCR3<TIM1>

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impl DMASet<StreamX<DMA2, 6>, 7, MemoryToPeripheral> for SPI5

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impl DMASet<StreamX<DMA2, 7>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 7>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 7>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 7>, 1, PeripheralToMemory> for DCMI

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impl DMASet<StreamX<DMA2, 7>, 2, MemoryToPeripheral> for HASH

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impl DMASet<StreamX<DMA2, 7>, 4, MemoryToPeripheral> for USART1

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impl DMASet<StreamX<DMA2, 7>, 5, MemoryToPeripheral> for USART6

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impl DMASet<StreamX<DMA2, 7>, 7, MemoryToPeripheral> for DMAR<TIM8>

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impl DMASet<StreamX<DMA2, 7>, 7, MemoryToPeripheral> for CCR4<TIM8>

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impl DMASet<StreamX<DMA2, 7>, 7, PeripheralToMemory> for DMAR<TIM8>

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impl DMASet<StreamX<DMA2, 7>, 7, PeripheralToMemory> for CCR4<TIM8>

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impl<ADC, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, PeripheralToMemory> for Adc<ADC>
where ADC: DMASet<STREAM, CHANNEL, PeripheralToMemory>,

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impl<I2C, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, MemoryToPeripheral> for stm32f4xx_hal::i2c::dma::Tx<I2C>
where I2C: DMASet<STREAM, CHANNEL, MemoryToPeripheral>,

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impl<I2C, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, PeripheralToMemory> for stm32f4xx_hal::i2c::dma::Rx<I2C>
where I2C: DMASet<STREAM, CHANNEL, PeripheralToMemory>,

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impl<SPI, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, MemoryToPeripheral> for stm32f4xx_hal::spi::Tx<SPI>
where SPI: DMASet<STREAM, CHANNEL, MemoryToPeripheral>,

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impl<SPI, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, PeripheralToMemory> for stm32f4xx_hal::spi::Rx<SPI>
where SPI: DMASet<STREAM, CHANNEL, PeripheralToMemory>,

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impl<SPIext, PART, MS, TR, STD, STREAM, const CHANNEL: u8, DIR> DMASet<STREAM, CHANNEL, DIR> for DualI2sDmaTarget<DualI2s<SPIext>, PART, MS, TR, STD>
where SPIext: DMASet<STREAM, CHANNEL, DIR> + DualInstance,

DMA is available for I2S based on the underlying implementations for SPI

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impl<Serial_, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, MemoryToPeripheral> for stm32f4xx_hal::serial::dma::Tx<Serial_>
where Serial_: DMASet<STREAM, CHANNEL, MemoryToPeripheral>,

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impl<Serial_, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, PeripheralToMemory> for stm32f4xx_hal::serial::dma::Rx<Serial_>
where Serial_: DMASet<STREAM, CHANNEL, PeripheralToMemory>,

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impl<UART, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, MemoryToPeripheral> for stm32f4xx_hal::serial::Tx<UART>
where UART: DMASet<STREAM, CHANNEL, MemoryToPeripheral> + CommonPins,

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impl<UART, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, PeripheralToMemory> for stm32f4xx_hal::serial::Rx<UART>
where UART: DMASet<STREAM, CHANNEL, PeripheralToMemory> + CommonPins,