Expand description
Direct Memory Access.
Transfer::init is only implemented for valid combinations of peripheral-stream-channel-direction, providing compile time checking.
This module implements Memory To Memory, Peripheral To Memory and Memory to Peripheral transfers, double buffering is supported only for Peripheral To Memory and Memory to Peripheral transfers.
Modules§
Structs§
- ChannelX
- A Channel that can be configured on a DMA stream.
- Memory
ToMemory - DMA from one memory location to another memory location.
- Memory
ToPeripheral - DMA from a memory location to a peripheral.
- Peripheral
ToMemory - DMA from a peripheral to a memory location.
- StreamX
- Stream on the DMA controller.
- Streams
Tuple - Alias for a tuple with all DMA streams.
- Transfer
- DMA Transfer.
Enums§
- Current
Buffer - Which DMA buffer is in use.
- DMAError
- Errors.
- DmaChannel
- Possible Channel of a DMA Stream.
- DmaData
Size - Size of data transfered during a dma stream request
- DmaDirection
- Possible DMA’s directions.
- DmaEvent
- Structure to get or set common interrupts setup
- DmaFlag
- Structure returned by Stream or Transfer flags() method.
- DmaFlow
Controller - Dma flow controller selection
- Fifo
Level - How full the DMA stream’s fifo is.
- Peripheral
Increment Offset - Peripheral increment offset size (pincos)
Type Aliases§
- Channel0
- Channel1
- Channel2
- Channel3
- Channel4
- Channel5
- Channel6
- Channel7
- Stream0
- Stream 0 on the DMA controller.
- Stream1
- Stream 1 on the DMA controller.
- Stream2
- Stream 2 on the DMA controller.
- Stream3
- Stream 3 on the DMA controller.
- Stream4
- Stream 4 on the DMA controller.
- Stream5
- Stream 5 on the DMA controller.
- Stream6
- Stream 6 on the DMA controller.
- Stream7
- Stream 7 on the DMA controller.