Struct stm32f4xx_hal::dma::MemoryToPeripheral
source · pub struct MemoryToPeripheral;
Expand description
DMA from a memory location to a peripheral.
Trait Implementations§
source§impl Clone for MemoryToPeripheral
impl Clone for MemoryToPeripheral
source§fn clone(&self) -> MemoryToPeripheral
fn clone(&self) -> MemoryToPeripheral
Returns a copy of the value. Read more
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
Performs copy-assignment from
source
. Read moresource§impl Debug for MemoryToPeripheral
impl Debug for MemoryToPeripheral
source§impl Direction for MemoryToPeripheral
impl Direction for MemoryToPeripheral
impl Copy for MemoryToPeripheral
impl<I2C, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, MemoryToPeripheral> for Tx<I2C>where
I2C: DMASet<STREAM, CHANNEL, MemoryToPeripheral>,
impl<SPI, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, MemoryToPeripheral> for Tx<SPI>where
SPI: DMASet<STREAM, CHANNEL, MemoryToPeripheral>,
impl<UART, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, MemoryToPeripheral> for Tx<UART>
impl DMASet<StreamX<DMA1, 0>, 2, MemoryToPeripheral> for CCR1<TIM4>
impl DMASet<StreamX<DMA1, 0>, 5, MemoryToPeripheral> for UART8
impl DMASet<StreamX<DMA1, 0>, 6, MemoryToPeripheral> for CCR3<TIM5>
impl DMASet<StreamX<DMA1, 0>, 6, MemoryToPeripheral> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 1>, 3, MemoryToPeripheral> for CCR3<TIM2>
impl DMASet<StreamX<DMA1, 1>, 3, MemoryToPeripheral> for DMAR<TIM2>
impl DMASet<StreamX<DMA1, 1>, 5, MemoryToPeripheral> for UART7
impl DMASet<StreamX<DMA1, 1>, 6, MemoryToPeripheral> for CCR4<TIM5>
impl DMASet<StreamX<DMA1, 1>, 6, MemoryToPeripheral> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 2>, 5, MemoryToPeripheral> for CCR4<TIM3>
impl DMASet<StreamX<DMA1, 2>, 5, MemoryToPeripheral> for DMAR<TIM3>
impl DMASet<StreamX<DMA1, 2>, 6, MemoryToPeripheral> for CCR1<TIM5>
impl DMASet<StreamX<DMA1, 3>, 2, MemoryToPeripheral> for CCR2<TIM4>
impl DMASet<StreamX<DMA1, 3>, 4, MemoryToPeripheral> for USART3
impl DMASet<StreamX<DMA1, 3>, 6, MemoryToPeripheral> for CCR4<TIM5>
impl DMASet<StreamX<DMA1, 3>, 6, MemoryToPeripheral> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 4>, 0, MemoryToPeripheral> for SPI2
impl DMASet<StreamX<DMA1, 4>, 3, MemoryToPeripheral> for I2C3
impl DMASet<StreamX<DMA1, 4>, 4, MemoryToPeripheral> for UART4
impl DMASet<StreamX<DMA1, 4>, 5, MemoryToPeripheral> for CCR1<TIM3>
impl DMASet<StreamX<DMA1, 4>, 5, MemoryToPeripheral> for DMAR<TIM3>
impl DMASet<StreamX<DMA1, 4>, 6, MemoryToPeripheral> for CCR2<TIM5>
impl DMASet<StreamX<DMA1, 4>, 7, MemoryToPeripheral> for USART3
impl DMASet<StreamX<DMA1, 5>, 0, MemoryToPeripheral> for SPI3
impl DMASet<StreamX<DMA1, 5>, 3, MemoryToPeripheral> for CCR1<TIM2>
impl DMASet<StreamX<DMA1, 5>, 5, MemoryToPeripheral> for CCR2<TIM3>
impl DMASet<StreamX<DMA1, 6>, 1, MemoryToPeripheral> for I2C1
impl DMASet<StreamX<DMA1, 6>, 2, MemoryToPeripheral> for DMAR<TIM4>
impl DMASet<StreamX<DMA1, 6>, 3, MemoryToPeripheral> for CCR2<TIM2>
impl DMASet<StreamX<DMA1, 6>, 3, MemoryToPeripheral> for CCR4<TIM2>
impl DMASet<StreamX<DMA1, 6>, 4, MemoryToPeripheral> for USART2
impl DMASet<StreamX<DMA1, 6>, 6, MemoryToPeripheral> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 7>, 0, MemoryToPeripheral> for SPI3
impl DMASet<StreamX<DMA1, 7>, 1, MemoryToPeripheral> for I2C1
impl DMASet<StreamX<DMA1, 7>, 2, MemoryToPeripheral> for CCR3<TIM4>
impl DMASet<StreamX<DMA1, 7>, 3, MemoryToPeripheral> for CCR4<TIM2>
impl DMASet<StreamX<DMA1, 7>, 3, MemoryToPeripheral> for DMAR<TIM2>
impl DMASet<StreamX<DMA1, 7>, 4, MemoryToPeripheral> for UART5
impl DMASet<StreamX<DMA1, 7>, 5, MemoryToPeripheral> for CCR3<TIM3>
impl DMASet<StreamX<DMA1, 7>, 7, MemoryToPeripheral> for I2C2
impl DMASet<StreamX<DMA2, 0>, 6, MemoryToPeripheral> for DMAR<TIM1>
impl DMASet<StreamX<DMA2, 1>, 0, MemoryToPeripheral> for SAICH<SAI, 0>
impl DMASet<StreamX<DMA2, 1>, 4, MemoryToPeripheral> for SPI4
impl DMASet<StreamX<DMA2, 1>, 6, MemoryToPeripheral> for CCR1<TIM1>
impl DMASet<StreamX<DMA2, 1>, 7, MemoryToPeripheral> for DMAR<TIM8>
impl DMASet<StreamX<DMA2, 2>, 0, MemoryToPeripheral> for CCR1<TIM8>
impl DMASet<StreamX<DMA2, 2>, 0, MemoryToPeripheral> for CCR2<TIM8>
impl DMASet<StreamX<DMA2, 2>, 0, MemoryToPeripheral> for CCR3<TIM8>
impl DMASet<StreamX<DMA2, 2>, 6, MemoryToPeripheral> for CCR2<TIM1>
impl DMASet<StreamX<DMA2, 2>, 7, MemoryToPeripheral> for CCR1<TIM8>
impl DMASet<StreamX<DMA2, 3>, 0, MemoryToPeripheral> for SAICH<SAI, 0>
impl DMASet<StreamX<DMA2, 3>, 3, MemoryToPeripheral> for SPI1
impl DMASet<StreamX<DMA2, 3>, 4, MemoryToPeripheral> for SDIO
impl DMASet<StreamX<DMA2, 3>, 6, MemoryToPeripheral> for CCR1<TIM1>
impl DMASet<StreamX<DMA2, 3>, 7, MemoryToPeripheral> for CCR2<TIM8>
impl DMASet<StreamX<DMA2, 4>, 1, MemoryToPeripheral> for SAICH<SAI, 1>
impl DMASet<StreamX<DMA2, 4>, 2, MemoryToPeripheral> for SPI5
impl DMASet<StreamX<DMA2, 4>, 5, MemoryToPeripheral> for SPI4
impl DMASet<StreamX<DMA2, 4>, 6, MemoryToPeripheral> for CCR4<TIM1>
impl DMASet<StreamX<DMA2, 4>, 6, MemoryToPeripheral> for DMAR<TIM1>
impl DMASet<StreamX<DMA2, 4>, 7, MemoryToPeripheral> for CCR3<TIM8>
impl DMASet<StreamX<DMA2, 5>, 0, MemoryToPeripheral> for SAICH<SAI, 1>
impl DMASet<StreamX<DMA2, 5>, 1, MemoryToPeripheral> for SPI6
impl DMASet<StreamX<DMA2, 5>, 3, MemoryToPeripheral> for SPI1
impl DMASet<StreamX<DMA2, 5>, 6, MemoryToPeripheral> for DMAR<TIM1>
impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR1<TIM1>
impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR2<TIM1>
impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR3<TIM1>
impl DMASet<StreamX<DMA2, 6>, 2, MemoryToPeripheral> for CRYP
impl DMASet<StreamX<DMA2, 6>, 4, MemoryToPeripheral> for SDIO
impl DMASet<StreamX<DMA2, 6>, 5, MemoryToPeripheral> for USART6
impl DMASet<StreamX<DMA2, 6>, 6, MemoryToPeripheral> for CCR3<TIM1>
impl DMASet<StreamX<DMA2, 6>, 7, MemoryToPeripheral> for SPI5
impl DMASet<StreamX<DMA2, 7>, 2, MemoryToPeripheral> for HASH
impl DMASet<StreamX<DMA2, 7>, 4, MemoryToPeripheral> for USART1
impl DMASet<StreamX<DMA2, 7>, 5, MemoryToPeripheral> for USART6
impl DMASet<StreamX<DMA2, 7>, 7, MemoryToPeripheral> for CCR4<TIM8>
impl DMASet<StreamX<DMA2, 7>, 7, MemoryToPeripheral> for DMAR<TIM8>
Auto Trait Implementations§
impl RefUnwindSafe for MemoryToPeripheral
impl Send for MemoryToPeripheral
impl Sync for MemoryToPeripheral
impl Unpin for MemoryToPeripheral
impl UnwindSafe for MemoryToPeripheral
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more