Struct stm32f4xx_hal::serial::Tx

pub struct Tx<USART: CommonPins, WORD = u8> { /* private fields */ }

Serial transmitter containing TX pin

Implementations

impl<UART: CommonPins, WORD> Tx<UART, WORD>

pub fn join(self, rx: Rx<UART, WORD>) -> Serial<UART, WORD>

Trait Implementations

impl<UART: Instance, WORD> AsMut<Tx<UART, WORD>> for Serial<UART, WORD>

fn as_mut(&mut self) -> &mut Tx<UART, WORD>

Converts this type into a mutable reference of the (usually inferred) input type.

impl<UART: Instance, WORD> AsRef<Tx<UART, WORD>> for Serial<UART, WORD>

fn as_ref(&self) -> &Tx<UART, WORD>

Converts this type into a shared reference of the (usually inferred) input type.

impl<USART: Instance, WORD> ErrorType for Tx<USART, WORD>

type Error = Error

Error type

impl<UART> PeriAddress for Tx<UART, u8>

where <UART as Instance>::RegisterBlock: RegisterBlockImpl, UART: Deref<Target = <UART as Instance>::RegisterBlock> + Instance,

fn address(&self) -> u32

Returns the address to be used by the DMA stream.

type MemSize = u8

Memory size of the peripheral.

impl<UART, WORD> TxISR for Tx<UART, WORD>

where <UART as Instance>::RegisterBlock: RegisterBlockImpl, UART: Deref<Target = <UART as Instance>::RegisterBlock> + Instance,

fn is_tx_empty(&self) -> bool

Return true if the tx register is empty (and can accept data)

impl<UART, WORD> TxListen for Tx<UART, WORD>

where <UART as Instance>::RegisterBlock: RegisterBlockImpl, UART: Deref<Target = <UART as Instance>::RegisterBlock> + Instance,

fn listen(&mut self)

Start listening for a tx empty interrupt event

fn unlisten(&mut self)

Stop listening for the tx empty interrupt event

impl<USART> Write<u16> for Tx<USART, u16>

where <USART as Instance>::RegisterBlock: RegisterBlockImpl, USART: Deref<Target = <USART as Instance>::RegisterBlock> + Instance,

Writes 9-bit words to the UART/USART

If the UART/USART was configured with WordLength::DataBits9, the 9 least significant bits will be transmitted and the other 7 bits will be ignored. Otherwise, the 8 least significant bits will be transmitted and the other 8 bits will be ignored.

fn write(&mut self, word: u16) -> Result<(), Self::Error>

Writes a single word to the serial interface.

fn flush(&mut self) -> Result<(), Self::Error>

Ensures that none of the previously written words are still buffered.

impl<UART> Write for Tx<UART>

where <UART as Instance>::RegisterBlock: RegisterBlockImpl, UART: Deref<Target = <UART as Instance>::RegisterBlock> + Instance,

fn write_str(&mut self, s: &str) -> Result

Writes a string slice into this writer, returning whether the write succeeded.

fn write_char(&mut self, c: char) -> Result<(), Error>

Writes a char into this writer, returning whether the write succeeded.

fn write_fmt(&mut self, args: Arguments<'_>) -> Result<(), Error>

Glue for usage of the write! macro with implementors of this trait.

impl<USART> Write for Tx<USART, u8>

where <USART as Instance>::RegisterBlock: RegisterBlockImpl, USART: Deref<Target = <USART as Instance>::RegisterBlock> + Instance,

fn write(&mut self, word: u8) -> Result<(), Self::Error>

Writes a single word to the serial interface.

fn flush(&mut self) -> Result<(), Self::Error>

Ensures that none of the previously written words are still buffered.

impl<USART> Write<u16> for Tx<USART, u16>

where <USART as Instance>::RegisterBlock: RegisterBlockImpl, USART: Deref<Target = <USART as Instance>::RegisterBlock> + Instance,

type Error = Error

The type of error that can occur when writing

fn bwrite_all(&mut self, slice: &[u16]) -> Result<(), Self::Error>

Writes a slice, blocking until everything has been written

fn bflush(&mut self) -> Result<(), Self::Error>

Block until the serial interface has sent all buffered words

impl<USART> Write<u8> for Tx<USART, u8>

where <USART as Instance>::RegisterBlock: RegisterBlockImpl, USART: Deref<Target = <USART as Instance>::RegisterBlock> + Instance,

type Error = Error

The type of error that can occur when writing

fn bwrite_all(&mut self, bytes: &[u8]) -> Result<(), Self::Error>

Writes a slice, blocking until everything has been written

fn bflush(&mut self) -> Result<(), Self::Error>

Block until the serial interface has sent all buffered words

impl<USART> Write<u16> for Tx<USART, u16>

where <USART as Instance>::RegisterBlock: RegisterBlockImpl, USART: Deref<Target = <USART as Instance>::RegisterBlock> + Instance,

Writes 9-bit words to the UART/USART

If the UART/USART was configured with WordLength::DataBits9, the 9 least significant bits will be transmitted and the other 7 bits will be ignored. Otherwise, the 8 least significant bits will be transmitted and the other 8 bits will be ignored.

type Error = Error

Write error

fn write(&mut self, word: u16) -> Result<(), Self::Error>

Writes a single word to the serial interface

fn flush(&mut self) -> Result<(), Self::Error>

Ensures that none of the previously written words are still buffered

impl<USART> Write<u8> for Tx<USART, u8>

where <USART as Instance>::RegisterBlock: RegisterBlockImpl, USART: Deref<Target = <USART as Instance>::RegisterBlock> + Instance,

type Error = Error

Write error

fn write(&mut self, word: u8) -> Result<(), Self::Error>

Writes a single word to the serial interface

fn flush(&mut self) -> Result<(), Self::Error>

Ensures that none of the previously written words are still buffered

impl<UART, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, MemoryToPeripheral> for Tx<UART>

where UART: DMASet<STREAM, CHANNEL, MemoryToPeripheral> + CommonPins,