Struct stm32f4xx_hal::dma::PeripheralToMemory
source · pub struct PeripheralToMemory;
Expand description
DMA from a peripheral to a memory location.
Trait Implementations§
source§impl Clone for PeripheralToMemory
impl Clone for PeripheralToMemory
source§fn clone(&self) -> PeripheralToMemory
fn clone(&self) -> PeripheralToMemory
Returns a copy of the value. Read more
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
Performs copy-assignment from
source
. Read moresource§impl Debug for PeripheralToMemory
impl Debug for PeripheralToMemory
source§impl Direction for PeripheralToMemory
impl Direction for PeripheralToMemory
impl Copy for PeripheralToMemory
impl<ADC, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, PeripheralToMemory> for Adc<ADC>where
ADC: DMASet<STREAM, CHANNEL, PeripheralToMemory>,
impl<I2C, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, PeripheralToMemory> for Rx<I2C>where
I2C: DMASet<STREAM, CHANNEL, PeripheralToMemory>,
impl<SPI, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, PeripheralToMemory> for Rx<SPI>where
SPI: DMASet<STREAM, CHANNEL, PeripheralToMemory>,
impl<UART, STREAM, const CHANNEL: u8> DMASet<STREAM, CHANNEL, PeripheralToMemory> for Rx<UART>
impl DMASet<StreamX<DMA1, 0>, 0, PeripheralToMemory> for SPI3
impl DMASet<StreamX<DMA1, 0>, 1, PeripheralToMemory> for I2C1
impl DMASet<StreamX<DMA1, 0>, 2, PeripheralToMemory> for CCR1<TIM4>
impl DMASet<StreamX<DMA1, 0>, 4, PeripheralToMemory> for UART5
impl DMASet<StreamX<DMA1, 0>, 6, PeripheralToMemory> for CCR3<TIM5>
impl DMASet<StreamX<DMA1, 0>, 6, PeripheralToMemory> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 1>, 3, PeripheralToMemory> for CCR3<TIM2>
impl DMASet<StreamX<DMA1, 1>, 3, PeripheralToMemory> for DMAR<TIM2>
impl DMASet<StreamX<DMA1, 1>, 4, PeripheralToMemory> for USART3
impl DMASet<StreamX<DMA1, 1>, 6, PeripheralToMemory> for CCR4<TIM5>
impl DMASet<StreamX<DMA1, 1>, 6, PeripheralToMemory> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 2>, 0, PeripheralToMemory> for SPI3
impl DMASet<StreamX<DMA1, 2>, 3, PeripheralToMemory> for I2C3
impl DMASet<StreamX<DMA1, 2>, 4, PeripheralToMemory> for UART4
impl DMASet<StreamX<DMA1, 2>, 5, PeripheralToMemory> for CCR4<TIM3>
impl DMASet<StreamX<DMA1, 2>, 5, PeripheralToMemory> for DMAR<TIM3>
impl DMASet<StreamX<DMA1, 2>, 6, PeripheralToMemory> for CCR1<TIM5>
impl DMASet<StreamX<DMA1, 2>, 7, PeripheralToMemory> for I2C2
impl DMASet<StreamX<DMA1, 3>, 0, PeripheralToMemory> for SPI2
impl DMASet<StreamX<DMA1, 3>, 2, PeripheralToMemory> for CCR2<TIM4>
impl DMASet<StreamX<DMA1, 3>, 5, PeripheralToMemory> for UART7
impl DMASet<StreamX<DMA1, 3>, 6, PeripheralToMemory> for CCR4<TIM5>
impl DMASet<StreamX<DMA1, 3>, 6, PeripheralToMemory> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 3>, 7, PeripheralToMemory> for I2C2
impl DMASet<StreamX<DMA1, 4>, 5, PeripheralToMemory> for CCR1<TIM3>
impl DMASet<StreamX<DMA1, 4>, 5, PeripheralToMemory> for DMAR<TIM3>
impl DMASet<StreamX<DMA1, 4>, 6, PeripheralToMemory> for CCR2<TIM5>
impl DMASet<StreamX<DMA1, 5>, 1, PeripheralToMemory> for I2C1
impl DMASet<StreamX<DMA1, 5>, 3, PeripheralToMemory> for CCR1<TIM2>
impl DMASet<StreamX<DMA1, 5>, 4, PeripheralToMemory> for USART2
impl DMASet<StreamX<DMA1, 5>, 5, PeripheralToMemory> for CCR2<TIM3>
impl DMASet<StreamX<DMA1, 6>, 2, PeripheralToMemory> for DMAR<TIM4>
impl DMASet<StreamX<DMA1, 6>, 3, PeripheralToMemory> for CCR2<TIM2>
impl DMASet<StreamX<DMA1, 6>, 3, PeripheralToMemory> for CCR4<TIM2>
impl DMASet<StreamX<DMA1, 6>, 5, PeripheralToMemory> for UART8
impl DMASet<StreamX<DMA1, 6>, 6, PeripheralToMemory> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 7>, 2, PeripheralToMemory> for CCR3<TIM4>
impl DMASet<StreamX<DMA1, 7>, 3, PeripheralToMemory> for CCR4<TIM2>
impl DMASet<StreamX<DMA1, 7>, 3, PeripheralToMemory> for DMAR<TIM2>
impl DMASet<StreamX<DMA1, 7>, 5, PeripheralToMemory> for CCR3<TIM3>
impl DMASet<StreamX<DMA2, 0>, 0, PeripheralToMemory> for ADC1
impl DMASet<StreamX<DMA2, 0>, 2, PeripheralToMemory> for ADC3
impl DMASet<StreamX<DMA2, 0>, 3, PeripheralToMemory> for SPI1
impl DMASet<StreamX<DMA2, 0>, 4, PeripheralToMemory> for SPI4
impl DMASet<StreamX<DMA2, 0>, 6, PeripheralToMemory> for DMAR<TIM1>
impl DMASet<StreamX<DMA2, 1>, 0, PeripheralToMemory> for SAICH<SAI, 0>
impl DMASet<StreamX<DMA2, 1>, 1, PeripheralToMemory> for DCMI
impl DMASet<StreamX<DMA2, 1>, 2, PeripheralToMemory> for ADC3
impl DMASet<StreamX<DMA2, 1>, 5, PeripheralToMemory> for USART6
impl DMASet<StreamX<DMA2, 1>, 6, PeripheralToMemory> for CCR1<TIM1>
impl DMASet<StreamX<DMA2, 1>, 7, PeripheralToMemory> for DMAR<TIM8>
impl DMASet<StreamX<DMA2, 2>, 0, PeripheralToMemory> for CCR1<TIM8>
impl DMASet<StreamX<DMA2, 2>, 0, PeripheralToMemory> for CCR2<TIM8>
impl DMASet<StreamX<DMA2, 2>, 0, PeripheralToMemory> for CCR3<TIM8>
impl DMASet<StreamX<DMA2, 2>, 1, PeripheralToMemory> for ADC2
impl DMASet<StreamX<DMA2, 2>, 3, PeripheralToMemory> for SPI1
impl DMASet<StreamX<DMA2, 2>, 4, PeripheralToMemory> for USART1
impl DMASet<StreamX<DMA2, 2>, 5, PeripheralToMemory> for USART6
impl DMASet<StreamX<DMA2, 2>, 6, PeripheralToMemory> for CCR2<TIM1>
impl DMASet<StreamX<DMA2, 2>, 7, PeripheralToMemory> for CCR1<TIM8>
impl DMASet<StreamX<DMA2, 3>, 0, PeripheralToMemory> for SAICH<SAI, 0>
impl DMASet<StreamX<DMA2, 3>, 1, PeripheralToMemory> for ADC2
impl DMASet<StreamX<DMA2, 3>, 2, PeripheralToMemory> for SPI5
impl DMASet<StreamX<DMA2, 3>, 4, PeripheralToMemory> for SDIO
impl DMASet<StreamX<DMA2, 3>, 5, PeripheralToMemory> for SPI4
impl DMASet<StreamX<DMA2, 3>, 6, PeripheralToMemory> for CCR1<TIM1>
impl DMASet<StreamX<DMA2, 3>, 7, PeripheralToMemory> for CCR2<TIM8>
impl DMASet<StreamX<DMA2, 4>, 0, PeripheralToMemory> for ADC1
impl DMASet<StreamX<DMA2, 4>, 1, PeripheralToMemory> for SAICH<SAI, 1>
impl DMASet<StreamX<DMA2, 4>, 6, PeripheralToMemory> for CCR4<TIM1>
impl DMASet<StreamX<DMA2, 4>, 6, PeripheralToMemory> for DMAR<TIM1>
impl DMASet<StreamX<DMA2, 4>, 7, PeripheralToMemory> for CCR3<TIM8>
impl DMASet<StreamX<DMA2, 5>, 0, PeripheralToMemory> for SAICH<SAI, 1>
impl DMASet<StreamX<DMA2, 5>, 2, PeripheralToMemory> for CRYP
impl DMASet<StreamX<DMA2, 5>, 4, PeripheralToMemory> for USART1
impl DMASet<StreamX<DMA2, 5>, 6, PeripheralToMemory> for DMAR<TIM1>
impl DMASet<StreamX<DMA2, 5>, 7, PeripheralToMemory> for SPI5
impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR1<TIM1>
impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR2<TIM1>
impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR3<TIM1>
impl DMASet<StreamX<DMA2, 6>, 1, PeripheralToMemory> for SPI6
impl DMASet<StreamX<DMA2, 6>, 4, PeripheralToMemory> for SDIO
impl DMASet<StreamX<DMA2, 6>, 6, PeripheralToMemory> for CCR3<TIM1>
impl DMASet<StreamX<DMA2, 7>, 1, PeripheralToMemory> for DCMI
impl DMASet<StreamX<DMA2, 7>, 7, PeripheralToMemory> for CCR4<TIM8>
impl DMASet<StreamX<DMA2, 7>, 7, PeripheralToMemory> for DMAR<TIM8>
Auto Trait Implementations§
impl RefUnwindSafe for PeripheralToMemory
impl Send for PeripheralToMemory
impl Sync for PeripheralToMemory
impl Unpin for PeripheralToMemory
impl UnwindSafe for PeripheralToMemory
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more