Struct stm32f4::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CCR>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn vbate(&mut self) -> VBATE_W<'_>

Bit 22 - VBAT enable

pub fn adcpre(&mut self) -> ADCPRE_W<'_>

Bits 16:17 - ADC prescaler

impl W<u32, Reg<u32, _SR>>

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 5 - Overrun

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 26 - Overrun interrupt enable

pub fn res(&mut self) -> RES_W<'_>

Bits 24:25 - Resolution

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 30 - Start conversion of regular channels

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 28:29 - External trigger enable for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 24:27 - External event select for regular group

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 22 - Start conversion of injected channels

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 20:21 - External trigger enable for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 16:19 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn eocs(&mut self) -> EOCS_W<'_>

Bit 10 - End of conversion selection

pub fn dds(&mut self) -> DDS_W<'_>

Bit 9 - DMA disable selection (for single ADC mode)

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode (for single ADC mode)

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D Converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp18(&mut self) -> SMP18_W<'_>

Bits 24:26 - Channel 18 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sampling time selection

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sampling time selection

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sampling time selection

impl W<u32, Reg<u32, _JOFR>>

pub fn joffset(&mut self) -> JOFFSET_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data Register

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - Independent Data register

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - Control regidter

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - DBG_SLEEP

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - DBG_STOP

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - DBG_STANDBY

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - TRACE_IOEN

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - TRACE_MODE

impl W<u32, Reg<u32, _APB1_FZ>>

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 0 - DBG_TIM2_STOP

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - DBG_TIM3 _STOP

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 2 - DBG_TIM4_STOP

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 3 - DBG_TIM5_STOP

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - DBG_WWDG_STOP

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - DBG_IWDEG_STOP

pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>

Bit 21 - DBG_J2C1_SMBUS_TIMEOUT

pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W<'_>

Bit 22 - DBG_J2C2_SMBUS_TIMEOUT

pub fn dbg_i2c3smbus_timeout(&mut self) -> DBG_I2C3SMBUS_TIMEOUT_W<'_>

Bit 23 - DBG_J2C3SMBUS_TIMEOUT

impl W<u32, Reg<u32, _APB2_FZ>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 0 - TIM1 counter stopped when core is halted

pub fn dbg_tim9_stop(&mut self) -> DBG_TIM9_STOP_W<'_>

Bit 16 - TIM9 counter stopped when core is halted

pub fn dbg_tim10_stop(&mut self) -> DBG_TIM10_STOP_W<'_>

Bit 17 - TIM10 counter stopped when core is halted

pub fn dbg_tim11_stop(&mut self) -> DBG_TIM11_STOP_W<'_>

Bit 18 - TIM11 counter stopped when core is halted

impl W<u32, Reg<u32, _IMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Interrupt Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Interrupt Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Interrupt Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Interrupt Mask on line 22

impl W<u32, Reg<u32, _EMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Event Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Event Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Event Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Event Mask on line 22

impl W<u32, Reg<u32, _RTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Rising trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Rising trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Rising trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Rising trigger event configuration of line 22

impl W<u32, Reg<u32, _FTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Falling trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Falling trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Falling trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Falling trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Falling trigger event configuration of line 22

impl W<u32, Reg<u32, _SWIER>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

pub fn swier19(&mut self) -> SWIER19_W<'_>

Bit 19 - Software Interrupt on line 19

pub fn swier20(&mut self) -> SWIER20_W<'_>

Bit 20 - Software Interrupt on line 20

pub fn swier21(&mut self) -> SWIER21_W<'_>

Bit 21 - Software Interrupt on line 21

pub fn swier22(&mut self) -> SWIER22_W<'_>

Bit 22 - Software Interrupt on line 22

impl W<u32, Reg<u32, _PR>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

pub fn pr19(&mut self) -> PR19_W<'_>

Bit 19 - Pending bit 19

pub fn pr20(&mut self) -> PR20_W<'_>

Bit 20 - Pending bit 20

pub fn pr21(&mut self) -> PR21_W<'_>

Bit 21 - Pending bit 21

pub fn pr22(&mut self) -> PR22_W<'_>

Bit 22 - Pending bit 22

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn dcen(&mut self) -> DCEN_W<'_>

Bit 10 - Data cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn dcrst(&mut self) -> DCRST_W<'_>

Bit 12 - Data cache reset

impl W<u32, Reg<u32, _KEYR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - FPEC key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkey(&mut self) -> OPTKEY_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protection error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn pgperr(&mut self) -> PGPERR_W<'_>

Bit 6 - Programming parallelism error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn ser(&mut self) -> SER_W<'_>

Bit 1 - Sector Erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass Erase

pub fn snb(&mut self) -> SNB_W<'_>

Bits 3:6 - Sector number

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Program size

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - Lock

impl W<u32, Reg<u32, _OPTCR>>

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 0 - Option lock

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 1 - Option start

pub fn bor_lev(&mut self) -> BOR_LEV_W<'_>

Bits 2:3 - BOR reset Level

pub fn wdg_sw(&mut self) -> WDG_SW_W<'_>

Bit 5 - WDG_SW User option bytes

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 6 - nRST_STOP User option bytes

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 7 - nRST_STDBY User option bytes

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 8:15 - Read protect

pub fn n_wrp(&mut self) -> NWRP_W<'_>

Bits 16:27 - Not write protect

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _DCFG>>

pub fn dspd(&mut self) -> DSPD_W<'_>

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>

Bit 2 - Non-zero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>

Bits 11:12 - Periodic frame interval

impl W<u32, Reg<u32, _DCTL>>

pub fn rwusig(&mut self) -> RWUSIG_W<'_>

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _DIEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

impl W<u32, Reg<u32, _DOEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>

Bit 4 - OUT token received when endpoint disabled mask

impl W<u32, Reg<u32, _DAINTMSK>>

pub fn iepm(&mut self) -> IEPM_W<'_>

Bits 0:15 - IN EP interrupt mask bits

pub fn oepm(&mut self) -> OEPM_W<'_>

Bits 16:31 - OUT EP interrupt mask bits

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _DIEPCTL0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:1 - Maximum packet size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPCTL>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm_sd1pid(&mut self) -> SODDFRM_SD1PID_W<'_>

Bit 29 - SODDFRM/SD1PID

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL0>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

impl W<u32, Reg<u32, _DOEPCTL>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPINT0>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT1>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT2>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT3>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT0>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT1>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT2>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT3>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPTSIZ0>>

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ0>>

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>

Bits 29:30 - SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bit 19 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ1>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ2>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ3>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ1>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ2>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ3>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _GOTGCTL>>

pub fn srq(&mut self) -> SRQ_W<'_>

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>

Bit 11 - Device HNP enabled

impl W<u32, Reg<u32, _GOTGINT>>

pub fn sedet(&mut self) -> SEDET_W<'_>

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>

Bit 19 - Debounce done

impl W<u32, Reg<u32, _GAHBCFG>>

pub fn gint(&mut self) -> GINT_W<'_>

Bit 0 - Global interrupt mask

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _GUSBCFG>>

pub fn tocal(&mut self) -> TOCAL_W<'_>

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>

Bit 6 - Full Speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>

Bits 10:13 - USB turnaround time

pub fn fhmod(&mut self) -> FHMOD_W<'_>

Bit 29 - Force host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>

Bit 30 - Force device mode

pub fn ctxpkt(&mut self) -> CTXPKT_W<'_>

Bit 31 - Corrupt Tx packet

impl W<u32, Reg<u32, _GRSTCTL>>

pub fn csrst(&mut self) -> CSRST_W<'_>

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _GINTSTS>>

pub fn mmis(&mut self) -> MMIS_W<'_>

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>

Bit 20 - Incomplete isochronous IN transfer

pub fn ipxfr_incompisoout(&mut self) -> IPXFR_INCOMPISOOUT_W<'_>

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>

Bit 30 - Session request/new session detected interrupt

pub fn wkupint(&mut self) -> WKUPINT_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _GINTMSK>>

pub fn mmism(&mut self) -> MMISM_W<'_>

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>

Bit 4 - Receive FIFO non-empty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>

Bit 5 - Non-periodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>

Bit 6 - Global non-periodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>

Bit 15 - End of periodic frame interrupt mask

pub fn epmism(&mut self) -> EPMISM_W<'_>

Bit 17 - Endpoint mismatch interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>

Bit 20 - Incomplete isochronous IN transfer mask

pub fn ipxfrm_iisooxfrm(&mut self) -> IPXFRM_IISOOXFRM_W<'_>

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

pub fn hcim(&mut self) -> HCIM_W<'_>

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt mask

impl W<u32, Reg<u32, _GRXFSIZ>>

pub fn rxfd(&mut self) -> RXFD_W<'_>

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF0>>

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _HNPTXFSIZ>>

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>

Bits 0:15 - Non-periodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>

Bits 16:31 - Non-periodic TxFIFO depth

impl W<u32, Reg<u32, _GCCFG>>

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>

Bit 16 - Power down

pub fn vbusasen(&mut self) -> VBUSASEN_W<'_>

Bit 18 - Enable the VBUS sensing device

pub fn vbusbsen(&mut self) -> VBUSBSEN_W<'_>

Bit 19 - Enable the VBUS sensing device

pub fn sofouten(&mut self) -> SOFOUTEN_W<'_>

Bit 20 - SOF output enable

impl W<u32, Reg<u32, _CID>>

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _HPTXFSIZ>>

pub fn ptxsa(&mut self) -> PTXSA_W<'_>

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfsiz(&mut self) -> PTXFSIZ_W<'_>

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _HCFG>>

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _HFIR>>

pub fn frivl(&mut self) -> FRIVL_W<'_>

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _HPTXSTS>>

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _HAINTMSK>>

pub fn haintm(&mut self) -> HAINTM_W<'_>

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _HPRT>>

pub fn pcdet(&mut self) -> PCDET_W<'_>

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _HCCHAR0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR4>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR5>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR6>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR7>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINTMSK0>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK2>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK3>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK4>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK5>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK6>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK7>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ5>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ6>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ7>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _PCGCCTL>>

pub fn stppclk(&mut self) -> STPPCLK_W<'_>

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>

Bit 4 - PHY Suspended

impl W<u32, Reg<u32, _CR>>

pub fn vos(&mut self) -> VOS_W<'_>

Bits 14:15 - Regulator voltage scaling output selection

pub fn adcdc1(&mut self) -> ADCDC1_W<'_>

Bit 13 - ADCDC1

pub fn fpds(&mut self) -> FPDS_W<'_>

Bit 9 - Flash power down in Stop mode

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD level selection

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power voltage detector enable

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear standby flag

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear wakeup flag

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power down deepsleep

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low-power deep sleep

impl W<u32, Reg<u32, _CSR>>

pub fn ewup(&mut self) -> EWUP_W<'_>

Bit 8 - Enable WKUP pin

pub fn bre(&mut self) -> BRE_W<'_>

Bit 9 - Backup regulator enable

pub fn vosrdy(&mut self) -> VOSRDY_W<'_>

Bit 14 - Regulator voltage scaling output selection ready bit

impl W<u32, Reg<u32, _CR>>

pub fn plli2son(&mut self) -> PLLI2SON_W<'_>

Bit 26 - PLLI2S enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - Main PLL (PLL) enable

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE clock bypass

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal high-speed clock trimming

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal high-speed clock enable

impl W<u32, Reg<u32, _PLLCFGR>>

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 6:14 - Main PLL (PLL) multiplication factor for VCO

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 16:17 - Main PLL (PLL) division factor for main system clock

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks

impl W<u32, Reg<u32, _CFGR>>

pub fn mco2(&mut self) -> MCO2_W<'_>

Bits 30:31 - Microcontroller clock output 2

pub fn mco2pre(&mut self) -> MCO2PRE_W<'_>

Bits 27:29 - MCO2 prescaler

pub fn mco1pre(&mut self) -> MCO1PRE_W<'_>

Bits 24:26 - MCO1 prescaler

pub fn i2ssrc(&mut self) -> I2SSRC_W<'_>

Bit 23 - I2S clock selection

pub fn mco1(&mut self) -> MCO1_W<'_>

Bits 21:22 - Microcontroller clock output 1

pub fn rtcpre(&mut self) -> RTCPRE_W<'_>

Bits 16:20 - HSE division factor for RTC clock

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 13:15 - APB high-speed prescaler (APB2)

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 10:12 - APB Low speed prescaler (APB1)

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock switch

pub fn sws(&mut self) -> SWS_W<'_>

Bits 2:3 - System clock switch status

impl W<u32, Reg<u32, _CIR>>

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

pub fn plli2srdyc(&mut self) -> PLLI2SRDYC_W<'_>

Bit 21 - PLLI2S ready interrupt clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - Main PLL(PLL) ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE ready interrupt clear

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI ready interrupt clear

pub fn plli2srdyie(&mut self) -> PLLI2SRDYIE_W<'_>

Bit 13 - PLLI2S ready interrupt enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - Main PLL (PLL) ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE ready interrupt enable

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI ready interrupt enable

impl W<u32, Reg<u32, _AHB1RSTR>>

pub fn dma2rst(&mut self) -> DMA2RST_W<'_>

Bit 22 - DMA2 reset

pub fn dma1rst(&mut self) -> DMA1RST_W<'_>

Bit 21 - DMA2 reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 12 - CRC reset

pub fn gpiohrst(&mut self) -> GPIOHRST_W<'_>

Bit 7 - IO port H reset

pub fn gpioerst(&mut self) -> GPIOERST_W<'_>

Bit 4 - IO port E reset

pub fn gpiodrst(&mut self) -> GPIODRST_W<'_>

Bit 3 - IO port D reset

pub fn gpiocrst(&mut self) -> GPIOCRST_W<'_>

Bit 2 - IO port C reset

pub fn gpiobrst(&mut self) -> GPIOBRST_W<'_>

Bit 1 - IO port B reset

pub fn gpioarst(&mut self) -> GPIOARST_W<'_>

Bit 0 - IO port A reset

impl W<u32, Reg<u32, _AHB2RSTR>>

pub fn otgfsrst(&mut self) -> OTGFSRST_W<'_>

Bit 7 - USB OTG FS module reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn i2c3rst(&mut self) -> I2C3RST_W<'_>

Bit 23 - I2C3 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C 2 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C 1 reset

pub fn uart2rst(&mut self) -> UART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI 3 reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI 2 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>

Bit 3 - TIM5 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - TIM4 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - TIM3 reset

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 reset

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn tim11rst(&mut self) -> TIM11RST_W<'_>

Bit 18 - TIM11 reset

pub fn tim10rst(&mut self) -> TIM10RST_W<'_>

Bit 17 - TIM10 reset

pub fn tim9rst(&mut self) -> TIM9RST_W<'_>

Bit 16 - TIM9 reset

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 14 - System configuration controller reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn sdiorst(&mut self) -> SDIORST_W<'_>

Bit 11 - SDIO reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 8 - ADC interface reset (common to all ADCs)

pub fn usart6rst(&mut self) -> USART6RST_W<'_>

Bit 5 - USART6 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 4 - USART1 reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 0 - TIM1 reset

pub fn spi4rst(&mut self) -> SPI4RST_W<'_>

Bit 13 - SPI4 reset

impl W<u32, Reg<u32, _AHB1ENR>>

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 22 - DMA2 clock enable

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 21 - DMA1 clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CRC clock enable

pub fn gpiohen(&mut self) -> GPIOHEN_W<'_>

Bit 7 - IO port H clock enable

pub fn gpioeen(&mut self) -> GPIOEEN_W<'_>

Bit 4 - IO port E clock enable

pub fn gpioden(&mut self) -> GPIODEN_W<'_>

Bit 3 - IO port D clock enable

pub fn gpiocen(&mut self) -> GPIOCEN_W<'_>

Bit 2 - IO port C clock enable

pub fn gpioben(&mut self) -> GPIOBEN_W<'_>

Bit 1 - IO port B clock enable

pub fn gpioaen(&mut self) -> GPIOAEN_W<'_>

Bit 0 - IO port A clock enable

impl W<u32, Reg<u32, _AHB2ENR>>

pub fn otgfsen(&mut self) -> OTGFSEN_W<'_>

Bit 7 - USB OTG FS clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>

Bit 23 - I2C3 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI3 clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>

Bit 3 - TIM5 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - TIM4 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 clock enable

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - TIM2 clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn tim11en(&mut self) -> TIM11EN_W<'_>

Bit 18 - TIM11 clock enable

pub fn tim10en(&mut self) -> TIM10EN_W<'_>

Bit 17 - TIM10 clock enable

pub fn tim9en(&mut self) -> TIM9EN_W<'_>

Bit 16 - TIM9 clock enable

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 14 - System configuration controller clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SDIO clock enable

pub fn adc1en(&mut self) -> ADC1EN_W<'_>

Bit 8 - ADC1 clock enable

pub fn usart6en(&mut self) -> USART6EN_W<'_>

Bit 5 - USART6 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 4 - USART1 clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 0 - TIM1 clock enable

pub fn spi4en(&mut self) -> SPI4EN_W<'_>

Bit 13 - SPI4 clock enable

impl W<u32, Reg<u32, _AHB1LPENR>>

pub fn dma2lpen(&mut self) -> DMA2LPEN_W<'_>

Bit 22 - DMA2 clock enable during Sleep mode

pub fn dma1lpen(&mut self) -> DMA1LPEN_W<'_>

Bit 21 - DMA1 clock enable during Sleep mode

pub fn sram1lpen(&mut self) -> SRAM1LPEN_W<'_>

Bit 16 - SRAM 1interface clock enable during Sleep mode

pub fn flitflpen(&mut self) -> FLITFLPEN_W<'_>

Bit 15 - Flash interface clock enable during Sleep mode

pub fn crclpen(&mut self) -> CRCLPEN_W<'_>

Bit 12 - CRC clock enable during Sleep mode

pub fn gpiohlpen(&mut self) -> GPIOHLPEN_W<'_>

Bit 7 - IO port H clock enable during Sleep mode

pub fn gpioelpen(&mut self) -> GPIOELPEN_W<'_>

Bit 4 - IO port E clock enable during Sleep mode

pub fn gpiodlpen(&mut self) -> GPIODLPEN_W<'_>

Bit 3 - IO port D clock enable during Sleep mode

pub fn gpioclpen(&mut self) -> GPIOCLPEN_W<'_>

Bit 2 - IO port C clock enable during Sleep mode

pub fn gpioblpen(&mut self) -> GPIOBLPEN_W<'_>

Bit 1 - IO port B clock enable during Sleep mode

pub fn gpioalpen(&mut self) -> GPIOALPEN_W<'_>

Bit 0 - IO port A clock enable during sleep mode

impl W<u32, Reg<u32, _AHB2LPENR>>

pub fn otgfslpen(&mut self) -> OTGFSLPEN_W<'_>

Bit 7 - USB OTG FS clock enable during Sleep mode

impl W<u32, Reg<u32, _APB1LPENR>>

pub fn pwrlpen(&mut self) -> PWRLPEN_W<'_>

Bit 28 - Power interface clock enable during Sleep mode

pub fn i2c3lpen(&mut self) -> I2C3LPEN_W<'_>

Bit 23 - I2C3 clock enable during Sleep mode

pub fn i2c2lpen(&mut self) -> I2C2LPEN_W<'_>

Bit 22 - I2C2 clock enable during Sleep mode

pub fn i2c1lpen(&mut self) -> I2C1LPEN_W<'_>

Bit 21 - I2C1 clock enable during Sleep mode

pub fn usart2lpen(&mut self) -> USART2LPEN_W<'_>

Bit 17 - USART2 clock enable during Sleep mode

pub fn spi3lpen(&mut self) -> SPI3LPEN_W<'_>

Bit 15 - SPI3 clock enable during Sleep mode

pub fn spi2lpen(&mut self) -> SPI2LPEN_W<'_>

Bit 14 - SPI2 clock enable during Sleep mode

pub fn wwdglpen(&mut self) -> WWDGLPEN_W<'_>

Bit 11 - Window watchdog clock enable during Sleep mode

pub fn tim5lpen(&mut self) -> TIM5LPEN_W<'_>

Bit 3 - TIM5 clock enable during Sleep mode

pub fn tim4lpen(&mut self) -> TIM4LPEN_W<'_>

Bit 2 - TIM4 clock enable during Sleep mode

pub fn tim3lpen(&mut self) -> TIM3LPEN_W<'_>

Bit 1 - TIM3 clock enable during Sleep mode

pub fn tim2lpen(&mut self) -> TIM2LPEN_W<'_>

Bit 0 - TIM2 clock enable during Sleep mode

impl W<u32, Reg<u32, _APB2LPENR>>

pub fn tim11lpen(&mut self) -> TIM11LPEN_W<'_>

Bit 18 - TIM11 clock enable during Sleep mode

pub fn tim10lpen(&mut self) -> TIM10LPEN_W<'_>

Bit 17 - TIM10 clock enable during Sleep mode

pub fn tim9lpen(&mut self) -> TIM9LPEN_W<'_>

Bit 16 - TIM9 clock enable during sleep mode

pub fn syscfglpen(&mut self) -> SYSCFGLPEN_W<'_>

Bit 14 - System configuration controller clock enable during Sleep mode

pub fn spi1lpen(&mut self) -> SPI1LPEN_W<'_>

Bit 12 - SPI 1 clock enable during Sleep mode

pub fn sdiolpen(&mut self) -> SDIOLPEN_W<'_>

Bit 11 - SDIO clock enable during Sleep mode

pub fn adc1lpen(&mut self) -> ADC1LPEN_W<'_>

Bit 8 - ADC1 clock enable during Sleep mode

pub fn usart6lpen(&mut self) -> USART6LPEN_W<'_>

Bit 5 - USART6 clock enable during Sleep mode

pub fn usart1lpen(&mut self) -> USART1LPEN_W<'_>

Bit 4 - USART1 clock enable during Sleep mode

pub fn tim1lpen(&mut self) -> TIM1LPEN_W<'_>

Bit 0 - TIM1 clock enable during Sleep mode

pub fn spi4lpen(&mut self) -> SPI4LPEN_W<'_>

Bit 13 - SPI4 clock enable during Sleep mode

impl W<u32, Reg<u32, _BDCR>>

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External low-speed oscillator bypass

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External low-speed oscillator enable

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

impl W<u32, Reg<u32, _CSR>>

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn wdgrstf(&mut self) -> WDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn padrstf(&mut self) -> PADRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn borrstf(&mut self) -> BORRSTF_W<'_>

Bit 25 - BOR reset flag

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low-speed oscillator enable

impl W<u32, Reg<u32, _SSCGR>>

pub fn sscgen(&mut self) -> SSCGEN_W<'_>

Bit 31 - Spread spectrum modulation enable

pub fn spreadsel(&mut self) -> SPREADSEL_W<'_>

Bit 30 - Spread Select

pub fn incstep(&mut self) -> INCSTEP_W<'_>

Bits 13:27 - Incrementation step

pub fn modper(&mut self) -> MODPER_W<'_>

Bits 0:12 - Modulation period

impl W<u32, Reg<u32, _PLLI2SCFGR>>

pub fn plli2sr(&mut self) -> PLLI2SR_W<'_>

Bits 28:30 - PLLI2S division factor for I2S clocks

pub fn plli2sn(&mut self) -> PLLI2SN_W<'_>

Bits 6:14 - PLLI2S multiplication factor for VCO

impl W<u32, Reg<u32, _DCKCFGR>>

pub fn timpre(&mut self) -> TIMPRE_W<'_>

Bit 24 - Timers clocks prescalers selection

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - Calibration output enable

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - Output selection

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - Output polarity

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - Calibration Output selection

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - Backup

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - Subtract 1 hour (winter time change)

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - Add 1 hour (summer time change)

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - Time-stamp interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - Wakeup timer interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - Alarm B interrupt enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - Alarm A interrupt enable

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - Time stamp enable

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - Wakeup timer enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - Alarm B enable

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - Alarm A enable

pub fn dce(&mut self) -> DCE_W<'_>

Bit 7 - Coarse digital calibration enable

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - Hour format

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - Bypass the shadow registers

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - Time-stamp event active edge

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - Wakeup clock selection

impl W<u32, Reg<u32, _ISR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

pub fn alraf(&mut self) -> ALRAF_W<'_>

Bit 8 - Alarm A flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>

Bit 9 - Alarm B flag

pub fn wutf(&mut self) -> WUTF_W<'_>

Bit 10 - Wakeup timer flag

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 11 - Time-stamp flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>

Bit 12 - Time-stamp overflow flag

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>

Bit 13 - Tamper detection flag

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>

Bit 14 - TAMPER2 detection flag

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _CALIBR>>

pub fn dcs(&mut self) -> DCS_W<'_>

Bit 7 - Digital calibration sign

pub fn dc(&mut self) -> DC_W<'_>

Bits 0:4 - Digital calibration

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAFCR>>

pub fn alarmouttype(&mut self) -> ALARMOUTTYPE_W<'_>

Bit 18 - AFO_ALARM output type

pub fn tsinsel(&mut self) -> TSINSEL_W<'_>

Bit 17 - TIMESTAMP mapping

pub fn tamp1insel(&mut self) -> TAMP1INSEL_W<'_>

Bit 16 - TAMPER1 mapping

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 15 - TAMPER pull-up disable

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 13:14 - Tamper precharge duration

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 11:12 - Tamper filter count

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 8:10 - Tamper sampling frequency

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 7 - Activate timestamp on tamper detection event

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 4 - Active level for tamper 2

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 3 - Tamper 2 detection enable

pub fn tampie(&mut self) -> TAMPIE_W<'_>

Bit 2 - Tamper interrupt enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 1 - Active level for tamper 1

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - Tamper 1 detection enable

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _BKPR>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _POWER>>

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>

Bit 14 - HW Flow Control enable

pub fn negedge(&mut self) -> NEGEDGE_W<'_>

Bit 13 - SDIO_CK dephasing selection bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>

Bits 11:12 - Wide bus mode enable bit

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 10 - Clock divider bypass enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>

Bit 9 - Power saving configuration bit

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 8 - Clock enable bit

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 0:7 - Clock divide factor

impl W<u32, Reg<u32, _ARG>>

pub fn cmdarg(&mut self) -> CMDARG_W<'_>

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>

pub fn ce_atacmd(&mut self) -> CE_ATACMD_W<'_>

Bit 14 - CE-ATA command

pub fn n_ien(&mut self) -> NIEN_W<'_>

Bit 13 - not Interrupt Enable

pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W<'_>

Bit 12 - Enable CMD completion

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>

Bit 11 - SD I/O suspend command

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>

Bit 10 - Command path state machine (CPSM) Enable bit

pub fn waitpend(&mut self) -> WAITPEND_W<'_>

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).

pub fn waitint(&mut self) -> WAITINT_W<'_>

Bit 8 - CPSM waits for interrupt request

pub fn waitresp(&mut self) -> WAITRESP_W<'_>

Bits 6:7 - Wait for response bits

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>

Bits 0:5 - Command index

impl W<u32, Reg<u32, _DTIMER>>

pub fn datatime(&mut self) -> DATATIME_W<'_>

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>

pub fn datalength(&mut self) -> DATALENGTH_W<'_>

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SD I/O enable functions

pub fn rwmod(&mut self) -> RWMOD_W<'_>

Bit 10 - Read wait mode

pub fn rwstop(&mut self) -> RWSTOP_W<'_>

Bit 9 - Read wait stop

pub fn rwstart(&mut self) -> RWSTART_W<'_>

Bit 8 - Read wait start

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>

Bits 4:7 - Data block size

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 3 - DMA enable bit

pub fn dtmode(&mut self) -> DTMODE_W<'_>

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

pub fn dtdir(&mut self) -> DTDIR_W<'_>

Bit 1 - Data transfer direction selection

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTEN

impl W<u32, Reg<u32, _ICR>>

pub fn ceataendc(&mut self) -> CEATAENDC_W<'_>

Bit 23 - CEATAEND flag clear bit

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>

Bit 22 - SDIOIT flag clear bit

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>

Bit 10 - DBCKEND flag clear bit

pub fn stbiterrc(&mut self) -> STBITERRC_W<'_>

Bit 9 - STBITERR flag clear bit

pub fn dataendc(&mut self) -> DATAENDC_W<'_>

Bit 8 - DATAEND flag clear bit

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>

Bit 7 - CMDSENT flag clear bit

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>

Bit 6 - CMDREND flag clear bit

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>

Bit 5 - RXOVERR flag clear bit

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>

Bit 4 - TXUNDERR flag clear bit

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>

Bit 3 - DTIMEOUT flag clear bit

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>

Bit 2 - CTIMEOUT flag clear bit

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>

Bit 1 - DCRCFAIL flag clear bit

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>

Bit 0 - CCRCFAIL flag clear bit

impl W<u32, Reg<u32, _MASK>>

pub fn ceataendie(&mut self) -> CEATAENDIE_W<'_>

Bit 23 - CE-ATA command completion signal received interrupt enable

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>

Bit 22 - SDIO mode interrupt received interrupt enable

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>

Bit 21 - Data available in Rx FIFO interrupt enable

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>

Bit 20 - Data available in Tx FIFO interrupt enable

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>

Bit 19 - Rx FIFO empty interrupt enable

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>

Bit 18 - Tx FIFO empty interrupt enable

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>

Bit 17 - Rx FIFO full interrupt enable

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>

Bit 16 - Tx FIFO full interrupt enable

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>

Bit 15 - Rx FIFO half full interrupt enable

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>

Bit 14 - Tx FIFO half empty interrupt enable

pub fn rxactie(&mut self) -> RXACTIE_W<'_>

Bit 13 - Data receive acting interrupt enable

pub fn txactie(&mut self) -> TXACTIE_W<'_>

Bit 12 - Data transmit acting interrupt enable

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>

Bit 11 - Command acting interrupt enable

pub fn dbckendie(&mut self) -> DBCKENDIE_W<'_>

Bit 10 - Data block end interrupt enable

pub fn stbiterrie(&mut self) -> STBITERRIE_W<'_>

Bit 9 - Start bit error interrupt enable

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>

Bit 8 - Data end interrupt enable

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>

Bit 7 - Command sent interrupt enable

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>

Bit 6 - Command response received interrupt enable

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>

Bit 5 - Rx FIFO overrun error interrupt enable

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>

Bit 4 - Tx FIFO underrun error interrupt enable

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>

Bit 3 - Data timeout interrupt enable

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>

Bit 2 - Command timeout interrupt enable

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>

Bit 1 - Data CRC fail interrupt enable

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>

Bit 0 - Command CRC fail interrupt enable

impl W<u32, Reg<u32, _FIFO>>

pub fn fifodata(&mut self) -> FIFODATA_W<'_>

Bits 0:31 - Receive and transmit FIFO data

impl W<u32, Reg<u32, _MEMRM>>

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:1 - MEM_MODE

impl W<u32, Reg<u32, _PMC>>

pub fn adc1dc2(&mut self) -> ADC1DC2_W<'_>

Bit 16 - ADC1DC2

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI x configuration (x = 0 to 3)

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI x configuration (x = 0 to 3)

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI x configuration (x = 0 to 3)

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI x configuration (x = 0 to 3)

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI x configuration (x = 4 to 7)

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI x configuration (x = 4 to 7)

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI x configuration (x = 4 to 7)

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI x configuration (x = 4 to 7)

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI x configuration (x = 8 to 11)

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI10

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI x configuration (x = 8 to 11)

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI x configuration (x = 8 to 11)

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI x configuration (x = 12 to 15)

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI x configuration (x = 12 to 15)

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI x configuration (x = 12 to 15)

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI x configuration (x = 12 to 15)

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _OR>>

pub fn rmp(&mut self) -> RMP_W<'_>

Bits 0:1 - Input 1 remapping capability

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn itr1_rmp(&mut self) -> ITR1_RMP_W<'_>

Bits 10:11 - Timer Input 4 remap

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn it4_rmp(&mut self) -> IT4_RMP_W<'_>

Bits 6:7 - Timer Input 4 remap

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:14 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:6 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _SR>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 9 - CTS flag

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - Data value

impl W<u32, Reg<u32, _BRR>>

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - mantissa of USARTDIV

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - fraction of USARTDIV

impl W<u32, Reg<u32, _CR1>>

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

impl W<u32, Reg<u32, _CR2>>

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _CR>>

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 25:27 - Channel selection

pub fn mburst(&mut self) -> MBURST_W<'_>

Bits 23:24 - Memory burst transfer configuration

pub fn pburst(&mut self) -> PBURST_W<'_>

Bits 21:22 - Peripheral burst transfer configuration

pub fn ct(&mut self) -> CT_W<'_>

Bit 19 - Current target (only in double buffer mode)

pub fn dbm(&mut self) -> DBM_W<'_>

Bit 18 - Double buffer mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 16:17 - Priority level

pub fn pincos(&mut self) -> PINCOS_W<'_>

Bit 15 - Peripheral increment offset size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 13:14 - Memory data size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 11:12 - Peripheral data size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 10 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 9 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 8 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bits 6:7 - Data transfer direction

pub fn pfctrl(&mut self) -> PFCTRL_W<'_>

Bit 5 - Peripheral flow controller

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 4 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 3 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 2 - Transfer error interrupt enable

pub fn dmeie(&mut self) -> DMEIE_W<'_>

Bit 1 - Direct mode error interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Stream enable / flag stream ready when read low

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data items to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _M0AR>>

pub fn m0a(&mut self) -> M0A_W<'_>

Bits 0:31 - Memory 0 address

impl W<u32, Reg<u32, _M1AR>>

pub fn m1a(&mut self) -> M1A_W<'_>

Bits 0:31 - Memory 1 address (used in case of Double buffer mode)

impl W<u32, Reg<u32, _FCR>>

pub fn feie(&mut self) -> FEIE_W<'_>

Bit 7 - FIFO error interrupt enable

pub fn dmdis(&mut self) -> DMDIS_W<'_>

Bit 2 - Direct mode disable

pub fn fth(&mut self) -> FTH_W<'_>

Bits 0:1 - FIFO threshold selection

impl W<u32, Reg<u32, _LIFCR>>

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif3(&mut self) -> CDMEIF3_W<'_>

Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif3(&mut self) -> CFEIF3_W<'_>

Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif2(&mut self) -> CDMEIF2_W<'_>

Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif2(&mut self) -> CFEIF2_W<'_>

Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif1(&mut self) -> CDMEIF1_W<'_>

Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif1(&mut self) -> CFEIF1_W<'_>

Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif0(&mut self) -> CTCIF0_W<'_>

Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif0(&mut self) -> CHTIF0_W<'_>

Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif0(&mut self) -> CTEIF0_W<'_>

Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif0(&mut self) -> CDMEIF0_W<'_>

Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif0(&mut self) -> CFEIF0_W<'_>

Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)

impl W<u32, Reg<u32, _HIFCR>>

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif7(&mut self) -> CDMEIF7_W<'_>

Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif7(&mut self) -> CFEIF7_W<'_>

Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif6(&mut self) -> CDMEIF6_W<'_>

Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif6(&mut self) -> CFEIF6_W<'_>

Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif5(&mut self) -> CDMEIF5_W<'_>

Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif5(&mut self) -> CFEIF5_W<'_>

Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif4(&mut self) -> CDMEIF4_W<'_>

Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif4(&mut self) -> CFEIF4_W<'_>

Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _CR1>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 15 - Software reset

pub fn alert(&mut self) -> ALERT_W<'_>

Bit 13 - SMBus alert

pub fn pec(&mut self) -> PEC_W<'_>

Bit 12 - Packet error checking

pub fn pos(&mut self) -> POS_W<'_>

Bit 11 - Acknowledge/PEC Position (for data reception)

pub fn ack(&mut self) -> ACK_W<'_>

Bit 10 - Acknowledge enable

pub fn stop(&mut self) -> STOP_W<'_>

Bit 9 - Stop generation

pub fn start(&mut self) -> START_W<'_>

Bit 8 - Start generation

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 7 - Clock stretching disable (Slave mode)

pub fn engc(&mut self) -> ENGC_W<'_>

Bit 6 - General call enable

pub fn enpec(&mut self) -> ENPEC_W<'_>

Bit 5 - PEC enable

pub fn enarp(&mut self) -> ENARP_W<'_>

Bit 4 - ARP enable

pub fn smbtype(&mut self) -> SMBTYPE_W<'_>

Bit 3 - SMBus type

pub fn smbus(&mut self) -> SMBUS_W<'_>

Bit 1 - SMBus mode

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

impl W<u32, Reg<u32, _CR2>>

pub fn last(&mut self) -> LAST_W<'_>

Bit 12 - DMA last transfer

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 11 - DMA requests enable

pub fn itbufen(&mut self) -> ITBUFEN_W<'_>

Bit 10 - Buffer interrupt enable

pub fn itevten(&mut self) -> ITEVTEN_W<'_>

Bit 9 - Event interrupt enable

pub fn iterren(&mut self) -> ITERREN_W<'_>

Bit 8 - Error interrupt enable

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:5 - Peripheral clock frequency

impl W<u32, Reg<u32, _OAR1>>

pub fn addmode(&mut self) -> ADDMODE_W<'_>

Bit 15 - Addressing mode (slave mode)

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn add2(&mut self) -> ADD2_W<'_>

Bits 1:7 - Interface address

pub fn endual(&mut self) -> ENDUAL_W<'_>

Bit 0 - Dual addressing mode enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:7 - 8-bit data register

impl W<u32, Reg<u32, _SR1>>

pub fn smbalert(&mut self) -> SMBALERT_W<'_>

Bit 15 - SMBus alert

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 14 - Timeout or Tlow error

pub fn pecerr(&mut self) -> PECERR_W<'_>

Bit 12 - PEC Error in reception

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 11 - Overrun/Underrun

pub fn af(&mut self) -> AF_W<'_>

Bit 10 - Acknowledge failure

pub fn arlo(&mut self) -> ARLO_W<'_>

Bit 9 - Arbitration lost (master mode)

pub fn berr(&mut self) -> BERR_W<'_>

Bit 8 - Bus error

impl W<u32, Reg<u32, _CCR>>

pub fn f_s(&mut self) -> F_S_W<'_>

Bit 15 - I2C master mode selection

pub fn duty(&mut self) -> DUTY_W<'_>

Bit 14 - Fast mode duty cycle

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _TRISE>>

pub fn trise(&mut self) -> TRISE_W<'_>

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

impl W<u32, Reg<u32, _I2SPR>>

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _CR>>

pub fn ie(&mut self) -> IE_W<'_>

Bit 3 - Interrupt enable

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 2 - Random number generator enable

impl W<u32, Reg<u32, _SR>>

pub fn seis(&mut self) -> SEIS_W<'_>

Bit 6 - Seed error interrupt status

pub fn ceis(&mut self) -> CEIS_W<'_>

Bit 5 - Clock error interrupt status

impl W<u32, Reg<u32, _CR>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 14 - DCMI enable

pub fn edm(&mut self) -> EDM_W<'_>

Bits 10:11 - Extended data mode

pub fn fcrc(&mut self) -> FCRC_W<'_>

Bits 8:9 - Frame capture rate control

pub fn vspol(&mut self) -> VSPOL_W<'_>

Bit 7 - Vertical synchronization polarity

pub fn hspol(&mut self) -> HSPOL_W<'_>

Bit 6 - Horizontal synchronization polarity

pub fn pckpol(&mut self) -> PCKPOL_W<'_>

Bit 5 - Pixel clock polarity

pub fn ess(&mut self) -> ESS_W<'_>

Bit 4 - Embedded synchronization select

pub fn jpeg(&mut self) -> JPEG_W<'_>

Bit 3 - JPEG format

pub fn crop(&mut self) -> CROP_W<'_>

Bit 2 - Crop feature

pub fn cm(&mut self) -> CM_W<'_>

Bit 1 - Capture mode

pub fn capture(&mut self) -> CAPTURE_W<'_>

Bit 0 - Capture enable

impl W<u32, Reg<u32, _IER>>

pub fn line_ie(&mut self) -> LINE_IE_W<'_>

Bit 4 - Line interrupt enable

pub fn vsync_ie(&mut self) -> VSYNC_IE_W<'_>

Bit 3 - VSYNC interrupt enable

pub fn err_ie(&mut self) -> ERR_IE_W<'_>

Bit 2 - Synchronization error interrupt enable

pub fn ovr_ie(&mut self) -> OVR_IE_W<'_>

Bit 1 - Overrun interrupt enable

pub fn frame_ie(&mut self) -> FRAME_IE_W<'_>

Bit 0 - Capture complete interrupt enable

impl W<u32, Reg<u32, _ICR>>

pub fn line_isc(&mut self) -> LINE_ISC_W<'_>

Bit 4 - line interrupt status clear

pub fn vsync_isc(&mut self) -> VSYNC_ISC_W<'_>

Bit 3 - Vertical synch interrupt status clear

pub fn err_isc(&mut self) -> ERR_ISC_W<'_>

Bit 2 - Synchronization error interrupt status clear

pub fn ovr_isc(&mut self) -> OVR_ISC_W<'_>

Bit 1 - Overrun interrupt status clear

pub fn frame_isc(&mut self) -> FRAME_ISC_W<'_>

Bit 0 - Capture complete interrupt status clear

impl W<u32, Reg<u32, _ESCR>>

pub fn fec(&mut self) -> FEC_W<'_>

Bits 24:31 - Frame end delimiter code

pub fn lec(&mut self) -> LEC_W<'_>

Bits 16:23 - Line end delimiter code

pub fn lsc(&mut self) -> LSC_W<'_>

Bits 8:15 - Line start delimiter code

pub fn fsc(&mut self) -> FSC_W<'_>

Bits 0:7 - Frame start delimiter code

impl W<u32, Reg<u32, _ESUR>>

pub fn feu(&mut self) -> FEU_W<'_>

Bits 24:31 - Frame end delimiter unmask

pub fn leu(&mut self) -> LEU_W<'_>

Bits 16:23 - Line end delimiter unmask

pub fn lsu(&mut self) -> LSU_W<'_>

Bits 8:15 - Line start delimiter unmask

pub fn fsu(&mut self) -> FSU_W<'_>

Bits 0:7 - Frame start delimiter unmask

impl W<u32, Reg<u32, _CWSTRT>>

pub fn vst(&mut self) -> VST_W<'_>

Bits 16:28 - Vertical start line count

pub fn hoffcnt(&mut self) -> HOFFCNT_W<'_>

Bits 0:13 - Horizontal offset count

impl W<u32, Reg<u32, _CWSIZE>>

pub fn vline(&mut self) -> VLINE_W<'_>

Bits 16:29 - Vertical line count

pub fn capcnt(&mut self) -> CAPCNT_W<'_>

Bits 0:13 - Capture count

impl W<u32, Reg<u32, _BCR1>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _BTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _PCR>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM2>>

pub fn memhiz(&mut self) -> MEMHIZ_W<'_>

Bits 24:31 - MEMHIZx

pub fn memhold(&mut self) -> MEMHOLD_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwait(&mut self) -> MEMWAIT_W<'_>

Bits 8:15 - MEMWAITx

pub fn memset(&mut self) -> MEMSET_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT2>>

pub fn atthiz(&mut self) -> ATTHIZ_W<'_>

Bits 24:31 - ATTHIZx

pub fn atthold(&mut self) -> ATTHOLD_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwait(&mut self) -> ATTWAIT_W<'_>

Bits 8:15 - ATTWAITx

pub fn attset(&mut self) -> ATTSET_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PMEM3>>

pub fn memhiz(&mut self) -> MEMHIZ_W<'_>

Bits 24:31 - MEMHIZx

pub fn memhold(&mut self) -> MEMHOLD_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwait(&mut self) -> MEMWAIT_W<'_>

Bits 8:15 - MEMWAITx

pub fn memset(&mut self) -> MEMSET_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT3>>

pub fn atthiz(&mut self) -> ATTHIZ_W<'_>

Bits 24:31 - ATTHIZx

pub fn atthold(&mut self) -> ATTHOLD_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwait(&mut self) -> ATTWAIT_W<'_>

Bits 8:15 - ATTWAITx

pub fn attset(&mut self) -> ATTSET_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PMEM4>>

pub fn memhiz(&mut self) -> MEMHIZ_W<'_>

Bits 24:31 - MEMHIZx

pub fn memhold(&mut self) -> MEMHOLD_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwait(&mut self) -> MEMWAIT_W<'_>

Bits 8:15 - MEMWAITx

pub fn memset(&mut self) -> MEMSET_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT4>>

pub fn atthiz(&mut self) -> ATTHIZ_W<'_>

Bits 24:31 - ATTHIZx

pub fn atthold(&mut self) -> ATTHOLD_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwait(&mut self) -> ATTWAIT_W<'_>

Bits 8:15 - ATTWAITx

pub fn attset(&mut self) -> ATTSET_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PIO4>>

pub fn iohizx(&mut self) -> IOHIZX_W<'_>

Bits 24:31 - IOHIZx

pub fn ioholdx(&mut self) -> IOHOLDX_W<'_>

Bits 16:23 - IOHOLDx

pub fn iowaitx(&mut self) -> IOWAITX_W<'_>

Bits 8:15 - IOWAITx

pub fn iosetx(&mut self) -> IOSETX_W<'_>

Bits 0:7 - IOSETx

impl W<u32, Reg<u32, _BWTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - DBG_SLEEP

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - DBG_STOP

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - DBG_STANDBY

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - TRACE_IOEN

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - TRACE_MODE

pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W<'_>

Bit 16 - DBG_I2C2_SMBUS_TIMEOUT

pub fn dbg_tim8_stop(&mut self) -> DBG_TIM8_STOP_W<'_>

Bit 17 - DBG_TIM8_STOP

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 18 - DBG_TIM5_STOP

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>

Bit 19 - DBG_TIM6_STOP

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 20 - DBG_TIM7_STOP

impl W<u32, Reg<u32, _APB1_FZ>>

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 0 - DBG_TIM2_STOP

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - DBG_TIM3 _STOP

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 2 - DBG_TIM4_STOP

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 3 - DBG_TIM5_STOP

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>

Bit 4 - DBG_TIM6_STOP

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 5 - DBG_TIM7_STOP

pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<'_>

Bit 6 - DBG_TIM12_STOP

pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<'_>

Bit 7 - DBG_TIM13_STOP

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>

Bit 8 - DBG_TIM14_STOP

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - DBG_WWDG_STOP

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - DBG_IWDEG_STOP

pub fn dbg_j2c1_smbus_timeout(&mut self) -> DBG_J2C1_SMBUS_TIMEOUT_W<'_>

Bit 21 - DBG_J2C1_SMBUS_TIMEOUT

pub fn dbg_j2c2_smbus_timeout(&mut self) -> DBG_J2C2_SMBUS_TIMEOUT_W<'_>

Bit 22 - DBG_J2C2_SMBUS_TIMEOUT

pub fn dbg_j2c3smbus_timeout(&mut self) -> DBG_J2C3SMBUS_TIMEOUT_W<'_>

Bit 23 - DBG_J2C3SMBUS_TIMEOUT

pub fn dbg_can1_stop(&mut self) -> DBG_CAN1_STOP_W<'_>

Bit 25 - DBG_CAN1_STOP

pub fn dbg_can2_stop(&mut self) -> DBG_CAN2_STOP_W<'_>

Bit 26 - DBG_CAN2_STOP

impl W<u32, Reg<u32, _APB2_FZ>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 0 - TIM1 counter stopped when core is halted

pub fn dbg_tim8_stop(&mut self) -> DBG_TIM8_STOP_W<'_>

Bit 1 - TIM8 counter stopped when core is halted

pub fn dbg_tim9_stop(&mut self) -> DBG_TIM9_STOP_W<'_>

Bit 16 - TIM9 counter stopped when core is halted

pub fn dbg_tim10_stop(&mut self) -> DBG_TIM10_STOP_W<'_>

Bit 17 - TIM10 counter stopped when core is halted

pub fn dbg_tim11_stop(&mut self) -> DBG_TIM11_STOP_W<'_>

Bit 18 - TIM11 counter stopped when core is halted

impl W<u32, Reg<u32, _CR>>

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 25:27 - Channel selection

pub fn mburst(&mut self) -> MBURST_W<'_>

Bits 23:24 - Memory burst transfer configuration

pub fn pburst(&mut self) -> PBURST_W<'_>

Bits 21:22 - Peripheral burst transfer configuration

pub fn ct(&mut self) -> CT_W<'_>

Bit 19 - Current target (only in double buffer mode)

pub fn dbm(&mut self) -> DBM_W<'_>

Bit 18 - Double buffer mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 16:17 - Priority level

pub fn pincos(&mut self) -> PINCOS_W<'_>

Bit 15 - Peripheral increment offset size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 13:14 - Memory data size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 11:12 - Peripheral data size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 10 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 9 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 8 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bits 6:7 - Data transfer direction

pub fn pfctrl(&mut self) -> PFCTRL_W<'_>

Bit 5 - Peripheral flow controller

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 4 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 3 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 2 - Transfer error interrupt enable

pub fn dmeie(&mut self) -> DMEIE_W<'_>

Bit 1 - Direct mode error interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Stream enable / flag stream ready when read low

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data items to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _M0AR>>

pub fn m0a(&mut self) -> M0A_W<'_>

Bits 0:31 - Memory 0 address

impl W<u32, Reg<u32, _M1AR>>

pub fn m1a(&mut self) -> M1A_W<'_>

Bits 0:31 - Memory 1 address (used in case of Double buffer mode)

impl W<u32, Reg<u32, _FCR>>

pub fn feie(&mut self) -> FEIE_W<'_>

Bit 7 - FIFO error interrupt enable

pub fn dmdis(&mut self) -> DMDIS_W<'_>

Bit 2 - Direct mode disable

pub fn fth(&mut self) -> FTH_W<'_>

Bits 0:1 - FIFO threshold selection

impl W<u32, Reg<u32, _LIFCR>>

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif3(&mut self) -> CDMEIF3_W<'_>

Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif3(&mut self) -> CFEIF3_W<'_>

Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif2(&mut self) -> CDMEIF2_W<'_>

Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif2(&mut self) -> CFEIF2_W<'_>

Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif1(&mut self) -> CDMEIF1_W<'_>

Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif1(&mut self) -> CFEIF1_W<'_>

Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif0(&mut self) -> CTCIF0_W<'_>

Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif0(&mut self) -> CHTIF0_W<'_>

Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif0(&mut self) -> CTEIF0_W<'_>

Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif0(&mut self) -> CDMEIF0_W<'_>

Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif0(&mut self) -> CFEIF0_W<'_>

Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)

impl W<u32, Reg<u32, _HIFCR>>

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif7(&mut self) -> CDMEIF7_W<'_>

Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif7(&mut self) -> CFEIF7_W<'_>

Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif6(&mut self) -> CDMEIF6_W<'_>

Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif6(&mut self) -> CFEIF6_W<'_>

Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif5(&mut self) -> CDMEIF5_W<'_>

Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif5(&mut self) -> CFEIF5_W<'_>

Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif4(&mut self) -> CDMEIF4_W<'_>

Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif4(&mut self) -> CFEIF4_W<'_>

Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)

impl W<u32, Reg<u32, _CR>>

pub fn plli2son(&mut self) -> PLLI2SON_W<'_>

Bit 26 - PLLI2S enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - Main PLL (PLL) enable

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE clock bypass

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal high-speed clock trimming

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal high-speed clock enable

impl W<u32, Reg<u32, _PLLCFGR>>

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 6:14 - Main PLL (PLL) multiplication factor for VCO

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 16:17 - Main PLL (PLL) division factor for main system clock

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks

impl W<u32, Reg<u32, _CFGR>>

pub fn mco2(&mut self) -> MCO2_W<'_>

Bits 30:31 - Microcontroller clock output 2

pub fn mco2pre(&mut self) -> MCO2PRE_W<'_>

Bits 27:29 - MCO2 prescaler

pub fn mco1pre(&mut self) -> MCO1PRE_W<'_>

Bits 24:26 - MCO1 prescaler

pub fn i2ssrc(&mut self) -> I2SSRC_W<'_>

Bit 23 - I2S clock selection

pub fn mco1(&mut self) -> MCO1_W<'_>

Bits 21:22 - Microcontroller clock output 1

pub fn rtcpre(&mut self) -> RTCPRE_W<'_>

Bits 16:20 - HSE division factor for RTC clock

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 13:15 - APB high-speed prescaler (APB2)

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 10:12 - APB Low speed prescaler (APB1)

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock switch

pub fn sws(&mut self) -> SWS_W<'_>

Bits 2:3 - System clock switch status

impl W<u32, Reg<u32, _CIR>>

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

pub fn plli2srdyc(&mut self) -> PLLI2SRDYC_W<'_>

Bit 21 - PLLI2S ready interrupt clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - Main PLL(PLL) ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE ready interrupt clear

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI ready interrupt clear

pub fn plli2srdyie(&mut self) -> PLLI2SRDYIE_W<'_>

Bit 13 - PLLI2S ready interrupt enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - Main PLL (PLL) ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE ready interrupt enable

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI ready interrupt enable

impl W<u32, Reg<u32, _AHB1RSTR>>

pub fn otghsrst(&mut self) -> OTGHSRST_W<'_>

Bit 29 - USB OTG HS module reset

pub fn ethmacrst(&mut self) -> ETHMACRST_W<'_>

Bit 25 - Ethernet MAC reset

pub fn dma2rst(&mut self) -> DMA2RST_W<'_>

Bit 22 - DMA2 reset

pub fn dma1rst(&mut self) -> DMA1RST_W<'_>

Bit 21 - DMA2 reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 12 - CRC reset

pub fn gpioirst(&mut self) -> GPIOIRST_W<'_>

Bit 8 - IO port I reset

pub fn gpiohrst(&mut self) -> GPIOHRST_W<'_>

Bit 7 - IO port H reset

pub fn gpiogrst(&mut self) -> GPIOGRST_W<'_>

Bit 6 - IO port G reset

pub fn gpiofrst(&mut self) -> GPIOFRST_W<'_>

Bit 5 - IO port F reset

pub fn gpioerst(&mut self) -> GPIOERST_W<'_>

Bit 4 - IO port E reset

pub fn gpiodrst(&mut self) -> GPIODRST_W<'_>

Bit 3 - IO port D reset

pub fn gpiocrst(&mut self) -> GPIOCRST_W<'_>

Bit 2 - IO port C reset

pub fn gpiobrst(&mut self) -> GPIOBRST_W<'_>

Bit 1 - IO port B reset

pub fn gpioarst(&mut self) -> GPIOARST_W<'_>

Bit 0 - IO port A reset

impl W<u32, Reg<u32, _AHB2RSTR>>

pub fn otgfsrst(&mut self) -> OTGFSRST_W<'_>

Bit 7 - USB OTG FS module reset

pub fn rngrst(&mut self) -> RNGRST_W<'_>

Bit 6 - Random number generator module reset

pub fn dcmirst(&mut self) -> DCMIRST_W<'_>

Bit 0 - Camera interface reset

impl W<u32, Reg<u32, _AHB3RSTR>>

pub fn fsmcrst(&mut self) -> FSMCRST_W<'_>

Bit 0 - Flexible static memory controller module reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn dacrst(&mut self) -> DACRST_W<'_>

Bit 29 - DAC reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn can2rst(&mut self) -> CAN2RST_W<'_>

Bit 26 - CAN2 reset

pub fn can1rst(&mut self) -> CAN1RST_W<'_>

Bit 25 - CAN1 reset

pub fn i2c3rst(&mut self) -> I2C3RST_W<'_>

Bit 23 - I2C3 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C 2 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C 1 reset

pub fn uart5rst(&mut self) -> UART5RST_W<'_>

Bit 20 - USART 5 reset

pub fn uart4rst(&mut self) -> UART4RST_W<'_>

Bit 19 - USART 4 reset

pub fn uart3rst(&mut self) -> UART3RST_W<'_>

Bit 18 - USART 3 reset

pub fn uart2rst(&mut self) -> UART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI 3 reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI 2 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 8 - TIM14 reset

pub fn tim13rst(&mut self) -> TIM13RST_W<'_>

Bit 7 - TIM13 reset

pub fn tim12rst(&mut self) -> TIM12RST_W<'_>

Bit 6 - TIM12 reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - TIM7 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - TIM6 reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>

Bit 3 - TIM5 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - TIM4 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - TIM3 reset

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 reset

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn tim11rst(&mut self) -> TIM11RST_W<'_>

Bit 18 - TIM11 reset

pub fn tim10rst(&mut self) -> TIM10RST_W<'_>

Bit 17 - TIM10 reset

pub fn tim9rst(&mut self) -> TIM9RST_W<'_>

Bit 16 - TIM9 reset

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 14 - System configuration controller reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn sdiorst(&mut self) -> SDIORST_W<'_>

Bit 11 - SDIO reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 8 - ADC interface reset (common to all ADCs)

pub fn usart6rst(&mut self) -> USART6RST_W<'_>

Bit 5 - USART6 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 4 - USART1 reset

pub fn tim8rst(&mut self) -> TIM8RST_W<'_>

Bit 1 - TIM8 reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 0 - TIM1 reset

impl W<u32, Reg<u32, _AHB1ENR>>

pub fn otghsulpien(&mut self) -> OTGHSULPIEN_W<'_>

Bit 30 - USB OTG HSULPI clock enable

pub fn otghsen(&mut self) -> OTGHSEN_W<'_>

Bit 29 - USB OTG HS clock enable

pub fn ethmacptpen(&mut self) -> ETHMACPTPEN_W<'_>

Bit 28 - Ethernet PTP clock enable

pub fn ethmacrxen(&mut self) -> ETHMACRXEN_W<'_>

Bit 27 - Ethernet Reception clock enable

pub fn ethmactxen(&mut self) -> ETHMACTXEN_W<'_>

Bit 26 - Ethernet Transmission clock enable

pub fn ethmacen(&mut self) -> ETHMACEN_W<'_>

Bit 25 - Ethernet MAC clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 22 - DMA2 clock enable

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 21 - DMA1 clock enable

pub fn bkpsramen(&mut self) -> BKPSRAMEN_W<'_>

Bit 18 - Backup SRAM interface clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CRC clock enable

pub fn gpioien(&mut self) -> GPIOIEN_W<'_>

Bit 8 - IO port I clock enable

pub fn gpiohen(&mut self) -> GPIOHEN_W<'_>

Bit 7 - IO port H clock enable

pub fn gpiogen(&mut self) -> GPIOGEN_W<'_>

Bit 6 - IO port G clock enable

pub fn gpiofen(&mut self) -> GPIOFEN_W<'_>

Bit 5 - IO port F clock enable

pub fn gpioeen(&mut self) -> GPIOEEN_W<'_>

Bit 4 - IO port E clock enable

pub fn gpioden(&mut self) -> GPIODEN_W<'_>

Bit 3 - IO port D clock enable

pub fn gpiocen(&mut self) -> GPIOCEN_W<'_>

Bit 2 - IO port C clock enable

pub fn gpioben(&mut self) -> GPIOBEN_W<'_>

Bit 1 - IO port B clock enable

pub fn gpioaen(&mut self) -> GPIOAEN_W<'_>

Bit 0 - IO port A clock enable

impl W<u32, Reg<u32, _AHB2ENR>>

pub fn otgfsen(&mut self) -> OTGFSEN_W<'_>

Bit 7 - USB OTG FS clock enable

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 6 - Random number generator clock enable

pub fn dcmien(&mut self) -> DCMIEN_W<'_>

Bit 0 - Camera interface enable

impl W<u32, Reg<u32, _AHB3ENR>>

pub fn fsmcen(&mut self) -> FSMCEN_W<'_>

Bit 0 - Flexible static memory controller module clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn dacen(&mut self) -> DACEN_W<'_>

Bit 29 - DAC interface clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn can2en(&mut self) -> CAN2EN_W<'_>

Bit 26 - CAN 2 clock enable

pub fn can1en(&mut self) -> CAN1EN_W<'_>

Bit 25 - CAN 1 clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>

Bit 23 - I2C3 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>

Bit 20 - UART5 clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>

Bit 19 - UART4 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI3 clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 8 - TIM14 clock enable

pub fn tim13en(&mut self) -> TIM13EN_W<'_>

Bit 7 - TIM13 clock enable

pub fn tim12en(&mut self) -> TIM12EN_W<'_>

Bit 6 - TIM12 clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - TIM7 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - TIM6 clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>

Bit 3 - TIM5 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - TIM4 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 clock enable

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - TIM2 clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn tim11en(&mut self) -> TIM11EN_W<'_>

Bit 18 - TIM11 clock enable

pub fn tim10en(&mut self) -> TIM10EN_W<'_>

Bit 17 - TIM10 clock enable

pub fn tim9en(&mut self) -> TIM9EN_W<'_>

Bit 16 - TIM9 clock enable

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 14 - System configuration controller clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SDIO clock enable

pub fn adc3en(&mut self) -> ADC3EN_W<'_>

Bit 10 - ADC3 clock enable

pub fn adc2en(&mut self) -> ADC2EN_W<'_>

Bit 9 - ADC2 clock enable

pub fn adc1en(&mut self) -> ADC1EN_W<'_>

Bit 8 - ADC1 clock enable

pub fn usart6en(&mut self) -> USART6EN_W<'_>

Bit 5 - USART6 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 4 - USART1 clock enable

pub fn tim8en(&mut self) -> TIM8EN_W<'_>

Bit 1 - TIM8 clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 0 - TIM1 clock enable

impl W<u32, Reg<u32, _AHB1LPENR>>

pub fn otghsulpilpen(&mut self) -> OTGHSULPILPEN_W<'_>

Bit 30 - USB OTG HS ULPI clock enable during Sleep mode

pub fn otghslpen(&mut self) -> OTGHSLPEN_W<'_>

Bit 29 - USB OTG HS clock enable during Sleep mode

pub fn ethmacptplpen(&mut self) -> ETHMACPTPLPEN_W<'_>

Bit 28 - Ethernet PTP clock enable during Sleep mode

pub fn ethmacrxlpen(&mut self) -> ETHMACRXLPEN_W<'_>

Bit 27 - Ethernet reception clock enable during Sleep mode

pub fn ethmactxlpen(&mut self) -> ETHMACTXLPEN_W<'_>

Bit 26 - Ethernet transmission clock enable during Sleep mode

pub fn ethmaclpen(&mut self) -> ETHMACLPEN_W<'_>

Bit 25 - Ethernet MAC clock enable during Sleep mode

pub fn dma2lpen(&mut self) -> DMA2LPEN_W<'_>

Bit 22 - DMA2 clock enable during Sleep mode

pub fn dma1lpen(&mut self) -> DMA1LPEN_W<'_>

Bit 21 - DMA1 clock enable during Sleep mode

pub fn bkpsramlpen(&mut self) -> BKPSRAMLPEN_W<'_>

Bit 18 - Backup SRAM interface clock enable during Sleep mode

pub fn sram2lpen(&mut self) -> SRAM2LPEN_W<'_>

Bit 17 - SRAM 2 interface clock enable during Sleep mode

pub fn sram1lpen(&mut self) -> SRAM1LPEN_W<'_>

Bit 16 - SRAM 1interface clock enable during Sleep mode

pub fn flitflpen(&mut self) -> FLITFLPEN_W<'_>

Bit 15 - Flash interface clock enable during Sleep mode

pub fn crclpen(&mut self) -> CRCLPEN_W<'_>

Bit 12 - CRC clock enable during Sleep mode

pub fn gpioilpen(&mut self) -> GPIOILPEN_W<'_>

Bit 8 - IO port I clock enable during Sleep mode

pub fn gpiohlpen(&mut self) -> GPIOHLPEN_W<'_>

Bit 7 - IO port H clock enable during Sleep mode

pub fn gpioglpen(&mut self) -> GPIOGLPEN_W<'_>

Bit 6 - IO port G clock enable during Sleep mode

pub fn gpioflpen(&mut self) -> GPIOFLPEN_W<'_>

Bit 5 - IO port F clock enable during Sleep mode

pub fn gpioelpen(&mut self) -> GPIOELPEN_W<'_>

Bit 4 - IO port E clock enable during Sleep mode

pub fn gpiodlpen(&mut self) -> GPIODLPEN_W<'_>

Bit 3 - IO port D clock enable during Sleep mode

pub fn gpioclpen(&mut self) -> GPIOCLPEN_W<'_>

Bit 2 - IO port C clock enable during Sleep mode

pub fn gpioblpen(&mut self) -> GPIOBLPEN_W<'_>

Bit 1 - IO port B clock enable during Sleep mode

pub fn gpioalpen(&mut self) -> GPIOALPEN_W<'_>

Bit 0 - IO port A clock enable during sleep mode

impl W<u32, Reg<u32, _AHB2LPENR>>

pub fn otgfslpen(&mut self) -> OTGFSLPEN_W<'_>

Bit 7 - USB OTG FS clock enable during Sleep mode

pub fn rnglpen(&mut self) -> RNGLPEN_W<'_>

Bit 6 - Random number generator clock enable during Sleep mode

pub fn dcmilpen(&mut self) -> DCMILPEN_W<'_>

Bit 0 - Camera interface enable during Sleep mode

impl W<u32, Reg<u32, _AHB3LPENR>>

pub fn fsmclpen(&mut self) -> FSMCLPEN_W<'_>

Bit 0 - Flexible static memory controller module clock enable during Sleep mode

impl W<u32, Reg<u32, _APB1LPENR>>

pub fn daclpen(&mut self) -> DACLPEN_W<'_>

Bit 29 - DAC interface clock enable during Sleep mode

pub fn pwrlpen(&mut self) -> PWRLPEN_W<'_>

Bit 28 - Power interface clock enable during Sleep mode

pub fn can2lpen(&mut self) -> CAN2LPEN_W<'_>

Bit 26 - CAN 2 clock enable during Sleep mode

pub fn can1lpen(&mut self) -> CAN1LPEN_W<'_>

Bit 25 - CAN 1 clock enable during Sleep mode

pub fn i2c3lpen(&mut self) -> I2C3LPEN_W<'_>

Bit 23 - I2C3 clock enable during Sleep mode

pub fn i2c2lpen(&mut self) -> I2C2LPEN_W<'_>

Bit 22 - I2C2 clock enable during Sleep mode

pub fn i2c1lpen(&mut self) -> I2C1LPEN_W<'_>

Bit 21 - I2C1 clock enable during Sleep mode

pub fn uart5lpen(&mut self) -> UART5LPEN_W<'_>

Bit 20 - UART5 clock enable during Sleep mode

pub fn uart4lpen(&mut self) -> UART4LPEN_W<'_>

Bit 19 - UART4 clock enable during Sleep mode

pub fn usart3lpen(&mut self) -> USART3LPEN_W<'_>

Bit 18 - USART3 clock enable during Sleep mode

pub fn usart2lpen(&mut self) -> USART2LPEN_W<'_>

Bit 17 - USART2 clock enable during Sleep mode

pub fn spi3lpen(&mut self) -> SPI3LPEN_W<'_>

Bit 15 - SPI3 clock enable during Sleep mode

pub fn spi2lpen(&mut self) -> SPI2LPEN_W<'_>

Bit 14 - SPI2 clock enable during Sleep mode

pub fn wwdglpen(&mut self) -> WWDGLPEN_W<'_>

Bit 11 - Window watchdog clock enable during Sleep mode

pub fn tim14lpen(&mut self) -> TIM14LPEN_W<'_>

Bit 8 - TIM14 clock enable during Sleep mode

pub fn tim13lpen(&mut self) -> TIM13LPEN_W<'_>

Bit 7 - TIM13 clock enable during Sleep mode

pub fn tim12lpen(&mut self) -> TIM12LPEN_W<'_>

Bit 6 - TIM12 clock enable during Sleep mode

pub fn tim7lpen(&mut self) -> TIM7LPEN_W<'_>

Bit 5 - TIM7 clock enable during Sleep mode

pub fn tim6lpen(&mut self) -> TIM6LPEN_W<'_>

Bit 4 - TIM6 clock enable during Sleep mode

pub fn tim5lpen(&mut self) -> TIM5LPEN_W<'_>

Bit 3 - TIM5 clock enable during Sleep mode

pub fn tim4lpen(&mut self) -> TIM4LPEN_W<'_>

Bit 2 - TIM4 clock enable during Sleep mode

pub fn tim3lpen(&mut self) -> TIM3LPEN_W<'_>

Bit 1 - TIM3 clock enable during Sleep mode

pub fn tim2lpen(&mut self) -> TIM2LPEN_W<'_>

Bit 0 - TIM2 clock enable during Sleep mode

impl W<u32, Reg<u32, _APB2LPENR>>

pub fn tim11lpen(&mut self) -> TIM11LPEN_W<'_>

Bit 18 - TIM11 clock enable during Sleep mode

pub fn tim10lpen(&mut self) -> TIM10LPEN_W<'_>

Bit 17 - TIM10 clock enable during Sleep mode

pub fn tim9lpen(&mut self) -> TIM9LPEN_W<'_>

Bit 16 - TIM9 clock enable during sleep mode

pub fn syscfglpen(&mut self) -> SYSCFGLPEN_W<'_>

Bit 14 - System configuration controller clock enable during Sleep mode

pub fn spi1lpen(&mut self) -> SPI1LPEN_W<'_>

Bit 12 - SPI 1 clock enable during Sleep mode

pub fn sdiolpen(&mut self) -> SDIOLPEN_W<'_>

Bit 11 - SDIO clock enable during Sleep mode

pub fn adc3lpen(&mut self) -> ADC3LPEN_W<'_>

Bit 10 - ADC 3 clock enable during Sleep mode

pub fn adc2lpen(&mut self) -> ADC2LPEN_W<'_>

Bit 9 - ADC2 clock enable during Sleep mode

pub fn adc1lpen(&mut self) -> ADC1LPEN_W<'_>

Bit 8 - ADC1 clock enable during Sleep mode

pub fn usart6lpen(&mut self) -> USART6LPEN_W<'_>

Bit 5 - USART6 clock enable during Sleep mode

pub fn usart1lpen(&mut self) -> USART1LPEN_W<'_>

Bit 4 - USART1 clock enable during Sleep mode

pub fn tim8lpen(&mut self) -> TIM8LPEN_W<'_>

Bit 1 - TIM8 clock enable during Sleep mode

pub fn tim1lpen(&mut self) -> TIM1LPEN_W<'_>

Bit 0 - TIM1 clock enable during Sleep mode

impl W<u32, Reg<u32, _BDCR>>

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External low-speed oscillator bypass

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External low-speed oscillator enable

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

impl W<u32, Reg<u32, _CSR>>

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn wdgrstf(&mut self) -> WDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn padrstf(&mut self) -> PADRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn borrstf(&mut self) -> BORRSTF_W<'_>

Bit 25 - BOR reset flag

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low-speed oscillator enable

impl W<u32, Reg<u32, _SSCGR>>

pub fn sscgen(&mut self) -> SSCGEN_W<'_>

Bit 31 - Spread spectrum modulation enable

pub fn spreadsel(&mut self) -> SPREADSEL_W<'_>

Bit 30 - Spread Select

pub fn incstep(&mut self) -> INCSTEP_W<'_>

Bits 13:27 - Incrementation step

pub fn modper(&mut self) -> MODPER_W<'_>

Bits 0:12 - Modulation period

impl W<u32, Reg<u32, _PLLI2SCFGR>>

pub fn plli2sr(&mut self) -> PLLI2SR_W<'_>

Bits 28:30 - PLLI2S division factor for I2S clocks

pub fn plli2sn(&mut self) -> PLLI2SN_W<'_>

Bits 6:14 - PLLI2S multiplication factor for VCO

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MEMRM>>

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:1 - MEM_MODE

impl W<u32, Reg<u32, _PMC>>

pub fn mii_rmii_sel(&mut self) -> MII_RMII_SEL_W<'_>

Bit 23 - Ethernet PHY interface selection

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI x configuration (x = 0 to 3)

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI x configuration (x = 0 to 3)

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI x configuration (x = 0 to 3)

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI x configuration (x = 0 to 3)

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI x configuration (x = 4 to 7)

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI x configuration (x = 4 to 7)

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI x configuration (x = 4 to 7)

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI x configuration (x = 4 to 7)

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI x configuration (x = 8 to 11)

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI10

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI x configuration (x = 8 to 11)

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI x configuration (x = 8 to 11)

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI x configuration (x = 12 to 15)

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI x configuration (x = 12 to 15)

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI x configuration (x = 12 to 15)

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI x configuration (x = 12 to 15)

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

impl W<u32, Reg<u32, _I2SPR>>

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _POWER>>

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>

Bit 14 - HW Flow Control enable

pub fn negedge(&mut self) -> NEGEDGE_W<'_>

Bit 13 - SDIO_CK dephasing selection bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>

Bits 11:12 - Wide bus mode enable bit

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 10 - Clock divider bypass enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>

Bit 9 - Power saving configuration bit

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 8 - Clock enable bit

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 0:7 - Clock divide factor

impl W<u32, Reg<u32, _ARG>>

pub fn cmdarg(&mut self) -> CMDARG_W<'_>

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>

pub fn ce_atacmd(&mut self) -> CE_ATACMD_W<'_>

Bit 14 - CE-ATA command

pub fn n_ien(&mut self) -> NIEN_W<'_>

Bit 13 - not Interrupt Enable

pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W<'_>

Bit 12 - Enable CMD completion

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>

Bit 11 - SD I/O suspend command

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>

Bit 10 - Command path state machine (CPSM) Enable bit

pub fn waitpend(&mut self) -> WAITPEND_W<'_>

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).

pub fn waitint(&mut self) -> WAITINT_W<'_>

Bit 8 - CPSM waits for interrupt request

pub fn waitresp(&mut self) -> WAITRESP_W<'_>

Bits 6:7 - Wait for response bits

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>

Bits 0:5 - Command index

impl W<u32, Reg<u32, _DTIMER>>

pub fn datatime(&mut self) -> DATATIME_W<'_>

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>

pub fn datalength(&mut self) -> DATALENGTH_W<'_>

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SD I/O enable functions

pub fn rwmod(&mut self) -> RWMOD_W<'_>

Bit 10 - Read wait mode

pub fn rwstop(&mut self) -> RWSTOP_W<'_>

Bit 9 - Read wait stop

pub fn rwstart(&mut self) -> RWSTART_W<'_>

Bit 8 - Read wait start

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>

Bits 4:7 - Data block size

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 3 - DMA enable bit

pub fn dtmode(&mut self) -> DTMODE_W<'_>

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

pub fn dtdir(&mut self) -> DTDIR_W<'_>

Bit 1 - Data transfer direction selection

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTEN

impl W<u32, Reg<u32, _ICR>>

pub fn ceataendc(&mut self) -> CEATAENDC_W<'_>

Bit 23 - CEATAEND flag clear bit

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>

Bit 22 - SDIOIT flag clear bit

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>

Bit 10 - DBCKEND flag clear bit

pub fn stbiterrc(&mut self) -> STBITERRC_W<'_>

Bit 9 - STBITERR flag clear bit

pub fn dataendc(&mut self) -> DATAENDC_W<'_>

Bit 8 - DATAEND flag clear bit

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>

Bit 7 - CMDSENT flag clear bit

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>

Bit 6 - CMDREND flag clear bit

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>

Bit 5 - RXOVERR flag clear bit

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>

Bit 4 - TXUNDERR flag clear bit

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>

Bit 3 - DTIMEOUT flag clear bit

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>

Bit 2 - CTIMEOUT flag clear bit

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>

Bit 1 - DCRCFAIL flag clear bit

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>

Bit 0 - CCRCFAIL flag clear bit

impl W<u32, Reg<u32, _MASK>>

pub fn ceataendie(&mut self) -> CEATAENDIE_W<'_>

Bit 23 - CE-ATA command completion signal received interrupt enable

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>

Bit 22 - SDIO mode interrupt received interrupt enable

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>

Bit 21 - Data available in Rx FIFO interrupt enable

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>

Bit 20 - Data available in Tx FIFO interrupt enable

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>

Bit 19 - Rx FIFO empty interrupt enable

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>

Bit 18 - Tx FIFO empty interrupt enable

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>

Bit 17 - Rx FIFO full interrupt enable

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>

Bit 16 - Tx FIFO full interrupt enable

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>

Bit 15 - Rx FIFO half full interrupt enable

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>

Bit 14 - Tx FIFO half empty interrupt enable

pub fn rxactie(&mut self) -> RXACTIE_W<'_>

Bit 13 - Data receive acting interrupt enable

pub fn txactie(&mut self) -> TXACTIE_W<'_>

Bit 12 - Data transmit acting interrupt enable

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>

Bit 11 - Command acting interrupt enable

pub fn dbckendie(&mut self) -> DBCKENDIE_W<'_>

Bit 10 - Data block end interrupt enable

pub fn stbiterrie(&mut self) -> STBITERRIE_W<'_>

Bit 9 - Start bit error interrupt enable

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>

Bit 8 - Data end interrupt enable

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>

Bit 7 - Command sent interrupt enable

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>

Bit 6 - Command response received interrupt enable

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>

Bit 5 - Rx FIFO overrun error interrupt enable

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>

Bit 4 - Tx FIFO underrun error interrupt enable

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>

Bit 3 - Data timeout interrupt enable

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>

Bit 2 - Command timeout interrupt enable

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>

Bit 1 - Data CRC fail interrupt enable

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>

Bit 0 - Command CRC fail interrupt enable

impl W<u32, Reg<u32, _FIFO>>

pub fn fifodata(&mut self) -> FIFODATA_W<'_>

Bits 0:31 - Receive and transmit FIFO data

impl W<u32, Reg<u32, _SR>>

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 5 - Overrun

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 26 - Overrun interrupt enable

pub fn res(&mut self) -> RES_W<'_>

Bits 24:25 - Resolution

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 30 - Start conversion of regular channels

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 28:29 - External trigger enable for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 24:27 - External event select for regular group

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 22 - Start conversion of injected channels

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 20:21 - External trigger enable for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 16:19 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn eocs(&mut self) -> EOCS_W<'_>

Bit 10 - End of conversion selection

pub fn dds(&mut self) -> DDS_W<'_>

Bit 9 - DMA disable selection (for single ADC mode)

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode (for single ADC mode)

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D Converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp18(&mut self) -> SMP18_W<'_>

Bits 24:26 - Channel 18 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sampling time selection

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sampling time selection

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sampling time selection

impl W<u32, Reg<u32, _JOFR>>

pub fn joffset(&mut self) -> JOFFSET_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _SR>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 9 - CTS flag

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - Data value

impl W<u32, Reg<u32, _BRR>>

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - mantissa of USARTDIV

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - fraction of USARTDIV

impl W<u32, Reg<u32, _CR1>>

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

impl W<u32, Reg<u32, _CR2>>

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _CR>>

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn boff2(&mut self) -> BOFF2_W<'_>

Bit 17 - DAC channel2 output buffer disable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit left-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

impl W<u32, Reg<u32, _CR>>

pub fn fpds(&mut self) -> FPDS_W<'_>

Bit 9 - Flash power down in Stop mode

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD level selection

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power voltage detector enable

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear standby flag

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear wakeup flag

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power down deepsleep

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low-power deep sleep

impl W<u32, Reg<u32, _CSR>>

pub fn ewup(&mut self) -> EWUP_W<'_>

Bit 8 - Enable WKUP pin

pub fn bre(&mut self) -> BRE_W<'_>

Bit 9 - Backup regulator enable

pub fn vosrdy(&mut self) -> VOSRDY_W<'_>

Bit 14 - Regulator voltage scaling output selection ready bit

impl W<u32, Reg<u32, _CR1>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 15 - Software reset

pub fn alert(&mut self) -> ALERT_W<'_>

Bit 13 - SMBus alert

pub fn pec(&mut self) -> PEC_W<'_>

Bit 12 - Packet error checking

pub fn pos(&mut self) -> POS_W<'_>

Bit 11 - Acknowledge/PEC Position (for data reception)

pub fn ack(&mut self) -> ACK_W<'_>

Bit 10 - Acknowledge enable

pub fn stop(&mut self) -> STOP_W<'_>

Bit 9 - Stop generation

pub fn start(&mut self) -> START_W<'_>

Bit 8 - Start generation

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 7 - Clock stretching disable (Slave mode)

pub fn engc(&mut self) -> ENGC_W<'_>

Bit 6 - General call enable

pub fn enpec(&mut self) -> ENPEC_W<'_>

Bit 5 - PEC enable

pub fn enarp(&mut self) -> ENARP_W<'_>

Bit 4 - ARP enable

pub fn smbtype(&mut self) -> SMBTYPE_W<'_>

Bit 3 - SMBus type

pub fn smbus(&mut self) -> SMBUS_W<'_>

Bit 1 - SMBus mode

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

impl W<u32, Reg<u32, _CR2>>

pub fn last(&mut self) -> LAST_W<'_>

Bit 12 - DMA last transfer

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 11 - DMA requests enable

pub fn itbufen(&mut self) -> ITBUFEN_W<'_>

Bit 10 - Buffer interrupt enable

pub fn itevten(&mut self) -> ITEVTEN_W<'_>

Bit 9 - Event interrupt enable

pub fn iterren(&mut self) -> ITERREN_W<'_>

Bit 8 - Error interrupt enable

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:5 - Peripheral clock frequency

impl W<u32, Reg<u32, _OAR1>>

pub fn addmode(&mut self) -> ADDMODE_W<'_>

Bit 15 - Addressing mode (slave mode)

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn add2(&mut self) -> ADD2_W<'_>

Bits 1:7 - Interface address

pub fn endual(&mut self) -> ENDUAL_W<'_>

Bit 0 - Dual addressing mode enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:7 - 8-bit data register

impl W<u32, Reg<u32, _SR1>>

pub fn smbalert(&mut self) -> SMBALERT_W<'_>

Bit 15 - SMBus alert

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 14 - Timeout or Tlow error

pub fn pecerr(&mut self) -> PECERR_W<'_>

Bit 12 - PEC Error in reception

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 11 - Overrun/Underrun

pub fn af(&mut self) -> AF_W<'_>

Bit 10 - Acknowledge failure

pub fn arlo(&mut self) -> ARLO_W<'_>

Bit 9 - Arbitration lost (master mode)

pub fn berr(&mut self) -> BERR_W<'_>

Bit 8 - Bus error

impl W<u32, Reg<u32, _CCR>>

pub fn f_s(&mut self) -> F_S_W<'_>

Bit 15 - I2C master mode selection

pub fn duty(&mut self) -> DUTY_W<'_>

Bit 14 - Fast mode duty cycle

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _TRISE>>

pub fn trise(&mut self) -> TRISE_W<'_>

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value (write only, read 0000h)

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - Calibration output enable

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - Output selection

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - Output polarity

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - Backup

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - Subtract 1 hour (winter time change)

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - Add 1 hour (summer time change)

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - Time-stamp interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - Wakeup timer interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - Alarm B interrupt enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - Alarm A interrupt enable

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - Time stamp enable

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - Wakeup timer enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - Alarm B enable

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - Alarm A enable

pub fn dce(&mut self) -> DCE_W<'_>

Bit 7 - Coarse digital calibration enable

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - Hour format

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - Time-stamp event active edge

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - Wakeup clock selection

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - Bypass the shadow registers

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - Calibration output selection

impl W<u32, Reg<u32, _ISR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

pub fn alraf(&mut self) -> ALRAF_W<'_>

Bit 8 - Alarm A flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>

Bit 9 - Alarm B flag

pub fn wutf(&mut self) -> WUTF_W<'_>

Bit 10 - Wakeup timer flag

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 11 - Time-stamp flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>

Bit 12 - Time-stamp overflow flag

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>

Bit 13 - Tamper detection flag

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>

Bit 14 - TAMPER2 detection flag

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _CALIBR>>

pub fn dcs(&mut self) -> DCS_W<'_>

Bit 7 - Digital calibration sign

pub fn dc(&mut self) -> DC_W<'_>

Bits 0:4 - Digital calibration

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAFCR>>

pub fn alarmouttype(&mut self) -> ALARMOUTTYPE_W<'_>

Bit 18 - AFO_ALARM output type

pub fn tsinsel(&mut self) -> TSINSEL_W<'_>

Bit 17 - TIMESTAMP mapping

pub fn tamp1insel(&mut self) -> TAMP1INSEL_W<'_>

Bit 16 - TAMPER1 mapping

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 15 - TAMPER pull-up disable

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 13:14 - Tamper precharge duration

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 11:12 - Tamper filter count

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 8:10 - Tamper sampling frequency

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 7 - Activate timestamp on tamper detection event

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 4 - Active level for tamper 2

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 3 - Tamper 2 detection enable

pub fn tampie(&mut self) -> TAMPIE_W<'_>

Bit 2 - Tamper interrupt enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 1 - Active level for tamper 1

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - Tamper 1 detection enable

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _BKPR>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _SR>>

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - Data value

impl W<u32, Reg<u32, _BRR>>

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - mantissa of USARTDIV

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - fraction of USARTDIV

impl W<u32, Reg<u32, _CR1>>

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

impl W<u32, Reg<u32, _CR2>>

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _CCR>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn vbate(&mut self) -> VBATE_W<'_>

Bit 22 - VBAT enable

pub fn adcpre(&mut self) -> ADCPRE_W<'_>

Bits 16:17 - ADC prescaler

pub fn dma(&mut self) -> DMA_W<'_>

Bits 14:15 - Direct memory access mode for multi ADC mode

pub fn dds(&mut self) -> DDS_W<'_>

Bit 13 - DMA disable selection for multi-ADC mode

pub fn delay(&mut self) -> DELAY_W<'_>

Bits 8:11 - Delay between 2 sampling phases

pub fn multi(&mut self) -> MULTI_W<'_>

Bits 0:4 - Multi ADC mode selection

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn itr1_rmp(&mut self) -> ITR1_RMP_W<'_>

Bits 10:11 - Timer Input 4 remap

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn it4_rmp(&mut self) -> IT4_RMP_W<'_>

Bits 6:7 - Timer Input 4 remap

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:14 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:6 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _OR>>

pub fn rmp(&mut self) -> RMP_W<'_>

Bits 0:1 - Input 1 remapping capability

impl W<u32, Reg<u32, _CR1>>

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _MACCR>>

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn dc(&mut self) -> DC_W<'_>

Bit 4 - Deferral check

pub fn bl(&mut self) -> BL_W<'_>

Bits 5:6 - Back-off limit

pub fn apcs(&mut self) -> APCS_W<'_>

Bit 7 - Automatic pad/CRC stripping

pub fn rd(&mut self) -> RD_W<'_>

Bit 9 - Retry disable

pub fn ipco(&mut self) -> IPCO_W<'_>

Bit 10 - IPv4 checksum offload

pub fn dm(&mut self) -> DM_W<'_>

Bit 11 - Duplex mode

pub fn lm(&mut self) -> LM_W<'_>

Bit 12 - Loopback mode

pub fn rod(&mut self) -> ROD_W<'_>

Bit 13 - Receive own disable

pub fn fes(&mut self) -> FES_W<'_>

Bit 14 - Fast Ethernet speed

pub fn csd(&mut self) -> CSD_W<'_>

Bit 16 - Carrier sense disable

pub fn ifg(&mut self) -> IFG_W<'_>

Bits 17:19 - Interframe gap

pub fn jd(&mut self) -> JD_W<'_>

Bit 22 - Jabber disable

pub fn wd(&mut self) -> WD_W<'_>

Bit 23 - Watchdog disable

pub fn cstf(&mut self) -> CSTF_W<'_>

Bit 25 - CRC stripping for type frames

impl W<u32, Reg<u32, _MACFFR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 0 - Promiscuous mode

pub fn hu(&mut self) -> HU_W<'_>

Bit 1 - Hash unicast

pub fn hm(&mut self) -> HM_W<'_>

Bit 2 - Hash multicast

pub fn daif(&mut self) -> DAIF_W<'_>

Bit 3 - Destination address unique filtering

pub fn pam(&mut self) -> PAM_W<'_>

Bit 4 - Pass all multicast

pub fn bfd(&mut self) -> BFD_W<'_>

Bit 5 - Broadcast frames disable

pub fn pcf(&mut self) -> PCF_W<'_>

Bits 6:7 - Pass control frames

pub fn saif(&mut self) -> SAIF_W<'_>

Bit 7 - Source address inverse filtering

pub fn saf(&mut self) -> SAF_W<'_>

Bit 8 - Source address filter

pub fn hpf(&mut self) -> HPF_W<'_>

Bit 9 - Hash or perfect filter

pub fn ra(&mut self) -> RA_W<'_>

Bit 31 - Receive all

impl W<u32, Reg<u32, _MACHTHR>>

pub fn hth(&mut self) -> HTH_W<'_>

Bits 0:31 - Upper 32 bits of hash table

impl W<u32, Reg<u32, _MACHTLR>>

pub fn htl(&mut self) -> HTL_W<'_>

Bits 0:31 - Lower 32 bits of hash table

impl W<u32, Reg<u32, _MACMIIAR>>

pub fn mb(&mut self) -> MB_W<'_>

Bit 0 - MII busy

pub fn mw(&mut self) -> MW_W<'_>

Bit 1 - MII write

pub fn cr(&mut self) -> CR_W<'_>

Bits 2:4 - Clock range

pub fn mr(&mut self) -> MR_W<'_>

Bits 6:10 - MII register - select the desired MII register in the PHY device

pub fn pa(&mut self) -> PA_W<'_>

Bits 11:15 - PHY address - select which of possible 32 PHYs is being accessed

impl W<u32, Reg<u32, _MACMIIDR>>

pub fn md(&mut self) -> MD_W<'_>

Bits 0:15 - MII data read from/written to the PHY

impl W<u32, Reg<u32, _MACFCR>>

pub fn fcb(&mut self) -> FCB_W<'_>

Bit 0 - Flow control busy/back pressure activate

pub fn tfce(&mut self) -> TFCE_W<'_>

Bit 1 - Transmit flow control enable

pub fn rfce(&mut self) -> RFCE_W<'_>

Bit 2 - Receive flow control enable

pub fn upfd(&mut self) -> UPFD_W<'_>

Bit 3 - Unicast pause frame detect

pub fn plt(&mut self) -> PLT_W<'_>

Bits 4:5 - Pause low threshold

pub fn zqpd(&mut self) -> ZQPD_W<'_>

Bit 7 - Zero-quanta pause disable

pub fn pt(&mut self) -> PT_W<'_>

Bits 16:31 - Pause time

impl W<u32, Reg<u32, _MACVLANTR>>

pub fn vlanti(&mut self) -> VLANTI_W<'_>

Bits 0:15 - VLAN tag identifier (for receive frames)

pub fn vlantc(&mut self) -> VLANTC_W<'_>

Bit 16 - 12-bit VLAN tag comparison

impl W<u32, Reg<u32, _MACPMTCSR>>

pub fn pd(&mut self) -> PD_W<'_>

Bit 0 - Power down

pub fn mpe(&mut self) -> MPE_W<'_>

Bit 1 - Magic packet enable

pub fn wfe(&mut self) -> WFE_W<'_>

Bit 2 - Wakeup frame enable

pub fn mpr(&mut self) -> MPR_W<'_>

Bit 5 - Magic packet received

pub fn wfr(&mut self) -> WFR_W<'_>

Bit 6 - Wakeup frame received

pub fn gu(&mut self) -> GU_W<'_>

Bit 9 - Global unicast

pub fn wffrpr(&mut self) -> WFFRPR_W<'_>

Bit 31 - Wakeup frame filter register pointer reset

impl W<u32, Reg<u32, _MACSR>>

pub fn tsts(&mut self) -> TSTS_W<'_>

Bit 9 - Time stamp trigger status

impl W<u32, Reg<u32, _MACIMR>>

pub fn pmtim(&mut self) -> PMTIM_W<'_>

Bit 3 - PMT interrupt mask

pub fn tstim(&mut self) -> TSTIM_W<'_>

Bit 9 - Time stamp trigger interrupt mask

impl W<u32, Reg<u32, _MACA0HR>>

pub fn maca0h(&mut self) -> MACA0H_W<'_>

Bits 0:15 - MAC address0 high

impl W<u32, Reg<u32, _MACA0LR>>

pub fn maca0l(&mut self) -> MACA0L_W<'_>

Bits 0:31 - 0

impl W<u32, Reg<u32, _MACA1HR>>

pub fn maca1h(&mut self) -> MACA1H_W<'_>

Bits 0:15 - MACA1H

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - MBC

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - SA

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - AE

impl W<u32, Reg<u32, _MACA1LR>>

pub fn maca1l(&mut self) -> MACA1L_W<'_>

Bits 0:31 - MACA1LR

impl W<u32, Reg<u32, _MACA2HR>>

pub fn maca2h(&mut self) -> MACA2H_W<'_>

Bits 0:15 - MAC2AH

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - MBC

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - SA

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - AE

impl W<u32, Reg<u32, _MACA2LR>>

pub fn maca2l(&mut self) -> MACA2L_W<'_>

Bits 0:31 - MACA2L

impl W<u32, Reg<u32, _MACA3HR>>

pub fn maca3h(&mut self) -> MACA3H_W<'_>

Bits 0:15 - MACA3H

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - MBC

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - SA

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - AE

impl W<u32, Reg<u32, _MACA3LR>>

pub fn maca3l(&mut self) -> MACA3L_W<'_>

Bits 0:31 - MBCA3L

impl W<u32, Reg<u32, _MMCCR>>

pub fn cr(&mut self) -> CR_W<'_>

Bit 0 - Counter reset

pub fn csr(&mut self) -> CSR_W<'_>

Bit 1 - Counter stop rollover

pub fn ror(&mut self) -> ROR_W<'_>

Bit 2 - Reset on read

pub fn mcf(&mut self) -> MCF_W<'_>

Bit 3 - MMC counter freeze

pub fn mcp(&mut self) -> MCP_W<'_>

Bit 4 - MMC counter preset

pub fn mcfhp(&mut self) -> MCFHP_W<'_>

Bit 5 - MMC counter Full-Half preset

impl W<u32, Reg<u32, _MMCRIR>>

pub fn rfces(&mut self) -> RFCES_W<'_>

Bit 5 - Received frames CRC error status

pub fn rfaes(&mut self) -> RFAES_W<'_>

Bit 6 - Received frames alignment error status

pub fn rgufs(&mut self) -> RGUFS_W<'_>

Bit 17 - Received good Unicast frames status

impl W<u32, Reg<u32, _MMCRIMR>>

pub fn rfcem(&mut self) -> RFCEM_W<'_>

Bit 5 - Received frame CRC error mask

pub fn rfaem(&mut self) -> RFAEM_W<'_>

Bit 6 - Received frames alignment error mask

pub fn rgufm(&mut self) -> RGUFM_W<'_>

Bit 17 - Received good Unicast frames mask

impl W<u32, Reg<u32, _MMCTIMR>>

pub fn tgfscm(&mut self) -> TGFSCM_W<'_>

Bit 14 - Transmitted good frames single collision mask

pub fn tgfmscm(&mut self) -> TGFMSCM_W<'_>

Bit 15 - Transmitted good frames more than single collision mask

pub fn tgfm(&mut self) -> TGFM_W<'_>

Bit 16 - Transmitted good frames mask

impl W<u32, Reg<u32, _PTPTSCR>>

pub fn tse(&mut self) -> TSE_W<'_>

Bit 0 - TSE

pub fn tsfcu(&mut self) -> TSFCU_W<'_>

Bit 1 - TSFCU

pub fn tsptppsv2e(&mut self) -> TSPTPPSV2E_W<'_>

Bit 10 - TSPTPPSV2E

pub fn tssptpoefe(&mut self) -> TSSPTPOEFE_W<'_>

Bit 11 - TSSPTPOEFE

pub fn tssipv6fe(&mut self) -> TSSIPV6FE_W<'_>

Bit 12 - TSSIPV6FE

pub fn tssipv4fe(&mut self) -> TSSIPV4FE_W<'_>

Bit 13 - TSSIPV4FE

pub fn tsseme(&mut self) -> TSSEME_W<'_>

Bit 14 - TSSEME

pub fn tssmrme(&mut self) -> TSSMRME_W<'_>

Bit 15 - TSSMRME

pub fn tscnt(&mut self) -> TSCNT_W<'_>

Bits 16:17 - TSCNT

pub fn tspffmae(&mut self) -> TSPFFMAE_W<'_>

Bit 18 - TSPFFMAE

pub fn tssti(&mut self) -> TSSTI_W<'_>

Bit 2 - TSSTI

pub fn tsstu(&mut self) -> TSSTU_W<'_>

Bit 3 - TSSTU

pub fn tsite(&mut self) -> TSITE_W<'_>

Bit 4 - TSITE

pub fn ttsaru(&mut self) -> TTSARU_W<'_>

Bit 5 - TTSARU

pub fn tssarfe(&mut self) -> TSSARFE_W<'_>

Bit 8 - TSSARFE

pub fn tsssr(&mut self) -> TSSSR_W<'_>

Bit 9 - TSSSR

impl W<u32, Reg<u32, _PTPSSIR>>

pub fn stssi(&mut self) -> STSSI_W<'_>

Bits 0:7 - STSSI

impl W<u32, Reg<u32, _PTPTSHUR>>

pub fn tsus(&mut self) -> TSUS_W<'_>

Bits 0:31 - TSUS

impl W<u32, Reg<u32, _PTPTSLUR>>

pub fn tsuss(&mut self) -> TSUSS_W<'_>

Bits 0:30 - TSUSS

pub fn tsupns(&mut self) -> TSUPNS_W<'_>

Bit 31 - TSUPNS

impl W<u32, Reg<u32, _PTPTSAR>>

pub fn tsa(&mut self) -> TSA_W<'_>

Bits 0:31 - TSA

impl W<u32, Reg<u32, _PTPTTHR>>

pub fn ttsh(&mut self) -> TTSH_W<'_>

Bits 0:31 - 0

impl W<u32, Reg<u32, _PTPTTLR>>

pub fn ttsl(&mut self) -> TTSL_W<'_>

Bits 0:31 - TTSL

impl W<u32, Reg<u32, _DMABMR>>

pub fn sr(&mut self) -> SR_W<'_>

Bit 0 - Software reset

pub fn da(&mut self) -> DA_W<'_>

Bit 1 - DMA arbitration

pub fn dsl(&mut self) -> DSL_W<'_>

Bits 2:6 - Descriptor skip length

pub fn edfe(&mut self) -> EDFE_W<'_>

Bit 7 - Enhanced descriptor format enable

pub fn pbl(&mut self) -> PBL_W<'_>

Bits 8:13 - Programmable burst length

pub fn pm(&mut self) -> PM_W<'_>

Bits 14:15 - Rx-Tx priority ratio

pub fn fb(&mut self) -> FB_W<'_>

Bit 16 - Fixed burst

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 17:22 - Rx DMA PBL

pub fn usp(&mut self) -> USP_W<'_>

Bit 23 - Use separate PBL

pub fn fpm(&mut self) -> FPM_W<'_>

Bit 24 - 4xPBL mode

pub fn aab(&mut self) -> AAB_W<'_>

Bit 25 - Address-aligned beats

pub fn mb(&mut self) -> MB_W<'_>

Bit 26 - Mixed burst

impl W<u32, Reg<u32, _DMATPDR>>

pub fn tpd(&mut self) -> TPD_W<'_>

Bits 0:31 - Transmit poll demand

impl W<u32, Reg<u32, _DMARPDR>>

pub fn rpd(&mut self) -> RPD_W<'_>

Bits 0:31 - Receive poll demand

impl W<u32, Reg<u32, _DMARDLAR>>

pub fn srl(&mut self) -> SRL_W<'_>

Bits 0:31 - Start of receive list

impl W<u32, Reg<u32, _DMATDLAR>>

pub fn stl(&mut self) -> STL_W<'_>

Bits 0:31 - Start of transmit list

impl W<u32, Reg<u32, _DMASR>>

pub fn ts(&mut self) -> TS_W<'_>

Bit 0 - Transmit status

pub fn tpss(&mut self) -> TPSS_W<'_>

Bit 1 - Transmit process stopped status

pub fn tbus(&mut self) -> TBUS_W<'_>

Bit 2 - Transmit buffer unavailable status

pub fn tjts(&mut self) -> TJTS_W<'_>

Bit 3 - Transmit jabber timeout status

pub fn ros(&mut self) -> ROS_W<'_>

Bit 4 - Receive overflow status

pub fn tus(&mut self) -> TUS_W<'_>

Bit 5 - Transmit underflow status

pub fn rs(&mut self) -> RS_W<'_>

Bit 6 - Receive status

pub fn rbus(&mut self) -> RBUS_W<'_>

Bit 7 - Receive buffer unavailable status

pub fn rpss(&mut self) -> RPSS_W<'_>

Bit 8 - Receive process stopped status

pub fn pwts(&mut self) -> PWTS_W<'_>

Bit 9 - PWTS

pub fn ets(&mut self) -> ETS_W<'_>

Bit 10 - Early transmit status

pub fn fbes(&mut self) -> FBES_W<'_>

Bit 13 - Fatal bus error status

pub fn ers(&mut self) -> ERS_W<'_>

Bit 14 - Early receive status

pub fn ais(&mut self) -> AIS_W<'_>

Bit 15 - Abnormal interrupt summary

pub fn nis(&mut self) -> NIS_W<'_>

Bit 16 - Normal interrupt summary

impl W<u32, Reg<u32, _DMAOMR>>

pub fn sr(&mut self) -> SR_W<'_>

Bit 1 - Start/stop receive

pub fn osf(&mut self) -> OSF_W<'_>

Bit 2 - Operate on second frame

pub fn rtc(&mut self) -> RTC_W<'_>

Bits 3:4 - Receive threshold control

pub fn fugf(&mut self) -> FUGF_W<'_>

Bit 6 - Forward undersized good frames

pub fn fef(&mut self) -> FEF_W<'_>

Bit 7 - Forward error frames

pub fn st(&mut self) -> ST_W<'_>

Bit 13 - Start/stop transmission

pub fn ttc(&mut self) -> TTC_W<'_>

Bits 14:16 - Transmit threshold control

pub fn ftf(&mut self) -> FTF_W<'_>

Bit 20 - Flush transmit FIFO

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 21 - Transmit store and forward

pub fn dfrf(&mut self) -> DFRF_W<'_>

Bit 24 - Disable flushing of received frames

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 25 - Receive store and forward

pub fn dtcefd(&mut self) -> DTCEFD_W<'_>

Bit 26 - Dropping of TCP/IP checksum error frames disable

impl W<u32, Reg<u32, _DMAIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 0 - Transmit interrupt enable

pub fn tpsie(&mut self) -> TPSIE_W<'_>

Bit 1 - Transmit process stopped interrupt enable

pub fn tbuie(&mut self) -> TBUIE_W<'_>

Bit 2 - Transmit buffer unavailable interrupt enable

pub fn tjtie(&mut self) -> TJTIE_W<'_>

Bit 3 - Transmit jabber timeout interrupt enable

pub fn roie(&mut self) -> ROIE_W<'_>

Bit 4 - Receive overflow interrupt enable

pub fn tuie(&mut self) -> TUIE_W<'_>

Bit 5 - Transmit underflow interrupt enable

pub fn rie(&mut self) -> RIE_W<'_>

Bit 6 - Receive interrupt enable

pub fn rbuie(&mut self) -> RBUIE_W<'_>

Bit 7 - Receive buffer unavailable interrupt enable

pub fn rpsie(&mut self) -> RPSIE_W<'_>

Bit 8 - Receive process stopped interrupt enable

pub fn rwtie(&mut self) -> RWTIE_W<'_>

Bit 9 - Receive watchdog timeout interrupt enable

pub fn etie(&mut self) -> ETIE_W<'_>

Bit 10 - Early transmit interrupt enable

pub fn fbeie(&mut self) -> FBEIE_W<'_>

Bit 13 - Fatal bus error interrupt enable

pub fn erie(&mut self) -> ERIE_W<'_>

Bit 14 - Early receive interrupt enable

pub fn aise(&mut self) -> AISE_W<'_>

Bit 15 - Abnormal interrupt summary enable

pub fn nise(&mut self) -> NISE_W<'_>

Bit 16 - Normal interrupt summary enable

impl W<u32, Reg<u32, _DMAMFBOCR>>

pub fn mfc(&mut self) -> MFC_W<'_>

Bits 0:15 - Missed frames by the controller

pub fn omfc(&mut self) -> OMFC_W<'_>

Bit 16 - Overflow bit for missed frame counter

pub fn mfa(&mut self) -> MFA_W<'_>

Bits 17:27 - Missed frames by the application

pub fn ofoc(&mut self) -> OFOC_W<'_>

Bit 28 - Overflow bit for FIFO overflow counter

impl W<u32, Reg<u32, _DMARSWTR>>

pub fn rswtc(&mut self) -> RSWTC_W<'_>

Bits 0:7 - Receive status watchdog timer count

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data Register

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - Independent Data register

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - Control regidter

impl W<u32, Reg<u32, _GOTGCTL>>

pub fn srq(&mut self) -> SRQ_W<'_>

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>

Bit 11 - Device HNP enabled

impl W<u32, Reg<u32, _GOTGINT>>

pub fn sedet(&mut self) -> SEDET_W<'_>

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>

Bit 19 - Debounce done

impl W<u32, Reg<u32, _GAHBCFG>>

pub fn gint(&mut self) -> GINT_W<'_>

Bit 0 - Global interrupt mask

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _GUSBCFG>>

pub fn tocal(&mut self) -> TOCAL_W<'_>

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>

Bit 6 - Full Speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>

Bits 10:13 - USB turnaround time

pub fn fhmod(&mut self) -> FHMOD_W<'_>

Bit 29 - Force host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>

Bit 30 - Force device mode

pub fn ctxpkt(&mut self) -> CTXPKT_W<'_>

Bit 31 - Corrupt Tx packet

impl W<u32, Reg<u32, _GRSTCTL>>

pub fn csrst(&mut self) -> CSRST_W<'_>

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _GINTSTS>>

pub fn mmis(&mut self) -> MMIS_W<'_>

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>

Bit 20 - Incomplete isochronous IN transfer

pub fn ipxfr_incompisoout(&mut self) -> IPXFR_INCOMPISOOUT_W<'_>

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>

Bit 30 - Session request/new session detected interrupt

pub fn wkupint(&mut self) -> WKUPINT_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _GINTMSK>>

pub fn mmism(&mut self) -> MMISM_W<'_>

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>

Bit 4 - Receive FIFO non-empty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>

Bit 5 - Non-periodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>

Bit 6 - Global non-periodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>

Bit 15 - End of periodic frame interrupt mask

pub fn epmism(&mut self) -> EPMISM_W<'_>

Bit 17 - Endpoint mismatch interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>

Bit 20 - Incomplete isochronous IN transfer mask

pub fn ipxfrm_iisooxfrm(&mut self) -> IPXFRM_IISOOXFRM_W<'_>

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

pub fn hcim(&mut self) -> HCIM_W<'_>

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt mask

impl W<u32, Reg<u32, _GRXFSIZ>>

pub fn rxfd(&mut self) -> RXFD_W<'_>

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF0>>

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _HNPTXFSIZ>>

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>

Bits 0:15 - Non-periodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>

Bits 16:31 - Non-periodic TxFIFO depth

impl W<u32, Reg<u32, _GCCFG>>

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>

Bit 16 - Power down

pub fn vbusasen(&mut self) -> VBUSASEN_W<'_>

Bit 18 - Enable the VBUS sensing device

pub fn vbusbsen(&mut self) -> VBUSBSEN_W<'_>

Bit 19 - Enable the VBUS sensing device

pub fn sofouten(&mut self) -> SOFOUTEN_W<'_>

Bit 20 - SOF output enable

impl W<u32, Reg<u32, _CID>>

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _HPTXFSIZ>>

pub fn ptxsa(&mut self) -> PTXSA_W<'_>

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfsiz(&mut self) -> PTXFSIZ_W<'_>

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _HCFG>>

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _HFIR>>

pub fn frivl(&mut self) -> FRIVL_W<'_>

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _HPTXSTS>>

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _HAINTMSK>>

pub fn haintm(&mut self) -> HAINTM_W<'_>

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _HPRT>>

pub fn pcdet(&mut self) -> PCDET_W<'_>

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _HCCHAR0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR4>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR5>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR6>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR7>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINTMSK0>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK2>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK3>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK4>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK5>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK6>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK7>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ5>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ6>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ7>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _DCFG>>

pub fn dspd(&mut self) -> DSPD_W<'_>

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>

Bit 2 - Non-zero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>

Bits 11:12 - Periodic frame interval

impl W<u32, Reg<u32, _DCTL>>

pub fn rwusig(&mut self) -> RWUSIG_W<'_>

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _DIEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

impl W<u32, Reg<u32, _DOEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>

Bit 4 - OUT token received when endpoint disabled mask

impl W<u32, Reg<u32, _DAINTMSK>>

pub fn iepm(&mut self) -> IEPM_W<'_>

Bits 0:15 - IN EP interrupt mask bits

pub fn oepm(&mut self) -> OEPM_W<'_>

Bits 16:31 - OUT EP interrupt mask bits

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _DIEPCTL0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:1 - Maximum packet size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPCTL>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm_sd1pid(&mut self) -> SODDFRM_SD1PID_W<'_>

Bit 29 - SODDFRM/SD1PID

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL0>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

impl W<u32, Reg<u32, _DOEPCTL>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPINT0>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT1>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT2>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT3>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT0>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT1>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT2>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT3>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPTSIZ0>>

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ0>>

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>

Bits 29:30 - SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bit 19 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ1>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ2>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ3>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ1>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ2>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ3>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _PCGCCTL>>

pub fn stppclk(&mut self) -> STPPCLK_W<'_>

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>

Bit 4 - PHY Suspended

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>

pub fn can2sb(&mut self) -> CAN2SB_W<'_>

Bits 8:13 - CAN2SB

pub fn finit(&mut self) -> FINIT_W<'_>

Bit 0 - FINIT

impl W<u32, Reg<u32, _FM1R>>

pub fn fbm0(&mut self) -> FBM0_W<'_>

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>

Bit 13 - Filter mode

pub fn fbm14(&mut self) -> FBM14_W<'_>

Bit 14 - Filter mode

pub fn fbm15(&mut self) -> FBM15_W<'_>

Bit 15 - Filter mode

pub fn fbm16(&mut self) -> FBM16_W<'_>

Bit 16 - Filter mode

pub fn fbm17(&mut self) -> FBM17_W<'_>

Bit 17 - Filter mode

pub fn fbm18(&mut self) -> FBM18_W<'_>

Bit 18 - Filter mode

pub fn fbm19(&mut self) -> FBM19_W<'_>

Bit 19 - Filter mode

pub fn fbm20(&mut self) -> FBM20_W<'_>

Bit 20 - Filter mode

pub fn fbm21(&mut self) -> FBM21_W<'_>

Bit 21 - Filter mode

pub fn fbm22(&mut self) -> FBM22_W<'_>

Bit 22 - Filter mode

pub fn fbm23(&mut self) -> FBM23_W<'_>

Bit 23 - Filter mode

pub fn fbm24(&mut self) -> FBM24_W<'_>

Bit 24 - Filter mode

pub fn fbm25(&mut self) -> FBM25_W<'_>

Bit 25 - Filter mode

pub fn fbm26(&mut self) -> FBM26_W<'_>

Bit 26 - Filter mode

pub fn fbm27(&mut self) -> FBM27_W<'_>

Bit 27 - Filter mode

impl W<u32, Reg<u32, _FS1R>>

pub fn fsc0(&mut self) -> FSC0_W<'_>

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>

Bit 13 - Filter scale configuration

pub fn fsc14(&mut self) -> FSC14_W<'_>

Bit 14 - Filter scale configuration

pub fn fsc15(&mut self) -> FSC15_W<'_>

Bit 15 - Filter scale configuration

pub fn fsc16(&mut self) -> FSC16_W<'_>

Bit 16 - Filter scale configuration

pub fn fsc17(&mut self) -> FSC17_W<'_>

Bit 17 - Filter scale configuration

pub fn fsc18(&mut self) -> FSC18_W<'_>

Bit 18 - Filter scale configuration

pub fn fsc19(&mut self) -> FSC19_W<'_>

Bit 19 - Filter scale configuration

pub fn fsc20(&mut self) -> FSC20_W<'_>

Bit 20 - Filter scale configuration

pub fn fsc21(&mut self) -> FSC21_W<'_>

Bit 21 - Filter scale configuration

pub fn fsc22(&mut self) -> FSC22_W<'_>

Bit 22 - Filter scale configuration

pub fn fsc23(&mut self) -> FSC23_W<'_>

Bit 23 - Filter scale configuration

pub fn fsc24(&mut self) -> FSC24_W<'_>

Bit 24 - Filter scale configuration

pub fn fsc25(&mut self) -> FSC25_W<'_>

Bit 25 - Filter scale configuration

pub fn fsc26(&mut self) -> FSC26_W<'_>

Bit 26 - Filter scale configuration

pub fn fsc27(&mut self) -> FSC27_W<'_>

Bit 27 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>

pub fn ffa0(&mut self) -> FFA0_W<'_>

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>

Bit 13 - Filter FIFO assignment for filter 13

pub fn ffa14(&mut self) -> FFA14_W<'_>

Bit 14 - Filter FIFO assignment for filter 14

pub fn ffa15(&mut self) -> FFA15_W<'_>

Bit 15 - Filter FIFO assignment for filter 15

pub fn ffa16(&mut self) -> FFA16_W<'_>

Bit 16 - Filter FIFO assignment for filter 16

pub fn ffa17(&mut self) -> FFA17_W<'_>

Bit 17 - Filter FIFO assignment for filter 17

pub fn ffa18(&mut self) -> FFA18_W<'_>

Bit 18 - Filter FIFO assignment for filter 18

pub fn ffa19(&mut self) -> FFA19_W<'_>

Bit 19 - Filter FIFO assignment for filter 19

pub fn ffa20(&mut self) -> FFA20_W<'_>

Bit 20 - Filter FIFO assignment for filter 20

pub fn ffa21(&mut self) -> FFA21_W<'_>

Bit 21 - Filter FIFO assignment for filter 21

pub fn ffa22(&mut self) -> FFA22_W<'_>

Bit 22 - Filter FIFO assignment for filter 22

pub fn ffa23(&mut self) -> FFA23_W<'_>

Bit 23 - Filter FIFO assignment for filter 23

pub fn ffa24(&mut self) -> FFA24_W<'_>

Bit 24 - Filter FIFO assignment for filter 24

pub fn ffa25(&mut self) -> FFA25_W<'_>

Bit 25 - Filter FIFO assignment for filter 25

pub fn ffa26(&mut self) -> FFA26_W<'_>

Bit 26 - Filter FIFO assignment for filter 26

pub fn ffa27(&mut self) -> FFA27_W<'_>

Bit 27 - Filter FIFO assignment for filter 27

impl W<u32, Reg<u32, _FA1R>>

pub fn fact0(&mut self) -> FACT0_W<'_>

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>

Bit 13 - Filter active

pub fn fact14(&mut self) -> FACT14_W<'_>

Bit 14 - Filter active

pub fn fact15(&mut self) -> FACT15_W<'_>

Bit 15 - Filter active

pub fn fact16(&mut self) -> FACT16_W<'_>

Bit 16 - Filter active

pub fn fact17(&mut self) -> FACT17_W<'_>

Bit 17 - Filter active

pub fn fact18(&mut self) -> FACT18_W<'_>

Bit 18 - Filter active

pub fn fact19(&mut self) -> FACT19_W<'_>

Bit 19 - Filter active

pub fn fact20(&mut self) -> FACT20_W<'_>

Bit 20 - Filter active

pub fn fact21(&mut self) -> FACT21_W<'_>

Bit 21 - Filter active

pub fn fact22(&mut self) -> FACT22_W<'_>

Bit 22 - Filter active

pub fn fact23(&mut self) -> FACT23_W<'_>

Bit 23 - Filter active

pub fn fact24(&mut self) -> FACT24_W<'_>

Bit 24 - Filter active

pub fn fact25(&mut self) -> FACT25_W<'_>

Bit 25 - Filter active

pub fn fact26(&mut self) -> FACT26_W<'_>

Bit 26 - Filter active

pub fn fact27(&mut self) -> FACT27_W<'_>

Bit 27 - Filter active

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn dcen(&mut self) -> DCEN_W<'_>

Bit 10 - Data cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn dcrst(&mut self) -> DCRST_W<'_>

Bit 12 - Data cache reset

impl W<u32, Reg<u32, _KEYR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - FPEC key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkey(&mut self) -> OPTKEY_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protection error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn pgperr(&mut self) -> PGPERR_W<'_>

Bit 6 - Programming parallelism error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn ser(&mut self) -> SER_W<'_>

Bit 1 - Sector Erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass Erase

pub fn snb(&mut self) -> SNB_W<'_>

Bits 3:6 - Sector number

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Program size

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - Lock

impl W<u32, Reg<u32, _OPTCR>>

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 0 - Option lock

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 1 - Option start

pub fn bor_lev(&mut self) -> BOR_LEV_W<'_>

Bits 2:3 - BOR reset Level

pub fn wdg_sw(&mut self) -> WDG_SW_W<'_>

Bit 5 - WDG_SW User option bytes

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 6 - nRST_STOP User option bytes

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 7 - nRST_STDBY User option bytes

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 8:15 - Read protect

pub fn n_wrp(&mut self) -> NWRP_W<'_>

Bits 16:27 - Not write protect

impl W<u32, Reg<u32, _IMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Interrupt Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Interrupt Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Interrupt Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Interrupt Mask on line 22

impl W<u32, Reg<u32, _EMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Event Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Event Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Event Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Event Mask on line 22

impl W<u32, Reg<u32, _RTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Rising trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Rising trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Rising trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Rising trigger event configuration of line 22

impl W<u32, Reg<u32, _FTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Falling trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Falling trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Falling trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Falling trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Falling trigger event configuration of line 22

impl W<u32, Reg<u32, _SWIER>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

pub fn swier19(&mut self) -> SWIER19_W<'_>

Bit 19 - Software Interrupt on line 19

pub fn swier20(&mut self) -> SWIER20_W<'_>

Bit 20 - Software Interrupt on line 20

pub fn swier21(&mut self) -> SWIER21_W<'_>

Bit 21 - Software Interrupt on line 21

pub fn swier22(&mut self) -> SWIER22_W<'_>

Bit 22 - Software Interrupt on line 22

impl W<u32, Reg<u32, _PR>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

pub fn pr19(&mut self) -> PR19_W<'_>

Bit 19 - Pending bit 19

pub fn pr20(&mut self) -> PR20_W<'_>

Bit 20 - Pending bit 20

pub fn pr21(&mut self) -> PR21_W<'_>

Bit 21 - Pending bit 21

pub fn pr22(&mut self) -> PR22_W<'_>

Bit 22 - Pending bit 22

impl W<u32, Reg<u32, _GOTGCTL>>

pub fn srq(&mut self) -> SRQ_W<'_>

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>

Bit 11 - Device HNP enabled

impl W<u32, Reg<u32, _GOTGINT>>

pub fn sedet(&mut self) -> SEDET_W<'_>

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>

Bit 19 - Debounce done

impl W<u32, Reg<u32, _GAHBCFG>>

pub fn gint(&mut self) -> GINT_W<'_>

Bit 0 - Global interrupt mask

pub fn hbstlen(&mut self) -> HBSTLEN_W<'_>

Bits 1:4 - Burst length/type

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 5 - DMA enable

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _GUSBCFG>>

pub fn tocal(&mut self) -> TOCAL_W<'_>

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>

Bit 6 - USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>

Bits 10:13 - USB turnaround time

pub fn phylpcs(&mut self) -> PHYLPCS_W<'_>

Bit 15 - PHY Low-power clock select

pub fn ulpifsls(&mut self) -> ULPIFSLS_W<'_>

Bit 17 - ULPI FS/LS select

pub fn ulpiar(&mut self) -> ULPIAR_W<'_>

Bit 18 - ULPI Auto-resume

pub fn ulpicsm(&mut self) -> ULPICSM_W<'_>

Bit 19 - ULPI Clock SuspendM

pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W<'_>

Bit 20 - ULPI External VBUS Drive

pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W<'_>

Bit 21 - ULPI external VBUS indicator

pub fn tsdps(&mut self) -> TSDPS_W<'_>

Bit 22 - TermSel DLine pulsing selection

pub fn pcci(&mut self) -> PCCI_W<'_>

Bit 23 - Indicator complement

pub fn ptci(&mut self) -> PTCI_W<'_>

Bit 24 - Indicator pass through

pub fn ulpiipd(&mut self) -> ULPIIPD_W<'_>

Bit 25 - ULPI interface protect disable

pub fn fhmod(&mut self) -> FHMOD_W<'_>

Bit 29 - Forced host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>

Bit 30 - Forced peripheral mode

pub fn ctxpkt(&mut self) -> CTXPKT_W<'_>

Bit 31 - Corrupt Tx packet

impl W<u32, Reg<u32, _GRSTCTL>>

pub fn csrst(&mut self) -> CSRST_W<'_>

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _GINTSTS>>

pub fn mmis(&mut self) -> MMIS_W<'_>

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>

Bit 20 - Incomplete isochronous IN transfer

pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W<'_>

Bit 21 - Incomplete periodic transfer

pub fn datafsusp(&mut self) -> DATAFSUSP_W<'_>

Bit 22 - Data fetch suspended

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>

Bit 30 - Session request/new session detected interrupt

pub fn wkupint(&mut self) -> WKUPINT_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _GINTMSK>>

pub fn mmism(&mut self) -> MMISM_W<'_>

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>

Bit 4 - Receive FIFO nonempty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>

Bit 5 - Nonperiodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>

Bit 6 - Global nonperiodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>

Bit 15 - End of periodic frame interrupt mask

pub fn epmism(&mut self) -> EPMISM_W<'_>

Bit 17 - Endpoint mismatch interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>

Bit 20 - Incomplete isochronous IN transfer mask

pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W<'_>

Bit 21 - Incomplete periodic transfer mask

pub fn fsuspm(&mut self) -> FSUSPM_W<'_>

Bit 22 - Data fetch suspended mask

pub fn hcim(&mut self) -> HCIM_W<'_>

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt mask

impl W<u32, Reg<u32, _GRXFSIZ>>

pub fn rxfd(&mut self) -> RXFD_W<'_>

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _GNPTXFSIZ>>

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>

Bits 0:15 - Nonperiodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>

Bits 16:31 - Nonperiodic TxFIFO depth

impl W<u32, Reg<u32, _TX0FSIZ>>

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _GCCFG>>

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>

Bit 16 - Power down

pub fn i2cpaden(&mut self) -> I2CPADEN_W<'_>

Bit 17 - Enable I2C bus connection for the external I2C PHY interface

pub fn vbusasen(&mut self) -> VBUSASEN_W<'_>

Bit 18 - Enable the VBUS sensing device

pub fn vbusbsen(&mut self) -> VBUSBSEN_W<'_>

Bit 19 - Enable the VBUS sensing device

pub fn sofouten(&mut self) -> SOFOUTEN_W<'_>

Bit 20 - SOF output enable

pub fn novbussens(&mut self) -> NOVBUSSENS_W<'_>

Bit 21 - VBUS sensing disable option

impl W<u32, Reg<u32, _CID>>

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _HPTXFSIZ>>

pub fn ptxsa(&mut self) -> PTXSA_W<'_>

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfd(&mut self) -> PTXFD_W<'_>

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _HCFG>>

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _HFIR>>

pub fn frivl(&mut self) -> FRIVL_W<'_>

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _HPTXSTS>>

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _HAINTMSK>>

pub fn haintm(&mut self) -> HAINTM_W<'_>

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _HPRT>>

pub fn pcdet(&mut self) -> PCDET_W<'_>

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _HCCHAR0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR4>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR5>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR6>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR7>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR8>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR9>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR10>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR11>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCSPLT0>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT1>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT2>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT3>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT4>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT5>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT6>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT7>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT8>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT9>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT10>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT11>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT8>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT9>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT10>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT11>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINTMSK0>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK2>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK3>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK4>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK5>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK6>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK7>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK8>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK9>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK10>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK11>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ5>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ6>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ7>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ8>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ9>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ10>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ11>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCDMA0>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA1>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA2>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA3>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA4>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA5>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA6>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA7>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA8>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA9>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA10>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA11>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DCFG>>

pub fn dspd(&mut self) -> DSPD_W<'_>

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>

Bit 2 - Nonzero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>

Bits 11:12 - Periodic (micro)frame interval

pub fn perschivl(&mut self) -> PERSCHIVL_W<'_>

Bits 24:25 - Periodic scheduling interval

impl W<u32, Reg<u32, _DCTL>>

pub fn rwusig(&mut self) -> RWUSIG_W<'_>

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _DIEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (nonisochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

pub fn txfurm(&mut self) -> TXFURM_W<'_>

Bit 8 - FIFO underrun mask

pub fn bim(&mut self) -> BIM_W<'_>

Bit 9 - BNA interrupt mask

impl W<u32, Reg<u32, _DOEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>

Bit 4 - OUT token received when endpoint disabled mask

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - Back-to-back SETUP packets received mask

pub fn opem(&mut self) -> OPEM_W<'_>

Bit 8 - OUT packet error mask

pub fn boim(&mut self) -> BOIM_W<'_>

Bit 9 - BNA interrupt mask

impl W<u32, Reg<u32, _DAINTMSK>>

pub fn iepm(&mut self) -> IEPM_W<'_>

Bits 0:15 - IN EP interrupt mask bits

pub fn oepm(&mut self) -> OEPM_W<'_>

Bits 16:31 - OUT EP interrupt mask bits

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _DTHRCTL>>

pub fn nonisothren(&mut self) -> NONISOTHREN_W<'_>

Bit 0 - Nonisochronous IN endpoints threshold enable

pub fn isothren(&mut self) -> ISOTHREN_W<'_>

Bit 1 - ISO IN endpoint threshold enable

pub fn txthrlen(&mut self) -> TXTHRLEN_W<'_>

Bits 2:10 - Transmit threshold length

pub fn rxthren(&mut self) -> RXTHREN_W<'_>

Bit 16 - Receive threshold enable

pub fn rxthrlen(&mut self) -> RXTHRLEN_W<'_>

Bits 17:25 - Receive threshold length

pub fn arpen(&mut self) -> ARPEN_W<'_>

Bit 27 - Arbiter parking enable

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _DEACHINT>>

pub fn iep1int(&mut self) -> IEP1INT_W<'_>

Bit 1 - IN endpoint 1interrupt bit

pub fn oep1int(&mut self) -> OEP1INT_W<'_>

Bit 17 - OUT endpoint 1 interrupt bit

impl W<u32, Reg<u32, _DEACHINTMSK>>

pub fn iep1intm(&mut self) -> IEP1INTM_W<'_>

Bit 1 - IN Endpoint 1 interrupt mask bit

pub fn oep1intm(&mut self) -> OEP1INTM_W<'_>

Bit 17 - OUT Endpoint 1 interrupt mask bit

impl W<u32, Reg<u32, _DIEPEACHMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (nonisochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

pub fn txfurm(&mut self) -> TXFURM_W<'_>

Bit 8 - FIFO underrun mask

pub fn bim(&mut self) -> BIM_W<'_>

Bit 9 - BNA interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 13 - NAK interrupt mask

impl W<u32, Reg<u32, _DOEPEACHMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

pub fn txfurm(&mut self) -> TXFURM_W<'_>

Bit 8 - OUT packet error mask

pub fn bim(&mut self) -> BIM_W<'_>

Bit 9 - BNA interrupt mask

pub fn berrm(&mut self) -> BERRM_W<'_>

Bit 12 - Bubble error interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 13 - NAK interrupt mask

pub fn nyetm(&mut self) -> NYETM_W<'_>

Bit 14 - NYET interrupt mask

impl W<u32, Reg<u32, _DIEPCTL0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPCTL>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPINT>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _DIEPTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet count

impl W<u32, Reg<u32, _DIEPDMA1>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DIEPDMA2>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DIEPDMA3>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DIEPDMA4>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DIEPDMA5>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DIEPTSIZ>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _DOEPCTL0>>

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DOEPCTL>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DOEPINT>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _DOEPTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bit 19 - Packet count

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>

Bits 29:30 - SETUP packet count

impl W<u32, Reg<u32, _DOEPTSIZ>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _PCGCCTL>>

pub fn stppclk(&mut self) -> STPPCLK_W<'_>

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>

Bit 4 - PHY suspended

impl W<u32, Reg<u32, _CR1>>

pub fn mckdiv(&mut self) -> MCKDIV_W<'_>

Bits 20:23 - Master clock divider

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Audio block mode

pub fn prtcfg(&mut self) -> PRTCFG_W<'_>

Bits 2:3 - Protocol configuration

pub fn ds(&mut self) -> DS_W<'_>

Bits 5:7 - Data size

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 8 - Least significant bit first

pub fn ckstr(&mut self) -> CKSTR_W<'_>

Bit 9 - Clock strobing edge

pub fn syncen(&mut self) -> SYNCEN_W<'_>

Bits 10:11 - Synchronization enable

pub fn mono(&mut self) -> MONO_W<'_>

Bit 12 - Mono mode

pub fn outdriv(&mut self) -> OUTDRIV_W<'_>

Bit 13 - Output drive

pub fn saien(&mut self) -> SAIEN_W<'_>

Bit 16 - Audio block enable

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 17 - DMA enable

pub fn nodiv(&mut self) -> NODIV_W<'_>

Bit 19 - No divider

impl W<u32, Reg<u32, _CR2>>

pub fn fth(&mut self) -> FTH_W<'_>

Bits 0:2 - FIFO threshold

pub fn fflush(&mut self) -> FFLUSH_W<'_>

Bit 3 - FIFO flush

pub fn tris(&mut self) -> TRIS_W<'_>

Bit 4 - Tristate management on data line

pub fn mute(&mut self) -> MUTE_W<'_>

Bit 5 - Mute

pub fn muteval(&mut self) -> MUTEVAL_W<'_>

Bit 6 - Mute value

pub fn mutecnt(&mut self) -> MUTECNT_W<'_>

Bits 7:12 - Mute counter

pub fn cpl(&mut self) -> CPL_W<'_>

Bit 13 - Complement bit

pub fn comp(&mut self) -> COMP_W<'_>

Bits 14:15 - Companding mode

impl W<u32, Reg<u32, _FRCR>>

pub fn frl(&mut self) -> FRL_W<'_>

Bits 0:7 - Frame length

pub fn fsall(&mut self) -> FSALL_W<'_>

Bits 8:14 - Frame synchronization active level length

pub fn fspol(&mut self) -> FSPOL_W<'_>

Bit 17 - Frame synchronization polarity

pub fn fsoff(&mut self) -> FSOFF_W<'_>

Bit 18 - Frame synchronization offset

impl W<u32, Reg<u32, _SLOTR>>

pub fn fboff(&mut self) -> FBOFF_W<'_>

Bits 0:4 - First bit offset

pub fn slotsz(&mut self) -> SLOTSZ_W<'_>

Bits 6:7 - Slot size

pub fn nbslot(&mut self) -> NBSLOT_W<'_>

Bits 8:11 - Number of slots in an audio frame

pub fn sloten(&mut self) -> SLOTEN_W<'_>

Bits 16:31 - Slot enable

impl W<u32, Reg<u32, _IM>>

pub fn ovrudrie(&mut self) -> OVRUDRIE_W<'_>

Bit 0 - Overrun/underrun interrupt enable

pub fn mutedetie(&mut self) -> MUTEDETIE_W<'_>

Bit 1 - Mute detection interrupt enable

pub fn wckcfgie(&mut self) -> WCKCFGIE_W<'_>

Bit 2 - Wrong clock configuration interrupt enable

pub fn freqie(&mut self) -> FREQIE_W<'_>

Bit 3 - FIFO request interrupt enable

pub fn cnrdyie(&mut self) -> CNRDYIE_W<'_>

Bit 4 - Codec not ready interrupt enable

pub fn afsdetie(&mut self) -> AFSDETIE_W<'_>

Bit 5 - Anticipated frame synchronization detection interrupt enable

pub fn lfsdetie(&mut self) -> LFSDETIE_W<'_>

Bit 6 - Late frame synchronization detection interrupt enable

impl W<u32, Reg<u32, _CLRFR>>

pub fn covrudr(&mut self) -> COVRUDR_W<'_>

Bit 0 - Clear overrun / underrun

pub fn cmutedet(&mut self) -> CMUTEDET_W<'_>

Bit 1 - Mute detection flag

pub fn cwckcfg(&mut self) -> CWCKCFG_W<'_>

Bit 2 - Clear wrong clock configuration flag

pub fn ccnrdy(&mut self) -> CCNRDY_W<'_>

Bit 4 - Clear codec not ready flag

pub fn cafsdet(&mut self) -> CAFSDET_W<'_>

Bit 5 - Clear anticipated frame synchronization detection flag

pub fn clfsdet(&mut self) -> CLFSDET_W<'_>

Bit 6 - Clear late frame synchronization detection flag

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _CR>>

pub fn cluten(&mut self) -> CLUTEN_W<'_>

Bit 4 - Color Look-Up Table Enable

pub fn colken(&mut self) -> COLKEN_W<'_>

Bit 1 - Color Keying Enable

pub fn len(&mut self) -> LEN_W<'_>

Bit 0 - Layer Enable

impl W<u32, Reg<u32, _WHPCR>>

pub fn whsppos(&mut self) -> WHSPPOS_W<'_>

Bits 16:27 - Window Horizontal Stop Position

pub fn whstpos(&mut self) -> WHSTPOS_W<'_>

Bits 0:11 - Window Horizontal Start Position

impl W<u32, Reg<u32, _WVPCR>>

pub fn wvsppos(&mut self) -> WVSPPOS_W<'_>

Bits 16:26 - Window Vertical Stop Position

pub fn wvstpos(&mut self) -> WVSTPOS_W<'_>

Bits 0:10 - Window Vertical Start Position

impl W<u32, Reg<u32, _CKCR>>

pub fn ckred(&mut self) -> CKRED_W<'_>

Bits 16:23 - Color Key Red value

pub fn ckgreen(&mut self) -> CKGREEN_W<'_>

Bits 8:15 - Color Key Green value

pub fn ckblue(&mut self) -> CKBLUE_W<'_>

Bits 0:7 - Color Key Blue value

impl W<u32, Reg<u32, _PFCR>>

pub fn pf(&mut self) -> PF_W<'_>

Bits 0:2 - Pixel Format

impl W<u32, Reg<u32, _CACR>>

pub fn consta(&mut self) -> CONSTA_W<'_>

Bits 0:7 - Constant Alpha

impl W<u32, Reg<u32, _DCCR>>

pub fn dcalpha(&mut self) -> DCALPHA_W<'_>

Bits 24:31 - Default Color Alpha

pub fn dcred(&mut self) -> DCRED_W<'_>

Bits 16:23 - Default Color Red

pub fn dcgreen(&mut self) -> DCGREEN_W<'_>

Bits 8:15 - Default Color Green

pub fn dcblue(&mut self) -> DCBLUE_W<'_>

Bits 0:7 - Default Color Blue

impl W<u32, Reg<u32, _BFCR>>

pub fn bf1(&mut self) -> BF1_W<'_>

Bits 8:10 - Blending Factor 1

pub fn bf2(&mut self) -> BF2_W<'_>

Bits 0:2 - Blending Factor 2

impl W<u32, Reg<u32, _CFBAR>>

pub fn cfbadd(&mut self) -> CFBADD_W<'_>

Bits 0:31 - Color Frame Buffer Start Address

impl W<u32, Reg<u32, _CFBLR>>

pub fn cfbp(&mut self) -> CFBP_W<'_>

Bits 16:28 - Color Frame Buffer Pitch in bytes

pub fn cfbll(&mut self) -> CFBLL_W<'_>

Bits 0:12 - Color Frame Buffer Line Length

impl W<u32, Reg<u32, _CFBLNR>>

pub fn cfblnbr(&mut self) -> CFBLNBR_W<'_>

Bits 0:10 - Frame Buffer Line Number

impl W<u32, Reg<u32, _CLUTWR>>

pub fn clutadd(&mut self) -> CLUTADD_W<'_>

Bits 24:31 - CLUT Address

pub fn red(&mut self) -> RED_W<'_>

Bits 16:23 - Red value

pub fn green(&mut self) -> GREEN_W<'_>

Bits 8:15 - Green value

pub fn blue(&mut self) -> BLUE_W<'_>

Bits 0:7 - Blue value

impl W<u32, Reg<u32, _SSCR>>

pub fn hsw(&mut self) -> HSW_W<'_>

Bits 16:27 - Horizontal Synchronization Width (in units of pixel clock period)

pub fn vsh(&mut self) -> VSH_W<'_>

Bits 0:10 - Vertical Synchronization Height (in units of horizontal scan line)

impl W<u32, Reg<u32, _BPCR>>

pub fn ahbp(&mut self) -> AHBP_W<'_>

Bits 16:27 - Accumulated Horizontal back porch (in units of pixel clock period)

pub fn avbp(&mut self) -> AVBP_W<'_>

Bits 0:10 - Accumulated Vertical back porch (in units of horizontal scan line)

impl W<u32, Reg<u32, _AWCR>>

pub fn aaw(&mut self) -> AAW_W<'_>

Bits 16:27 - Accumulated Active Width (in units of pixel clock period)

pub fn aah(&mut self) -> AAH_W<'_>

Bits 0:10 - Accumulated Active Height (in units of horizontal scan line)

impl W<u32, Reg<u32, _TWCR>>

pub fn totalw(&mut self) -> TOTALW_W<'_>

Bits 16:27 - Total Width (in units of pixel clock period)

pub fn totalh(&mut self) -> TOTALH_W<'_>

Bits 0:10 - Total Height (in units of horizontal scan line)

impl W<u32, Reg<u32, _GCR>>

pub fn hspol(&mut self) -> HSPOL_W<'_>

Bit 31 - Horizontal Synchronization Polarity

pub fn vspol(&mut self) -> VSPOL_W<'_>

Bit 30 - Vertical Synchronization Polarity

pub fn depol(&mut self) -> DEPOL_W<'_>

Bit 29 - Data Enable Polarity

pub fn pcpol(&mut self) -> PCPOL_W<'_>

Bit 28 - Pixel Clock Polarity

pub fn den(&mut self) -> DEN_W<'_>

Bit 16 - Dither Enable

pub fn ltdcen(&mut self) -> LTDCEN_W<'_>

Bit 0 - LCD-TFT controller enable bit

impl W<u32, Reg<u32, _SRCR>>

pub fn vbr(&mut self) -> VBR_W<'_>

Bit 1 - Vertical Blanking Reload

pub fn imr(&mut self) -> IMR_W<'_>

Bit 0 - Immediate Reload

impl W<u32, Reg<u32, _BCCR>>

pub fn bcblue(&mut self) -> BCBLUE_W<'_>

Bits 0:7 - Background color blue value

pub fn bcgreen(&mut self) -> BCGREEN_W<'_>

Bits 8:15 - Background color green value

pub fn bcred(&mut self) -> BCRED_W<'_>

Bits 16:23 - Background color red value

impl W<u32, Reg<u32, _IER>>

pub fn rrie(&mut self) -> RRIE_W<'_>

Bit 3 - Register Reload interrupt enable

pub fn terrie(&mut self) -> TERRIE_W<'_>

Bit 2 - Transfer Error Interrupt Enable

pub fn fuie(&mut self) -> FUIE_W<'_>

Bit 1 - FIFO Underrun Interrupt Enable

pub fn lie(&mut self) -> LIE_W<'_>

Bit 0 - Line Interrupt Enable

impl W<u32, Reg<u32, _ICR>>

pub fn crrif(&mut self) -> CRRIF_W<'_>

Bit 3 - Clears Register Reload Interrupt Flag

pub fn cterrif(&mut self) -> CTERRIF_W<'_>

Bit 2 - Clears the Transfer Error Interrupt Flag

pub fn cfuif(&mut self) -> CFUIF_W<'_>

Bit 1 - Clears the FIFO Underrun Interrupt flag

pub fn clif(&mut self) -> CLIF_W<'_>

Bit 0 - Clears the Line Interrupt Flag

impl W<u32, Reg<u32, _LIPCR>>

pub fn lipos(&mut self) -> LIPOS_W<'_>

Bits 0:10 - Line Interrupt Position

impl W<u32, Reg<u32, _CR>>

pub fn init(&mut self) -> INIT_W<'_>

Bit 2 - Initialize message digest calculation

pub fn dmae(&mut self) -> DMAE_W<'_>

Bit 3 - DMA enable

pub fn datatype(&mut self) -> DATATYPE_W<'_>

Bits 4:5 - Data type selection

pub fn mode(&mut self) -> MODE_W<'_>

Bit 6 - Mode selection

pub fn algo0(&mut self) -> ALGO0_W<'_>

Bit 7 - Algorithm selection

pub fn mdmat(&mut self) -> MDMAT_W<'_>

Bit 13 - Multiple DMA Transfers

pub fn lkey(&mut self) -> LKEY_W<'_>

Bit 16 - Long key selection

pub fn algo1(&mut self) -> ALGO1_W<'_>

Bit 18 - ALGO

impl W<u32, Reg<u32, _DIN>>

pub fn datain(&mut self) -> DATAIN_W<'_>

Bits 0:31 - Data input

impl W<u32, Reg<u32, _STR>>

pub fn dcal(&mut self) -> DCAL_W<'_>

Bit 8 - Digest calculation

pub fn nblw(&mut self) -> NBLW_W<'_>

Bits 0:4 - Number of valid bits in the last word of the message

impl W<u32, Reg<u32, _IMR>>

pub fn dcie(&mut self) -> DCIE_W<'_>

Bit 1 - Digest calculation completion interrupt enable

pub fn dinie(&mut self) -> DINIE_W<'_>

Bit 0 - Data input interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn dcis(&mut self) -> DCIS_W<'_>

Bit 1 - Digest calculation completion interrupt status

pub fn dinis(&mut self) -> DINIS_W<'_>

Bit 0 - Data input interrupt status

impl W<u32, Reg<u32, _CSR>>

pub fn csr(&mut self) -> CSR_W<'_>

Bits 0:31 - CSR0

impl W<u32, Reg<u32, _KLR>>

pub fn b2(&mut self) -> B2_W<'_>

Bits 0:31 - b224

impl W<u32, Reg<u32, _KRR>>

pub fn b(&mut self) -> B_W<'_>

Bits 0:31 - b192

impl W<u32, Reg<u32, _IVLR>>

pub fn iv(&mut self) -> IV_W<'_>

Bits 0:31 - IV31

impl W<u32, Reg<u32, _IVRR>>

pub fn iv(&mut self) -> IV_W<'_>

Bits 0:31 - IV63

impl W<u32, Reg<u32, _CR>>

pub fn algodir(&mut self) -> ALGODIR_W<'_>

Bit 2 - Algorithm direction

pub fn algomode0(&mut self) -> ALGOMODE0_W<'_>

Bits 3:5 - Algorithm mode

pub fn datatype(&mut self) -> DATATYPE_W<'_>

Bits 6:7 - Data type selection

pub fn keysize(&mut self) -> KEYSIZE_W<'_>

Bits 8:9 - Key size selection (AES mode only)

pub fn fflush(&mut self) -> FFLUSH_W<'_>

Bit 14 - FIFO flush

pub fn crypen(&mut self) -> CRYPEN_W<'_>

Bit 15 - Cryptographic processor enable

pub fn gcm_ccmph(&mut self) -> GCM_CCMPH_W<'_>

Bits 16:17 - GCM_CCMPH

pub fn algomode3(&mut self) -> ALGOMODE3_W<'_>

Bit 19 - ALGOMODE

impl W<u32, Reg<u32, _DIN>>

pub fn datain(&mut self) -> DATAIN_W<'_>

Bits 0:31 - Data input

impl W<u32, Reg<u32, _DMACR>>

pub fn doen(&mut self) -> DOEN_W<'_>

Bit 1 - DMA output enable

pub fn dien(&mut self) -> DIEN_W<'_>

Bit 0 - DMA input enable

impl W<u32, Reg<u32, _IMSCR>>

pub fn outim(&mut self) -> OUTIM_W<'_>

Bit 1 - Output FIFO service interrupt mask

pub fn inim(&mut self) -> INIM_W<'_>

Bit 0 - Input FIFO service interrupt mask

impl W<u32, Reg<u32, _CSGCMCCMR>>

pub fn csgcmccm0r(&mut self) -> CSGCMCCM0R_W<'_>

Bits 0:31 - CSGCMCCM0R

impl W<u32, Reg<u32, _CSGCMR>>

pub fn csgcmr(&mut self) -> CSGCMR_W<'_>

Bits 0:31 - CSGCM0R

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _CR>>

pub fn dmaouten(&mut self) -> DMAOUTEN_W<'_>

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&mut self) -> DMAINEN_W<'_>

Bit 11 - Enable DMA management of data input phase

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn ccfie(&mut self) -> CCFIE_W<'_>

Bit 9 - CCF flag interrupt enable

pub fn errc(&mut self) -> ERRC_W<'_>

Bit 8 - Error clear

pub fn ccfc(&mut self) -> CCFC_W<'_>

Bit 7 - Computation Complete Flag Clear

pub fn chmod(&mut self) -> CHMOD_W<'_>

Bits 5:6 - AES chaining mode

pub fn mode(&mut self) -> MODE_W<'_>

Bits 3:4 - AES operating mode

pub fn datatype(&mut self) -> DATATYPE_W<'_>

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - AES enable

impl W<u32, Reg<u32, _DINR>>

pub fn aes_dinr(&mut self) -> AES_DINR_W<'_>

Bits 0:31 - Data Input Register

impl W<u32, Reg<u32, _KEYR0>>

pub fn aes_keyr0(&mut self) -> AES_KEYR0_W<'_>

Bits 0:31 - Data Output Register (LSB key [31:0])

impl W<u32, Reg<u32, _KEYR1>>

pub fn aes_keyr1(&mut self) -> AES_KEYR1_W<'_>

Bits 0:31 - AES key register (key [63:32])

impl W<u32, Reg<u32, _KEYR2>>

pub fn aes_keyr2(&mut self) -> AES_KEYR2_W<'_>

Bits 0:31 - AES key register (key [95:64])

impl W<u32, Reg<u32, _KEYR3>>

pub fn aes_keyr3(&mut self) -> AES_KEYR3_W<'_>

Bits 0:31 - AES key register (MSB key [127:96])

impl W<u32, Reg<u32, _IVR0>>

pub fn aes_ivr0(&mut self) -> AES_IVR0_W<'_>

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl W<u32, Reg<u32, _IVR1>>

pub fn aes_ivr1(&mut self) -> AES_IVR1_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl W<u32, Reg<u32, _IVR2>>

pub fn aes_ivr2(&mut self) -> AES_IVR2_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl W<u32, Reg<u32, _IVR3>>

pub fn aes_ivr3(&mut self) -> AES_IVR3_W<'_>

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _SR>>

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 5 - Overrun

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 26 - Overrun interrupt enable

pub fn res(&mut self) -> RES_W<'_>

Bits 24:25 - Resolution

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 30 - Start conversion of regular channels

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 28:29 - External trigger enable for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 24:27 - External event select for regular group

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 22 - Start conversion of injected channels

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 20:21 - External trigger enable for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 16:19 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn eocs(&mut self) -> EOCS_W<'_>

Bit 10 - End of conversion selection

pub fn dds(&mut self) -> DDS_W<'_>

Bit 9 - DMA disable selection (for single ADC mode)

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode (for single ADC mode)

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D Converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp18(&mut self) -> SMP18_W<'_>

Bits 24:26 - Channel 18 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sampling time selection

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sampling time selection

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sampling time selection

impl W<u32, Reg<u32, _JOFR>>

pub fn joffset(&mut self) -> JOFFSET_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>

pub fn can2sb(&mut self) -> CAN2SB_W<'_>

Bits 8:13 - CAN2SB

pub fn finit(&mut self) -> FINIT_W<'_>

Bit 0 - FINIT

impl W<u32, Reg<u32, _FM1R>>

pub fn fbm0(&mut self) -> FBM0_W<'_>

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>

Bit 13 - Filter mode

pub fn fbm14(&mut self) -> FBM14_W<'_>

Bit 14 - Filter mode

pub fn fbm15(&mut self) -> FBM15_W<'_>

Bit 15 - Filter mode

pub fn fbm16(&mut self) -> FBM16_W<'_>

Bit 16 - Filter mode

pub fn fbm17(&mut self) -> FBM17_W<'_>

Bit 17 - Filter mode

pub fn fbm18(&mut self) -> FBM18_W<'_>

Bit 18 - Filter mode

pub fn fbm19(&mut self) -> FBM19_W<'_>

Bit 19 - Filter mode

pub fn fbm20(&mut self) -> FBM20_W<'_>

Bit 20 - Filter mode

pub fn fbm21(&mut self) -> FBM21_W<'_>

Bit 21 - Filter mode

pub fn fbm22(&mut self) -> FBM22_W<'_>

Bit 22 - Filter mode

pub fn fbm23(&mut self) -> FBM23_W<'_>

Bit 23 - Filter mode

pub fn fbm24(&mut self) -> FBM24_W<'_>

Bit 24 - Filter mode

pub fn fbm25(&mut self) -> FBM25_W<'_>

Bit 25 - Filter mode

pub fn fbm26(&mut self) -> FBM26_W<'_>

Bit 26 - Filter mode

pub fn fbm27(&mut self) -> FBM27_W<'_>

Bit 27 - Filter mode

impl W<u32, Reg<u32, _FS1R>>

pub fn fsc0(&mut self) -> FSC0_W<'_>

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>

Bit 13 - Filter scale configuration

pub fn fsc14(&mut self) -> FSC14_W<'_>

Bit 14 - Filter scale configuration

pub fn fsc15(&mut self) -> FSC15_W<'_>

Bit 15 - Filter scale configuration

pub fn fsc16(&mut self) -> FSC16_W<'_>

Bit 16 - Filter scale configuration

pub fn fsc17(&mut self) -> FSC17_W<'_>

Bit 17 - Filter scale configuration

pub fn fsc18(&mut self) -> FSC18_W<'_>

Bit 18 - Filter scale configuration

pub fn fsc19(&mut self) -> FSC19_W<'_>

Bit 19 - Filter scale configuration

pub fn fsc20(&mut self) -> FSC20_W<'_>

Bit 20 - Filter scale configuration

pub fn fsc21(&mut self) -> FSC21_W<'_>

Bit 21 - Filter scale configuration

pub fn fsc22(&mut self) -> FSC22_W<'_>

Bit 22 - Filter scale configuration

pub fn fsc23(&mut self) -> FSC23_W<'_>

Bit 23 - Filter scale configuration

pub fn fsc24(&mut self) -> FSC24_W<'_>

Bit 24 - Filter scale configuration

pub fn fsc25(&mut self) -> FSC25_W<'_>

Bit 25 - Filter scale configuration

pub fn fsc26(&mut self) -> FSC26_W<'_>

Bit 26 - Filter scale configuration

pub fn fsc27(&mut self) -> FSC27_W<'_>

Bit 27 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>

pub fn ffa0(&mut self) -> FFA0_W<'_>

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>

Bit 13 - Filter FIFO assignment for filter 13

pub fn ffa14(&mut self) -> FFA14_W<'_>

Bit 14 - Filter FIFO assignment for filter 14

pub fn ffa15(&mut self) -> FFA15_W<'_>

Bit 15 - Filter FIFO assignment for filter 15

pub fn ffa16(&mut self) -> FFA16_W<'_>

Bit 16 - Filter FIFO assignment for filter 16

pub fn ffa17(&mut self) -> FFA17_W<'_>

Bit 17 - Filter FIFO assignment for filter 17

pub fn ffa18(&mut self) -> FFA18_W<'_>

Bit 18 - Filter FIFO assignment for filter 18

pub fn ffa19(&mut self) -> FFA19_W<'_>

Bit 19 - Filter FIFO assignment for filter 19

pub fn ffa20(&mut self) -> FFA20_W<'_>

Bit 20 - Filter FIFO assignment for filter 20

pub fn ffa21(&mut self) -> FFA21_W<'_>

Bit 21 - Filter FIFO assignment for filter 21

pub fn ffa22(&mut self) -> FFA22_W<'_>

Bit 22 - Filter FIFO assignment for filter 22

pub fn ffa23(&mut self) -> FFA23_W<'_>

Bit 23 - Filter FIFO assignment for filter 23

pub fn ffa24(&mut self) -> FFA24_W<'_>

Bit 24 - Filter FIFO assignment for filter 24

pub fn ffa25(&mut self) -> FFA25_W<'_>

Bit 25 - Filter FIFO assignment for filter 25

pub fn ffa26(&mut self) -> FFA26_W<'_>

Bit 26 - Filter FIFO assignment for filter 26

pub fn ffa27(&mut self) -> FFA27_W<'_>

Bit 27 - Filter FIFO assignment for filter 27

impl W<u32, Reg<u32, _FA1R>>

pub fn fact0(&mut self) -> FACT0_W<'_>

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>

Bit 13 - Filter active

pub fn fact14(&mut self) -> FACT14_W<'_>

Bit 14 - Filter active

pub fn fact15(&mut self) -> FACT15_W<'_>

Bit 15 - Filter active

pub fn fact16(&mut self) -> FACT16_W<'_>

Bit 16 - Filter active

pub fn fact17(&mut self) -> FACT17_W<'_>

Bit 17 - Filter active

pub fn fact18(&mut self) -> FACT18_W<'_>

Bit 18 - Filter active

pub fn fact19(&mut self) -> FACT19_W<'_>

Bit 19 - Filter active

pub fn fact20(&mut self) -> FACT20_W<'_>

Bit 20 - Filter active

pub fn fact21(&mut self) -> FACT21_W<'_>

Bit 21 - Filter active

pub fn fact22(&mut self) -> FACT22_W<'_>

Bit 22 - Filter active

pub fn fact23(&mut self) -> FACT23_W<'_>

Bit 23 - Filter active

pub fn fact24(&mut self) -> FACT24_W<'_>

Bit 24 - Filter active

pub fn fact25(&mut self) -> FACT25_W<'_>

Bit 25 - Filter active

pub fn fact26(&mut self) -> FACT26_W<'_>

Bit 26 - Filter active

pub fn fact27(&mut self) -> FACT27_W<'_>

Bit 27 - Filter active

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data Register

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - Independent Data register

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - Control regidter

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - DBG_SLEEP

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - DBG_STOP

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - DBG_STANDBY

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - TRACE_IOEN

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - TRACE_MODE

impl W<u32, Reg<u32, _APB1_FZ>>

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 0 - DBG_TIM2_STOP

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - DBG_TIM3 _STOP

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 2 - DBG_TIM4_STOP

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 3 - DBG_TIM5_STOP

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - DBG_WWDG_STOP

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - DBG_IWDEG_STOP

pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>

Bit 21 - DBG_J2C1_SMBUS_TIMEOUT

pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W<'_>

Bit 22 - DBG_J2C2_SMBUS_TIMEOUT

pub fn dbg_i2c3smbus_timeout(&mut self) -> DBG_I2C3SMBUS_TIMEOUT_W<'_>

Bit 23 - DBG_J2C3SMBUS_TIMEOUT

impl W<u32, Reg<u32, _APB2_FZ>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 0 - TIM1 counter stopped when core is halted

pub fn dbg_tim9_stop(&mut self) -> DBG_TIM9_STOP_W<'_>

Bit 16 - TIM9 counter stopped when core is halted

pub fn dbg_tim10_stop(&mut self) -> DBG_TIM10_STOP_W<'_>

Bit 17 - TIM10 counter stopped when core is halted

pub fn dbg_tim11_stop(&mut self) -> DBG_TIM11_STOP_W<'_>

Bit 18 - TIM11 counter stopped when core is halted

impl W<u32, Reg<u32, _CFGR1>>

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>

Bit 31 - DFSDMEN

pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<'_>

Bit 30 - CKOUTSRC

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>

Bits 16:23 - CKOUTDIV

pub fn datpack(&mut self) -> DATPACK_W<'_>

Bits 14:15 - DATPACK

pub fn datmpx(&mut self) -> DATMPX_W<'_>

Bits 12:13 - DATMPX

pub fn chinsel(&mut self) -> CHINSEL_W<'_>

Bit 8 - CHINSEL

pub fn chen(&mut self) -> CHEN_W<'_>

Bit 7 - CHEN

pub fn ckaben(&mut self) -> CKABEN_W<'_>

Bit 6 - CKABEN

pub fn scden(&mut self) -> SCDEN_W<'_>

Bit 5 - SCDEN

pub fn spicksel(&mut self) -> SPICKSEL_W<'_>

Bits 2:3 - SPICKSEL

pub fn sitp(&mut self) -> SITP_W<'_>

Bits 0:1 - SITP

impl W<u32, Reg<u32, _CFGR2>>

pub fn offset(&mut self) -> OFFSET_W<'_>

Bits 8:31 - OFFSET

pub fn dtrbs(&mut self) -> DTRBS_W<'_>

Bits 3:7 - DTRBS

impl W<u32, Reg<u32, _AWSCDR>>

pub fn awford(&mut self) -> AWFORD_W<'_>

Bits 22:23 - AWFORD

pub fn awfosr(&mut self) -> AWFOSR_W<'_>

Bits 16:20 - AWFOSR

pub fn bkscd(&mut self) -> BKSCD_W<'_>

Bits 12:15 - BKSCD

pub fn scdt(&mut self) -> SCDT_W<'_>

Bits 0:7 - SCDT

impl W<u32, Reg<u32, _WDATR>>

pub fn wdata(&mut self) -> WDATA_W<'_>

Bits 0:15 - WDATA

impl W<u32, Reg<u32, _DATINR>>

pub fn indat1(&mut self) -> INDAT1_W<'_>

Bits 16:31 - INDAT1

pub fn indat0(&mut self) -> INDAT0_W<'_>

Bits 0:15 - INDAT0

impl W<u32, Reg<u32, _CR1>>

pub fn awfsel(&mut self) -> AWFSEL_W<'_>

Bit 30 - Analog watchdog fast mode select

pub fn fast(&mut self) -> FAST_W<'_>

Bit 29 - Fast conversion mode selection for regular conversions

pub fn rch(&mut self) -> RCH_W<'_>

Bits 24:26 - Regular channel selection

pub fn rdmaen(&mut self) -> RDMAEN_W<'_>

Bit 21 - DMA channel enabled to read data for the regular conversion

pub fn rsync(&mut self) -> RSYNC_W<'_>

Bit 19 - Launch regular conversion synchronously with DFSDM0

pub fn rcont(&mut self) -> RCONT_W<'_>

Bit 18 - Continuous mode selection for regular conversions

pub fn rswstart(&mut self) -> RSWSTART_W<'_>

Bit 17 - Software start of a conversion on the regular channel

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 8:10 - Trigger signal selection for launching injected conversions

pub fn jdmaen(&mut self) -> JDMAEN_W<'_>

Bit 5 - DMA channel enabled to read data for the injected channel group

pub fn jscan(&mut self) -> JSCAN_W<'_>

Bit 4 - Scanning conversion mode for injected conversions

pub fn jsync(&mut self) -> JSYNC_W<'_>

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 1 - Start a conversion of the injected group of channels

pub fn dfen(&mut self) -> DFEN_W<'_>

Bit 0 - DFSDM enable

impl W<u32, Reg<u32, _CR2>>

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 16:23 - Analog watchdog channel selection

pub fn exch(&mut self) -> EXCH_W<'_>

Bits 8:15 - Extremes detector channel selection

pub fn ckabie(&mut self) -> CKABIE_W<'_>

Bit 6 - Clock absence interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>

Bit 5 - Short-circuit detector interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 4 - Analog watchdog interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>

Bit 3 - Regular data overrun interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>

Bit 2 - Injected data overrun interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>

Bit 1 - Regular end of conversion interrupt enable

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 0 - Injected end of conversion interrupt enable

impl W<u32, Reg<u32, _ICR>>

pub fn clrscdf(&mut self) -> CLRSCDF_W<'_>

Bits 24:31 - Clear the short-circuit detector flag

pub fn clrckabf(&mut self) -> CLRCKABF_W<'_>

Bits 16:23 - Clear the clock absence flag

pub fn clrrovrf(&mut self) -> CLRROVRF_W<'_>

Bit 3 - Clear the regular conversion overrun flag

pub fn clrjovrf(&mut self) -> CLRJOVRF_W<'_>

Bit 2 - Clear the injected conversion overrun flag

impl W<u32, Reg<u32, _JCHGR>>

pub fn jchg(&mut self) -> JCHG_W<'_>

Bits 0:7 - Injected channel group selection

impl W<u32, Reg<u32, _FCR>>

pub fn ford(&mut self) -> FORD_W<'_>

Bits 29:31 - Sinc filter order

pub fn fosr(&mut self) -> FOSR_W<'_>

Bits 16:25 - Sinc filter oversampling ratio (decimation rate)

pub fn iosr(&mut self) -> IOSR_W<'_>

Bits 0:7 - Integrator oversampling ratio (averaging length)

impl W<u32, Reg<u32, _AWHTR>>

pub fn awht(&mut self) -> AWHT_W<'_>

Bits 8:31 - Analog watchdog high threshold

pub fn bkawh(&mut self) -> BKAWH_W<'_>

Bits 0:3 - Break signal assignment to analog watchdog high threshold event

impl W<u32, Reg<u32, _AWLTR>>

pub fn awlt(&mut self) -> AWLT_W<'_>

Bits 8:31 - Analog watchdog low threshold

pub fn bkawl(&mut self) -> BKAWL_W<'_>

Bits 0:3 - Break signal assignment to analog watchdog low threshold event

impl W<u32, Reg<u32, _AWCFR>>

pub fn clrawhtf(&mut self) -> CLRAWHTF_W<'_>

Bits 8:15 - Clear the analog watchdog high threshold flag

pub fn clrawltf(&mut self) -> CLRAWLTF_W<'_>

Bits 0:7 - Clear the analog watchdog low threshold flag

impl W<u32, Reg<u32, _CR>>

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn boff2(&mut self) -> BOFF2_W<'_>

Bit 17 - DAC channel2 output buffer disable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit left-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

impl W<u32, Reg<u32, _CR>>

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 25:28 - Channel selection

pub fn mburst(&mut self) -> MBURST_W<'_>

Bits 23:24 - Memory burst transfer configuration

pub fn pburst(&mut self) -> PBURST_W<'_>

Bits 21:22 - Peripheral burst transfer configuration

pub fn ct(&mut self) -> CT_W<'_>

Bit 19 - Current target (only in double buffer mode)

pub fn dbm(&mut self) -> DBM_W<'_>

Bit 18 - Double buffer mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 16:17 - Priority level

pub fn pincos(&mut self) -> PINCOS_W<'_>

Bit 15 - Peripheral increment offset size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 13:14 - Memory data size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 11:12 - Peripheral data size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 10 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 9 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 8 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bits 6:7 - Data transfer direction

pub fn pfctrl(&mut self) -> PFCTRL_W<'_>

Bit 5 - Peripheral flow controller

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 4 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 3 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 2 - Transfer error interrupt enable

pub fn dmeie(&mut self) -> DMEIE_W<'_>

Bit 1 - Direct mode error interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Stream enable / flag stream ready when read low

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data items to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _M0AR>>

pub fn m0a(&mut self) -> M0A_W<'_>

Bits 0:31 - Memory 0 address

impl W<u32, Reg<u32, _M1AR>>

pub fn m1a(&mut self) -> M1A_W<'_>

Bits 0:31 - Memory 1 address (used in case of Double buffer mode)

impl W<u32, Reg<u32, _FCR>>

pub fn feie(&mut self) -> FEIE_W<'_>

Bit 7 - FIFO error interrupt enable

pub fn dmdis(&mut self) -> DMDIS_W<'_>

Bit 2 - Direct mode disable

pub fn fth(&mut self) -> FTH_W<'_>

Bits 0:1 - FIFO threshold selection

impl W<u32, Reg<u32, _LIFCR>>

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif3(&mut self) -> CDMEIF3_W<'_>

Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif3(&mut self) -> CFEIF3_W<'_>

Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif2(&mut self) -> CDMEIF2_W<'_>

Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif2(&mut self) -> CFEIF2_W<'_>

Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif1(&mut self) -> CDMEIF1_W<'_>

Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif1(&mut self) -> CFEIF1_W<'_>

Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif0(&mut self) -> CTCIF0_W<'_>

Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif0(&mut self) -> CHTIF0_W<'_>

Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif0(&mut self) -> CTEIF0_W<'_>

Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif0(&mut self) -> CDMEIF0_W<'_>

Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif0(&mut self) -> CFEIF0_W<'_>

Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)

impl W<u32, Reg<u32, _HIFCR>>

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif7(&mut self) -> CDMEIF7_W<'_>

Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif7(&mut self) -> CFEIF7_W<'_>

Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif6(&mut self) -> CDMEIF6_W<'_>

Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif6(&mut self) -> CFEIF6_W<'_>

Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif5(&mut self) -> CDMEIF5_W<'_>

Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif5(&mut self) -> CFEIF5_W<'_>

Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif4(&mut self) -> CDMEIF4_W<'_>

Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif4(&mut self) -> CFEIF4_W<'_>

Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)

impl W<u32, Reg<u32, _IMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Interrupt Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Interrupt Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Interrupt Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Interrupt Mask on line 22

impl W<u32, Reg<u32, _EMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Event Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Event Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Event Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Event Mask on line 22

impl W<u32, Reg<u32, _RTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Rising trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Rising trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Rising trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Rising trigger event configuration of line 22

impl W<u32, Reg<u32, _FTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Falling trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Falling trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Falling trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Falling trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Falling trigger event configuration of line 22

impl W<u32, Reg<u32, _SWIER>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

pub fn swier19(&mut self) -> SWIER19_W<'_>

Bit 19 - Software Interrupt on line 19

pub fn swier20(&mut self) -> SWIER20_W<'_>

Bit 20 - Software Interrupt on line 20

pub fn swier21(&mut self) -> SWIER21_W<'_>

Bit 21 - Software Interrupt on line 21

pub fn swier22(&mut self) -> SWIER22_W<'_>

Bit 22 - Software Interrupt on line 22

impl W<u32, Reg<u32, _PR>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

pub fn pr19(&mut self) -> PR19_W<'_>

Bit 19 - Pending bit 19

pub fn pr20(&mut self) -> PR20_W<'_>

Bit 20 - Pending bit 20

pub fn pr21(&mut self) -> PR21_W<'_>

Bit 21 - Pending bit 21

pub fn pr22(&mut self) -> PR22_W<'_>

Bit 22 - Pending bit 22

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TXIE

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RXIE

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - ADDRE

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - NACKIE

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOPIE

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - TCIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - ERRIE

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - DNF

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - ANFOFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - TCDMAEN

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - RXDMAEN

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - SBC

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - NOSTRETCH

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - GCEN

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBHEN

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBDEN

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - ALERTEN

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PECEN

impl W<u32, Reg<u32, _CR2>>

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit 0

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1(&mut self) -> OA1_W<'_>

Bit 0 - OA1

pub fn oa11_7(&mut self) -> OA11_7_W<'_>

Bits 1:7 - OA11_7

pub fn oa18_9(&mut self) -> OA18_9_W<'_>

Bits 8:9 - OA18_9

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - OA1MODE

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - OA1EN

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - OA21_7

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - OA2MSK

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - OA2EN

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCLL

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCLH

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - SDADEL

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - SCLDEL

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - PRESC

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - TIMEOUTA

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - TIDLE

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - TIMOUTEN

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - TIMEOUTB

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - TEXTEN

impl W<u32, Reg<u32, _ISR>>

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - TXE

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - TXIS

impl W<u32, Reg<u32, _ICR>>

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address matched flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration Lost flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TXDATA

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn dcen(&mut self) -> DCEN_W<'_>

Bit 10 - Data cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn dcrst(&mut self) -> DCRST_W<'_>

Bit 12 - Data cache reset

impl W<u32, Reg<u32, _KEYR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - FPEC key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkey(&mut self) -> OPTKEY_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protection error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn pgperr(&mut self) -> PGPERR_W<'_>

Bit 6 - Programming parallelism error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn ser(&mut self) -> SER_W<'_>

Bit 1 - Sector Erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass Erase

pub fn snb(&mut self) -> SNB_W<'_>

Bits 3:6 - Sector number

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Program size

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - Lock

impl W<u32, Reg<u32, _OPTCR>>

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 0 - Option lock

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 1 - Option start

pub fn bor_lev(&mut self) -> BOR_LEV_W<'_>

Bits 2:3 - BOR reset Level

pub fn wdg_sw(&mut self) -> WDG_SW_W<'_>

Bit 5 - WDG_SW User option bytes

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 6 - nRST_STOP User option bytes

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 7 - nRST_STDBY User option bytes

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 8:15 - Read protect

pub fn n_wrp(&mut self) -> NWRP_W<'_>

Bits 16:27 - Not write protect

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:6 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:14 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:6 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn itr1_rmp(&mut self) -> ITR1_RMP_W<'_>

Bits 10:11 - Timer Input 4 remap

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _OR>>

pub fn rmp(&mut self) -> RMP_W<'_>

Bits 0:1 - Input 1 remapping capability

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn it4_rmp(&mut self) -> IT4_RMP_W<'_>

Bits 6:7 - Timer Input 4 remap

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _CR1>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 15 - Software reset

pub fn alert(&mut self) -> ALERT_W<'_>

Bit 13 - SMBus alert

pub fn pec(&mut self) -> PEC_W<'_>

Bit 12 - Packet error checking

pub fn pos(&mut self) -> POS_W<'_>

Bit 11 - Acknowledge/PEC Position (for data reception)

pub fn ack(&mut self) -> ACK_W<'_>

Bit 10 - Acknowledge enable

pub fn stop(&mut self) -> STOP_W<'_>

Bit 9 - Stop generation

pub fn start(&mut self) -> START_W<'_>

Bit 8 - Start generation

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 7 - Clock stretching disable (Slave mode)

pub fn engc(&mut self) -> ENGC_W<'_>

Bit 6 - General call enable

pub fn enpec(&mut self) -> ENPEC_W<'_>

Bit 5 - PEC enable

pub fn enarp(&mut self) -> ENARP_W<'_>

Bit 4 - ARP enable

pub fn smbtype(&mut self) -> SMBTYPE_W<'_>

Bit 3 - SMBus type

pub fn smbus(&mut self) -> SMBUS_W<'_>

Bit 1 - SMBus mode

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

impl W<u32, Reg<u32, _CR2>>

pub fn last(&mut self) -> LAST_W<'_>

Bit 12 - DMA last transfer

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 11 - DMA requests enable

pub fn itbufen(&mut self) -> ITBUFEN_W<'_>

Bit 10 - Buffer interrupt enable

pub fn itevten(&mut self) -> ITEVTEN_W<'_>

Bit 9 - Event interrupt enable

pub fn iterren(&mut self) -> ITERREN_W<'_>

Bit 8 - Error interrupt enable

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:5 - Peripheral clock frequency

impl W<u32, Reg<u32, _OAR1>>

pub fn addmode(&mut self) -> ADDMODE_W<'_>

Bit 15 - Addressing mode (slave mode)

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn add2(&mut self) -> ADD2_W<'_>

Bits 1:7 - Interface address

pub fn endual(&mut self) -> ENDUAL_W<'_>

Bit 0 - Dual addressing mode enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:7 - 8-bit data register

impl W<u32, Reg<u32, _SR1>>

pub fn smbalert(&mut self) -> SMBALERT_W<'_>

Bit 15 - SMBus alert

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 14 - Timeout or Tlow error

pub fn pecerr(&mut self) -> PECERR_W<'_>

Bit 12 - PEC Error in reception

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 11 - Overrun/Underrun

pub fn af(&mut self) -> AF_W<'_>

Bit 10 - Acknowledge failure

pub fn arlo(&mut self) -> ARLO_W<'_>

Bit 9 - Arbitration lost (master mode)

pub fn berr(&mut self) -> BERR_W<'_>

Bit 8 - Bus error

impl W<u32, Reg<u32, _CCR>>

pub fn f_s(&mut self) -> F_S_W<'_>

Bit 15 - I2C master mode selection

pub fn duty(&mut self) -> DUTY_W<'_>

Bit 14 - Fast mode duty cycle

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _TRISE>>

pub fn trise(&mut self) -> TRISE_W<'_>

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _FLTR>>

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 0:3 - Digital noise filter

pub fn anoff(&mut self) -> ANOFF_W<'_>

Bit 4 - Analog noise filter OFF

impl W<u32, Reg<u32, _ICR>>

pub fn downcf(&mut self) -> DOWNCF_W<'_>

Bit 6 - Direction change to down Clear Flag

pub fn upcf(&mut self) -> UPCF_W<'_>

Bit 5 - Direction change to UP Clear Flag

pub fn arrokcf(&mut self) -> ARROKCF_W<'_>

Bit 4 - Autoreload register update OK Clear Flag

pub fn cmpokcf(&mut self) -> CMPOKCF_W<'_>

Bit 3 - Compare register update OK Clear Flag

pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<'_>

Bit 2 - External trigger valid edge Clear Flag

pub fn arrmcf(&mut self) -> ARRMCF_W<'_>

Bit 1 - Autoreload match Clear Flag

pub fn cmpmcf(&mut self) -> CMPMCF_W<'_>

Bit 0 - compare match Clear Flag

impl W<u32, Reg<u32, _IER>>

pub fn downie(&mut self) -> DOWNIE_W<'_>

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&mut self) -> UPIE_W<'_>

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&mut self) -> ARROKIE_W<'_>

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&mut self) -> CMPOKIE_W<'_>

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&mut self) -> EXTTRIGIE_W<'_>

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&mut self) -> ARRMIE_W<'_>

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&mut self) -> CMPMIE_W<'_>

Bit 0 - Compare match Interrupt Enable

impl W<u32, Reg<u32, _CFGR>>

pub fn enc(&mut self) -> ENC_W<'_>

Bit 24 - Encoder mode enable

pub fn countmode(&mut self) -> COUNTMODE_W<'_>

Bit 23 - counter mode enabled

pub fn preload(&mut self) -> PRELOAD_W<'_>

Bit 22 - Registers update mode

pub fn wavpol(&mut self) -> WAVPOL_W<'_>

Bit 21 - Waveform shape polarity

pub fn wave(&mut self) -> WAVE_W<'_>

Bit 20 - Waveform shape

pub fn timout(&mut self) -> TIMOUT_W<'_>

Bit 19 - Timeout enable

pub fn trigen(&mut self) -> TRIGEN_W<'_>

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>

Bits 13:15 - Trigger selector

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 9:11 - Clock prescaler

pub fn trgflt(&mut self) -> TRGFLT_W<'_>

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&mut self) -> CKFLT_W<'_>

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bits 1:2 - Clock Polarity

pub fn cksel(&mut self) -> CKSEL_W<'_>

Bit 0 - Clock selector

impl W<u32, Reg<u32, _CR>>

pub fn cntstrt(&mut self) -> CNTSTRT_W<'_>

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&mut self) -> SNGSTRT_W<'_>

Bit 1 - LPTIM start in single mode

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - LPTIM Enable

impl W<u32, Reg<u32, _CMP>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bits 0:15 - Compare value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto reload value

impl W<u32, Reg<u32, _CR>>

pub fn vos(&mut self) -> VOS_W<'_>

Bits 14:15 - Regulator voltage scaling output selection

pub fn adcdc1(&mut self) -> ADCDC1_W<'_>

Bit 13 - ADCDC1

pub fn fpds(&mut self) -> FPDS_W<'_>

Bit 9 - Flash power down in Stop mode

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD level selection

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power voltage detector enable

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear standby flag

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear wakeup flag

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power down deepsleep

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low-power deep sleep

impl W<u32, Reg<u32, _CSR>>

pub fn ewup(&mut self) -> EWUP_W<'_>

Bit 8 - Enable WKUP pin

pub fn bre(&mut self) -> BRE_W<'_>

Bit 9 - Backup regulator enable

pub fn vosrdy(&mut self) -> VOSRDY_W<'_>

Bit 14 - Regulator voltage scaling output selection ready bit

impl W<u32, Reg<u32, _CR>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 24:31 - Clock prescaler

pub fn pmm(&mut self) -> PMM_W<'_>

Bit 23 - Polling match mode

pub fn apms(&mut self) -> APMS_W<'_>

Bit 22 - Automatic poll mode stop

pub fn toie(&mut self) -> TOIE_W<'_>

Bit 20 - TimeOut interrupt enable

pub fn smie(&mut self) -> SMIE_W<'_>

Bit 19 - Status match interrupt enable

pub fn ftie(&mut self) -> FTIE_W<'_>

Bit 18 - FIFO threshold interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 17 - Transfer complete interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 16 - Transfer error interrupt enable

pub fn fthres(&mut self) -> FTHRES_W<'_>

Bits 8:12 - IFO threshold level

pub fn fsel(&mut self) -> FSEL_W<'_>

Bit 7 - FLASH memory selection

pub fn dfm(&mut self) -> DFM_W<'_>

Bit 6 - Dual-flash mode

pub fn sshift(&mut self) -> SSHIFT_W<'_>

Bit 4 - Sample shift

pub fn tcen(&mut self) -> TCEN_W<'_>

Bit 3 - Timeout counter enable

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 2 - DMA enable

pub fn abort(&mut self) -> ABORT_W<'_>

Bit 1 - Abort request

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

impl W<u32, Reg<u32, _DCR>>

pub fn fsize(&mut self) -> FSIZE_W<'_>

Bits 16:20 - FLASH memory size

pub fn csht(&mut self) -> CSHT_W<'_>

Bits 8:10 - Chip select high time

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bit 0 - Mode 0 / mode 3

impl W<u32, Reg<u32, _FCR>>

pub fn ctof(&mut self) -> CTOF_W<'_>

Bit 4 - Clear timeout flag

pub fn csmf(&mut self) -> CSMF_W<'_>

Bit 3 - Clear status match flag

pub fn ctcf(&mut self) -> CTCF_W<'_>

Bit 1 - Clear transfer complete flag

pub fn ctef(&mut self) -> CTEF_W<'_>

Bit 0 - Clear transfer error flag

impl W<u32, Reg<u32, _DLR>>

pub fn dl(&mut self) -> DL_W<'_>

Bits 0:31 - Data length

impl W<u32, Reg<u32, _CCR>>

pub fn ddrm(&mut self) -> DDRM_W<'_>

Bit 31 - Double data rate mode

pub fn dhhc(&mut self) -> DHHC_W<'_>

Bit 30 - DDR hold half cycle

pub fn sioo(&mut self) -> SIOO_W<'_>

Bit 28 - Send instruction only once mode

pub fn fmode(&mut self) -> FMODE_W<'_>

Bits 26:27 - Functional mode

pub fn dmode(&mut self) -> DMODE_W<'_>

Bits 24:25 - Data mode

pub fn dcyc(&mut self) -> DCYC_W<'_>

Bits 18:22 - Number of dummy cycles

pub fn absize(&mut self) -> ABSIZE_W<'_>

Bits 16:17 - Alternate bytes size

pub fn abmode(&mut self) -> ABMODE_W<'_>

Bits 14:15 - Alternate bytes mode

pub fn adsize(&mut self) -> ADSIZE_W<'_>

Bits 12:13 - Address size

pub fn admode(&mut self) -> ADMODE_W<'_>

Bits 10:11 - Address mode

pub fn imode(&mut self) -> IMODE_W<'_>

Bits 8:9 - Instruction mode

pub fn instruction(&mut self) -> INSTRUCTION_W<'_>

Bits 0:7 - Instruction

impl W<u32, Reg<u32, _AR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:31 - Address

impl W<u32, Reg<u32, _ABR>>

pub fn alternate(&mut self) -> ALTERNATE_W<'_>

Bits 0:31 - ALTERNATE

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _PSMKR>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 0:31 - Status mask

impl W<u32, Reg<u32, _PSMAR>>

pub fn match_(&mut self) -> MATCH_W<'_>

Bits 0:31 - Status match

impl W<u32, Reg<u32, _PIR>>

pub fn interval(&mut self) -> INTERVAL_W<'_>

Bits 0:15 - Polling interval

impl W<u32, Reg<u32, _LPTR>>

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bits 0:15 - Timeout period

impl W<u32, Reg<u32, _CR>>

pub fn ie(&mut self) -> IE_W<'_>

Bit 3 - Interrupt enable

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 2 - Random number generator enable

impl W<u32, Reg<u32, _SR>>

pub fn seis(&mut self) -> SEIS_W<'_>

Bit 6 - Seed error interrupt status

pub fn ceis(&mut self) -> CEIS_W<'_>

Bit 5 - Clock error interrupt status

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - Calibration output enable

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - Output selection

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - Output polarity

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - Calibration Output selection

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - Backup

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - Subtract 1 hour (winter time change)

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - Add 1 hour (summer time change)

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - Time-stamp interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - Wakeup timer interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - Alarm B interrupt enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - Alarm A interrupt enable

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - Time stamp enable

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - Wakeup timer enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - Alarm B enable

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - Alarm A enable

pub fn dce(&mut self) -> DCE_W<'_>

Bit 7 - Coarse digital calibration enable

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - Hour format

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - Bypass the shadow registers

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - Time-stamp event active edge

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - Wakeup clock selection

impl W<u32, Reg<u32, _ISR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

pub fn alraf(&mut self) -> ALRAF_W<'_>

Bit 8 - Alarm A flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>

Bit 9 - Alarm B flag

pub fn wutf(&mut self) -> WUTF_W<'_>

Bit 10 - Wakeup timer flag

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 11 - Time-stamp flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>

Bit 12 - Time-stamp overflow flag

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>

Bit 13 - Tamper detection flag

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>

Bit 14 - TAMPER2 detection flag

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _CALIBR>>

pub fn dcs(&mut self) -> DCS_W<'_>

Bit 7 - Digital calibration sign

pub fn dc(&mut self) -> DC_W<'_>

Bits 0:4 - Digital calibration

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAFCR>>

pub fn alarmouttype(&mut self) -> ALARMOUTTYPE_W<'_>

Bit 18 - AFO_ALARM output type

pub fn tsinsel(&mut self) -> TSINSEL_W<'_>

Bit 17 - TIMESTAMP mapping

pub fn tamp1insel(&mut self) -> TAMP1INSEL_W<'_>

Bit 16 - TAMPER1 mapping

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 15 - TAMPER pull-up disable

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 13:14 - Tamper precharge duration

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 11:12 - Tamper filter count

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 8:10 - Tamper sampling frequency

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 7 - Activate timestamp on tamper detection event

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 4 - Active level for tamper 2

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 3 - Tamper 2 detection enable

pub fn tampie(&mut self) -> TAMPIE_W<'_>

Bit 2 - Tamper interrupt enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 1 - Active level for tamper 1

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - Tamper 1 detection enable

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _BKPR>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal high-speed clock enable

pub fn hsirdy(&mut self) -> HSIRDY_W<'_>

Bit 1 - Internal high-speed clock ready flag

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal high-speed clock trimming

pub fn hsical(&mut self) -> HSICAL_W<'_>

Bits 8:15 - Internal high-speed clock calibration

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hserdy(&mut self) -> HSERDY_W<'_>

Bit 17 - HSE clock ready flag

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE clock bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - Main PLL (PLL) enable

pub fn pllrdy(&mut self) -> PLLRDY_W<'_>

Bit 25 - Main PLL (PLL) clock ready flag

pub fn plli2son(&mut self) -> PLLI2SON_W<'_>

Bit 26 - PLLI2S enable

pub fn plli2srdy(&mut self) -> PLLI2SRDY_W<'_>

Bit 27 - PLLI2S clock ready flag

impl W<u32, Reg<u32, _PLLCFGR>>

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 28:30 - Main PLL (PLL) division factor for I2S, DFSDM clocks

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 6:14 - Main PLL (PLL) multiplication factor for VCO

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 16:17 - Main PLL (PLL) division factor for main system clock

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks

impl W<u32, Reg<u32, _CFGR>>

pub fn mco2(&mut self) -> MCO2_W<'_>

Bits 30:31 - Microcontroller clock output 2

pub fn mco2pre(&mut self) -> MCO2PRE_W<'_>

Bits 27:29 - MCO2 prescaler

pub fn mco1pre(&mut self) -> MCO1PRE_W<'_>

Bits 24:26 - MCO1 prescaler

pub fn mco1(&mut self) -> MCO1_W<'_>

Bits 21:22 - Microcontroller clock output 1

pub fn rtcpre(&mut self) -> RTCPRE_W<'_>

Bits 16:20 - HSE division factor for RTC clock

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 13:15 - APB high-speed prescaler (APB2)

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 10:12 - APB Low speed prescaler (APB1)

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock switch

pub fn sws(&mut self) -> SWS_W<'_>

Bits 2:3 - System clock switch status

impl W<u32, Reg<u32, _CIR>>

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

pub fn plli2srdyc(&mut self) -> PLLI2SRDYC_W<'_>

Bit 21 - PLLI2S ready interrupt clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - Main PLL(PLL) ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE ready interrupt clear

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI ready interrupt clear

pub fn plli2srdyie(&mut self) -> PLLI2SRDYIE_W<'_>

Bit 13 - PLLI2S ready interrupt enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - Main PLL (PLL) ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE ready interrupt enable

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI ready interrupt enable

impl W<u32, Reg<u32, _AHB1RSTR>>

pub fn gpioarst(&mut self) -> GPIOARST_W<'_>

Bit 0 - IO port A reset

pub fn gpiobrst(&mut self) -> GPIOBRST_W<'_>

Bit 1 - IO port B reset

pub fn gpiocrst(&mut self) -> GPIOCRST_W<'_>

Bit 2 - IO port C reset

pub fn gpiodrst(&mut self) -> GPIODRST_W<'_>

Bit 3 - IO port D reset

pub fn gpioerst(&mut self) -> GPIOERST_W<'_>

Bit 4 - IO port E reset

pub fn gpiofrst(&mut self) -> GPIOFRST_W<'_>

Bit 5 - IO port F reset

pub fn gpiogrst(&mut self) -> GPIOGRST_W<'_>

Bit 6 - IO port G reset

pub fn gpiohrst(&mut self) -> GPIOHRST_W<'_>

Bit 7 - IO port H reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 12 - CRC reset

pub fn dma1rst(&mut self) -> DMA1RST_W<'_>

Bit 21 - DMA2 reset

pub fn dma2rst(&mut self) -> DMA2RST_W<'_>

Bit 22 - DMA2 reset

impl W<u32, Reg<u32, _AHB2RSTR>>

pub fn otgfsrst(&mut self) -> OTGFSRST_W<'_>

Bit 7 - USB OTG FS module reset

pub fn rngrst(&mut self) -> RNGRST_W<'_>

Bit 6 - RNGRST

pub fn cryprst(&mut self) -> CRYPRST_W<'_>

Bit 4 - CRYP module reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - TIM3 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - TIM4 reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>

Bit 3 - TIM5 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - TIM6RST

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - TIM7RST

pub fn tim12rst(&mut self) -> TIM12RST_W<'_>

Bit 6 - TIM12RST

pub fn tim13rst(&mut self) -> TIM13RST_W<'_>

Bit 7 - TIM13RST

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 8 - TIM14RST

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI 2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI 3 reset

pub fn uart2rst(&mut self) -> UART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART3RST

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C 1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C 2 reset

pub fn i2c3rst(&mut self) -> I2C3RST_W<'_>

Bit 23 - I2C3 reset

pub fn fmpi2c1rst(&mut self) -> FMPI2C1RST_W<'_>

Bit 24 - FMPI2C1 reset

pub fn can1rst(&mut self) -> CAN1RST_W<'_>

Bit 25 - CAN1RST

pub fn can2rst(&mut self) -> CAN2RST_W<'_>

Bit 26 - CAN2RST

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn lptimer1rst(&mut self) -> LPTIMER1RST_W<'_>

Bit 9 - LPTimer1 reset

pub fn usart4rst(&mut self) -> USART4RST_W<'_>

Bit 19 - USART4 reset

pub fn usart5rst(&mut self) -> USART5RST_W<'_>

Bit 20 - USART5 reset

pub fn can3rst(&mut self) -> CAN3RST_W<'_>

Bit 27 - CAN 3 reset

pub fn dacrst(&mut self) -> DACRST_W<'_>

Bit 29 - DAC reset

pub fn uart7rst(&mut self) -> UART7RST_W<'_>

Bit 30 - UART 7 reset

pub fn uart8rst(&mut self) -> UART8RST_W<'_>

Bit 31 - UART 8 reset

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 0 - TIM1 reset

pub fn tim8rst(&mut self) -> TIM8RST_W<'_>

Bit 1 - TIM8RST

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 4 - USART1 reset

pub fn usart6rst(&mut self) -> USART6RST_W<'_>

Bit 5 - USART6 reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 8 - ADC interface reset (common to all ADCs)

pub fn sdiorst(&mut self) -> SDIORST_W<'_>

Bit 11 - SDIO reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 14 - System configuration controller reset

pub fn tim9rst(&mut self) -> TIM9RST_W<'_>

Bit 16 - TIM9 reset

pub fn tim10rst(&mut self) -> TIM10RST_W<'_>

Bit 17 - TIM10 reset

pub fn tim11rst(&mut self) -> TIM11RST_W<'_>

Bit 18 - TIM11 reset

pub fn dfsdmrst(&mut self) -> DFSDMRST_W<'_>

Bit 24 - DFSDMRST

pub fn usart9rst(&mut self) -> USART9RST_W<'_>

Bit 6 - USART9 reset

pub fn sart10rst(&mut self) -> SART10RST_W<'_>

Bit 7 - USART10 reset

pub fn spi4rst(&mut self) -> SPI4RST_W<'_>

Bit 13 - SPI4 reset

pub fn spi5rst(&mut self) -> SPI5RST_W<'_>

Bit 20 - SPI5RST

pub fn sai1rst(&mut self) -> SAI1RST_W<'_>

Bit 22 - SAI1 reset

pub fn dfsdm2rst(&mut self) -> DFSDM2RST_W<'_>

Bit 25 - DFSDM2 reset

pub fn uart9rst(&mut self) -> UART9RST_W<'_>

Bit 6 - UART9 reset

pub fn uart10rst(&mut self) -> UART10RST_W<'_>

Bit 7 - UART10 reset

impl W<u32, Reg<u32, _AHB1ENR>>

pub fn gpioaen(&mut self) -> GPIOAEN_W<'_>

Bit 0 - IO port A clock enable

pub fn gpioben(&mut self) -> GPIOBEN_W<'_>

Bit 1 - IO port B clock enable

pub fn gpiocen(&mut self) -> GPIOCEN_W<'_>

Bit 2 - IO port C clock enable

pub fn gpioden(&mut self) -> GPIODEN_W<'_>

Bit 3 - IO port D clock enable

pub fn gpioeen(&mut self) -> GPIOEEN_W<'_>

Bit 4 - IO port E clock enable

pub fn gpiofen(&mut self) -> GPIOFEN_W<'_>

Bit 5 - IO port F clock enable

pub fn gpiogen(&mut self) -> GPIOGEN_W<'_>

Bit 6 - IO port G clock enable

pub fn gpiohen(&mut self) -> GPIOHEN_W<'_>

Bit 7 - IO port H clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CRC clock enable

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 21 - DMA1 clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 22 - DMA2 clock enable

impl W<u32, Reg<u32, _AHB2ENR>>

pub fn otgfsen(&mut self) -> OTGFSEN_W<'_>

Bit 7 - USB OTG FS clock enable

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 6 - RNGEN

pub fn crypen(&mut self) -> CRYPEN_W<'_>

Bit 4 - CRYP clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - TIM2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - TIM4 clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>

Bit 3 - TIM5 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - TIM6EN

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - TIM7EN

pub fn tim12en(&mut self) -> TIM12EN_W<'_>

Bit 6 - TIM12EN

pub fn tim13en(&mut self) -> TIM13EN_W<'_>

Bit 7 - TIM13EN

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 8 - TIM14EN

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART3EN

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>

Bit 23 - I2C3 clock enable

pub fn fmpi2c1en(&mut self) -> FMPI2C1EN_W<'_>

Bit 24 - FMPI2C1 clock enable

pub fn can1en(&mut self) -> CAN1EN_W<'_>

Bit 25 - CAN1EN

pub fn can2en(&mut self) -> CAN2EN_W<'_>

Bit 26 - CAN2EN

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn lptimer1en(&mut self) -> LPTIMER1EN_W<'_>

Bit 9 - LPTimer 1 clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>

Bit 10 - clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>

Bit 19 - UART 4 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>

Bit 20 - UART 5 clock enable

pub fn can3en(&mut self) -> CAN3EN_W<'_>

Bit 27 - CAN 3 clock enable

pub fn dacen(&mut self) -> DACEN_W<'_>

Bit 29 - DAC clock enable

pub fn uart7en(&mut self) -> UART7EN_W<'_>

Bit 30 - UART7 clock enable

pub fn uart8en(&mut self) -> UART8EN_W<'_>

Bit 31 - UART8 clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 0 - TIM1 clock enable

pub fn tim8en(&mut self) -> TIM8EN_W<'_>

Bit 1 - TIM8EN

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 4 - USART1 clock enable

pub fn usart6en(&mut self) -> USART6EN_W<'_>

Bit 5 - USART6 clock enable

pub fn adc1en(&mut self) -> ADC1EN_W<'_>

Bit 8 - ADC1 clock enable

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SDIO clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn spi4en(&mut self) -> SPI4EN_W<'_>

Bit 13 - SPI4 clock enable

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 14 - System configuration controller clock enable

pub fn tim9en(&mut self) -> TIM9EN_W<'_>

Bit 16 - TIM9 clock enable

pub fn tim10en(&mut self) -> TIM10EN_W<'_>

Bit 17 - TIM10 clock enable

pub fn tim11en(&mut self) -> TIM11EN_W<'_>

Bit 18 - TIM11 clock enable

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>

Bit 24 - DFSDMEN

pub fn spi5en(&mut self) -> SPI5EN_W<'_>

Bit 20 - SPI5 clock enable

pub fn sai1en(&mut self) -> SAI1EN_W<'_>

Bit 22 - SAI 1 clock enable

pub fn dfsdm2en(&mut self) -> DFSDM2EN_W<'_>

Bit 25 - DFSDM2 clock enable

pub fn uart9en(&mut self) -> UART9EN_W<'_>

Bit 6 - UART9 clock enable

pub fn uart10en(&mut self) -> UART10EN_W<'_>

Bit 7 - UART10 clock enable

impl W<u32, Reg<u32, _AHB1LPENR>>

pub fn gpioalpen(&mut self) -> GPIOALPEN_W<'_>

Bit 0 - IO port A clock enable during sleep mode

pub fn gpioblpen(&mut self) -> GPIOBLPEN_W<'_>

Bit 1 - IO port B clock enable during Sleep mode

pub fn gpioclpen(&mut self) -> GPIOCLPEN_W<'_>

Bit 2 - IO port C clock enable during Sleep mode

pub fn gpiodlpen(&mut self) -> GPIODLPEN_W<'_>

Bit 3 - IO port D clock enable during Sleep mode

pub fn gpioelpen(&mut self) -> GPIOELPEN_W<'_>

Bit 4 - IO port E clock enable during Sleep mode

pub fn gpioflpen(&mut self) -> GPIOFLPEN_W<'_>

Bit 5 - IO port F clock enable during sleep mode

pub fn gpioglpen(&mut self) -> GPIOGLPEN_W<'_>

Bit 6 - IO port G clock enable during sleep mode

pub fn gpiohlpen(&mut self) -> GPIOHLPEN_W<'_>

Bit 7 - IO port H clock enable during Sleep mode

pub fn crclpen(&mut self) -> CRCLPEN_W<'_>

Bit 12 - CRC clock enable during Sleep mode

pub fn flitflpen(&mut self) -> FLITFLPEN_W<'_>

Bit 15 - Flash interface clock enable during Sleep mode

pub fn sram1lpen(&mut self) -> SRAM1LPEN_W<'_>

Bit 16 - SRAM 1interface clock enable during Sleep mode

pub fn dma1lpen(&mut self) -> DMA1LPEN_W<'_>

Bit 21 - DMA1 clock enable during Sleep mode

pub fn dma2lpen(&mut self) -> DMA2LPEN_W<'_>

Bit 22 - DMA2 clock enable during Sleep mode

pub fn sram2lpen(&mut self) -> SRAM2LPEN_W<'_>

Bit 17 - SRAM2interface clock enable during Sleep mode

impl W<u32, Reg<u32, _AHB2LPENR>>

pub fn otgfslpen(&mut self) -> OTGFSLPEN_W<'_>

Bit 7 - USB OTG FS clock enable during Sleep mode

pub fn rnglpen(&mut self) -> RNGLPEN_W<'_>

Bit 6 - RNGLPEN

pub fn fsmclpen(&mut self) -> FSMCLPEN_W<'_>

Bit 0 - Flexible memory controller module clock enable during Sleep mode

pub fn qspilpen(&mut self) -> QSPILPEN_W<'_>

Bit 1 - QUADSPI memory controller module clock enable during Sleep mode

impl W<u32, Reg<u32, _APB1LPENR>>

pub fn tim2lpen(&mut self) -> TIM2LPEN_W<'_>

Bit 0 - TIM2 clock enable during Sleep mode

pub fn tim3lpen(&mut self) -> TIM3LPEN_W<'_>

Bit 1 - TIM3 clock enable during Sleep mode

pub fn tim4lpen(&mut self) -> TIM4LPEN_W<'_>

Bit 2 - TIM4 clock enable during Sleep mode

pub fn tim5lpen(&mut self) -> TIM5LPEN_W<'_>

Bit 3 - TIM5 clock enable during Sleep mode

pub fn tim6lpen(&mut self) -> TIM6LPEN_W<'_>

Bit 4 - TIM6LPEN

pub fn tim7lpen(&mut self) -> TIM7LPEN_W<'_>

Bit 5 - TIM7LPEN

pub fn tim12lpen(&mut self) -> TIM12LPEN_W<'_>

Bit 6 - TIM12LPEN

pub fn tim13lpen(&mut self) -> TIM13LPEN_W<'_>

Bit 7 - TIM13LPEN

pub fn tim14lpen(&mut self) -> TIM14LPEN_W<'_>

Bit 8 - TIM14LPEN

pub fn wwdglpen(&mut self) -> WWDGLPEN_W<'_>

Bit 11 - Window watchdog clock enable during Sleep mode

pub fn spi2lpen(&mut self) -> SPI2LPEN_W<'_>

Bit 14 - SPI2 clock enable during Sleep mode

pub fn spi3lpen(&mut self) -> SPI3LPEN_W<'_>

Bit 15 - SPI3 clock enable during Sleep mode

pub fn usart2lpen(&mut self) -> USART2LPEN_W<'_>

Bit 17 - USART2 clock enable during Sleep mode

pub fn usart3lpen(&mut self) -> USART3LPEN_W<'_>

Bit 18 - USART3LPEN

pub fn i2c1lpen(&mut self) -> I2C1LPEN_W<'_>

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2lpen(&mut self) -> I2C2LPEN_W<'_>

Bit 22 - I2C2 clock enable during Sleep mode

pub fn i2c3lpen(&mut self) -> I2C3LPEN_W<'_>

Bit 23 - I2C3 clock enable during Sleep mode

pub fn fmpi2c1lpen(&mut self) -> FMPI2C1LPEN_W<'_>

Bit 24 - FMPI2C1 clock enable during Sleep

pub fn can1lpen(&mut self) -> CAN1LPEN_W<'_>

Bit 25 - CAN1LPEN

pub fn can2lpen(&mut self) -> CAN2LPEN_W<'_>

Bit 26 - CAN2LPEN

pub fn pwrlpen(&mut self) -> PWRLPEN_W<'_>

Bit 28 - Power interface clock enable during Sleep mode

pub fn lptimer1lpen(&mut self) -> LPTIMER1LPEN_W<'_>

Bit 9 - TIM14 clock enable during Sleep mode

pub fn rtcapblpen(&mut self) -> RTCAPBLPEN_W<'_>

Bit 10 - RTC APB clock enable during Sleep mode

pub fn usart4lpen(&mut self) -> USART4LPEN_W<'_>

Bit 19 - USART4 clock enable during Sleep mode

pub fn usart5lpen(&mut self) -> USART5LPEN_W<'_>

Bit 20 - USART5 clock enable during Sleep mode

pub fn can3lpen(&mut self) -> CAN3LPEN_W<'_>

Bit 27 - CAN3 clock enable during Sleep mode

pub fn daclpen(&mut self) -> DACLPEN_W<'_>

Bit 29 - DAC clock enable during Sleep mode

pub fn uart7lpen(&mut self) -> UART7LPEN_W<'_>

Bit 30 - UART7 clock enable during Sleep mode

pub fn uart8lpen(&mut self) -> UART8LPEN_W<'_>

Bit 31 - UART8 clock enable during Sleep mode

impl W<u32, Reg<u32, _APB2LPENR>>

pub fn tim1lpen(&mut self) -> TIM1LPEN_W<'_>

Bit 0 - TIM1 clock enable during Sleep mode

pub fn tim8lpen(&mut self) -> TIM8LPEN_W<'_>

Bit 1 - TIM8LPEN

pub fn usart1lpen(&mut self) -> USART1LPEN_W<'_>

Bit 4 - USART1 clock enable during Sleep mode

pub fn usart6lpen(&mut self) -> USART6LPEN_W<'_>

Bit 5 - USART6 clock enable during Sleep mode

pub fn adc1lpen(&mut self) -> ADC1LPEN_W<'_>

Bit 8 - ADC1 clock enable during Sleep mode

pub fn sdiolpen(&mut self) -> SDIOLPEN_W<'_>

Bit 11 - SDIO clock enable during Sleep mode

pub fn spi1lpen(&mut self) -> SPI1LPEN_W<'_>

Bit 12 - SPI 1 clock enable during Sleep mode

pub fn spi4lpen(&mut self) -> SPI4LPEN_W<'_>

Bit 13 - SPI4 clock enable during Sleep mode

pub fn syscfglpen(&mut self) -> SYSCFGLPEN_W<'_>

Bit 14 - System configuration controller clock enable during Sleep mode

pub fn tim9lpen(&mut self) -> TIM9LPEN_W<'_>

Bit 16 - TIM9 clock enable during sleep mode

pub fn tim10lpen(&mut self) -> TIM10LPEN_W<'_>

Bit 17 - TIM10 clock enable during Sleep mode

pub fn tim11lpen(&mut self) -> TIM11LPEN_W<'_>

Bit 18 - TIM11 clock enable during Sleep mode

pub fn dfsdmlpen(&mut self) -> DFSDMLPEN_W<'_>

Bit 24 - DFSDMLPEN

pub fn usart9lpen(&mut self) -> USART9LPEN_W<'_>

Bit 6 - USART9 clock enable during Sleep mode

pub fn usart10lpen(&mut self) -> USART10LPEN_W<'_>

Bit 7 - USART10 clock enable during Sleep mode

pub fn extitlpen(&mut self) -> EXTITLPEN_W<'_>

Bit 15 - EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode

pub fn spi5lpen(&mut self) -> SPI5LPEN_W<'_>

Bit 20 - SPI5 clock enable during Sleep mode

pub fn sai1lpen(&mut self) -> SAI1LPEN_W<'_>

Bit 22 - SAI1 clock enable during Sleep mode

pub fn dfsdm2lpen(&mut self) -> DFSDM2LPEN_W<'_>

Bit 25 - DFSDM2 clock enable during Sleep mode

pub fn uart9lpen(&mut self) -> UART9LPEN_W<'_>

Bit 6 - UART9 clock enable during Sleep mode

pub fn uart10lpen(&mut self) -> UART10LPEN_W<'_>

Bit 7 - UART10 clock enable during Sleep mode

impl W<u32, Reg<u32, _BDCR>>

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External low-speed oscillator bypass

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External low-speed oscillator enable

pub fn lsemod(&mut self) -> LSEMOD_W<'_>

Bit 3 - External low-speed oscillator bypass

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

impl W<u32, Reg<u32, _CSR>>

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn wdgrstf(&mut self) -> WDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn padrstf(&mut self) -> PADRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn borrstf(&mut self) -> BORRSTF_W<'_>

Bit 25 - BOR reset flag

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low-speed oscillator enable

impl W<u32, Reg<u32, _SSCGR>>

pub fn sscgen(&mut self) -> SSCGEN_W<'_>

Bit 31 - Spread spectrum modulation enable

pub fn spreadsel(&mut self) -> SPREADSEL_W<'_>

Bit 30 - Spread Select

pub fn incstep(&mut self) -> INCSTEP_W<'_>

Bits 13:27 - Incrementation step

pub fn modper(&mut self) -> MODPER_W<'_>

Bits 0:12 - Modulation period

impl W<u32, Reg<u32, _PLLI2SCFGR>>

pub fn plli2sr(&mut self) -> PLLI2SR_W<'_>

Bits 28:30 - PLLI2S division factor for I2S clocks

pub fn plli2sn(&mut self) -> PLLI2SN_W<'_>

Bits 6:14 - PLLI2S multiplication factor for VCO

pub fn plli2sm(&mut self) -> PLLI2SM_W<'_>

Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock

pub fn plli2ssrc(&mut self) -> PLLI2SSRC_W<'_>

Bit 22 - PLLI2S entry clock source

pub fn plli2sq(&mut self) -> PLLI2SQ_W<'_>

Bits 24:27 - PLLI2S division factor for USB OTG FS/SDIO/RNG clock

impl W<u32, Reg<u32, _AHB3RSTR>>

pub fn fsmcrst(&mut self) -> FSMCRST_W<'_>

Bit 0 - Flexible memory controller module reset

pub fn qspirst(&mut self) -> QSPIRST_W<'_>

Bit 1 - QUADSPI module reset

impl W<u32, Reg<u32, _AHB3ENR>>

pub fn fsmcen(&mut self) -> FSMCEN_W<'_>

Bit 0 - Flexible memory controller module clock enable

pub fn qspien(&mut self) -> QSPIEN_W<'_>

Bit 1 - QUADSPI memory controller module clock enable

impl W<u32, Reg<u32, _AHB3LPENR>>

pub fn fsmclpen(&mut self) -> FSMCLPEN_W<'_>

Bit 0 - Flexible memory controller module clock enable during Sleep mode

pub fn qspilpen(&mut self) -> QSPILPEN_W<'_>

Bit 1 - QUADSPI memory controller module clock enable during Sleep mode

impl W<u32, Reg<u32, _DCKCFGR>>

pub fn ckdfsdm1asel(&mut self) -> CKDFSDM1ASEL_W<'_>

Bit 15 - DFSDM1 audio clock selection.

pub fn timpre(&mut self) -> TIMPRE_W<'_>

Bit 24 - Timers clocks prescalers selection

pub fn i2s1src(&mut self) -> I2S1SRC_W<'_>

Bits 25:26 - I2S APB1 clocks source selection (I2S2/3)

pub fn i2s2src(&mut self) -> I2S2SRC_W<'_>

Bits 27:28 - I2S APB2 clocks source selection (I2S1/4/5)

pub fn plli2sdivr(&mut self) -> PLLI2SDIVR_W<'_>

Bits 0:4 - PLLI2S division factor for SAI1 A/B clock

pub fn plldivr(&mut self) -> PLLDIVR_W<'_>

Bits 8:12 - PLL division factor for SAI1 A/B clock

pub fn ckdfsdm2asel(&mut self) -> CKDFSDM2ASEL_W<'_>

Bit 14 - DFSDM2 audio clock selection

pub fn sai1asrc(&mut self) -> SAI1ASRC_W<'_>

Bits 20:21 - SAI1-A clock source selection

pub fn sai1bsrc(&mut self) -> SAI1BSRC_W<'_>

Bits 22:23 - SAI1-B clock source selection

pub fn ckdfsdm1sel(&mut self) -> CKDFSDM1SEL_W<'_>

Bit 31 - DFSDM1 Kernel clock selection

impl W<u32, Reg<u32, _CKGATENR>>

pub fn ahb2apb1_cken(&mut self) -> AHB2APB1_CKEN_W<'_>

Bit 0 - AHB to APB1 Bridge clock enable

pub fn ahb2apb2_cken(&mut self) -> AHB2APB2_CKEN_W<'_>

Bit 1 - AHB to APB2 Bridge clock enable

pub fn cm4dbg_cken(&mut self) -> CM4DBG_CKEN_W<'_>

Bit 2 - Cortex M4 ETM clock enable

pub fn spare_cken(&mut self) -> SPARE_CKEN_W<'_>

Bit 3 - Spare clock enable

pub fn sram_cken(&mut self) -> SRAM_CKEN_W<'_>

Bit 4 - SRQAM controller clock enable

pub fn flitf_cken(&mut self) -> FLITF_CKEN_W<'_>

Bit 5 - Flash Interface clock enable

pub fn rcc_cken(&mut self) -> RCC_CKEN_W<'_>

Bit 6 - RCC clock enable

pub fn evtcl_cken(&mut self) -> EVTCL_CKEN_W<'_>

Bit 7 - EVTCL_CKEN

impl W<u32, Reg<u32, _DCKCFGR2>>

pub fn sdiosel(&mut self) -> SDIOSEL_W<'_>

Bit 28 - SDIO clock selection.

pub fn ck48msel(&mut self) -> CK48MSEL_W<'_>

Bit 27 - SDIO/USBFS clock selection.

pub fn fmpi2c1sel(&mut self) -> FMPI2C1SEL_W<'_>

Bits 22:23 - I2CFMP1 kernel clock source selection

pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<'_>

Bits 30:31 - LPTIM1 kernel clock source selection

impl W<u32, Reg<u32, _POWER>>

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>

Bit 14 - HW Flow Control enable

pub fn negedge(&mut self) -> NEGEDGE_W<'_>

Bit 13 - SDIO_CK dephasing selection bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>

Bits 11:12 - Wide bus mode enable bit

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 10 - Clock divider bypass enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>

Bit 9 - Power saving configuration bit

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 8 - Clock enable bit

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 0:7 - Clock divide factor

impl W<u32, Reg<u32, _ARG>>

pub fn cmdarg(&mut self) -> CMDARG_W<'_>

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>

pub fn ce_atacmd(&mut self) -> CE_ATACMD_W<'_>

Bit 14 - CE-ATA command

pub fn n_ien(&mut self) -> NIEN_W<'_>

Bit 13 - not Interrupt Enable

pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W<'_>

Bit 12 - Enable CMD completion

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>

Bit 11 - SD I/O suspend command

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>

Bit 10 - Command path state machine (CPSM) Enable bit

pub fn waitpend(&mut self) -> WAITPEND_W<'_>

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).

pub fn waitint(&mut self) -> WAITINT_W<'_>

Bit 8 - CPSM waits for interrupt request

pub fn waitresp(&mut self) -> WAITRESP_W<'_>

Bits 6:7 - Wait for response bits

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>

Bits 0:5 - Command index

impl W<u32, Reg<u32, _DTIMER>>

pub fn datatime(&mut self) -> DATATIME_W<'_>

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>

pub fn datalength(&mut self) -> DATALENGTH_W<'_>

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SD I/O enable functions

pub fn rwmod(&mut self) -> RWMOD_W<'_>

Bit 10 - Read wait mode

pub fn rwstop(&mut self) -> RWSTOP_W<'_>

Bit 9 - Read wait stop

pub fn rwstart(&mut self) -> RWSTART_W<'_>

Bit 8 - Read wait start

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>

Bits 4:7 - Data block size

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 3 - DMA enable bit

pub fn dtmode(&mut self) -> DTMODE_W<'_>

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

pub fn dtdir(&mut self) -> DTDIR_W<'_>

Bit 1 - Data transfer direction selection

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTEN

impl W<u32, Reg<u32, _ICR>>

pub fn ceataendc(&mut self) -> CEATAENDC_W<'_>

Bit 23 - CEATAEND flag clear bit

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>

Bit 22 - SDIOIT flag clear bit

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>

Bit 10 - DBCKEND flag clear bit

pub fn stbiterrc(&mut self) -> STBITERRC_W<'_>

Bit 9 - STBITERR flag clear bit

pub fn dataendc(&mut self) -> DATAENDC_W<'_>

Bit 8 - DATAEND flag clear bit

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>

Bit 7 - CMDSENT flag clear bit

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>

Bit 6 - CMDREND flag clear bit

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>

Bit 5 - RXOVERR flag clear bit

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>

Bit 4 - TXUNDERR flag clear bit

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>

Bit 3 - DTIMEOUT flag clear bit

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>

Bit 2 - CTIMEOUT flag clear bit

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>

Bit 1 - DCRCFAIL flag clear bit

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>

Bit 0 - CCRCFAIL flag clear bit

impl W<u32, Reg<u32, _MASK>>

pub fn ceataendie(&mut self) -> CEATAENDIE_W<'_>

Bit 23 - CE-ATA command completion signal received interrupt enable

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>

Bit 22 - SDIO mode interrupt received interrupt enable

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>

Bit 21 - Data available in Rx FIFO interrupt enable

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>

Bit 20 - Data available in Tx FIFO interrupt enable

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>

Bit 19 - Rx FIFO empty interrupt enable

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>

Bit 18 - Tx FIFO empty interrupt enable

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>

Bit 17 - Rx FIFO full interrupt enable

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>

Bit 16 - Tx FIFO full interrupt enable

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>

Bit 15 - Rx FIFO half full interrupt enable

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>

Bit 14 - Tx FIFO half empty interrupt enable

pub fn rxactie(&mut self) -> RXACTIE_W<'_>

Bit 13 - Data receive acting interrupt enable

pub fn txactie(&mut self) -> TXACTIE_W<'_>

Bit 12 - Data transmit acting interrupt enable

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>

Bit 11 - Command acting interrupt enable

pub fn dbckendie(&mut self) -> DBCKENDIE_W<'_>

Bit 10 - Data block end interrupt enable

pub fn stbiterrie(&mut self) -> STBITERRIE_W<'_>

Bit 9 - Start bit error interrupt enable

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>

Bit 8 - Data end interrupt enable

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>

Bit 7 - Command sent interrupt enable

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>

Bit 6 - Command response received interrupt enable

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>

Bit 5 - Rx FIFO overrun error interrupt enable

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>

Bit 4 - Tx FIFO underrun error interrupt enable

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>

Bit 3 - Data timeout interrupt enable

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>

Bit 2 - Command timeout interrupt enable

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>

Bit 1 - Data CRC fail interrupt enable

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>

Bit 0 - Command CRC fail interrupt enable

impl W<u32, Reg<u32, _FIFO>>

pub fn fifodata(&mut self) -> FIFODATA_W<'_>

Bits 0:31 - Receive and transmit FIFO data

impl W<u32, Reg<u32, _CR1>>

pub fn mckdiv(&mut self) -> MCKDIV_W<'_>

Bits 20:23 - Master clock divider

pub fn nodiv(&mut self) -> NODIV_W<'_>

Bit 19 - No divider

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 17 - DMA enable

pub fn saien(&mut self) -> SAIEN_W<'_>

Bit 16 - Audio block A enable

pub fn outdriv(&mut self) -> OUTDRIV_W<'_>

Bit 13 - Output drive

pub fn mono(&mut self) -> MONO_W<'_>

Bit 12 - Mono mode

pub fn syncen(&mut self) -> SYNCEN_W<'_>

Bits 10:11 - Synchronization enable

pub fn ckstr(&mut self) -> CKSTR_W<'_>

Bit 9 - Clock strobing edge

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 8 - Least significant bit first

pub fn ds(&mut self) -> DS_W<'_>

Bits 5:7 - Data size

pub fn prtcfg(&mut self) -> PRTCFG_W<'_>

Bits 2:3 - Protocol configuration

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Audio block mode

impl W<u32, Reg<u32, _CR2>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 14:15 - Companding mode

pub fn cpl(&mut self) -> CPL_W<'_>

Bit 13 - Complement bit

pub fn mutecn(&mut self) -> MUTECN_W<'_>

Bits 7:12 - Mute counter

pub fn muteval(&mut self) -> MUTEVAL_W<'_>

Bit 6 - Mute value

pub fn mute(&mut self) -> MUTE_W<'_>

Bit 5 - Mute

pub fn tris(&mut self) -> TRIS_W<'_>

Bit 4 - Tristate management on data line

pub fn fflush(&mut self) -> FFLUSH_W<'_>

Bit 3 - FIFO flush

pub fn fth(&mut self) -> FTH_W<'_>

Bits 0:2 - FIFO threshold

impl W<u32, Reg<u32, _FRCR>>

pub fn fsoff(&mut self) -> FSOFF_W<'_>

Bit 18 - Frame synchronization offset

pub fn fspol(&mut self) -> FSPOL_W<'_>

Bit 17 - Frame synchronization polarity

pub fn fsdef(&mut self) -> FSDEF_W<'_>

Bit 16 - Frame synchronization definition

pub fn fsall(&mut self) -> FSALL_W<'_>

Bits 8:14 - Frame synchronization active level length

pub fn frl(&mut self) -> FRL_W<'_>

Bits 0:7 - Frame length

impl W<u32, Reg<u32, _SLOTR>>

pub fn sloten(&mut self) -> SLOTEN_W<'_>

Bits 16:31 - Slot enable

pub fn nbslot(&mut self) -> NBSLOT_W<'_>

Bits 8:11 - Number of slots in an audio frame

pub fn slotsz(&mut self) -> SLOTSZ_W<'_>

Bits 6:7 - Slot size

pub fn fboff(&mut self) -> FBOFF_W<'_>

Bits 0:4 - First bit offset

impl W<u32, Reg<u32, _IM>>

pub fn lfsdetie(&mut self) -> LFSDETIE_W<'_>

Bit 6 - Late frame synchronization detection interrupt enable

pub fn afsdetie(&mut self) -> AFSDETIE_W<'_>

Bit 5 - Anticipated frame synchronization detection interrupt enable

pub fn cnrdyie(&mut self) -> CNRDYIE_W<'_>

Bit 4 - Codec not ready interrupt enable

pub fn freqie(&mut self) -> FREQIE_W<'_>

Bit 3 - FIFO request interrupt enable

pub fn wckcfgie(&mut self) -> WCKCFGIE_W<'_>

Bit 2 - Wrong clock configuration interrupt enable

pub fn mutedetie(&mut self) -> MUTEDETIE_W<'_>

Bit 1 - Mute detection interrupt enable

pub fn ovrudrie(&mut self) -> OVRUDRIE_W<'_>

Bit 0 - Overrun/underrun interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn flvl(&mut self) -> FLVL_W<'_>

Bits 16:18 - FIFO level threshold

pub fn lfsdet(&mut self) -> LFSDET_W<'_>

Bit 6 - Late frame synchronization detection

pub fn afsdet(&mut self) -> AFSDET_W<'_>

Bit 5 - Anticipated frame synchronization detection

pub fn cnrdy(&mut self) -> CNRDY_W<'_>

Bit 4 - Codec not ready

pub fn freq(&mut self) -> FREQ_W<'_>

Bit 3 - FIFO request

pub fn wckcfg(&mut self) -> WCKCFG_W<'_>

Bit 2 - Wrong clock configuration flag. This bit is read only.

pub fn mutedet(&mut self) -> MUTEDET_W<'_>

Bit 1 - Mute detection

pub fn ovrudr(&mut self) -> OVRUDR_W<'_>

Bit 0 - Overrun / underrun

impl W<u32, Reg<u32, _CLRFR>>

pub fn clfsdet(&mut self) -> CLFSDET_W<'_>

Bit 6 - Clear late frame synchronization detection flag

pub fn cafsdet(&mut self) -> CAFSDET_W<'_>

Bit 5 - Clear anticipated frame synchronization detection flag.

pub fn ccnrdy(&mut self) -> CCNRDY_W<'_>

Bit 4 - Clear codec not ready flag

pub fn cwckcfg(&mut self) -> CWCKCFG_W<'_>

Bit 2 - Clear wrong clock configuration flag

pub fn cmutedet(&mut self) -> CMUTEDET_W<'_>

Bit 1 - Mute detection flag

pub fn covrudr(&mut self) -> COVRUDR_W<'_>

Bit 0 - Clear overrun / underrun

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

impl W<u32, Reg<u32, _I2SPR>>

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _MEMRM>>

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:1 - MEM_MODE

impl W<u32, Reg<u32, _PMC>>

pub fn adc1dc2(&mut self) -> ADC1DC2_W<'_>

Bit 16 - ADC1DC2

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI x configuration (x = 0 to 3)

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI x configuration (x = 0 to 3)

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI x configuration (x = 0 to 3)

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI x configuration (x = 0 to 3)

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI x configuration (x = 4 to 7)

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI x configuration (x = 4 to 7)

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI x configuration (x = 4 to 7)

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI x configuration (x = 4 to 7)

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI x configuration (x = 8 to 11)

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI10

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI x configuration (x = 8 to 11)

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI x configuration (x = 8 to 11)

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI x configuration (x = 12 to 15)

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI x configuration (x = 12 to 15)

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI x configuration (x = 12 to 15)

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI x configuration (x = 12 to 15)

impl W<u32, Reg<u32, _CFGR>>

pub fn fmpi2c1_scl(&mut self) -> FMPI2C1_SCL_W<'_>

Bit 0 - Forces FM+ drive capability on I2CFMP1_SCL pin

pub fn fmpi2c1_sda(&mut self) -> FMPI2C1_SDA_W<'_>

Bit 1 - Forces FM+ drive capability on I2CFMP1_SCL pin

impl W<u32, Reg<u32, _SR>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 9 - CTS flag

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - Data value

impl W<u32, Reg<u32, _BRR>>

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - mantissa of USARTDIV

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - fraction of USARTDIV

impl W<u32, Reg<u32, _CR1>>

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

impl W<u32, Reg<u32, _CR2>>

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _DCFG>>

pub fn dspd(&mut self) -> DSPD_W<'_>

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>

Bit 2 - Non-zero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>

Bits 11:12 - Periodic frame interval

impl W<u32, Reg<u32, _DCTL>>

pub fn rwusig(&mut self) -> RWUSIG_W<'_>

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _DIEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

impl W<u32, Reg<u32, _DOEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>

Bit 4 - OUT token received when endpoint disabled mask

impl W<u32, Reg<u32, _DAINTMSK>>

pub fn iepm(&mut self) -> IEPM_W<'_>

Bits 0:15 - IN EP interrupt mask bits

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bits 16:31 - OUT endpoint interrupt bits

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _DIEPCTL0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:1 - Maximum packet size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

impl W<u32, Reg<u32, _DIEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm_sd1pid(&mut self) -> SODDFRM_SD1PID_W<'_>

Bit 29 - SODDFRM/SD1PID

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL0>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

impl W<u32, Reg<u32, _DOEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPINT0>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT1>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT2>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT3>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT0>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT1>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT2>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT3>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPTSIZ0>>

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ0>>

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>

Bits 29:30 - SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bit 19 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ1>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ2>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ3>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ1>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ2>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ3>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _HCFG>>

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _HFIR>>

pub fn frivl(&mut self) -> FRIVL_W<'_>

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _HPTXSTS>>

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _HAINTMSK>>

pub fn haintm(&mut self) -> HAINTM_W<'_>

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _HPRT>>

pub fn pcdet(&mut self) -> PCDET_W<'_>

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _HCCHAR0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR4>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR5>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR6>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR7>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINTMSK0>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK2>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK3>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK4>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK5>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK6>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK7>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ5>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ6>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ7>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _PCGCCTL>>

pub fn stppclk(&mut self) -> STPPCLK_W<'_>

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>

Bit 4 - PHY Suspended

impl W<u32, Reg<u32, _GOTGCTL>>

pub fn srq(&mut self) -> SRQ_W<'_>

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>

Bit 11 - Device HNP enabled

impl W<u32, Reg<u32, _GOTGINT>>

pub fn sedet(&mut self) -> SEDET_W<'_>

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>

Bit 19 - Debounce done

impl W<u32, Reg<u32, _GAHBCFG>>

pub fn gint(&mut self) -> GINT_W<'_>

Bit 0 - Global interrupt mask

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _GUSBCFG>>

pub fn tocal(&mut self) -> TOCAL_W<'_>

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>

Bit 6 - Full Speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>

Bits 10:13 - USB turnaround time

pub fn fhmod(&mut self) -> FHMOD_W<'_>

Bit 29 - Force host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>

Bit 30 - Force device mode

pub fn ctxpkt(&mut self) -> CTXPKT_W<'_>

Bit 31 - Corrupt Tx packet

impl W<u32, Reg<u32, _GRSTCTL>>

pub fn csrst(&mut self) -> CSRST_W<'_>

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _GINTSTS>>

pub fn mmis(&mut self) -> MMIS_W<'_>

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>

Bit 20 - Incomplete isochronous IN transfer

pub fn ipxfr_incompisoout(&mut self) -> IPXFR_INCOMPISOOUT_W<'_>

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>

Bit 30 - Session request/new session detected interrupt

pub fn wkupint(&mut self) -> WKUPINT_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _GINTMSK>>

pub fn mmism(&mut self) -> MMISM_W<'_>

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>

Bit 4 - Receive FIFO non-empty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>

Bit 5 - Non-periodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>

Bit 6 - Global non-periodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>

Bit 15 - End of periodic frame interrupt mask

pub fn epmism(&mut self) -> EPMISM_W<'_>

Bit 17 - Endpoint mismatch interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>

Bit 20 - Incomplete isochronous IN transfer mask

pub fn ipxfrm_iisooxfrm(&mut self) -> IPXFRM_IISOOXFRM_W<'_>

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

pub fn hcim(&mut self) -> HCIM_W<'_>

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt mask

impl W<u32, Reg<u32, _GRXFSIZ>>

pub fn rxfd(&mut self) -> RXFD_W<'_>

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _GNPTXFSIZ_DEVICE>>

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _GNPTXFSIZ_HOST>>

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>

Bits 0:15 - Non-periodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>

Bits 16:31 - Non-periodic TxFIFO depth

impl W<u32, Reg<u32, _GCCFG>>

pub fn dcdet(&mut self) -> DCDET_W<'_>

Bit 0 - DCDET

pub fn pdet(&mut self) -> PDET_W<'_>

Bit 1 - PDET

pub fn sdet(&mut self) -> SDET_W<'_>

Bit 2 - SDET

pub fn ps2det(&mut self) -> PS2DET_W<'_>

Bit 3 - PS2DET

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>

Bit 16 - PWRDWN

pub fn bcden(&mut self) -> BCDEN_W<'_>

Bit 17 - BCDEN

pub fn dcden(&mut self) -> DCDEN_W<'_>

Bit 18 - DCDEN

pub fn pden(&mut self) -> PDEN_W<'_>

Bit 19 - PDEN

pub fn sden(&mut self) -> SDEN_W<'_>

Bit 20 - SDEN

pub fn vbden(&mut self) -> VBDEN_W<'_>

Bit 21 - VBDEN

impl W<u32, Reg<u32, _CID>>

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _HPTXFSIZ>>

pub fn ptxsa(&mut self) -> PTXSA_W<'_>

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfsiz(&mut self) -> PTXFSIZ_W<'_>

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF1>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF2>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO3 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF3>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO4 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _BCR1>>

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - Wait signal during asynchronous transfers

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - Extended mode enable

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - Wait enable bit

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - Write enable bitWREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - Wait timing configuration

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - Wait signal polarity bit

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - Burst enable bit

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - Flash access enable

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - Memory data bus width

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - Memory type

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - Memory bank enable bit

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - Memory bank enable bit

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - Write burst enable

pub fn cclken(&mut self) -> CCLKEN_W<'_>

Bit 20 - Continuous Clock Enable

pub fn wfdis(&mut self) -> WFDIS_W<'_>

Bit 21 - Write FIFO Disable

impl W<u32, Reg<u32, _BTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - Access mode

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - Data-phase duration

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - Address-hold phase duration

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - Address setup phase duration

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - Clock divide ratio

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - Data latency

impl W<u32, Reg<u32, _BCR>>

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - Wait signal during asynchronous transfers

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - Extended mode enable

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - Wait enable bit

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - Write enable bit

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - Wait timing configuration

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - Wait signal polarity bit

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - Burst enable bit

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - Flash access enable

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - Memory data bus width

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - Memory type

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - Address/data multiplexing enable bit

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - Memory bank enable bit

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - Write burst enable

pub fn cclken(&mut self) -> CCLKEN_W<'_>

Bit 20 - Continuous Clock Enable

pub fn wfdis(&mut self) -> WFDIS_W<'_>

Bit 21 - Write FIFO Disable

impl W<u32, Reg<u32, _BWTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - Access mode

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - Data-phase duration

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - Address-hold phase duration

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - Address setup phase duration

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

impl W<u32, Reg<u32, _CCR>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn vbate(&mut self) -> VBATE_W<'_>

Bit 22 - VBAT enable

pub fn adcpre(&mut self) -> ADCPRE_W<'_>

Bits 16:17 - ADC prescaler

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _CR>>

pub fn ie(&mut self) -> IE_W<'_>

Bit 3 - Interrupt enable

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 2 - Random number generator enable

impl W<u32, Reg<u32, _SR>>

pub fn seis(&mut self) -> SEIS_W<'_>

Bit 6 - Seed error interrupt status

pub fn ceis(&mut self) -> CEIS_W<'_>

Bit 5 - Clock error interrupt status

impl W<u32, Reg<u32, _CR>>

pub fn init(&mut self) -> INIT_W<'_>

Bit 2 - Initialize message digest calculation

pub fn dmae(&mut self) -> DMAE_W<'_>

Bit 3 - DMA enable

pub fn datatype(&mut self) -> DATATYPE_W<'_>

Bits 4:5 - Data type selection

pub fn mode(&mut self) -> MODE_W<'_>

Bit 6 - Mode selection

pub fn algo0(&mut self) -> ALGO0_W<'_>

Bit 7 - Algorithm selection

pub fn mdmat(&mut self) -> MDMAT_W<'_>

Bit 13 - Multiple DMA Transfers

pub fn lkey(&mut self) -> LKEY_W<'_>

Bit 16 - Long key selection

pub fn algo1(&mut self) -> ALGO1_W<'_>

Bit 18 - ALGO

impl W<u32, Reg<u32, _DIN>>

pub fn datain(&mut self) -> DATAIN_W<'_>

Bits 0:31 - Data input

impl W<u32, Reg<u32, _STR>>

pub fn dcal(&mut self) -> DCAL_W<'_>

Bit 8 - Digest calculation

pub fn nblw(&mut self) -> NBLW_W<'_>

Bits 0:4 - Number of valid bits in the last word of the message

impl W<u32, Reg<u32, _IMR>>

pub fn dcie(&mut self) -> DCIE_W<'_>

Bit 1 - Digest calculation completion interrupt enable

pub fn dinie(&mut self) -> DINIE_W<'_>

Bit 0 - Data input interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn dcis(&mut self) -> DCIS_W<'_>

Bit 1 - Digest calculation completion interrupt status

pub fn dinis(&mut self) -> DINIS_W<'_>

Bit 0 - Data input interrupt status

impl W<u32, Reg<u32, _CSR>>

pub fn csr(&mut self) -> CSR_W<'_>

Bits 0:31 - CSR0

impl W<u32, Reg<u32, _KLR>>

pub fn b2(&mut self) -> B2_W<'_>

Bits 0:31 - b224

impl W<u32, Reg<u32, _KRR>>

pub fn b(&mut self) -> B_W<'_>

Bits 0:31 - b192

impl W<u32, Reg<u32, _IVLR>>

pub fn iv(&mut self) -> IV_W<'_>

Bits 0:31 - IV31

impl W<u32, Reg<u32, _IVRR>>

pub fn iv(&mut self) -> IV_W<'_>

Bits 0:31 - IV63

impl W<u32, Reg<u32, _CR>>

pub fn algodir(&mut self) -> ALGODIR_W<'_>

Bit 2 - Algorithm direction

pub fn algomode0(&mut self) -> ALGOMODE0_W<'_>

Bits 3:5 - Algorithm mode

pub fn datatype(&mut self) -> DATATYPE_W<'_>

Bits 6:7 - Data type selection

pub fn keysize(&mut self) -> KEYSIZE_W<'_>

Bits 8:9 - Key size selection (AES mode only)

pub fn fflush(&mut self) -> FFLUSH_W<'_>

Bit 14 - FIFO flush

pub fn crypen(&mut self) -> CRYPEN_W<'_>

Bit 15 - Cryptographic processor enable

pub fn gcm_ccmph(&mut self) -> GCM_CCMPH_W<'_>

Bits 16:17 - GCM_CCMPH

pub fn algomode3(&mut self) -> ALGOMODE3_W<'_>

Bit 19 - ALGOMODE

impl W<u32, Reg<u32, _DIN>>

pub fn datain(&mut self) -> DATAIN_W<'_>

Bits 0:31 - Data input

impl W<u32, Reg<u32, _DMACR>>

pub fn doen(&mut self) -> DOEN_W<'_>

Bit 1 - DMA output enable

pub fn dien(&mut self) -> DIEN_W<'_>

Bit 0 - DMA input enable

impl W<u32, Reg<u32, _IMSCR>>

pub fn outim(&mut self) -> OUTIM_W<'_>

Bit 1 - Output FIFO service interrupt mask

pub fn inim(&mut self) -> INIM_W<'_>

Bit 0 - Input FIFO service interrupt mask

impl W<u32, Reg<u32, _CSGCMCCMR>>

pub fn csgcmccm0r(&mut self) -> CSGCMCCM0R_W<'_>

Bits 0:31 - CSGCMCCM0R

impl W<u32, Reg<u32, _CSGCMR>>

pub fn csgcmr(&mut self) -> CSGCMR_W<'_>

Bits 0:31 - CSGCM0R

impl W<u32, Reg<u32, _CR>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 14 - DCMI enable

pub fn edm(&mut self) -> EDM_W<'_>

Bits 10:11 - Extended data mode

pub fn fcrc(&mut self) -> FCRC_W<'_>

Bits 8:9 - Frame capture rate control

pub fn vspol(&mut self) -> VSPOL_W<'_>

Bit 7 - Vertical synchronization polarity

pub fn hspol(&mut self) -> HSPOL_W<'_>

Bit 6 - Horizontal synchronization polarity

pub fn pckpol(&mut self) -> PCKPOL_W<'_>

Bit 5 - Pixel clock polarity

pub fn ess(&mut self) -> ESS_W<'_>

Bit 4 - Embedded synchronization select

pub fn jpeg(&mut self) -> JPEG_W<'_>

Bit 3 - JPEG format

pub fn crop(&mut self) -> CROP_W<'_>

Bit 2 - Crop feature

pub fn cm(&mut self) -> CM_W<'_>

Bit 1 - Capture mode

pub fn capture(&mut self) -> CAPTURE_W<'_>

Bit 0 - Capture enable

impl W<u32, Reg<u32, _IER>>

pub fn line_ie(&mut self) -> LINE_IE_W<'_>

Bit 4 - Line interrupt enable

pub fn vsync_ie(&mut self) -> VSYNC_IE_W<'_>

Bit 3 - VSYNC interrupt enable

pub fn err_ie(&mut self) -> ERR_IE_W<'_>

Bit 2 - Synchronization error interrupt enable

pub fn ovr_ie(&mut self) -> OVR_IE_W<'_>

Bit 1 - Overrun interrupt enable

pub fn frame_ie(&mut self) -> FRAME_IE_W<'_>

Bit 0 - Capture complete interrupt enable

impl W<u32, Reg<u32, _ICR>>

pub fn line_isc(&mut self) -> LINE_ISC_W<'_>

Bit 4 - line interrupt status clear

pub fn vsync_isc(&mut self) -> VSYNC_ISC_W<'_>

Bit 3 - Vertical synch interrupt status clear

pub fn err_isc(&mut self) -> ERR_ISC_W<'_>

Bit 2 - Synchronization error interrupt status clear

pub fn ovr_isc(&mut self) -> OVR_ISC_W<'_>

Bit 1 - Overrun interrupt status clear

pub fn frame_isc(&mut self) -> FRAME_ISC_W<'_>

Bit 0 - Capture complete interrupt status clear

impl W<u32, Reg<u32, _ESCR>>

pub fn fec(&mut self) -> FEC_W<'_>

Bits 24:31 - Frame end delimiter code

pub fn lec(&mut self) -> LEC_W<'_>

Bits 16:23 - Line end delimiter code

pub fn lsc(&mut self) -> LSC_W<'_>

Bits 8:15 - Line start delimiter code

pub fn fsc(&mut self) -> FSC_W<'_>

Bits 0:7 - Frame start delimiter code

impl W<u32, Reg<u32, _ESUR>>

pub fn feu(&mut self) -> FEU_W<'_>

Bits 24:31 - Frame end delimiter unmask

pub fn leu(&mut self) -> LEU_W<'_>

Bits 16:23 - Line end delimiter unmask

pub fn lsu(&mut self) -> LSU_W<'_>

Bits 8:15 - Line start delimiter unmask

pub fn fsu(&mut self) -> FSU_W<'_>

Bits 0:7 - Frame start delimiter unmask

impl W<u32, Reg<u32, _CWSTRT>>

pub fn vst(&mut self) -> VST_W<'_>

Bits 16:28 - Vertical start line count

pub fn hoffcnt(&mut self) -> HOFFCNT_W<'_>

Bits 0:13 - Horizontal offset count

impl W<u32, Reg<u32, _CWSIZE>>

pub fn vline(&mut self) -> VLINE_W<'_>

Bits 16:29 - Vertical line count

pub fn capcnt(&mut self) -> CAPCNT_W<'_>

Bits 0:13 - Capture count

impl W<u32, Reg<u32, _BCR1>>

pub fn cclken(&mut self) -> CCLKEN_W<'_>

Bit 20 - CCLKEN

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn wfdis(&mut self) -> WFDIS_W<'_>

Bit 21 - Write FIFO disable

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _BTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _PCR>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM>>

pub fn memhiz(&mut self) -> MEMHIZ_W<'_>

Bits 24:31 - MEMHIZx

pub fn memhold(&mut self) -> MEMHOLD_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwait(&mut self) -> MEMWAIT_W<'_>

Bits 8:15 - MEMWAITx

pub fn memset(&mut self) -> MEMSET_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT>>

pub fn atthiz(&mut self) -> ATTHIZ_W<'_>

Bits 24:31 - ATTHIZx

pub fn atthold(&mut self) -> ATTHOLD_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwait(&mut self) -> ATTWAIT_W<'_>

Bits 8:15 - ATTWAITx

pub fn attset(&mut self) -> ATTSET_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _BWTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

impl W<u32, Reg<u32, _SDCR>>

pub fn nc(&mut self) -> NC_W<'_>

Bits 0:1 - Number of column address bits

pub fn nr(&mut self) -> NR_W<'_>

Bits 2:3 - Number of row address bits

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - Memory data bus width

pub fn nb(&mut self) -> NB_W<'_>

Bit 6 - Number of internal banks

pub fn cas(&mut self) -> CAS_W<'_>

Bits 7:8 - CAS latency

pub fn wp(&mut self) -> WP_W<'_>

Bit 9 - Write protection

pub fn sdclk(&mut self) -> SDCLK_W<'_>

Bits 10:11 - SDRAM clock configuration

pub fn rburst(&mut self) -> RBURST_W<'_>

Bit 12 - Burst read

pub fn rpipe(&mut self) -> RPIPE_W<'_>

Bits 13:14 - Read pipe

impl W<u32, Reg<u32, _SDTR>>

pub fn tmrd(&mut self) -> TMRD_W<'_>

Bits 0:3 - Load Mode Register to Active

pub fn txsr(&mut self) -> TXSR_W<'_>

Bits 4:7 - Exit self-refresh delay

pub fn tras(&mut self) -> TRAS_W<'_>

Bits 8:11 - Self refresh time

pub fn trc(&mut self) -> TRC_W<'_>

Bits 12:15 - Row cycle delay

pub fn twr(&mut self) -> TWR_W<'_>

Bits 16:19 - Recovery delay

pub fn trp(&mut self) -> TRP_W<'_>

Bits 20:23 - Row precharge delay

pub fn trcd(&mut self) -> TRCD_W<'_>

Bits 24:27 - Row to column delay

impl W<u32, Reg<u32, _SDCMR>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:2 - Command mode

pub fn ctb2(&mut self) -> CTB2_W<'_>

Bit 3 - Command target bank 2

pub fn ctb1(&mut self) -> CTB1_W<'_>

Bit 4 - Command target bank 1

pub fn nrfs(&mut self) -> NRFS_W<'_>

Bits 5:8 - Number of Auto-refresh

pub fn mrd(&mut self) -> MRD_W<'_>

Bits 9:21 - Mode Register definition

impl W<u32, Reg<u32, _SDRTR>>

pub fn cre(&mut self) -> CRE_W<'_>

Bit 0 - Clear Refresh error flag

pub fn count(&mut self) -> COUNT_W<'_>

Bits 1:13 - Refresh Timer Count

pub fn reie(&mut self) -> REIE_W<'_>

Bit 14 - RES Interrupt Enable

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - DBG_SLEEP

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - DBG_STOP

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - DBG_STANDBY

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - TRACE_IOEN

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - TRACE_MODE

impl W<u32, Reg<u32, _APB1_FZ>>

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 0 - DBG_TIM2_STOP

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - DBG_TIM3 _STOP

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 2 - DBG_TIM4_STOP

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 3 - DBG_TIM5_STOP

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>

Bit 4 - DBG_TIM6_STOP

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 5 - DBG_TIM7_STOP

pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<'_>

Bit 6 - DBG_TIM12_STOP

pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<'_>

Bit 7 - DBG_TIM13_STOP

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>

Bit 8 - DBG_TIM14_STOP

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - DBG_WWDG_STOP

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - DBG_IWDEG_STOP

pub fn dbg_j2c1_smbus_timeout(&mut self) -> DBG_J2C1_SMBUS_TIMEOUT_W<'_>

Bit 21 - DBG_J2C1_SMBUS_TIMEOUT

pub fn dbg_j2c2_smbus_timeout(&mut self) -> DBG_J2C2_SMBUS_TIMEOUT_W<'_>

Bit 22 - DBG_J2C2_SMBUS_TIMEOUT

pub fn dbg_j2c3smbus_timeout(&mut self) -> DBG_J2C3SMBUS_TIMEOUT_W<'_>

Bit 23 - DBG_J2C3SMBUS_TIMEOUT

pub fn dbg_can1_stop(&mut self) -> DBG_CAN1_STOP_W<'_>

Bit 25 - DBG_CAN1_STOP

pub fn dbg_can2_stop(&mut self) -> DBG_CAN2_STOP_W<'_>

Bit 26 - DBG_CAN2_STOP

impl W<u32, Reg<u32, _APB2_FZ>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 0 - TIM1 counter stopped when core is halted

pub fn dbg_tim8_stop(&mut self) -> DBG_TIM8_STOP_W<'_>

Bit 1 - TIM8 counter stopped when core is halted

pub fn dbg_tim9_stop(&mut self) -> DBG_TIM9_STOP_W<'_>

Bit 16 - TIM9 counter stopped when core is halted

pub fn dbg_tim10_stop(&mut self) -> DBG_TIM10_STOP_W<'_>

Bit 17 - TIM10 counter stopped when core is halted

pub fn dbg_tim11_stop(&mut self) -> DBG_TIM11_STOP_W<'_>

Bit 18 - TIM11 counter stopped when core is halted

impl W<u32, Reg<u32, _CR>>

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 25:27 - Channel selection

pub fn mburst(&mut self) -> MBURST_W<'_>

Bits 23:24 - Memory burst transfer configuration

pub fn pburst(&mut self) -> PBURST_W<'_>

Bits 21:22 - Peripheral burst transfer configuration

pub fn ct(&mut self) -> CT_W<'_>

Bit 19 - Current target (only in double buffer mode)

pub fn dbm(&mut self) -> DBM_W<'_>

Bit 18 - Double buffer mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 16:17 - Priority level

pub fn pincos(&mut self) -> PINCOS_W<'_>

Bit 15 - Peripheral increment offset size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 13:14 - Memory data size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 11:12 - Peripheral data size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 10 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 9 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 8 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bits 6:7 - Data transfer direction

pub fn pfctrl(&mut self) -> PFCTRL_W<'_>

Bit 5 - Peripheral flow controller

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 4 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 3 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 2 - Transfer error interrupt enable

pub fn dmeie(&mut self) -> DMEIE_W<'_>

Bit 1 - Direct mode error interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Stream enable / flag stream ready when read low

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data items to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _M0AR>>

pub fn m0a(&mut self) -> M0A_W<'_>

Bits 0:31 - Memory 0 address

impl W<u32, Reg<u32, _M1AR>>

pub fn m1a(&mut self) -> M1A_W<'_>

Bits 0:31 - Memory 1 address (used in case of Double buffer mode)

impl W<u32, Reg<u32, _FCR>>

pub fn feie(&mut self) -> FEIE_W<'_>

Bit 7 - FIFO error interrupt enable

pub fn dmdis(&mut self) -> DMDIS_W<'_>

Bit 2 - Direct mode disable

pub fn fth(&mut self) -> FTH_W<'_>

Bits 0:1 - FIFO threshold selection

impl W<u32, Reg<u32, _LIFCR>>

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif3(&mut self) -> CDMEIF3_W<'_>

Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif3(&mut self) -> CFEIF3_W<'_>

Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif2(&mut self) -> CDMEIF2_W<'_>

Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif2(&mut self) -> CFEIF2_W<'_>

Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif1(&mut self) -> CDMEIF1_W<'_>

Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif1(&mut self) -> CFEIF1_W<'_>

Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif0(&mut self) -> CTCIF0_W<'_>

Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif0(&mut self) -> CHTIF0_W<'_>

Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif0(&mut self) -> CTEIF0_W<'_>

Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif0(&mut self) -> CDMEIF0_W<'_>

Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif0(&mut self) -> CFEIF0_W<'_>

Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)

impl W<u32, Reg<u32, _HIFCR>>

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif7(&mut self) -> CDMEIF7_W<'_>

Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif7(&mut self) -> CFEIF7_W<'_>

Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif6(&mut self) -> CDMEIF6_W<'_>

Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif6(&mut self) -> CFEIF6_W<'_>

Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif5(&mut self) -> CDMEIF5_W<'_>

Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif5(&mut self) -> CFEIF5_W<'_>

Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif4(&mut self) -> CDMEIF4_W<'_>

Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif4(&mut self) -> CFEIF4_W<'_>

Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal high-speed clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal high-speed clock trimming

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE clock bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - Main PLL (PLL) enable

pub fn plli2son(&mut self) -> PLLI2SON_W<'_>

Bit 26 - PLLI2S enable

pub fn pllsaion(&mut self) -> PLLSAION_W<'_>

Bit 28 - PLLSAI enable

impl W<u32, Reg<u32, _PLLCFGR>>

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 28:30 - Main PLL division factor for DSI clock

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 6:14 - Main PLL (PLL) multiplication factor for VCO

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 16:17 - Main PLL (PLL) division factor for main system clock

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks

impl W<u32, Reg<u32, _CFGR>>

pub fn mco2(&mut self) -> MCO2_W<'_>

Bits 30:31 - Microcontroller clock output 2

pub fn mco2pre(&mut self) -> MCO2PRE_W<'_>

Bits 27:29 - MCO2 prescaler

pub fn mco1pre(&mut self) -> MCO1PRE_W<'_>

Bits 24:26 - MCO1 prescaler

pub fn i2ssrc(&mut self) -> I2SSRC_W<'_>

Bit 23 - I2S clock selection

pub fn mco1(&mut self) -> MCO1_W<'_>

Bits 21:22 - Microcontroller clock output 1

pub fn rtcpre(&mut self) -> RTCPRE_W<'_>

Bits 16:20 - HSE division factor for RTC clock

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 13:15 - APB high-speed prescaler (APB2)

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 10:12 - APB Low speed prescaler (APB1)

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock switch

impl W<u32, Reg<u32, _CIR>>

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

pub fn pllsairdyc(&mut self) -> PLLSAIRDYC_W<'_>

Bit 22 - PLLSAI Ready Interrupt Clear

pub fn plli2srdyc(&mut self) -> PLLI2SRDYC_W<'_>

Bit 21 - PLLI2S ready interrupt clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - Main PLL(PLL) ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE ready interrupt clear

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI ready interrupt clear

pub fn pllsairdyie(&mut self) -> PLLSAIRDYIE_W<'_>

Bit 14 - PLLSAI Ready Interrupt Enable

pub fn plli2srdyie(&mut self) -> PLLI2SRDYIE_W<'_>

Bit 13 - PLLI2S ready interrupt enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - Main PLL (PLL) ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE ready interrupt enable

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI ready interrupt enable

impl W<u32, Reg<u32, _AHB1RSTR>>

pub fn otghsrst(&mut self) -> OTGHSRST_W<'_>

Bit 29 - USB OTG HS module reset

pub fn ethmacrst(&mut self) -> ETHMACRST_W<'_>

Bit 25 - Ethernet MAC reset

pub fn dma2drst(&mut self) -> DMA2DRST_W<'_>

Bit 23 - DMA2D reset

pub fn dma2rst(&mut self) -> DMA2RST_W<'_>

Bit 22 - DMA2 reset

pub fn dma1rst(&mut self) -> DMA1RST_W<'_>

Bit 21 - DMA2 reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 12 - CRC reset

pub fn gpiokrst(&mut self) -> GPIOKRST_W<'_>

Bit 10 - IO port K reset

pub fn gpiojrst(&mut self) -> GPIOJRST_W<'_>

Bit 9 - IO port J reset

pub fn gpioirst(&mut self) -> GPIOIRST_W<'_>

Bit 8 - IO port I reset

pub fn gpiohrst(&mut self) -> GPIOHRST_W<'_>

Bit 7 - IO port H reset

pub fn gpiogrst(&mut self) -> GPIOGRST_W<'_>

Bit 6 - IO port G reset

pub fn gpiofrst(&mut self) -> GPIOFRST_W<'_>

Bit 5 - IO port F reset

pub fn gpioerst(&mut self) -> GPIOERST_W<'_>

Bit 4 - IO port E reset

pub fn gpiodrst(&mut self) -> GPIODRST_W<'_>

Bit 3 - IO port D reset

pub fn gpiocrst(&mut self) -> GPIOCRST_W<'_>

Bit 2 - IO port C reset

pub fn gpiobrst(&mut self) -> GPIOBRST_W<'_>

Bit 1 - IO port B reset

pub fn gpioarst(&mut self) -> GPIOARST_W<'_>

Bit 0 - IO port A reset

impl W<u32, Reg<u32, _AHB2RSTR>>

pub fn otgfsrst(&mut self) -> OTGFSRST_W<'_>

Bit 7 - USB OTG FS module reset

pub fn rngrst(&mut self) -> RNGRST_W<'_>

Bit 6 - Random number generator module reset

pub fn hsahrst(&mut self) -> HSAHRST_W<'_>

Bit 5 - Hash module reset

pub fn cryprst(&mut self) -> CRYPRST_W<'_>

Bit 4 - Cryptographic module reset

pub fn dcmirst(&mut self) -> DCMIRST_W<'_>

Bit 0 - Camera interface reset

impl W<u32, Reg<u32, _AHB3RSTR>>

pub fn fmcrst(&mut self) -> FMCRST_W<'_>

Bit 0 - Flexible memory controller module reset

pub fn qspirst(&mut self) -> QSPIRST_W<'_>

Bit 1 - QUADSPI memory controller reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - TIM3 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - TIM4 reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>

Bit 3 - TIM5 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - TIM6 reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - TIM7 reset

pub fn tim12rst(&mut self) -> TIM12RST_W<'_>

Bit 6 - TIM12 reset

pub fn tim13rst(&mut self) -> TIM13RST_W<'_>

Bit 7 - TIM13 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 8 - TIM14 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI 2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI 3 reset

pub fn uart2rst(&mut self) -> UART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn uart3rst(&mut self) -> UART3RST_W<'_>

Bit 18 - USART 3 reset

pub fn uart4rst(&mut self) -> UART4RST_W<'_>

Bit 19 - USART 4 reset

pub fn uart5rst(&mut self) -> UART5RST_W<'_>

Bit 20 - USART 5 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C 1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C 2 reset

pub fn i2c3rst(&mut self) -> I2C3RST_W<'_>

Bit 23 - I2C3 reset

pub fn can1rst(&mut self) -> CAN1RST_W<'_>

Bit 25 - CAN1 reset

pub fn can2rst(&mut self) -> CAN2RST_W<'_>

Bit 26 - CAN2 reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn dacrst(&mut self) -> DACRST_W<'_>

Bit 29 - DAC reset

pub fn uart7rst(&mut self) -> UART7RST_W<'_>

Bit 30 - UART7 reset

pub fn uart8rst(&mut self) -> UART8RST_W<'_>

Bit 31 - UART8 reset

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 0 - TIM1 reset

pub fn tim8rst(&mut self) -> TIM8RST_W<'_>

Bit 1 - TIM8 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 4 - USART1 reset

pub fn usart6rst(&mut self) -> USART6RST_W<'_>

Bit 5 - USART6 reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 8 - ADC interface reset (common to all ADCs)

pub fn sdiorst(&mut self) -> SDIORST_W<'_>

Bit 11 - SDIO reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn spi4rst(&mut self) -> SPI4RST_W<'_>

Bit 13 - SPI4 reset

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 14 - System configuration controller reset

pub fn tim9rst(&mut self) -> TIM9RST_W<'_>

Bit 16 - TIM9 reset

pub fn tim10rst(&mut self) -> TIM10RST_W<'_>

Bit 17 - TIM10 reset

pub fn tim11rst(&mut self) -> TIM11RST_W<'_>

Bit 18 - TIM11 reset

pub fn spi5rst(&mut self) -> SPI5RST_W<'_>

Bit 20 - SPI5 reset

pub fn spi6rst(&mut self) -> SPI6RST_W<'_>

Bit 21 - SPI6 reset

pub fn sai1rst(&mut self) -> SAI1RST_W<'_>

Bit 22 - SAI1 reset

pub fn ltdcrst(&mut self) -> LTDCRST_W<'_>

Bit 26 - LTDC reset

pub fn dsirst(&mut self) -> DSIRST_W<'_>

Bit 27 - DSI host reset

impl W<u32, Reg<u32, _AHB1ENR>>

pub fn otghsulpien(&mut self) -> OTGHSULPIEN_W<'_>

Bit 30 - USB OTG HSULPI clock enable

pub fn otghsen(&mut self) -> OTGHSEN_W<'_>

Bit 29 - USB OTG HS clock enable

pub fn ethmacptpen(&mut self) -> ETHMACPTPEN_W<'_>

Bit 28 - Ethernet PTP clock enable

pub fn ethmacrxen(&mut self) -> ETHMACRXEN_W<'_>

Bit 27 - Ethernet Reception clock enable

pub fn ethmactxen(&mut self) -> ETHMACTXEN_W<'_>

Bit 26 - Ethernet Transmission clock enable

pub fn ethmacen(&mut self) -> ETHMACEN_W<'_>

Bit 25 - Ethernet MAC clock enable

pub fn dma2den(&mut self) -> DMA2DEN_W<'_>

Bit 23 - DMA2D clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 22 - DMA2 clock enable

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 21 - DMA1 clock enable

pub fn ccmdataramen(&mut self) -> CCMDATARAMEN_W<'_>

Bit 20 - CCM data RAM clock enable

pub fn bkpsramen(&mut self) -> BKPSRAMEN_W<'_>

Bit 18 - Backup SRAM interface clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CRC clock enable

pub fn gpioken(&mut self) -> GPIOKEN_W<'_>

Bit 10 - IO port K clock enable

pub fn gpiojen(&mut self) -> GPIOJEN_W<'_>

Bit 9 - IO port J clock enable

pub fn gpioien(&mut self) -> GPIOIEN_W<'_>

Bit 8 - IO port I clock enable

pub fn gpiohen(&mut self) -> GPIOHEN_W<'_>

Bit 7 - IO port H clock enable

pub fn gpiogen(&mut self) -> GPIOGEN_W<'_>

Bit 6 - IO port G clock enable

pub fn gpiofen(&mut self) -> GPIOFEN_W<'_>

Bit 5 - IO port F clock enable

pub fn gpioeen(&mut self) -> GPIOEEN_W<'_>

Bit 4 - IO port E clock enable

pub fn gpioden(&mut self) -> GPIODEN_W<'_>

Bit 3 - IO port D clock enable

pub fn gpiocen(&mut self) -> GPIOCEN_W<'_>

Bit 2 - IO port C clock enable

pub fn gpioben(&mut self) -> GPIOBEN_W<'_>

Bit 1 - IO port B clock enable

pub fn gpioaen(&mut self) -> GPIOAEN_W<'_>

Bit 0 - IO port A clock enable

impl W<u32, Reg<u32, _AHB2ENR>>

pub fn otgfsen(&mut self) -> OTGFSEN_W<'_>

Bit 7 - USB OTG FS clock enable

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 6 - Random number generator clock enable

pub fn hashen(&mut self) -> HASHEN_W<'_>

Bit 5 - Hash modules clock enable

pub fn crypen(&mut self) -> CRYPEN_W<'_>

Bit 4 - Cryptographic modules clock enable

pub fn dcmien(&mut self) -> DCMIEN_W<'_>

Bit 0 - Camera interface enable

impl W<u32, Reg<u32, _AHB3ENR>>

pub fn fmcen(&mut self) -> FMCEN_W<'_>

Bit 0 - Flexible memory controller module clock enable

pub fn qspien(&mut self) -> QSPIEN_W<'_>

Bit 1 - QUADSPI memory controller module clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - TIM2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - TIM4 clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>

Bit 3 - TIM5 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - TIM6 clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - TIM7 clock enable

pub fn tim12en(&mut self) -> TIM12EN_W<'_>

Bit 6 - TIM12 clock enable

pub fn tim13en(&mut self) -> TIM13EN_W<'_>

Bit 7 - TIM13 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 8 - TIM14 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART3 clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>

Bit 19 - UART4 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>

Bit 20 - UART5 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>

Bit 23 - I2C3 clock enable

pub fn can1en(&mut self) -> CAN1EN_W<'_>

Bit 25 - CAN 1 clock enable

pub fn can2en(&mut self) -> CAN2EN_W<'_>

Bit 26 - CAN 2 clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn dacen(&mut self) -> DACEN_W<'_>

Bit 29 - DAC interface clock enable

pub fn uart7en(&mut self) -> UART7EN_W<'_>

Bit 30 - UART7 clock enable

pub fn uart8en(&mut self) -> UART8EN_W<'_>

Bit 31 - UART8 clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 0 - TIM1 clock enable

pub fn tim8en(&mut self) -> TIM8EN_W<'_>

Bit 1 - TIM8 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 4 - USART1 clock enable

pub fn usart6en(&mut self) -> USART6EN_W<'_>

Bit 5 - USART6 clock enable

pub fn adc1en(&mut self) -> ADC1EN_W<'_>

Bit 8 - ADC1 clock enable

pub fn adc2en(&mut self) -> ADC2EN_W<'_>

Bit 9 - ADC2 clock enable

pub fn adc3en(&mut self) -> ADC3EN_W<'_>

Bit 10 - ADC3 clock enable

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SDIO clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn spi4en(&mut self) -> SPI4EN_W<'_>

Bit 13 - SPI4 clock enable

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 14 - System configuration controller clock enable

pub fn tim9en(&mut self) -> TIM9EN_W<'_>

Bit 16 - TIM9 clock enable

pub fn tim10en(&mut self) -> TIM10EN_W<'_>

Bit 17 - TIM10 clock enable

pub fn tim11en(&mut self) -> TIM11EN_W<'_>

Bit 18 - TIM11 clock enable

pub fn spi5en(&mut self) -> SPI5EN_W<'_>

Bit 20 - SPI5 clock enable

pub fn spi6en(&mut self) -> SPI6EN_W<'_>

Bit 21 - SPI6 clock enable

pub fn sai1en(&mut self) -> SAI1EN_W<'_>

Bit 22 - SAI1 clock enable

pub fn ltdcen(&mut self) -> LTDCEN_W<'_>

Bit 26 - LTDC clock enable

pub fn dsien(&mut self) -> DSIEN_W<'_>

Bit 27 - DSI clocks enable

impl W<u32, Reg<u32, _AHB1LPENR>>

pub fn gpioalpen(&mut self) -> GPIOALPEN_W<'_>

Bit 0 - IO port A clock enable during sleep mode

pub fn gpioblpen(&mut self) -> GPIOBLPEN_W<'_>

Bit 1 - IO port B clock enable during Sleep mode

pub fn gpioclpen(&mut self) -> GPIOCLPEN_W<'_>

Bit 2 - IO port C clock enable during Sleep mode

pub fn gpiodlpen(&mut self) -> GPIODLPEN_W<'_>

Bit 3 - IO port D clock enable during Sleep mode

pub fn gpioelpen(&mut self) -> GPIOELPEN_W<'_>

Bit 4 - IO port E clock enable during Sleep mode

pub fn gpioflpen(&mut self) -> GPIOFLPEN_W<'_>

Bit 5 - IO port F clock enable during Sleep mode

pub fn gpioglpen(&mut self) -> GPIOGLPEN_W<'_>

Bit 6 - IO port G clock enable during Sleep mode

pub fn gpiohlpen(&mut self) -> GPIOHLPEN_W<'_>

Bit 7 - IO port H clock enable during Sleep mode

pub fn gpioilpen(&mut self) -> GPIOILPEN_W<'_>

Bit 8 - IO port I clock enable during Sleep mode

pub fn gpiojlpen(&mut self) -> GPIOJLPEN_W<'_>

Bit 9 - IO port J clock enable during Sleep mode

pub fn gpioklpen(&mut self) -> GPIOKLPEN_W<'_>

Bit 10 - IO port K clock enable during Sleep mode

pub fn crclpen(&mut self) -> CRCLPEN_W<'_>

Bit 12 - CRC clock enable during Sleep mode

pub fn flitflpen(&mut self) -> FLITFLPEN_W<'_>

Bit 15 - Flash interface clock enable during Sleep mode

pub fn sram1lpen(&mut self) -> SRAM1LPEN_W<'_>

Bit 16 - SRAM 1interface clock enable during Sleep mode

pub fn sram2lpen(&mut self) -> SRAM2LPEN_W<'_>

Bit 17 - SRAM 2 interface clock enable during Sleep mode

pub fn bkpsramlpen(&mut self) -> BKPSRAMLPEN_W<'_>

Bit 18 - Backup SRAM interface clock enable during Sleep mode

pub fn sram3lpen(&mut self) -> SRAM3LPEN_W<'_>

Bit 19 - SRAM 3 interface clock enable during Sleep mode

pub fn dma1lpen(&mut self) -> DMA1LPEN_W<'_>

Bit 21 - DMA1 clock enable during Sleep mode

pub fn dma2lpen(&mut self) -> DMA2LPEN_W<'_>

Bit 22 - DMA2 clock enable during Sleep mode

pub fn dma2dlpen(&mut self) -> DMA2DLPEN_W<'_>

Bit 23 - DMA2D clock enable during Sleep mode

pub fn ethmaclpen(&mut self) -> ETHMACLPEN_W<'_>

Bit 25 - Ethernet MAC clock enable during Sleep mode

pub fn ethmactxlpen(&mut self) -> ETHMACTXLPEN_W<'_>

Bit 26 - Ethernet transmission clock enable during Sleep mode

pub fn ethmacrxlpen(&mut self) -> ETHMACRXLPEN_W<'_>

Bit 27 - Ethernet reception clock enable during Sleep mode

pub fn ethmacptplpen(&mut self) -> ETHMACPTPLPEN_W<'_>

Bit 28 - Ethernet PTP clock enable during Sleep mode

pub fn otghslpen(&mut self) -> OTGHSLPEN_W<'_>

Bit 29 - USB OTG HS clock enable during Sleep mode

pub fn otghsulpilpen(&mut self) -> OTGHSULPILPEN_W<'_>

Bit 30 - USB OTG HS ULPI clock enable during Sleep mode

impl W<u32, Reg<u32, _AHB2LPENR>>

pub fn otgfslpen(&mut self) -> OTGFSLPEN_W<'_>

Bit 7 - USB OTG FS clock enable during Sleep mode

pub fn rnglpen(&mut self) -> RNGLPEN_W<'_>

Bit 6 - Random number generator clock enable during Sleep mode

pub fn hashlpen(&mut self) -> HASHLPEN_W<'_>

Bit 5 - Hash modules clock enable during Sleep mode

pub fn cryplpen(&mut self) -> CRYPLPEN_W<'_>

Bit 4 - Cryptography modules clock enable during Sleep mode

pub fn dcmilpen(&mut self) -> DCMILPEN_W<'_>

Bit 0 - Camera interface enable during Sleep mode

impl W<u32, Reg<u32, _AHB3LPENR>>

pub fn fmclpen(&mut self) -> FMCLPEN_W<'_>

Bit 0 - Flexible memory controller module clock enable during Sleep mode

pub fn qspilpen(&mut self) -> QSPILPEN_W<'_>

Bit 1 - QUADSPI memory controller module clock enable during Sleep mode

impl W<u32, Reg<u32, _APB1LPENR>>

pub fn tim2lpen(&mut self) -> TIM2LPEN_W<'_>

Bit 0 - TIM2 clock enable during Sleep mode

pub fn tim3lpen(&mut self) -> TIM3LPEN_W<'_>

Bit 1 - TIM3 clock enable during Sleep mode

pub fn tim4lpen(&mut self) -> TIM4LPEN_W<'_>

Bit 2 - TIM4 clock enable during Sleep mode

pub fn tim5lpen(&mut self) -> TIM5LPEN_W<'_>

Bit 3 - TIM5 clock enable during Sleep mode

pub fn tim6lpen(&mut self) -> TIM6LPEN_W<'_>

Bit 4 - TIM6 clock enable during Sleep mode

pub fn tim7lpen(&mut self) -> TIM7LPEN_W<'_>

Bit 5 - TIM7 clock enable during Sleep mode

pub fn tim12lpen(&mut self) -> TIM12LPEN_W<'_>

Bit 6 - TIM12 clock enable during Sleep mode

pub fn tim13lpen(&mut self) -> TIM13LPEN_W<'_>

Bit 7 - TIM13 clock enable during Sleep mode

pub fn tim14lpen(&mut self) -> TIM14LPEN_W<'_>

Bit 8 - TIM14 clock enable during Sleep mode

pub fn wwdglpen(&mut self) -> WWDGLPEN_W<'_>

Bit 11 - Window watchdog clock enable during Sleep mode

pub fn spi2lpen(&mut self) -> SPI2LPEN_W<'_>

Bit 14 - SPI2 clock enable during Sleep mode

pub fn spi3lpen(&mut self) -> SPI3LPEN_W<'_>

Bit 15 - SPI3 clock enable during Sleep mode

pub fn usart2lpen(&mut self) -> USART2LPEN_W<'_>

Bit 17 - USART2 clock enable during Sleep mode

pub fn usart3lpen(&mut self) -> USART3LPEN_W<'_>

Bit 18 - USART3 clock enable during Sleep mode

pub fn uart4lpen(&mut self) -> UART4LPEN_W<'_>

Bit 19 - UART4 clock enable during Sleep mode

pub fn uart5lpen(&mut self) -> UART5LPEN_W<'_>

Bit 20 - UART5 clock enable during Sleep mode

pub fn i2c1lpen(&mut self) -> I2C1LPEN_W<'_>

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2lpen(&mut self) -> I2C2LPEN_W<'_>

Bit 22 - I2C2 clock enable during Sleep mode

pub fn i2c3lpen(&mut self) -> I2C3LPEN_W<'_>

Bit 23 - I2C3 clock enable during Sleep mode

pub fn can1lpen(&mut self) -> CAN1LPEN_W<'_>

Bit 25 - CAN 1 clock enable during Sleep mode

pub fn can2lpen(&mut self) -> CAN2LPEN_W<'_>

Bit 26 - CAN 2 clock enable during Sleep mode

pub fn pwrlpen(&mut self) -> PWRLPEN_W<'_>

Bit 28 - Power interface clock enable during Sleep mode

pub fn daclpen(&mut self) -> DACLPEN_W<'_>

Bit 29 - DAC interface clock enable during Sleep mode

pub fn uart7lpen(&mut self) -> UART7LPEN_W<'_>

Bit 30 - UART7 clock enable during Sleep mode

pub fn uart8lpen(&mut self) -> UART8LPEN_W<'_>

Bit 31 - UART8 clock enable during Sleep mode

impl W<u32, Reg<u32, _APB2LPENR>>

pub fn tim1lpen(&mut self) -> TIM1LPEN_W<'_>

Bit 0 - TIM1 clock enable during Sleep mode

pub fn tim8lpen(&mut self) -> TIM8LPEN_W<'_>

Bit 1 - TIM8 clock enable during Sleep mode

pub fn usart1lpen(&mut self) -> USART1LPEN_W<'_>

Bit 4 - USART1 clock enable during Sleep mode

pub fn usart6lpen(&mut self) -> USART6LPEN_W<'_>

Bit 5 - USART6 clock enable during Sleep mode

pub fn adc1lpen(&mut self) -> ADC1LPEN_W<'_>

Bit 8 - ADC1 clock enable during Sleep mode

pub fn adc2lpen(&mut self) -> ADC2LPEN_W<'_>

Bit 9 - ADC2 clock enable during Sleep mode

pub fn adc3lpen(&mut self) -> ADC3LPEN_W<'_>

Bit 10 - ADC 3 clock enable during Sleep mode

pub fn sdiolpen(&mut self) -> SDIOLPEN_W<'_>

Bit 11 - SDIO clock enable during Sleep mode

pub fn spi1lpen(&mut self) -> SPI1LPEN_W<'_>

Bit 12 - SPI 1 clock enable during Sleep mode

pub fn spi4lpen(&mut self) -> SPI4LPEN_W<'_>

Bit 13 - SPI 4 clock enable during Sleep mode

pub fn syscfglpen(&mut self) -> SYSCFGLPEN_W<'_>

Bit 14 - System configuration controller clock enable during Sleep mode

pub fn tim9lpen(&mut self) -> TIM9LPEN_W<'_>

Bit 16 - TIM9 clock enable during sleep mode

pub fn tim10lpen(&mut self) -> TIM10LPEN_W<'_>

Bit 17 - TIM10 clock enable during Sleep mode

pub fn tim11lpen(&mut self) -> TIM11LPEN_W<'_>

Bit 18 - TIM11 clock enable during Sleep mode

pub fn spi5lpen(&mut self) -> SPI5LPEN_W<'_>

Bit 20 - SPI 5 clock enable during Sleep mode

pub fn spi6lpen(&mut self) -> SPI6LPEN_W<'_>

Bit 21 - SPI 6 clock enable during Sleep mode

pub fn sai1lpen(&mut self) -> SAI1LPEN_W<'_>

Bit 22 - SAI1 clock enable

pub fn ltdclpen(&mut self) -> LTDCLPEN_W<'_>

Bit 26 - LTDC clock enable

pub fn dsilpen(&mut self) -> DSILPEN_W<'_>

Bit 27 - DSI clocks enable during Sleep mode

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External low-speed oscillator enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External low-speed oscillator bypass

pub fn lsemod(&mut self) -> LSEMOD_W<'_>

Bit 3 - External low-speed oscillator mode

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

impl W<u32, Reg<u32, _CSR>>

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn wdgrstf(&mut self) -> WDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn padrstf(&mut self) -> PADRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn borrstf(&mut self) -> BORRSTF_W<'_>

Bit 25 - BOR reset flag

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low-speed oscillator enable

impl W<u32, Reg<u32, _SSCGR>>

pub fn sscgen(&mut self) -> SSCGEN_W<'_>

Bit 31 - Spread spectrum modulation enable

pub fn spreadsel(&mut self) -> SPREADSEL_W<'_>

Bit 30 - Spread Select

pub fn incstep(&mut self) -> INCSTEP_W<'_>

Bits 13:27 - Incrementation step

pub fn modper(&mut self) -> MODPER_W<'_>

Bits 0:12 - Modulation period

impl W<u32, Reg<u32, _PLLI2SCFGR>>

pub fn plli2sr(&mut self) -> PLLI2SR_W<'_>

Bits 28:30 - PLLI2S division factor for I2S clocks

pub fn plli2sq(&mut self) -> PLLI2SQ_W<'_>

Bits 24:27 - PLLI2S division factor for SAI1 clock

pub fn plli2sn(&mut self) -> PLLI2SN_W<'_>

Bits 6:14 - PLLI2S multiplication factor for VCO

impl W<u32, Reg<u32, _PLLSAICFGR>>

pub fn pllsain(&mut self) -> PLLSAIN_W<'_>

Bits 6:14 - PLLSAI division factor for VCO

pub fn pllsaip(&mut self) -> PLLSAIP_W<'_>

Bits 16:17 - PLLSAI division factor for 48 MHz clock

pub fn pllsaiq(&mut self) -> PLLSAIQ_W<'_>

Bits 24:27 - PLLSAI division factor for SAI1 clock

pub fn pllsair(&mut self) -> PLLSAIR_W<'_>

Bits 28:30 - PLLSAI division factor for LCD clock

impl W<u32, Reg<u32, _DCKCFGR>>

pub fn plli2sdivq(&mut self) -> PLLI2SDIVQ_W<'_>

Bits 0:4 - PLLI2S division factor for SAIs clock

pub fn pllsaidivq(&mut self) -> PLLSAIDIVQ_W<'_>

Bits 8:12 - PLLSAI division factor for SAIs clock

pub fn pllsaidivr(&mut self) -> PLLSAIDIVR_W<'_>

Bits 16:17 - PLLSAIDIVR

pub fn sai1asrc(&mut self) -> SAI1ASRC_W<'_>

Bits 20:21 - SAI1 clock source selection

pub fn sai1bsrc(&mut self) -> SAI1BSRC_W<'_>

Bits 22:23 - SAI1-B clock source selection

pub fn timpre(&mut self) -> TIMPRE_W<'_>

Bit 24 - Timers clocks prescalers selection

pub fn ck48msel(&mut self) -> CK48MSEL_W<'_>

Bit 27 - 48 MHz clock source selection

pub fn sdiosel(&mut self) -> SDIOSEL_W<'_>

Bit 28 - SDIO clock source selection

pub fn dsisel(&mut self) -> DSISEL_W<'_>

Bit 29 - DSI clock source selection

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MEMRM>>

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:2 - Memory mapping selection

pub fn fb_mode(&mut self) -> FB_MODE_W<'_>

Bit 8 - Flash bank mode selection

pub fn swp_fmc(&mut self) -> SWP_FMC_W<'_>

Bits 10:11 - FMC memory mapping swap

impl W<u32, Reg<u32, _PMC>>

pub fn mii_rmii_sel(&mut self) -> MII_RMII_SEL_W<'_>

Bit 23 - Ethernet PHY interface selection

pub fn adc1dc2(&mut self) -> ADC1DC2_W<'_>

Bit 16 - ADC1DC2

pub fn adc2dc2(&mut self) -> ADC2DC2_W<'_>

Bit 17 - ADC2DC2

pub fn adc3dc2(&mut self) -> ADC3DC2_W<'_>

Bit 18 - ADC3DC2

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI x configuration (x = 0 to 3)

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI x configuration (x = 0 to 3)

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI x configuration (x = 0 to 3)

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI x configuration (x = 0 to 3)

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI x configuration (x = 4 to 7)

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI x configuration (x = 4 to 7)

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI x configuration (x = 4 to 7)

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI x configuration (x = 4 to 7)

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI x configuration (x = 8 to 11)

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI10

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI x configuration (x = 8 to 11)

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI x configuration (x = 8 to 11)

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI x configuration (x = 12 to 15)

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI x configuration (x = 12 to 15)

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI x configuration (x = 12 to 15)

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI x configuration (x = 12 to 15)

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

impl W<u32, Reg<u32, _I2SPR>>

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _POWER>>

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>

Bit 14 - HW Flow Control enable

pub fn negedge(&mut self) -> NEGEDGE_W<'_>

Bit 13 - SDIO_CK dephasing selection bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>

Bits 11:12 - Wide bus mode enable bit

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 10 - Clock divider bypass enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>

Bit 9 - Power saving configuration bit

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 8 - Clock enable bit

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 0:7 - Clock divide factor

impl W<u32, Reg<u32, _ARG>>

pub fn cmdarg(&mut self) -> CMDARG_W<'_>

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>

pub fn ce_atacmd(&mut self) -> CE_ATACMD_W<'_>

Bit 14 - CE-ATA command

pub fn n_ien(&mut self) -> NIEN_W<'_>

Bit 13 - not Interrupt Enable

pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W<'_>

Bit 12 - Enable CMD completion

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>

Bit 11 - SD I/O suspend command

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>

Bit 10 - Command path state machine (CPSM) Enable bit

pub fn waitpend(&mut self) -> WAITPEND_W<'_>

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).

pub fn waitint(&mut self) -> WAITINT_W<'_>

Bit 8 - CPSM waits for interrupt request

pub fn waitresp(&mut self) -> WAITRESP_W<'_>

Bits 6:7 - Wait for response bits

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>

Bits 0:5 - Command index

impl W<u32, Reg<u32, _DTIMER>>

pub fn datatime(&mut self) -> DATATIME_W<'_>

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>

pub fn datalength(&mut self) -> DATALENGTH_W<'_>

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SD I/O enable functions

pub fn rwmod(&mut self) -> RWMOD_W<'_>

Bit 10 - Read wait mode

pub fn rwstop(&mut self) -> RWSTOP_W<'_>

Bit 9 - Read wait stop

pub fn rwstart(&mut self) -> RWSTART_W<'_>

Bit 8 - Read wait start

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>

Bits 4:7 - Data block size

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 3 - DMA enable bit

pub fn dtmode(&mut self) -> DTMODE_W<'_>

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

pub fn dtdir(&mut self) -> DTDIR_W<'_>

Bit 1 - Data transfer direction selection

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTEN

impl W<u32, Reg<u32, _ICR>>

pub fn ceataendc(&mut self) -> CEATAENDC_W<'_>

Bit 23 - CEATAEND flag clear bit

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>

Bit 22 - SDIOIT flag clear bit

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>

Bit 10 - DBCKEND flag clear bit

pub fn stbiterrc(&mut self) -> STBITERRC_W<'_>

Bit 9 - STBITERR flag clear bit

pub fn dataendc(&mut self) -> DATAENDC_W<'_>

Bit 8 - DATAEND flag clear bit

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>

Bit 7 - CMDSENT flag clear bit

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>

Bit 6 - CMDREND flag clear bit

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>

Bit 5 - RXOVERR flag clear bit

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>

Bit 4 - TXUNDERR flag clear bit

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>

Bit 3 - DTIMEOUT flag clear bit

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>

Bit 2 - CTIMEOUT flag clear bit

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>

Bit 1 - DCRCFAIL flag clear bit

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>

Bit 0 - CCRCFAIL flag clear bit

impl W<u32, Reg<u32, _MASK>>

pub fn ceataendie(&mut self) -> CEATAENDIE_W<'_>

Bit 23 - CE-ATA command completion signal received interrupt enable

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>

Bit 22 - SDIO mode interrupt received interrupt enable

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>

Bit 21 - Data available in Rx FIFO interrupt enable

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>

Bit 20 - Data available in Tx FIFO interrupt enable

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>

Bit 19 - Rx FIFO empty interrupt enable

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>

Bit 18 - Tx FIFO empty interrupt enable

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>

Bit 17 - Rx FIFO full interrupt enable

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>

Bit 16 - Tx FIFO full interrupt enable

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>

Bit 15 - Rx FIFO half full interrupt enable

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>

Bit 14 - Tx FIFO half empty interrupt enable

pub fn rxactie(&mut self) -> RXACTIE_W<'_>

Bit 13 - Data receive acting interrupt enable

pub fn txactie(&mut self) -> TXACTIE_W<'_>

Bit 12 - Data transmit acting interrupt enable

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>

Bit 11 - Command acting interrupt enable

pub fn dbckendie(&mut self) -> DBCKENDIE_W<'_>

Bit 10 - Data block end interrupt enable

pub fn stbiterrie(&mut self) -> STBITERRIE_W<'_>

Bit 9 - Start bit error interrupt enable

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>

Bit 8 - Data end interrupt enable

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>

Bit 7 - Command sent interrupt enable

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>

Bit 6 - Command response received interrupt enable

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>

Bit 5 - Rx FIFO overrun error interrupt enable

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>

Bit 4 - Tx FIFO underrun error interrupt enable

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>

Bit 3 - Data timeout interrupt enable

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>

Bit 2 - Command timeout interrupt enable

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>

Bit 1 - Data CRC fail interrupt enable

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>

Bit 0 - Command CRC fail interrupt enable

impl W<u32, Reg<u32, _FIFO>>

pub fn fifodata(&mut self) -> FIFODATA_W<'_>

Bits 0:31 - Receive and transmit FIFO data

impl W<u32, Reg<u32, _SR>>

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 5 - Overrun

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 26 - Overrun interrupt enable

pub fn res(&mut self) -> RES_W<'_>

Bits 24:25 - Resolution

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 30 - Start conversion of regular channels

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 28:29 - External trigger enable for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 24:27 - External event select for regular group

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 22 - Start conversion of injected channels

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 20:21 - External trigger enable for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 16:19 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn eocs(&mut self) -> EOCS_W<'_>

Bit 10 - End of conversion selection

pub fn dds(&mut self) -> DDS_W<'_>

Bit 9 - DMA disable selection (for single ADC mode)

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode (for single ADC mode)

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D Converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp18(&mut self) -> SMP18_W<'_>

Bits 24:26 - Channel 18 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sampling time selection

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sampling time selection

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sampling time selection

impl W<u32, Reg<u32, _JOFR>>

pub fn joffset(&mut self) -> JOFFSET_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _SR>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 9 - CTS flag

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - Data value

impl W<u32, Reg<u32, _BRR>>

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - mantissa of USARTDIV

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - fraction of USARTDIV

impl W<u32, Reg<u32, _CR1>>

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

impl W<u32, Reg<u32, _CR2>>

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _CR>>

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn boff2(&mut self) -> BOFF2_W<'_>

Bit 17 - DAC channel2 output buffer disable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit left-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

impl W<u32, Reg<u32, _CR>>

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low-power deep sleep

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power down deepsleep

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear wakeup flag

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear standby flag

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power voltage detector enable

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD level selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn fpds(&mut self) -> FPDS_W<'_>

Bit 9 - Flash power down in Stop mode

pub fn lplvds(&mut self) -> LPLVDS_W<'_>

Bit 10 - Low-Power Regulator Low Voltage in deepsleep

pub fn mrlvds(&mut self) -> MRLVDS_W<'_>

Bit 11 - Main regulator low voltage in deepsleep mode

pub fn vos(&mut self) -> VOS_W<'_>

Bits 14:15 - Regulator voltage scaling output selection

pub fn oden(&mut self) -> ODEN_W<'_>

Bit 16 - Over-drive enable

pub fn odswen(&mut self) -> ODSWEN_W<'_>

Bit 17 - Over-drive switching enabled

pub fn uden(&mut self) -> UDEN_W<'_>

Bits 18:19 - Under-drive enable in stop mode

impl W<u32, Reg<u32, _CSR>>

pub fn ewup(&mut self) -> EWUP_W<'_>

Bit 8 - Enable WKUP pin

pub fn bre(&mut self) -> BRE_W<'_>

Bit 9 - Backup regulator enable

pub fn vosrdy(&mut self) -> VOSRDY_W<'_>

Bit 14 - Regulator voltage scaling output selection ready bit

pub fn udrdy(&mut self) -> UDRDY_W<'_>

Bits 18:19 - Under-drive ready flag

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value (write only, read 0000h)

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - Calibration output enable

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - Output selection

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - Output polarity

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - Backup

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - Subtract 1 hour (winter time change)

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - Add 1 hour (summer time change)

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - Time-stamp interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - Wakeup timer interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - Alarm B interrupt enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - Alarm A interrupt enable

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - Time stamp enable

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - Wakeup timer enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - Alarm B enable

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - Alarm A enable

pub fn dce(&mut self) -> DCE_W<'_>

Bit 7 - Coarse digital calibration enable

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - Hour format

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - Time-stamp event active edge

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - Wakeup clock selection

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - Bypass the shadow registers

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - Calibration output selection

impl W<u32, Reg<u32, _ISR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

pub fn alraf(&mut self) -> ALRAF_W<'_>

Bit 8 - Alarm A flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>

Bit 9 - Alarm B flag

pub fn wutf(&mut self) -> WUTF_W<'_>

Bit 10 - Wakeup timer flag

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 11 - Time-stamp flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>

Bit 12 - Time-stamp overflow flag

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>

Bit 13 - Tamper detection flag

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>

Bit 14 - TAMPER2 detection flag

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _CALIBR>>

pub fn dcs(&mut self) -> DCS_W<'_>

Bit 7 - Digital calibration sign

pub fn dc(&mut self) -> DC_W<'_>

Bits 0:4 - Digital calibration

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAFCR>>

pub fn alarmouttype(&mut self) -> ALARMOUTTYPE_W<'_>

Bit 18 - AFO_ALARM output type

pub fn tsinsel(&mut self) -> TSINSEL_W<'_>

Bit 17 - TIMESTAMP mapping

pub fn tamp1insel(&mut self) -> TAMP1INSEL_W<'_>

Bit 16 - TAMPER1 mapping

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 15 - TAMPER pull-up disable

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 13:14 - Tamper precharge duration

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 11:12 - Tamper filter count

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 8:10 - Tamper sampling frequency

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 7 - Activate timestamp on tamper detection event

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 4 - Active level for tamper 2

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 3 - Tamper 2 detection enable

pub fn tampie(&mut self) -> TAMPIE_W<'_>

Bit 2 - Tamper interrupt enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 1 - Active level for tamper 1

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - Tamper 1 detection enable

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _BKPR>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _SR>>

pub fn lbd(&mut self) -> LBD_W<'_>

Bit 8 - LIN break detection flag

pub fn tc(&mut self) -> TC_W<'_>

Bit 6 - Transmission complete

pub fn rxne(&mut self) -> RXNE_W<'_>

Bit 5 - Read data register not empty

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:8 - Data value

impl W<u32, Reg<u32, _BRR>>

pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<'_>

Bits 4:15 - mantissa of USARTDIV

pub fn div_fraction(&mut self) -> DIV_FRACTION_W<'_>

Bits 0:3 - fraction of USARTDIV

impl W<u32, Reg<u32, _CR1>>

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 13 - USART enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - TXE interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn rwu(&mut self) -> RWU_W<'_>

Bit 1 - Receiver wakeup

pub fn sbk(&mut self) -> SBK_W<'_>

Bit 0 - Send break

impl W<u32, Reg<u32, _CR2>>

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - lin break detection length

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:3 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _CCR>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn vbate(&mut self) -> VBATE_W<'_>

Bit 22 - VBAT enable

pub fn adcpre(&mut self) -> ADCPRE_W<'_>

Bits 16:17 - ADC prescaler

pub fn dma(&mut self) -> DMA_W<'_>

Bits 14:15 - Direct memory access mode for multi ADC mode

pub fn dds(&mut self) -> DDS_W<'_>

Bit 13 - DMA disable selection for multi-ADC mode

pub fn delay(&mut self) -> DELAY_W<'_>

Bits 8:11 - Delay between 2 sampling phases

pub fn multi(&mut self) -> MULTI_W<'_>

Bits 0:4 - Multi ADC mode selection

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn itr1_rmp(&mut self) -> ITR1_RMP_W<'_>

Bits 10:11 - Timer Input 4 remap

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn it4_rmp(&mut self) -> IT4_RMP_W<'_>

Bits 6:7 - Timer Input 4 remap

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:14 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:6 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _OR>>

pub fn rmp(&mut self) -> RMP_W<'_>

Bits 0:1 - Input 1 remapping capability

impl W<u32, Reg<u32, _CR1>>

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _MACCR>>

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn dc(&mut self) -> DC_W<'_>

Bit 4 - Deferral check

pub fn bl(&mut self) -> BL_W<'_>

Bits 5:6 - Back-off limit

pub fn apcs(&mut self) -> APCS_W<'_>

Bit 7 - Automatic pad/CRC stripping

pub fn rd(&mut self) -> RD_W<'_>

Bit 9 - Retry disable

pub fn ipco(&mut self) -> IPCO_W<'_>

Bit 10 - IPv4 checksum offload

pub fn dm(&mut self) -> DM_W<'_>

Bit 11 - Duplex mode

pub fn lm(&mut self) -> LM_W<'_>

Bit 12 - Loopback mode

pub fn rod(&mut self) -> ROD_W<'_>

Bit 13 - Receive own disable

pub fn fes(&mut self) -> FES_W<'_>

Bit 14 - Fast Ethernet speed

pub fn csd(&mut self) -> CSD_W<'_>

Bit 16 - Carrier sense disable

pub fn ifg(&mut self) -> IFG_W<'_>

Bits 17:19 - Interframe gap

pub fn jd(&mut self) -> JD_W<'_>

Bit 22 - Jabber disable

pub fn wd(&mut self) -> WD_W<'_>

Bit 23 - Watchdog disable

pub fn cstf(&mut self) -> CSTF_W<'_>

Bit 25 - CRC stripping for type frames

impl W<u32, Reg<u32, _MACFFR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 0 - Promiscuous mode

pub fn hu(&mut self) -> HU_W<'_>

Bit 1 - Hash unicast

pub fn hm(&mut self) -> HM_W<'_>

Bit 2 - Hash multicast

pub fn daif(&mut self) -> DAIF_W<'_>

Bit 3 - Destination address unique filtering

pub fn pam(&mut self) -> PAM_W<'_>

Bit 4 - Pass all multicast

pub fn bfd(&mut self) -> BFD_W<'_>

Bit 5 - Broadcast frames disable

pub fn pcf(&mut self) -> PCF_W<'_>

Bits 6:7 - Pass control frames

pub fn saif(&mut self) -> SAIF_W<'_>

Bit 7 - Source address inverse filtering

pub fn saf(&mut self) -> SAF_W<'_>

Bit 8 - Source address filter

pub fn hpf(&mut self) -> HPF_W<'_>

Bit 9 - Hash or perfect filter

pub fn ra(&mut self) -> RA_W<'_>

Bit 31 - Receive all

impl W<u32, Reg<u32, _MACHTHR>>

pub fn hth(&mut self) -> HTH_W<'_>

Bits 0:31 - Upper 32 bits of hash table

impl W<u32, Reg<u32, _MACHTLR>>

pub fn htl(&mut self) -> HTL_W<'_>

Bits 0:31 - Lower 32 bits of hash table

impl W<u32, Reg<u32, _MACMIIAR>>

pub fn mb(&mut self) -> MB_W<'_>

Bit 0 - MII busy

pub fn mw(&mut self) -> MW_W<'_>

Bit 1 - MII write

pub fn cr(&mut self) -> CR_W<'_>

Bits 2:4 - Clock range

pub fn mr(&mut self) -> MR_W<'_>

Bits 6:10 - MII register - select the desired MII register in the PHY device

pub fn pa(&mut self) -> PA_W<'_>

Bits 11:15 - PHY address - select which of possible 32 PHYs is being accessed

impl W<u32, Reg<u32, _MACMIIDR>>

pub fn md(&mut self) -> MD_W<'_>

Bits 0:15 - MII data read from/written to the PHY

impl W<u32, Reg<u32, _MACFCR>>

pub fn fcb(&mut self) -> FCB_W<'_>

Bit 0 - Flow control busy/back pressure activate

pub fn tfce(&mut self) -> TFCE_W<'_>

Bit 1 - Transmit flow control enable

pub fn rfce(&mut self) -> RFCE_W<'_>

Bit 2 - Receive flow control enable

pub fn upfd(&mut self) -> UPFD_W<'_>

Bit 3 - Unicast pause frame detect

pub fn plt(&mut self) -> PLT_W<'_>

Bits 4:5 - Pause low threshold

pub fn zqpd(&mut self) -> ZQPD_W<'_>

Bit 7 - Zero-quanta pause disable

pub fn pt(&mut self) -> PT_W<'_>

Bits 16:31 - Pause time

impl W<u32, Reg<u32, _MACVLANTR>>

pub fn vlanti(&mut self) -> VLANTI_W<'_>

Bits 0:15 - VLAN tag identifier (for receive frames)

pub fn vlantc(&mut self) -> VLANTC_W<'_>

Bit 16 - 12-bit VLAN tag comparison

impl W<u32, Reg<u32, _MACPMTCSR>>

pub fn pd(&mut self) -> PD_W<'_>

Bit 0 - Power down

pub fn mpe(&mut self) -> MPE_W<'_>

Bit 1 - Magic packet enable

pub fn wfe(&mut self) -> WFE_W<'_>

Bit 2 - Wakeup frame enable

pub fn mpr(&mut self) -> MPR_W<'_>

Bit 5 - Magic packet received

pub fn wfr(&mut self) -> WFR_W<'_>

Bit 6 - Wakeup frame received

pub fn gu(&mut self) -> GU_W<'_>

Bit 9 - Global unicast

pub fn wffrpr(&mut self) -> WFFRPR_W<'_>

Bit 31 - Wakeup frame filter register pointer reset

impl W<u32, Reg<u32, _MACSR>>

pub fn tsts(&mut self) -> TSTS_W<'_>

Bit 9 - Time stamp trigger status

impl W<u32, Reg<u32, _MACIMR>>

pub fn pmtim(&mut self) -> PMTIM_W<'_>

Bit 3 - PMT interrupt mask

pub fn tstim(&mut self) -> TSTIM_W<'_>

Bit 9 - Time stamp trigger interrupt mask

impl W<u32, Reg<u32, _MACA0HR>>

pub fn maca0h(&mut self) -> MACA0H_W<'_>

Bits 0:15 - MAC address0 high

impl W<u32, Reg<u32, _MACA0LR>>

pub fn maca0l(&mut self) -> MACA0L_W<'_>

Bits 0:31 - 0

impl W<u32, Reg<u32, _MACA1HR>>

pub fn maca1h(&mut self) -> MACA1H_W<'_>

Bits 0:15 - MACA1H

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - MBC

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - SA

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - AE

impl W<u32, Reg<u32, _MACA1LR>>

pub fn maca1l(&mut self) -> MACA1L_W<'_>

Bits 0:31 - MACA1LR

impl W<u32, Reg<u32, _MACA2HR>>

pub fn maca2h(&mut self) -> MACA2H_W<'_>

Bits 0:15 - MAC2AH

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - MBC

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - SA

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - AE

impl W<u32, Reg<u32, _MACA2LR>>

pub fn maca2l(&mut self) -> MACA2L_W<'_>

Bits 0:31 - MACA2L

impl W<u32, Reg<u32, _MACA3HR>>

pub fn maca3h(&mut self) -> MACA3H_W<'_>

Bits 0:15 - MACA3H

pub fn mbc(&mut self) -> MBC_W<'_>

Bits 24:29 - MBC

pub fn sa(&mut self) -> SA_W<'_>

Bit 30 - SA

pub fn ae(&mut self) -> AE_W<'_>

Bit 31 - AE

impl W<u32, Reg<u32, _MACA3LR>>

pub fn maca3l(&mut self) -> MACA3L_W<'_>

Bits 0:31 - MBCA3L

impl W<u32, Reg<u32, _MMCCR>>

pub fn cr(&mut self) -> CR_W<'_>

Bit 0 - Counter reset

pub fn csr(&mut self) -> CSR_W<'_>

Bit 1 - Counter stop rollover

pub fn ror(&mut self) -> ROR_W<'_>

Bit 2 - Reset on read

pub fn mcf(&mut self) -> MCF_W<'_>

Bit 3 - MMC counter freeze

pub fn mcp(&mut self) -> MCP_W<'_>

Bit 4 - MMC counter preset

pub fn mcfhp(&mut self) -> MCFHP_W<'_>

Bit 5 - MMC counter Full-Half preset

impl W<u32, Reg<u32, _MMCRIR>>

pub fn rfces(&mut self) -> RFCES_W<'_>

Bit 5 - Received frames CRC error status

pub fn rfaes(&mut self) -> RFAES_W<'_>

Bit 6 - Received frames alignment error status

pub fn rgufs(&mut self) -> RGUFS_W<'_>

Bit 17 - Received good Unicast frames status

impl W<u32, Reg<u32, _MMCRIMR>>

pub fn rfcem(&mut self) -> RFCEM_W<'_>

Bit 5 - Received frame CRC error mask

pub fn rfaem(&mut self) -> RFAEM_W<'_>

Bit 6 - Received frames alignment error mask

pub fn rgufm(&mut self) -> RGUFM_W<'_>

Bit 17 - Received good Unicast frames mask

impl W<u32, Reg<u32, _MMCTIMR>>

pub fn tgfscm(&mut self) -> TGFSCM_W<'_>

Bit 14 - Transmitted good frames single collision mask

pub fn tgfmscm(&mut self) -> TGFMSCM_W<'_>

Bit 15 - Transmitted good frames more than single collision mask

pub fn tgfm(&mut self) -> TGFM_W<'_>

Bit 16 - Transmitted good frames mask

impl W<u32, Reg<u32, _PTPTSCR>>

pub fn tse(&mut self) -> TSE_W<'_>

Bit 0 - TSE

pub fn tsfcu(&mut self) -> TSFCU_W<'_>

Bit 1 - TSFCU

pub fn tsptppsv2e(&mut self) -> TSPTPPSV2E_W<'_>

Bit 10 - TSPTPPSV2E

pub fn tssptpoefe(&mut self) -> TSSPTPOEFE_W<'_>

Bit 11 - TSSPTPOEFE

pub fn tssipv6fe(&mut self) -> TSSIPV6FE_W<'_>

Bit 12 - TSSIPV6FE

pub fn tssipv4fe(&mut self) -> TSSIPV4FE_W<'_>

Bit 13 - TSSIPV4FE

pub fn tsseme(&mut self) -> TSSEME_W<'_>

Bit 14 - TSSEME

pub fn tssmrme(&mut self) -> TSSMRME_W<'_>

Bit 15 - TSSMRME

pub fn tscnt(&mut self) -> TSCNT_W<'_>

Bits 16:17 - TSCNT

pub fn tspffmae(&mut self) -> TSPFFMAE_W<'_>

Bit 18 - TSPFFMAE

pub fn tssti(&mut self) -> TSSTI_W<'_>

Bit 2 - TSSTI

pub fn tsstu(&mut self) -> TSSTU_W<'_>

Bit 3 - TSSTU

pub fn tsite(&mut self) -> TSITE_W<'_>

Bit 4 - TSITE

pub fn ttsaru(&mut self) -> TTSARU_W<'_>

Bit 5 - TTSARU

pub fn tssarfe(&mut self) -> TSSARFE_W<'_>

Bit 8 - TSSARFE

pub fn tsssr(&mut self) -> TSSSR_W<'_>

Bit 9 - TSSSR

impl W<u32, Reg<u32, _PTPSSIR>>

pub fn stssi(&mut self) -> STSSI_W<'_>

Bits 0:7 - STSSI

impl W<u32, Reg<u32, _PTPTSHUR>>

pub fn tsus(&mut self) -> TSUS_W<'_>

Bits 0:31 - TSUS

impl W<u32, Reg<u32, _PTPTSLUR>>

pub fn tsuss(&mut self) -> TSUSS_W<'_>

Bits 0:30 - TSUSS

pub fn tsupns(&mut self) -> TSUPNS_W<'_>

Bit 31 - TSUPNS

impl W<u32, Reg<u32, _PTPTSAR>>

pub fn tsa(&mut self) -> TSA_W<'_>

Bits 0:31 - TSA

impl W<u32, Reg<u32, _PTPTTHR>>

pub fn ttsh(&mut self) -> TTSH_W<'_>

Bits 0:31 - 0

impl W<u32, Reg<u32, _PTPTTLR>>

pub fn ttsl(&mut self) -> TTSL_W<'_>

Bits 0:31 - TTSL

impl W<u32, Reg<u32, _DMABMR>>

pub fn sr(&mut self) -> SR_W<'_>

Bit 0 - Software reset

pub fn da(&mut self) -> DA_W<'_>

Bit 1 - DMA arbitration

pub fn dsl(&mut self) -> DSL_W<'_>

Bits 2:6 - Descriptor skip length

pub fn edfe(&mut self) -> EDFE_W<'_>

Bit 7 - Enhanced descriptor format enable

pub fn pbl(&mut self) -> PBL_W<'_>

Bits 8:13 - Programmable burst length

pub fn pm(&mut self) -> PM_W<'_>

Bits 14:15 - Rx-Tx priority ratio

pub fn fb(&mut self) -> FB_W<'_>

Bit 16 - Fixed burst

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 17:22 - Rx DMA PBL

pub fn usp(&mut self) -> USP_W<'_>

Bit 23 - Use separate PBL

pub fn fpm(&mut self) -> FPM_W<'_>

Bit 24 - 4xPBL mode

pub fn aab(&mut self) -> AAB_W<'_>

Bit 25 - Address-aligned beats

pub fn mb(&mut self) -> MB_W<'_>

Bit 26 - Mixed burst

impl W<u32, Reg<u32, _DMATPDR>>

pub fn tpd(&mut self) -> TPD_W<'_>

Bits 0:31 - Transmit poll demand

impl W<u32, Reg<u32, _DMARPDR>>

pub fn rpd(&mut self) -> RPD_W<'_>

Bits 0:31 - Receive poll demand

impl W<u32, Reg<u32, _DMARDLAR>>

pub fn srl(&mut self) -> SRL_W<'_>

Bits 0:31 - Start of receive list

impl W<u32, Reg<u32, _DMATDLAR>>

pub fn stl(&mut self) -> STL_W<'_>

Bits 0:31 - Start of transmit list

impl W<u32, Reg<u32, _DMASR>>

pub fn ts(&mut self) -> TS_W<'_>

Bit 0 - Transmit status

pub fn tpss(&mut self) -> TPSS_W<'_>

Bit 1 - Transmit process stopped status

pub fn tbus(&mut self) -> TBUS_W<'_>

Bit 2 - Transmit buffer unavailable status

pub fn tjts(&mut self) -> TJTS_W<'_>

Bit 3 - Transmit jabber timeout status

pub fn ros(&mut self) -> ROS_W<'_>

Bit 4 - Receive overflow status

pub fn tus(&mut self) -> TUS_W<'_>

Bit 5 - Transmit underflow status

pub fn rs(&mut self) -> RS_W<'_>

Bit 6 - Receive status

pub fn rbus(&mut self) -> RBUS_W<'_>

Bit 7 - Receive buffer unavailable status

pub fn rpss(&mut self) -> RPSS_W<'_>

Bit 8 - Receive process stopped status

pub fn pwts(&mut self) -> PWTS_W<'_>

Bit 9 - PWTS

pub fn ets(&mut self) -> ETS_W<'_>

Bit 10 - Early transmit status

pub fn fbes(&mut self) -> FBES_W<'_>

Bit 13 - Fatal bus error status

pub fn ers(&mut self) -> ERS_W<'_>

Bit 14 - Early receive status

pub fn ais(&mut self) -> AIS_W<'_>

Bit 15 - Abnormal interrupt summary

pub fn nis(&mut self) -> NIS_W<'_>

Bit 16 - Normal interrupt summary

impl W<u32, Reg<u32, _DMAOMR>>

pub fn sr(&mut self) -> SR_W<'_>

Bit 1 - Start/stop receive

pub fn osf(&mut self) -> OSF_W<'_>

Bit 2 - Operate on second frame

pub fn rtc(&mut self) -> RTC_W<'_>

Bits 3:4 - Receive threshold control

pub fn fugf(&mut self) -> FUGF_W<'_>

Bit 6 - Forward undersized good frames

pub fn fef(&mut self) -> FEF_W<'_>

Bit 7 - Forward error frames

pub fn st(&mut self) -> ST_W<'_>

Bit 13 - Start/stop transmission

pub fn ttc(&mut self) -> TTC_W<'_>

Bits 14:16 - Transmit threshold control

pub fn ftf(&mut self) -> FTF_W<'_>

Bit 20 - Flush transmit FIFO

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 21 - Transmit store and forward

pub fn dfrf(&mut self) -> DFRF_W<'_>

Bit 24 - Disable flushing of received frames

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 25 - Receive store and forward

pub fn dtcefd(&mut self) -> DTCEFD_W<'_>

Bit 26 - Dropping of TCP/IP checksum error frames disable

impl W<u32, Reg<u32, _DMAIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 0 - Transmit interrupt enable

pub fn tpsie(&mut self) -> TPSIE_W<'_>

Bit 1 - Transmit process stopped interrupt enable

pub fn tbuie(&mut self) -> TBUIE_W<'_>

Bit 2 - Transmit buffer unavailable interrupt enable

pub fn tjtie(&mut self) -> TJTIE_W<'_>

Bit 3 - Transmit jabber timeout interrupt enable

pub fn roie(&mut self) -> ROIE_W<'_>

Bit 4 - Receive overflow interrupt enable

pub fn tuie(&mut self) -> TUIE_W<'_>

Bit 5 - Transmit underflow interrupt enable

pub fn rie(&mut self) -> RIE_W<'_>

Bit 6 - Receive interrupt enable

pub fn rbuie(&mut self) -> RBUIE_W<'_>

Bit 7 - Receive buffer unavailable interrupt enable

pub fn rpsie(&mut self) -> RPSIE_W<'_>

Bit 8 - Receive process stopped interrupt enable

pub fn rwtie(&mut self) -> RWTIE_W<'_>

Bit 9 - Receive watchdog timeout interrupt enable

pub fn etie(&mut self) -> ETIE_W<'_>

Bit 10 - Early transmit interrupt enable

pub fn fbeie(&mut self) -> FBEIE_W<'_>

Bit 13 - Fatal bus error interrupt enable

pub fn erie(&mut self) -> ERIE_W<'_>

Bit 14 - Early receive interrupt enable

pub fn aise(&mut self) -> AISE_W<'_>

Bit 15 - Abnormal interrupt summary enable

pub fn nise(&mut self) -> NISE_W<'_>

Bit 16 - Normal interrupt summary enable

impl W<u32, Reg<u32, _DMAMFBOCR>>

pub fn mfc(&mut self) -> MFC_W<'_>

Bits 0:15 - Missed frames by the controller

pub fn omfc(&mut self) -> OMFC_W<'_>

Bit 16 - Overflow bit for missed frame counter

pub fn mfa(&mut self) -> MFA_W<'_>

Bits 17:27 - Missed frames by the application

pub fn ofoc(&mut self) -> OFOC_W<'_>

Bit 28 - Overflow bit for FIFO overflow counter

impl W<u32, Reg<u32, _DMARSWTR>>

pub fn rswtc(&mut self) -> RSWTC_W<'_>

Bits 0:7 - Receive status watchdog timer count

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data Register

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - Independent Data register

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - Control regidter

impl W<u32, Reg<u32, _GOTGCTL>>

pub fn srq(&mut self) -> SRQ_W<'_>

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>

Bit 11 - Device HNP enabled

impl W<u32, Reg<u32, _GOTGINT>>

pub fn sedet(&mut self) -> SEDET_W<'_>

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>

Bit 19 - Debounce done

impl W<u32, Reg<u32, _GAHBCFG>>

pub fn gint(&mut self) -> GINT_W<'_>

Bit 0 - Global interrupt mask

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _GUSBCFG>>

pub fn tocal(&mut self) -> TOCAL_W<'_>

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>

Bit 6 - Full Speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>

Bits 10:13 - USB turnaround time

pub fn fhmod(&mut self) -> FHMOD_W<'_>

Bit 29 - Force host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>

Bit 30 - Force device mode

pub fn ctxpkt(&mut self) -> CTXPKT_W<'_>

Bit 31 - Corrupt Tx packet

impl W<u32, Reg<u32, _GRSTCTL>>

pub fn csrst(&mut self) -> CSRST_W<'_>

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _GINTSTS>>

pub fn mmis(&mut self) -> MMIS_W<'_>

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>

Bit 20 - Incomplete isochronous IN transfer

pub fn ipxfr_incompisoout(&mut self) -> IPXFR_INCOMPISOOUT_W<'_>

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>

Bit 30 - Session request/new session detected interrupt

pub fn wkupint(&mut self) -> WKUPINT_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _GINTMSK>>

pub fn mmism(&mut self) -> MMISM_W<'_>

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>

Bit 4 - Receive FIFO non-empty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>

Bit 5 - Non-periodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>

Bit 6 - Global non-periodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>

Bit 15 - End of periodic frame interrupt mask

pub fn epmism(&mut self) -> EPMISM_W<'_>

Bit 17 - Endpoint mismatch interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>

Bit 20 - Incomplete isochronous IN transfer mask

pub fn ipxfrm_iisooxfrm(&mut self) -> IPXFRM_IISOOXFRM_W<'_>

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

pub fn hcim(&mut self) -> HCIM_W<'_>

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt mask

impl W<u32, Reg<u32, _GRXFSIZ>>

pub fn rxfd(&mut self) -> RXFD_W<'_>

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _GNPTXFSIZ_DEVICE>>

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _GNPTXFSIZ_HOST>>

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>

Bits 0:15 - Non-periodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>

Bits 16:31 - Non-periodic TxFIFO depth

impl W<u32, Reg<u32, _GCCFG>>

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>

Bit 16 - Power down

pub fn vbusasen(&mut self) -> VBUSASEN_W<'_>

Bit 18 - Enable the VBUS sensing device

pub fn vbusbsen(&mut self) -> VBUSBSEN_W<'_>

Bit 19 - Enable the VBUS sensing device

pub fn sofouten(&mut self) -> SOFOUTEN_W<'_>

Bit 20 - SOF output enable

impl W<u32, Reg<u32, _CID>>

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _HPTXFSIZ>>

pub fn ptxsa(&mut self) -> PTXSA_W<'_>

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfsiz(&mut self) -> PTXFSIZ_W<'_>

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF1>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF2>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO3 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF3>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFO4 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _HCFG>>

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _HFIR>>

pub fn frivl(&mut self) -> FRIVL_W<'_>

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _HPTXSTS>>

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _HAINTMSK>>

pub fn haintm(&mut self) -> HAINTM_W<'_>

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _HPRT>>

pub fn pcdet(&mut self) -> PCDET_W<'_>

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _HCCHAR0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR4>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR5>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR6>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR7>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINTMSK0>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK2>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK3>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK4>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK5>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK6>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK7>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ5>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ6>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ7>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _DCFG>>

pub fn dspd(&mut self) -> DSPD_W<'_>

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>

Bit 2 - Non-zero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>

Bits 11:12 - Periodic frame interval

impl W<u32, Reg<u32, _DCTL>>

pub fn rwusig(&mut self) -> RWUSIG_W<'_>

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _DIEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

impl W<u32, Reg<u32, _DOEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>

Bit 4 - OUT token received when endpoint disabled mask

impl W<u32, Reg<u32, _DAINTMSK>>

pub fn iepm(&mut self) -> IEPM_W<'_>

Bits 0:15 - IN EP interrupt mask bits

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bits 16:31 - OUT endpoint interrupt bits

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _DIEPCTL0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:1 - Maximum packet size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

impl W<u32, Reg<u32, _DIEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm_sd1pid(&mut self) -> SODDFRM_SD1PID_W<'_>

Bit 29 - SODDFRM/SD1PID

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL0>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

impl W<u32, Reg<u32, _DOEPCTL1>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL2>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DOEPCTL3>>

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _DIEPINT0>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT1>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT2>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPINT3>>

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT0>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT1>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT2>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DOEPINT3>>

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - XFRC

impl W<u32, Reg<u32, _DIEPTSIZ0>>

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ0>>

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>

Bits 29:30 - SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bit 19 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ1>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ2>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DIEPTSIZ3>>

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ1>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ2>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _DOEPTSIZ3>>

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _PCGCCTL>>

pub fn stppclk(&mut self) -> STPPCLK_W<'_>

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>

Bit 4 - PHY Suspended

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>

pub fn can2sb(&mut self) -> CAN2SB_W<'_>

Bits 8:13 - CAN2SB

pub fn finit(&mut self) -> FINIT_W<'_>

Bit 0 - FINIT

impl W<u32, Reg<u32, _FM1R>>

pub fn fbm0(&mut self) -> FBM0_W<'_>

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>

Bit 13 - Filter mode

pub fn fbm14(&mut self) -> FBM14_W<'_>

Bit 14 - Filter mode

pub fn fbm15(&mut self) -> FBM15_W<'_>

Bit 15 - Filter mode

pub fn fbm16(&mut self) -> FBM16_W<'_>

Bit 16 - Filter mode

pub fn fbm17(&mut self) -> FBM17_W<'_>

Bit 17 - Filter mode

pub fn fbm18(&mut self) -> FBM18_W<'_>

Bit 18 - Filter mode

pub fn fbm19(&mut self) -> FBM19_W<'_>

Bit 19 - Filter mode

pub fn fbm20(&mut self) -> FBM20_W<'_>

Bit 20 - Filter mode

pub fn fbm21(&mut self) -> FBM21_W<'_>

Bit 21 - Filter mode

pub fn fbm22(&mut self) -> FBM22_W<'_>

Bit 22 - Filter mode

pub fn fbm23(&mut self) -> FBM23_W<'_>

Bit 23 - Filter mode

pub fn fbm24(&mut self) -> FBM24_W<'_>

Bit 24 - Filter mode

pub fn fbm25(&mut self) -> FBM25_W<'_>

Bit 25 - Filter mode

pub fn fbm26(&mut self) -> FBM26_W<'_>

Bit 26 - Filter mode

pub fn fbm27(&mut self) -> FBM27_W<'_>

Bit 27 - Filter mode

impl W<u32, Reg<u32, _FS1R>>

pub fn fsc0(&mut self) -> FSC0_W<'_>

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>

Bit 13 - Filter scale configuration

pub fn fsc14(&mut self) -> FSC14_W<'_>

Bit 14 - Filter scale configuration

pub fn fsc15(&mut self) -> FSC15_W<'_>

Bit 15 - Filter scale configuration

pub fn fsc16(&mut self) -> FSC16_W<'_>

Bit 16 - Filter scale configuration

pub fn fsc17(&mut self) -> FSC17_W<'_>

Bit 17 - Filter scale configuration

pub fn fsc18(&mut self) -> FSC18_W<'_>

Bit 18 - Filter scale configuration

pub fn fsc19(&mut self) -> FSC19_W<'_>

Bit 19 - Filter scale configuration

pub fn fsc20(&mut self) -> FSC20_W<'_>

Bit 20 - Filter scale configuration

pub fn fsc21(&mut self) -> FSC21_W<'_>

Bit 21 - Filter scale configuration

pub fn fsc22(&mut self) -> FSC22_W<'_>

Bit 22 - Filter scale configuration

pub fn fsc23(&mut self) -> FSC23_W<'_>

Bit 23 - Filter scale configuration

pub fn fsc24(&mut self) -> FSC24_W<'_>

Bit 24 - Filter scale configuration

pub fn fsc25(&mut self) -> FSC25_W<'_>

Bit 25 - Filter scale configuration

pub fn fsc26(&mut self) -> FSC26_W<'_>

Bit 26 - Filter scale configuration

pub fn fsc27(&mut self) -> FSC27_W<'_>

Bit 27 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>

pub fn ffa0(&mut self) -> FFA0_W<'_>

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>

Bit 13 - Filter FIFO assignment for filter 13

pub fn ffa14(&mut self) -> FFA14_W<'_>

Bit 14 - Filter FIFO assignment for filter 14

pub fn ffa15(&mut self) -> FFA15_W<'_>

Bit 15 - Filter FIFO assignment for filter 15

pub fn ffa16(&mut self) -> FFA16_W<'_>

Bit 16 - Filter FIFO assignment for filter 16

pub fn ffa17(&mut self) -> FFA17_W<'_>

Bit 17 - Filter FIFO assignment for filter 17

pub fn ffa18(&mut self) -> FFA18_W<'_>

Bit 18 - Filter FIFO assignment for filter 18

pub fn ffa19(&mut self) -> FFA19_W<'_>

Bit 19 - Filter FIFO assignment for filter 19

pub fn ffa20(&mut self) -> FFA20_W<'_>

Bit 20 - Filter FIFO assignment for filter 20

pub fn ffa21(&mut self) -> FFA21_W<'_>

Bit 21 - Filter FIFO assignment for filter 21

pub fn ffa22(&mut self) -> FFA22_W<'_>

Bit 22 - Filter FIFO assignment for filter 22

pub fn ffa23(&mut self) -> FFA23_W<'_>

Bit 23 - Filter FIFO assignment for filter 23

pub fn ffa24(&mut self) -> FFA24_W<'_>

Bit 24 - Filter FIFO assignment for filter 24

pub fn ffa25(&mut self) -> FFA25_W<'_>

Bit 25 - Filter FIFO assignment for filter 25

pub fn ffa26(&mut self) -> FFA26_W<'_>

Bit 26 - Filter FIFO assignment for filter 26

pub fn ffa27(&mut self) -> FFA27_W<'_>

Bit 27 - Filter FIFO assignment for filter 27

impl W<u32, Reg<u32, _FA1R>>

pub fn fact0(&mut self) -> FACT0_W<'_>

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>

Bit 13 - Filter active

pub fn fact14(&mut self) -> FACT14_W<'_>

Bit 14 - Filter active

pub fn fact15(&mut self) -> FACT15_W<'_>

Bit 15 - Filter active

pub fn fact16(&mut self) -> FACT16_W<'_>

Bit 16 - Filter active

pub fn fact17(&mut self) -> FACT17_W<'_>

Bit 17 - Filter active

pub fn fact18(&mut self) -> FACT18_W<'_>

Bit 18 - Filter active

pub fn fact19(&mut self) -> FACT19_W<'_>

Bit 19 - Filter active

pub fn fact20(&mut self) -> FACT20_W<'_>

Bit 20 - Filter active

pub fn fact21(&mut self) -> FACT21_W<'_>

Bit 21 - Filter active

pub fn fact22(&mut self) -> FACT22_W<'_>

Bit 22 - Filter active

pub fn fact23(&mut self) -> FACT23_W<'_>

Bit 23 - Filter active

pub fn fact24(&mut self) -> FACT24_W<'_>

Bit 24 - Filter active

pub fn fact25(&mut self) -> FACT25_W<'_>

Bit 25 - Filter active

pub fn fact26(&mut self) -> FACT26_W<'_>

Bit 26 - Filter active

pub fn fact27(&mut self) -> FACT27_W<'_>

Bit 27 - Filter active

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn dcen(&mut self) -> DCEN_W<'_>

Bit 10 - Data cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn dcrst(&mut self) -> DCRST_W<'_>

Bit 12 - Data cache reset

impl W<u32, Reg<u32, _KEYR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - FPEC key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkey(&mut self) -> OPTKEY_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protection error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn pgperr(&mut self) -> PGPERR_W<'_>

Bit 6 - Programming parallelism error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

pub fn rderr(&mut self) -> RDERR_W<'_>

Bit 8 - Proprietary readout protection (PCROP) error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn ser(&mut self) -> SER_W<'_>

Bit 1 - Sector Erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass Erase of sectors 0 to 11

pub fn snb(&mut self) -> SNB_W<'_>

Bits 3:7 - Sector number

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Program size

pub fn mer1(&mut self) -> MER1_W<'_>

Bit 15 - Mass Erase of sectors 12 to 23

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - Lock

impl W<u32, Reg<u32, _OPTCR>>

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 0 - Option lock

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 1 - Option start

pub fn bor_lev(&mut self) -> BOR_LEV_W<'_>

Bits 2:3 - BOR reset Level

pub fn bfb2(&mut self) -> BFB2_W<'_>

Bit 4 - Dual-bank Boot option byte

pub fn wdg_sw(&mut self) -> WDG_SW_W<'_>

Bit 5 - WDG_SW User option bytes

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 6 - nRST_STOP User option bytes

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 7 - nRST_STDBY User option bytes

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 8:15 - Read protect

pub fn n_wrp(&mut self) -> NWRP_W<'_>

Bits 16:27 - Not write protect

pub fn db1m(&mut self) -> DB1M_W<'_>

Bit 30 - Dual-bank on 1 Mbyte Flash memory devices

pub fn sprmod(&mut self) -> SPRMOD_W<'_>

Bit 31 - Selection of protection mode for nWPRi bits

impl W<u32, Reg<u32, _OPTCR1>>

pub fn n_wrp(&mut self) -> NWRP_W<'_>

Bits 16:27 - Not write protect

impl W<u32, Reg<u32, _IMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Interrupt Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Interrupt Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Interrupt Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Interrupt Mask on line 22

impl W<u32, Reg<u32, _EMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Event Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Event Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Event Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Event Mask on line 22

impl W<u32, Reg<u32, _RTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Rising trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Rising trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Rising trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Rising trigger event configuration of line 22

impl W<u32, Reg<u32, _FTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Falling trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Falling trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Falling trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Falling trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Falling trigger event configuration of line 22

impl W<u32, Reg<u32, _SWIER>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

pub fn swier19(&mut self) -> SWIER19_W<'_>

Bit 19 - Software Interrupt on line 19

pub fn swier20(&mut self) -> SWIER20_W<'_>

Bit 20 - Software Interrupt on line 20

pub fn swier21(&mut self) -> SWIER21_W<'_>

Bit 21 - Software Interrupt on line 21

pub fn swier22(&mut self) -> SWIER22_W<'_>

Bit 22 - Software Interrupt on line 22

impl W<u32, Reg<u32, _PR>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

pub fn pr19(&mut self) -> PR19_W<'_>

Bit 19 - Pending bit 19

pub fn pr20(&mut self) -> PR20_W<'_>

Bit 20 - Pending bit 20

pub fn pr21(&mut self) -> PR21_W<'_>

Bit 21 - Pending bit 21

pub fn pr22(&mut self) -> PR22_W<'_>

Bit 22 - Pending bit 22

impl W<u32, Reg<u32, _GOTGCTL>>

pub fn srq(&mut self) -> SRQ_W<'_>

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>

Bit 11 - Device HNP enabled

impl W<u32, Reg<u32, _GOTGINT>>

pub fn sedet(&mut self) -> SEDET_W<'_>

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>

Bit 19 - Debounce done

impl W<u32, Reg<u32, _GAHBCFG>>

pub fn gint(&mut self) -> GINT_W<'_>

Bit 0 - Global interrupt mask

pub fn hbstlen(&mut self) -> HBSTLEN_W<'_>

Bits 1:4 - Burst length/type

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 5 - DMA enable

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _GUSBCFG>>

pub fn tocal(&mut self) -> TOCAL_W<'_>

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>

Bit 6 - USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>

Bits 10:13 - USB turnaround time

pub fn phylpcs(&mut self) -> PHYLPCS_W<'_>

Bit 15 - PHY Low-power clock select

pub fn ulpifsls(&mut self) -> ULPIFSLS_W<'_>

Bit 17 - ULPI FS/LS select

pub fn ulpiar(&mut self) -> ULPIAR_W<'_>

Bit 18 - ULPI Auto-resume

pub fn ulpicsm(&mut self) -> ULPICSM_W<'_>

Bit 19 - ULPI Clock SuspendM

pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W<'_>

Bit 20 - ULPI External VBUS Drive

pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W<'_>

Bit 21 - ULPI external VBUS indicator

pub fn tsdps(&mut self) -> TSDPS_W<'_>

Bit 22 - TermSel DLine pulsing selection

pub fn pcci(&mut self) -> PCCI_W<'_>

Bit 23 - Indicator complement

pub fn ptci(&mut self) -> PTCI_W<'_>

Bit 24 - Indicator pass through

pub fn ulpiipd(&mut self) -> ULPIIPD_W<'_>

Bit 25 - ULPI interface protect disable

pub fn fhmod(&mut self) -> FHMOD_W<'_>

Bit 29 - Forced host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>

Bit 30 - Forced peripheral mode

pub fn ctxpkt(&mut self) -> CTXPKT_W<'_>

Bit 31 - Corrupt Tx packet

impl W<u32, Reg<u32, _GRSTCTL>>

pub fn csrst(&mut self) -> CSRST_W<'_>

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _GINTSTS>>

pub fn mmis(&mut self) -> MMIS_W<'_>

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>

Bit 20 - Incomplete isochronous IN transfer

pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W<'_>

Bit 21 - Incomplete periodic transfer

pub fn datafsusp(&mut self) -> DATAFSUSP_W<'_>

Bit 22 - Data fetch suspended

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>

Bit 30 - Session request/new session detected interrupt

pub fn wkuint(&mut self) -> WKUINT_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _GINTMSK>>

pub fn mmism(&mut self) -> MMISM_W<'_>

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>

Bit 4 - Receive FIFO nonempty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>

Bit 5 - Nonperiodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>

Bit 6 - Global nonperiodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>

Bit 15 - End of periodic frame interrupt mask

pub fn epmism(&mut self) -> EPMISM_W<'_>

Bit 17 - Endpoint mismatch interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>

Bit 20 - Incomplete isochronous IN transfer mask

pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W<'_>

Bit 21 - Incomplete periodic transfer mask

pub fn fsuspm(&mut self) -> FSUSPM_W<'_>

Bit 22 - Data fetch suspended mask

pub fn hcim(&mut self) -> HCIM_W<'_>

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>

Bit 31 - Resume/remote wakeup detected interrupt mask

impl W<u32, Reg<u32, _GRXFSIZ>>

pub fn rxfd(&mut self) -> RXFD_W<'_>

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _GNPTXFSIZ_HOST>>

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>

Bits 0:15 - Nonperiodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>

Bits 16:31 - Nonperiodic TxFIFO depth

impl W<u32, Reg<u32, _TX0FSIZ_PERIPHERAL>>

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _GCCFG>>

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>

Bit 16 - Power down

pub fn i2cpaden(&mut self) -> I2CPADEN_W<'_>

Bit 17 - Enable I2C bus connection for the external I2C PHY interface

pub fn vbusasen(&mut self) -> VBUSASEN_W<'_>

Bit 18 - Enable the VBUS sensing device

pub fn vbusbsen(&mut self) -> VBUSBSEN_W<'_>

Bit 19 - Enable the VBUS sensing device

pub fn sofouten(&mut self) -> SOFOUTEN_W<'_>

Bit 20 - SOF output enable

pub fn novbussens(&mut self) -> NOVBUSSENS_W<'_>

Bit 21 - VBUS sensing disable option

impl W<u32, Reg<u32, _CID>>

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _HPTXFSIZ>>

pub fn ptxsa(&mut self) -> PTXSA_W<'_>

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfd(&mut self) -> PTXFD_W<'_>

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF1>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF2>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF3>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF4>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF5>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF6>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _DIEPTXF7>>

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _HCFG>>

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _HFIR>>

pub fn frivl(&mut self) -> FRIVL_W<'_>

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _HPTXSTS>>

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _HAINTMSK>>

pub fn haintm(&mut self) -> HAINTM_W<'_>

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _HPRT>>

pub fn pcdet(&mut self) -> PCDET_W<'_>

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _HCCHAR0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR4>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR5>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR6>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR7>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR8>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR9>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR10>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCCHAR11>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel enable

impl W<u32, Reg<u32, _HCSPLT0>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT1>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT2>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT3>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT4>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT5>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT6>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT7>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT8>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT9>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT10>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCSPLT11>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>

Bit 31 - Split enable

impl W<u32, Reg<u32, _HCINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT8>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT9>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT10>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINT11>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _HCINTMSK0>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK2>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK3>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK4>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK5>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK6>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK7>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK8>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK9>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK10>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCINTMSK11>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _HCTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ5>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ6>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ7>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ8>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ9>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ10>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCTSIZ11>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _HCDMA0>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA1>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA2>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA3>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA4>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA5>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA6>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA7>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA8>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA9>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA10>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _HCDMA11>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DCFG>>

pub fn dspd(&mut self) -> DSPD_W<'_>

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>

Bit 2 - Nonzero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>

Bits 11:12 - Periodic (micro)frame interval

pub fn perschivl(&mut self) -> PERSCHIVL_W<'_>

Bits 24:25 - Periodic scheduling interval

impl W<u32, Reg<u32, _DCTL>>

pub fn rwusig(&mut self) -> RWUSIG_W<'_>

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _DIEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (nonisochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

pub fn txfurm(&mut self) -> TXFURM_W<'_>

Bit 8 - FIFO underrun mask

pub fn bim(&mut self) -> BIM_W<'_>

Bit 9 - BNA interrupt mask

impl W<u32, Reg<u32, _DOEPMSK>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>

Bit 4 - OUT token received when endpoint disabled mask

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - Back-to-back SETUP packets received mask

pub fn opem(&mut self) -> OPEM_W<'_>

Bit 8 - OUT packet error mask

pub fn boim(&mut self) -> BOIM_W<'_>

Bit 9 - BNA interrupt mask

impl W<u32, Reg<u32, _DAINTMSK>>

pub fn iepm(&mut self) -> IEPM_W<'_>

Bits 0:15 - IN EP interrupt mask bits

pub fn oepm(&mut self) -> OEPM_W<'_>

Bits 16:31 - OUT EP interrupt mask bits

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _DTHRCTL>>

pub fn nonisothren(&mut self) -> NONISOTHREN_W<'_>

Bit 0 - Nonisochronous IN endpoints threshold enable

pub fn isothren(&mut self) -> ISOTHREN_W<'_>

Bit 1 - ISO IN endpoint threshold enable

pub fn txthrlen(&mut self) -> TXTHRLEN_W<'_>

Bits 2:10 - Transmit threshold length

pub fn rxthren(&mut self) -> RXTHREN_W<'_>

Bit 16 - Receive threshold enable

pub fn rxthrlen(&mut self) -> RXTHRLEN_W<'_>

Bits 17:25 - Receive threshold length

pub fn arpen(&mut self) -> ARPEN_W<'_>

Bit 27 - Arbiter parking enable

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _DEACHINT>>

pub fn iep1int(&mut self) -> IEP1INT_W<'_>

Bit 1 - IN endpoint 1interrupt bit

pub fn oep1int(&mut self) -> OEP1INT_W<'_>

Bit 17 - OUT endpoint 1 interrupt bit

impl W<u32, Reg<u32, _DEACHINTMSK>>

pub fn iep1intm(&mut self) -> IEP1INTM_W<'_>

Bit 1 - IN Endpoint 1 interrupt mask bit

pub fn oep1intm(&mut self) -> OEP1INTM_W<'_>

Bit 17 - OUT Endpoint 1 interrupt mask bit

impl W<u32, Reg<u32, _DIEPEACHMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask (nonisochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

pub fn txfurm(&mut self) -> TXFURM_W<'_>

Bit 8 - FIFO underrun mask

pub fn bim(&mut self) -> BIM_W<'_>

Bit 9 - BNA interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 13 - NAK interrupt mask

impl W<u32, Reg<u32, _DOEPEACHMSK1>>

pub fn xfrcm(&mut self) -> XFRCM_W<'_>

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>

Bit 3 - Timeout condition mask

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>

Bit 6 - IN endpoint NAK effective mask

pub fn txfurm(&mut self) -> TXFURM_W<'_>

Bit 8 - OUT packet error mask

pub fn bim(&mut self) -> BIM_W<'_>

Bit 9 - BNA interrupt mask

pub fn berrm(&mut self) -> BERRM_W<'_>

Bit 12 - Bubble error interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>

Bit 13 - NAK interrupt mask

pub fn nyetm(&mut self) -> NYETM_W<'_>

Bit 14 - NYET interrupt mask

impl W<u32, Reg<u32, _DIEPCTL0>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPCTL1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPCTL2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPCTL3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPCTL4>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPCTL5>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPCTL6>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPCTL7>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DIEPINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _DIEPINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _DIEPINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _DIEPINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _DIEPINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _DIEPINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _DIEPINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _DIEPINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _DIEPTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet count

impl W<u32, Reg<u32, _DIEPDMA1>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DIEPDMA2>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DIEPDMA3>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DIEPDMA4>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DIEPDMA5>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _DIEPTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _DIEPTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _DIEPTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _DIEPTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _DIEPTSIZ5>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _DOEPCTL0>>

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DOEPCTL1>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DOEPCTL2>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DOEPCTL3>>

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _DOEPINT0>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _DOEPINT1>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _DOEPINT2>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _DOEPINT3>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _DOEPINT4>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _DOEPINT5>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _DOEPINT6>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _DOEPINT7>>

pub fn xfrc(&mut self) -> XFRC_W<'_>

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _DOEPTSIZ0>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:6 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bit 19 - Packet count

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>

Bits 29:30 - SETUP packet count

impl W<u32, Reg<u32, _DOEPTSIZ1>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _DOEPTSIZ2>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _DOEPTSIZ3>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _DOEPTSIZ4>>

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _PCGCR>>

pub fn stppclk(&mut self) -> STPPCLK_W<'_>

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>

Bit 4 - PHY suspended

impl W<u32, Reg<u32, _CR>>

pub fn cluten(&mut self) -> CLUTEN_W<'_>

Bit 4 - Color Look-Up Table Enable

pub fn colken(&mut self) -> COLKEN_W<'_>

Bit 1 - Color Keying Enable

pub fn len(&mut self) -> LEN_W<'_>

Bit 0 - Layer Enable

impl W<u32, Reg<u32, _WHPCR>>

pub fn whsppos(&mut self) -> WHSPPOS_W<'_>

Bits 16:27 - Window Horizontal Stop Position

pub fn whstpos(&mut self) -> WHSTPOS_W<'_>

Bits 0:11 - Window Horizontal Start Position

impl W<u32, Reg<u32, _WVPCR>>

pub fn wvsppos(&mut self) -> WVSPPOS_W<'_>

Bits 16:26 - Window Vertical Stop Position

pub fn wvstpos(&mut self) -> WVSTPOS_W<'_>

Bits 0:10 - Window Vertical Start Position

impl W<u32, Reg<u32, _CKCR>>

pub fn ckred(&mut self) -> CKRED_W<'_>

Bits 16:23 - Color Key Red value

pub fn ckgreen(&mut self) -> CKGREEN_W<'_>

Bits 8:15 - Color Key Green value

pub fn ckblue(&mut self) -> CKBLUE_W<'_>

Bits 0:7 - Color Key Blue value

impl W<u32, Reg<u32, _PFCR>>

pub fn pf(&mut self) -> PF_W<'_>

Bits 0:2 - Pixel Format

impl W<u32, Reg<u32, _CACR>>

pub fn consta(&mut self) -> CONSTA_W<'_>

Bits 0:7 - Constant Alpha

impl W<u32, Reg<u32, _DCCR>>

pub fn dcalpha(&mut self) -> DCALPHA_W<'_>

Bits 24:31 - Default Color Alpha

pub fn dcred(&mut self) -> DCRED_W<'_>

Bits 16:23 - Default Color Red

pub fn dcgreen(&mut self) -> DCGREEN_W<'_>

Bits 8:15 - Default Color Green

pub fn dcblue(&mut self) -> DCBLUE_W<'_>

Bits 0:7 - Default Color Blue

impl W<u32, Reg<u32, _BFCR>>

pub fn bf1(&mut self) -> BF1_W<'_>

Bits 8:10 - Blending Factor 1

pub fn bf2(&mut self) -> BF2_W<'_>

Bits 0:2 - Blending Factor 2

impl W<u32, Reg<u32, _CFBAR>>

pub fn cfbadd(&mut self) -> CFBADD_W<'_>

Bits 0:31 - Color Frame Buffer Start Address

impl W<u32, Reg<u32, _CFBLR>>

pub fn cfbp(&mut self) -> CFBP_W<'_>

Bits 16:28 - Color Frame Buffer Pitch in bytes

pub fn cfbll(&mut self) -> CFBLL_W<'_>

Bits 0:12 - Color Frame Buffer Line Length

impl W<u32, Reg<u32, _CFBLNR>>

pub fn cfblnbr(&mut self) -> CFBLNBR_W<'_>

Bits 0:10 - Frame Buffer Line Number

impl W<u32, Reg<u32, _CLUTWR>>

pub fn clutadd(&mut self) -> CLUTADD_W<'_>

Bits 24:31 - CLUT Address

pub fn red(&mut self) -> RED_W<'_>

Bits 16:23 - Red value

pub fn green(&mut self) -> GREEN_W<'_>

Bits 8:15 - Green value

pub fn blue(&mut self) -> BLUE_W<'_>

Bits 0:7 - Blue value

impl W<u32, Reg<u32, _SSCR>>

pub fn hsw(&mut self) -> HSW_W<'_>

Bits 16:27 - Horizontal Synchronization Width (in units of pixel clock period)

pub fn vsh(&mut self) -> VSH_W<'_>

Bits 0:10 - Vertical Synchronization Height (in units of horizontal scan line)

impl W<u32, Reg<u32, _BPCR>>

pub fn ahbp(&mut self) -> AHBP_W<'_>

Bits 16:27 - Accumulated Horizontal back porch (in units of pixel clock period)

pub fn avbp(&mut self) -> AVBP_W<'_>

Bits 0:10 - Accumulated Vertical back porch (in units of horizontal scan line)

impl W<u32, Reg<u32, _AWCR>>

pub fn aaw(&mut self) -> AAW_W<'_>

Bits 16:27 - Accumulated Active Width (in units of pixel clock period)

pub fn aah(&mut self) -> AAH_W<'_>

Bits 0:10 - Accumulated Active Height (in units of horizontal scan line)

impl W<u32, Reg<u32, _TWCR>>

pub fn totalw(&mut self) -> TOTALW_W<'_>

Bits 16:27 - Total Width (in units of pixel clock period)

pub fn totalh(&mut self) -> TOTALH_W<'_>

Bits 0:10 - Total Height (in units of horizontal scan line)

impl W<u32, Reg<u32, _GCR>>

pub fn hspol(&mut self) -> HSPOL_W<'_>

Bit 31 - Horizontal Synchronization Polarity

pub fn vspol(&mut self) -> VSPOL_W<'_>

Bit 30 - Vertical Synchronization Polarity

pub fn depol(&mut self) -> DEPOL_W<'_>

Bit 29 - Data Enable Polarity

pub fn pcpol(&mut self) -> PCPOL_W<'_>

Bit 28 - Pixel Clock Polarity

pub fn den(&mut self) -> DEN_W<'_>

Bit 16 - Dither Enable

pub fn ltdcen(&mut self) -> LTDCEN_W<'_>

Bit 0 - LCD-TFT controller enable bit

impl W<u32, Reg<u32, _SRCR>>

pub fn vbr(&mut self) -> VBR_W<'_>

Bit 1 - Vertical Blanking Reload

pub fn imr(&mut self) -> IMR_W<'_>

Bit 0 - Immediate Reload

impl W<u32, Reg<u32, _BCCR>>

pub fn bcblue(&mut self) -> BCBLUE_W<'_>

Bits 0:7 - Background color blue value

pub fn bcgreen(&mut self) -> BCGREEN_W<'_>

Bits 8:15 - Background color green value

pub fn bcred(&mut self) -> BCRED_W<'_>

Bits 16:23 - Background color red value

impl W<u32, Reg<u32, _IER>>

pub fn rrie(&mut self) -> RRIE_W<'_>

Bit 3 - Register Reload interrupt enable

pub fn terrie(&mut self) -> TERRIE_W<'_>

Bit 2 - Transfer Error Interrupt Enable

pub fn fuie(&mut self) -> FUIE_W<'_>

Bit 1 - FIFO Underrun Interrupt Enable

pub fn lie(&mut self) -> LIE_W<'_>

Bit 0 - Line Interrupt Enable

impl W<u32, Reg<u32, _ICR>>

pub fn crrif(&mut self) -> CRRIF_W<'_>

Bit 3 - Clears Register Reload Interrupt Flag

pub fn cterrif(&mut self) -> CTERRIF_W<'_>

Bit 2 - Clears the Transfer Error Interrupt Flag

pub fn cfuif(&mut self) -> CFUIF_W<'_>

Bit 1 - Clears the FIFO Underrun Interrupt flag

pub fn clif(&mut self) -> CLIF_W<'_>

Bit 0 - Clears the Line Interrupt Flag

impl W<u32, Reg<u32, _LIPCR>>

pub fn lipos(&mut self) -> LIPOS_W<'_>

Bits 0:10 - Line Interrupt Position

impl W<u32, Reg<u32, _CR1>>

pub fn mckdiv(&mut self) -> MCKDIV_W<'_>

Bits 20:23 - Master clock divider

pub fn nodiv(&mut self) -> NODIV_W<'_>

Bit 19 - No divider

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 17 - DMA enable

pub fn saien(&mut self) -> SAIEN_W<'_>

Bit 16 - Audio block A enable

pub fn outdriv(&mut self) -> OUTDRIV_W<'_>

Bit 13 - Output drive

pub fn mono(&mut self) -> MONO_W<'_>

Bit 12 - Mono mode

pub fn syncen(&mut self) -> SYNCEN_W<'_>

Bits 10:11 - Synchronization enable

pub fn ckstr(&mut self) -> CKSTR_W<'_>

Bit 9 - Clock strobing edge

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 8 - Least significant bit first

pub fn ds(&mut self) -> DS_W<'_>

Bits 5:7 - Data size

pub fn prtcfg(&mut self) -> PRTCFG_W<'_>

Bits 2:3 - Protocol configuration

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Audio block mode

impl W<u32, Reg<u32, _CR2>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 14:15 - Companding mode

pub fn cpl(&mut self) -> CPL_W<'_>

Bit 13 - Complement bit

pub fn mutecn(&mut self) -> MUTECN_W<'_>

Bits 7:12 - Mute counter

pub fn muteval(&mut self) -> MUTEVAL_W<'_>

Bit 6 - Mute value

pub fn mute(&mut self) -> MUTE_W<'_>

Bit 5 - Mute

pub fn tris(&mut self) -> TRIS_W<'_>

Bit 4 - Tristate management on data line

pub fn fflush(&mut self) -> FFLUSH_W<'_>

Bit 3 - FIFO flush

pub fn fth(&mut self) -> FTH_W<'_>

Bits 0:2 - FIFO threshold

impl W<u32, Reg<u32, _FRCR>>

pub fn fsoff(&mut self) -> FSOFF_W<'_>

Bit 18 - Frame synchronization offset

pub fn fspol(&mut self) -> FSPOL_W<'_>

Bit 17 - Frame synchronization polarity

pub fn fsdef(&mut self) -> FSDEF_W<'_>

Bit 16 - Frame synchronization definition

pub fn fsall(&mut self) -> FSALL_W<'_>

Bits 8:14 - Frame synchronization active level length

pub fn frl(&mut self) -> FRL_W<'_>

Bits 0:7 - Frame length

impl W<u32, Reg<u32, _SLOTR>>

pub fn sloten(&mut self) -> SLOTEN_W<'_>

Bits 16:31 - Slot enable

pub fn nbslot(&mut self) -> NBSLOT_W<'_>

Bits 8:11 - Number of slots in an audio frame

pub fn slotsz(&mut self) -> SLOTSZ_W<'_>

Bits 6:7 - Slot size

pub fn fboff(&mut self) -> FBOFF_W<'_>

Bits 0:4 - First bit offset

impl W<u32, Reg<u32, _IM>>

pub fn lfsdetie(&mut self) -> LFSDETIE_W<'_>

Bit 6 - Late frame synchronization detection interrupt enable

pub fn afsdetie(&mut self) -> AFSDETIE_W<'_>

Bit 5 - Anticipated frame synchronization detection interrupt enable

pub fn cnrdyie(&mut self) -> CNRDYIE_W<'_>

Bit 4 - Codec not ready interrupt enable

pub fn freqie(&mut self) -> FREQIE_W<'_>

Bit 3 - FIFO request interrupt enable

pub fn wckcfgie(&mut self) -> WCKCFGIE_W<'_>

Bit 2 - Wrong clock configuration interrupt enable

pub fn mutedetie(&mut self) -> MUTEDETIE_W<'_>

Bit 1 - Mute detection interrupt enable

pub fn ovrudrie(&mut self) -> OVRUDRIE_W<'_>

Bit 0 - Overrun/underrun interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn flvl(&mut self) -> FLVL_W<'_>

Bits 16:18 - FIFO level threshold

pub fn lfsdet(&mut self) -> LFSDET_W<'_>

Bit 6 - Late frame synchronization detection

pub fn afsdet(&mut self) -> AFSDET_W<'_>

Bit 5 - Anticipated frame synchronization detection

pub fn cnrdy(&mut self) -> CNRDY_W<'_>

Bit 4 - Codec not ready

pub fn freq(&mut self) -> FREQ_W<'_>

Bit 3 - FIFO request

pub fn wckcfg(&mut self) -> WCKCFG_W<'_>

Bit 2 - Wrong clock configuration flag. This bit is read only.

pub fn mutedet(&mut self) -> MUTEDET_W<'_>

Bit 1 - Mute detection

pub fn ovrudr(&mut self) -> OVRUDR_W<'_>

Bit 0 - Overrun / underrun

impl W<u32, Reg<u32, _CLRFR>>

pub fn clfsdet(&mut self) -> CLFSDET_W<'_>

Bit 6 - Clear late frame synchronization detection flag

pub fn cafsdet(&mut self) -> CAFSDET_W<'_>

Bit 5 - Clear anticipated frame synchronization detection flag.

pub fn ccnrdy(&mut self) -> CCNRDY_W<'_>

Bit 4 - Clear codec not ready flag

pub fn cwckcfg(&mut self) -> CWCKCFG_W<'_>

Bit 2 - Clear wrong clock configuration flag

pub fn cmutedet(&mut self) -> CMUTEDET_W<'_>

Bit 1 - Mute detection flag

pub fn covrudr(&mut self) -> COVRUDR_W<'_>

Bit 0 - Clear overrun / underrun

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _GCR>>

pub fn syncout(&mut self) -> SYNCOUT_W<'_>

Bits 0:1 - Synchronization outputs

impl W<u32, Reg<u32, _CR>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 16:17 - DMA2D mode

pub fn ceie(&mut self) -> CEIE_W<'_>

Bit 13 - Configuration Error Interrupt Enable

pub fn ctcie(&mut self) -> CTCIE_W<'_>

Bit 12 - CLUT transfer complete interrupt enable

pub fn caeie(&mut self) -> CAEIE_W<'_>

Bit 11 - CLUT access error interrupt enable

pub fn twie(&mut self) -> TWIE_W<'_>

Bit 10 - Transfer watermark interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 9 - Transfer complete interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 8 - Transfer error interrupt enable

pub fn abort(&mut self) -> ABORT_W<'_>

Bit 2 - Abort

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 1 - Suspend

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start

impl W<u32, Reg<u32, _IFCR>>

pub fn cceif(&mut self) -> CCEIF_W<'_>

Bit 5 - Clear configuration error interrupt flag

pub fn cctcif(&mut self) -> CCTCIF_W<'_>

Bit 4 - Clear CLUT transfer complete interrupt flag

pub fn caecif(&mut self) -> CAECIF_W<'_>

Bit 3 - Clear CLUT access error interrupt flag

pub fn ctwif(&mut self) -> CTWIF_W<'_>

Bit 2 - Clear transfer watermark interrupt flag

pub fn ctcif(&mut self) -> CTCIF_W<'_>

Bit 1 - Clear transfer complete interrupt flag

pub fn cteif(&mut self) -> CTEIF_W<'_>

Bit 0 - Clear Transfer error interrupt flag

impl W<u32, Reg<u32, _FGMAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _FGOR>>

pub fn lo(&mut self) -> LO_W<'_>

Bits 0:13 - Line offset

impl W<u32, Reg<u32, _BGMAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _BGOR>>

pub fn lo(&mut self) -> LO_W<'_>

Bits 0:13 - Line offset

impl W<u32, Reg<u32, _FGPFCCR>>

pub fn alpha(&mut self) -> ALPHA_W<'_>

Bits 24:31 - Alpha value

pub fn am(&mut self) -> AM_W<'_>

Bits 16:17 - Alpha mode

pub fn cs(&mut self) -> CS_W<'_>

Bits 8:15 - CLUT size

pub fn start(&mut self) -> START_W<'_>

Bit 5 - Start

pub fn ccm(&mut self) -> CCM_W<'_>

Bit 4 - CLUT color mode

pub fn cm(&mut self) -> CM_W<'_>

Bits 0:3 - Color mode

impl W<u32, Reg<u32, _FGCOLR>>

pub fn red(&mut self) -> RED_W<'_>

Bits 16:23 - Red Value

pub fn green(&mut self) -> GREEN_W<'_>

Bits 8:15 - Green Value

pub fn blue(&mut self) -> BLUE_W<'_>

Bits 0:7 - Blue Value

impl W<u32, Reg<u32, _BGPFCCR>>

pub fn alpha(&mut self) -> ALPHA_W<'_>

Bits 24:31 - Alpha value

pub fn am(&mut self) -> AM_W<'_>

Bits 16:17 - Alpha mode

pub fn cs(&mut self) -> CS_W<'_>

Bits 8:15 - CLUT size

pub fn start(&mut self) -> START_W<'_>

Bit 5 - Start

pub fn ccm(&mut self) -> CCM_W<'_>

Bit 4 - CLUT Color mode

pub fn cm(&mut self) -> CM_W<'_>

Bits 0:3 - Color mode

impl W<u32, Reg<u32, _BGCOLR>>

pub fn red(&mut self) -> RED_W<'_>

Bits 16:23 - Red Value

pub fn green(&mut self) -> GREEN_W<'_>

Bits 8:15 - Green Value

pub fn blue(&mut self) -> BLUE_W<'_>

Bits 0:7 - Blue Value

impl W<u32, Reg<u32, _FGCMAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory Address

impl W<u32, Reg<u32, _BGCMAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _OPFCCR>>

pub fn cm(&mut self) -> CM_W<'_>

Bits 0:2 - Color mode

impl W<u32, Reg<u32, _OCOLR>>

pub fn aplha(&mut self) -> APLHA_W<'_>

Bits 24:31 - Alpha Channel Value

pub fn red(&mut self) -> RED_W<'_>

Bits 16:23 - Red Value

pub fn green(&mut self) -> GREEN_W<'_>

Bits 8:15 - Green Value

pub fn blue(&mut self) -> BLUE_W<'_>

Bits 0:7 - Blue Value

impl W<u32, Reg<u32, _OMAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory Address

impl W<u32, Reg<u32, _OOR>>

pub fn lo(&mut self) -> LO_W<'_>

Bits 0:13 - Line Offset

impl W<u32, Reg<u32, _NLR>>

pub fn pl(&mut self) -> PL_W<'_>

Bits 16:29 - Pixel per lines

pub fn nl(&mut self) -> NL_W<'_>

Bits 0:15 - Number of lines

impl W<u32, Reg<u32, _LWR>>

pub fn lw(&mut self) -> LW_W<'_>

Bits 0:15 - Line watermark

impl W<u32, Reg<u32, _AMTCR>>

pub fn dt(&mut self) -> DT_W<'_>

Bits 8:15 - Dead Time

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

impl W<u32, Reg<u32, _FGCLUT>>

pub fn aplha(&mut self) -> APLHA_W<'_>

Bits 24:31 - APLHA

pub fn red(&mut self) -> RED_W<'_>

Bits 16:23 - RED

pub fn green(&mut self) -> GREEN_W<'_>

Bits 8:15 - GREEN

pub fn blue(&mut self) -> BLUE_W<'_>

Bits 0:7 - BLUE

impl W<u32, Reg<u32, _BGCLUT>>

pub fn aplha(&mut self) -> APLHA_W<'_>

Bits 24:31 - APLHA

pub fn red(&mut self) -> RED_W<'_>

Bits 16:23 - RED

pub fn green(&mut self) -> GREEN_W<'_>

Bits 8:15 - GREEN

pub fn blue(&mut self) -> BLUE_W<'_>

Bits 0:7 - BLUE

impl W<u32, Reg<u32, _CR1>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 15 - Software reset

pub fn alert(&mut self) -> ALERT_W<'_>

Bit 13 - SMBus alert

pub fn pec(&mut self) -> PEC_W<'_>

Bit 12 - Packet error checking

pub fn pos(&mut self) -> POS_W<'_>

Bit 11 - Acknowledge/PEC Position (for data reception)

pub fn ack(&mut self) -> ACK_W<'_>

Bit 10 - Acknowledge enable

pub fn stop(&mut self) -> STOP_W<'_>

Bit 9 - Stop generation

pub fn start(&mut self) -> START_W<'_>

Bit 8 - Start generation

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 7 - Clock stretching disable (Slave mode)

pub fn engc(&mut self) -> ENGC_W<'_>

Bit 6 - General call enable

pub fn enpec(&mut self) -> ENPEC_W<'_>

Bit 5 - PEC enable

pub fn enarp(&mut self) -> ENARP_W<'_>

Bit 4 - ARP enable

pub fn smbtype(&mut self) -> SMBTYPE_W<'_>

Bit 3 - SMBus type

pub fn smbus(&mut self) -> SMBUS_W<'_>

Bit 1 - SMBus mode

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

impl W<u32, Reg<u32, _CR2>>

pub fn last(&mut self) -> LAST_W<'_>

Bit 12 - DMA last transfer

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 11 - DMA requests enable

pub fn itbufen(&mut self) -> ITBUFEN_W<'_>

Bit 10 - Buffer interrupt enable

pub fn itevten(&mut self) -> ITEVTEN_W<'_>

Bit 9 - Event interrupt enable

pub fn iterren(&mut self) -> ITERREN_W<'_>

Bit 8 - Error interrupt enable

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:5 - Peripheral clock frequency

impl W<u32, Reg<u32, _OAR1>>

pub fn addmode(&mut self) -> ADDMODE_W<'_>

Bit 15 - Addressing mode (slave mode)

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn add2(&mut self) -> ADD2_W<'_>

Bits 1:7 - Interface address

pub fn endual(&mut self) -> ENDUAL_W<'_>

Bit 0 - Dual addressing mode enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:7 - 8-bit data register

impl W<u32, Reg<u32, _SR1>>

pub fn smbalert(&mut self) -> SMBALERT_W<'_>

Bit 15 - SMBus alert

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 14 - Timeout or Tlow error

pub fn pecerr(&mut self) -> PECERR_W<'_>

Bit 12 - PEC Error in reception

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 11 - Overrun/Underrun

pub fn af(&mut self) -> AF_W<'_>

Bit 10 - Acknowledge failure

pub fn arlo(&mut self) -> ARLO_W<'_>

Bit 9 - Arbitration lost (master mode)

pub fn berr(&mut self) -> BERR_W<'_>

Bit 8 - Bus error

impl W<u32, Reg<u32, _CCR>>

pub fn f_s(&mut self) -> F_S_W<'_>

Bit 15 - I2C master mode selection

pub fn duty(&mut self) -> DUTY_W<'_>

Bit 14 - Fast mode duty cycle

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _TRISE>>

pub fn trise(&mut self) -> TRISE_W<'_>

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

impl W<u32, Reg<u32, _FLTR>>

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 0:3 - Digital noise filter

pub fn anoff(&mut self) -> ANOFF_W<'_>

Bit 4 - Analog noise filter OFF

impl W<u32, Reg<u32, _DSI_VR>>

pub fn version(&mut self) -> VERSION_W<'_>

Bits 0:31 - Version of the DSI Host

impl W<u32, Reg<u32, _DSI_CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

impl W<u32, Reg<u32, _DSIHSOT_CCR>>

pub fn tockdiv(&mut self) -> TOCKDIV_W<'_>

Bits 8:15 - TOCKDIV

pub fn txeckdiv(&mut self) -> TXECKDIV_W<'_>

Bits 0:7 - TXECKDIV

impl W<u32, Reg<u32, _DSI_LVCIDR>>

pub fn vcid(&mut self) -> VCID_W<'_>

Bits 0:1 - Virtual Channel ID

impl W<u32, Reg<u32, _DSI_LCOLCR>>

pub fn lpe(&mut self) -> LPE_W<'_>

Bit 8 - Loosely Packet Enable

pub fn colc(&mut self) -> COLC_W<'_>

Bits 0:3 - Color Coding

impl W<u32, Reg<u32, _DSI_LPCR>>

pub fn hsp(&mut self) -> HSP_W<'_>

Bit 2 - HSYNC Polarity

pub fn vsp(&mut self) -> VSP_W<'_>

Bit 1 - VSYNC Polarity

pub fn dep(&mut self) -> DEP_W<'_>

Bit 0 - Data Enable Polarity

impl W<u32, Reg<u32, _DSI_LPMCR>>

pub fn lpsize(&mut self) -> LPSIZE_W<'_>

Bits 16:23 - Largest Packet Size

pub fn vlpsize(&mut self) -> VLPSIZE_W<'_>

Bits 0:7 - VACT Largest Packet Size

impl W<u32, Reg<u32, _DSI_PCR>>

pub fn crcrxe(&mut self) -> CRCRXE_W<'_>

Bit 4 - CRC Reception Enable

pub fn eccrxe(&mut self) -> ECCRXE_W<'_>

Bit 3 - ECC Reception Enable

pub fn btae(&mut self) -> BTAE_W<'_>

Bit 2 - Bus Turn Around Enable

pub fn etrxe(&mut self) -> ETRXE_W<'_>

Bit 1 - EoTp Reception Enable

pub fn ettxe(&mut self) -> ETTXE_W<'_>

Bit 0 - EoTp Transmission Enable

impl W<u32, Reg<u32, _DSI_GVCIDR>>

pub fn vcid(&mut self) -> VCID_W<'_>

Bits 0:1 - Virtual Channel ID

impl W<u32, Reg<u32, _DSI_MCR>>

pub fn cmdm(&mut self) -> CMDM_W<'_>

Bit 0 - Command mode

impl W<u32, Reg<u32, _DSI_VMCR>>

pub fn pgo(&mut self) -> PGO_W<'_>

Bit 24 - Pattern Generator Orientation

pub fn pgm(&mut self) -> PGM_W<'_>

Bit 20 - Pattern Generator Mode

pub fn pge(&mut self) -> PGE_W<'_>

Bit 16 - Pattern Generator Enable

pub fn lpce(&mut self) -> LPCE_W<'_>

Bit 15 - Low-Power Command Enable

pub fn fbtaae(&mut self) -> FBTAAE_W<'_>

Bit 14 - Frame Bus-Turn-Around Acknowledge Enable

pub fn lphfe(&mut self) -> LPHFE_W<'_>

Bit 13 - Low-Power Horizontal Front-Porch Enable

pub fn lphbpe(&mut self) -> LPHBPE_W<'_>

Bit 12 - Low-Power Horizontal Back-Porch Enable

pub fn lvae(&mut self) -> LVAE_W<'_>

Bit 11 - Low-Power Vertical Active Enable

pub fn lpvfpe(&mut self) -> LPVFPE_W<'_>

Bit 10 - Low-power Vertical Front-porch Enable

pub fn lpvbpe(&mut self) -> LPVBPE_W<'_>

Bit 9 - Low-power Vertical Back-Porch Enable

pub fn lpvsae(&mut self) -> LPVSAE_W<'_>

Bit 8 - Low-Power Vertical Sync Active Enable

pub fn vmt(&mut self) -> VMT_W<'_>

Bits 0:1 - Video mode Type

impl W<u32, Reg<u32, _DSI_VPCR>>

pub fn vpsize(&mut self) -> VPSIZE_W<'_>

Bits 0:14 - Video Packet Size

impl W<u32, Reg<u32, _DSI_VCCR>>

pub fn numc(&mut self) -> NUMC_W<'_>

Bits 0:13 - Number of Chunks

impl W<u32, Reg<u32, _DSI_VNPCR>>

pub fn npsize(&mut self) -> NPSIZE_W<'_>

Bits 0:13 - Null Packet Size

impl W<u32, Reg<u32, _DSI_VHSACR>>

pub fn hsa(&mut self) -> HSA_W<'_>

Bits 0:12 - Horizontal Synchronism Active duration

impl W<u32, Reg<u32, _DSI_VHBPCR>>

pub fn hbp(&mut self) -> HBP_W<'_>

Bits 0:12 - Horizontal Back-Porch duration

impl W<u32, Reg<u32, _DSI_VLCR>>

pub fn hline(&mut self) -> HLINE_W<'_>

Bits 0:14 - Horizontal Line duration

impl W<u32, Reg<u32, _DSI_VVSACR>>

pub fn vsa(&mut self) -> VSA_W<'_>

Bits 0:9 - Vertical Synchronism Active duration

impl W<u32, Reg<u32, _DSI_VVBPCR>>

pub fn vbp(&mut self) -> VBP_W<'_>

Bits 0:9 - Vertical Back-Porch duration

impl W<u32, Reg<u32, _DSI_VVFPCR>>

pub fn vfp(&mut self) -> VFP_W<'_>

Bits 0:9 - Vertical Front-Porch duration

impl W<u32, Reg<u32, _DSI_VVACR>>

pub fn va(&mut self) -> VA_W<'_>

Bits 0:13 - Vertical Active duration

impl W<u32, Reg<u32, _DSI_LCCR>>

pub fn cmdsize(&mut self) -> CMDSIZE_W<'_>

Bits 0:15 - Command Size

impl W<u32, Reg<u32, _DSI_CMCR>>

pub fn mrdps(&mut self) -> MRDPS_W<'_>

Bit 24 - Maximum Read Packet Size

pub fn dlwtx(&mut self) -> DLWTX_W<'_>

Bit 19 - DCS Long Write Transmission

pub fn dsr0tx(&mut self) -> DSR0TX_W<'_>

Bit 18 - DCS Short Read Zero parameter Transmission

pub fn dsw1tx(&mut self) -> DSW1TX_W<'_>

Bit 17 - DCS Short Read One parameter Transmission

pub fn dsw0tx(&mut self) -> DSW0TX_W<'_>

Bit 16 - DCS Short Write Zero parameter Transmission

pub fn glwtx(&mut self) -> GLWTX_W<'_>

Bit 14 - Generic Long Write Transmission

pub fn gsr2tx(&mut self) -> GSR2TX_W<'_>

Bit 13 - Generic Short Read Two parameters Transmission

pub fn gsr1tx(&mut self) -> GSR1TX_W<'_>

Bit 12 - Generic Short Read One parameters Transmission

pub fn gsr0tx(&mut self) -> GSR0TX_W<'_>

Bit 11 - Generic Short Read Zero parameters Transmission

pub fn gsw2tx(&mut self) -> GSW2TX_W<'_>

Bit 10 - Generic Short Write Two parameters Transmission

pub fn gsw1tx(&mut self) -> GSW1TX_W<'_>

Bit 9 - Generic Short Write One parameters Transmission

pub fn gsw0tx(&mut self) -> GSW0TX_W<'_>

Bit 8 - Generic Short Write Zero parameters Transmission

pub fn are(&mut self) -> ARE_W<'_>

Bit 1 - Acknowledge Request Enable

pub fn teare(&mut self) -> TEARE_W<'_>

Bit 0 - Tearing Effect Acknowledge Request Enable

impl W<u32, Reg<u32, _DSI_GHCR>>

pub fn wcmsb(&mut self) -> WCMSB_W<'_>

Bits 16:23 - WordCount MSB

pub fn wclsb(&mut self) -> WCLSB_W<'_>

Bits 8:15 - WordCount LSB

pub fn vcid(&mut self) -> VCID_W<'_>

Bits 6:7 - Channel

pub fn dt(&mut self) -> DT_W<'_>

Bits 0:5 - Type

impl W<u32, Reg<u32, _DSI_GPDR>>

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 24:31 - Payload Byte 4

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 16:23 - Payload Byte 3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 8:15 - Payload Byte 2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 0:7 - Payload Byte 1

impl W<u32, Reg<u32, _DSI_GPSR>>

pub fn rcb(&mut self) -> RCB_W<'_>

Bit 6 - RCB

pub fn prdff(&mut self) -> PRDFF_W<'_>

Bit 5 - PRDFF

pub fn prdfe(&mut self) -> PRDFE_W<'_>

Bit 4 - PRDFE

pub fn pwrff(&mut self) -> PWRFF_W<'_>

Bit 3 - PWRFF

pub fn pwrfe(&mut self) -> PWRFE_W<'_>

Bit 2 - PWRFE

pub fn cmdff(&mut self) -> CMDFF_W<'_>

Bit 1 - Acknowledge Request Enable

pub fn cmdfe(&mut self) -> CMDFE_W<'_>

Bit 0 - Tearing Effect Acknowledge Request Enable

impl W<u32, Reg<u32, _DSI_TCCR1>>

pub fn hstx_tocnt(&mut self) -> HSTX_TOCNT_W<'_>

Bits 16:31 - High-Speed Transmission Timeout Counter

pub fn lprx_tocnt(&mut self) -> LPRX_TOCNT_W<'_>

Bits 0:15 - Low-power Reception Timeout Counter

impl W<u32, Reg<u32, _DSI_TCCR2>>

pub fn hsrd_tocnt(&mut self) -> HSRD_TOCNT_W<'_>

Bits 0:15 - High-Speed Read Timeout Counter

impl W<u32, Reg<u32, _DSI_TCCR3>>

pub fn lprd_tocnt(&mut self) -> LPRD_TOCNT_W<'_>

Bits 0:15 - Low-Power Read Timeout Counter

impl W<u32, Reg<u32, _DSI_TCCR4>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 24 - Presp Mode

pub fn hswr_tocnt(&mut self) -> HSWR_TOCNT_W<'_>

Bits 0:15 - High-Speed Write Timeout Counter

impl W<u32, Reg<u32, _DSI_TCCR5>>

pub fn lswr_tocnt(&mut self) -> LSWR_TOCNT_W<'_>

Bits 0:15 - Low-Power Write Timeout Counter

impl W<u32, Reg<u32, _DSI_TCCR6>>

pub fn bta_tocnt(&mut self) -> BTA_TOCNT_W<'_>

Bits 0:15 - Bus-Turn-Around Timeout Counter

impl W<u32, Reg<u32, _DSI_CLCR>>

pub fn acr(&mut self) -> ACR_W<'_>

Bit 1 - Automatic Clock lane Control

pub fn dpcc(&mut self) -> DPCC_W<'_>

Bit 0 - D-PHY Clock Control

impl W<u32, Reg<u32, _DSI_CLTCR>>

pub fn hs2lp_time(&mut self) -> HS2LP_TIME_W<'_>

Bits 16:25 - High-Speed to Low-Power Time

pub fn lp2hs_time(&mut self) -> LP2HS_TIME_W<'_>

Bits 0:9 - Low-Power to High-Speed Time

impl W<u32, Reg<u32, _DSI_DLTCR>>

pub fn hs2lp_time(&mut self) -> HS2LP_TIME_W<'_>

Bits 24:31 - High-Speed To Low-Power Time

pub fn lp2hs_time(&mut self) -> LP2HS_TIME_W<'_>

Bits 16:23 - Low-Power To High-Speed Time

pub fn mrd_time(&mut self) -> MRD_TIME_W<'_>

Bits 0:14 - Maximum Read Time

impl W<u32, Reg<u32, _DSI_PCTLR>>

pub fn cke(&mut self) -> CKE_W<'_>

Bit 2 - Clock Enable

pub fn den(&mut self) -> DEN_W<'_>

Bit 1 - Digital Enable

impl W<u32, Reg<u32, _DSI_PCCONFR>>

pub fn sw_time(&mut self) -> SW_TIME_W<'_>

Bits 8:15 - SW_TIME

pub fn nl(&mut self) -> NL_W<'_>

Bits 0:1 - NL

impl W<u32, Reg<u32, _DSI_PUCR>>

pub fn uedl(&mut self) -> UEDL_W<'_>

Bit 3 - ULPS Exit on Data Lane

pub fn urdl(&mut self) -> URDL_W<'_>

Bit 2 - ULPS Request on Data Lane

pub fn uecl(&mut self) -> UECL_W<'_>

Bit 1 - ULPS Exit on Clock Lane

pub fn urcl(&mut self) -> URCL_W<'_>

Bit 0 - ULPS Request on Clock Lane

impl W<u32, Reg<u32, _DSI_PTTCR>>

pub fn tx_trig(&mut self) -> TX_TRIG_W<'_>

Bits 0:3 - Transmission Trigger

impl W<u32, Reg<u32, _DSI_PSR>>

pub fn uan1(&mut self) -> UAN1_W<'_>

Bit 8 - ULPS Active Not lane 1

pub fn pss1(&mut self) -> PSS1_W<'_>

Bit 7 - PHY Stop State lane 1

pub fn rue0(&mut self) -> RUE0_W<'_>

Bit 6 - RX ULPS Escape lane 0

pub fn uan0(&mut self) -> UAN0_W<'_>

Bit 5 - ULPS Active Not lane 1

pub fn pss0(&mut self) -> PSS0_W<'_>

Bit 4 - PHY Stop State lane 0

pub fn uanc(&mut self) -> UANC_W<'_>

Bit 3 - ULPS Active Not Clock lane

pub fn pssc(&mut self) -> PSSC_W<'_>

Bit 2 - PHY Stop State Clock lane

pub fn pd(&mut self) -> PD_W<'_>

Bit 1 - PHY Direction

impl W<u32, Reg<u32, _DSI_IER0>>

pub fn pe4ie(&mut self) -> PE4IE_W<'_>

Bit 20 - PHY Error 4 Interrupt Enable

pub fn pe3ie(&mut self) -> PE3IE_W<'_>

Bit 19 - PHY Error 3 Interrupt Enable

pub fn pe2ie(&mut self) -> PE2IE_W<'_>

Bit 18 - PHY Error 2 Interrupt Enable

pub fn pe1ie(&mut self) -> PE1IE_W<'_>

Bit 17 - PHY Error 1 Interrupt Enable

pub fn pe0ie(&mut self) -> PE0IE_W<'_>

Bit 16 - PHY Error 0 Interrupt Enable

pub fn ae15ie(&mut self) -> AE15IE_W<'_>

Bit 15 - Acknowledge Error 15 Interrupt Enable

pub fn ae14ie(&mut self) -> AE14IE_W<'_>

Bit 14 - Acknowledge Error 14 Interrupt Enable

pub fn ae13ie(&mut self) -> AE13IE_W<'_>

Bit 13 - Acknowledge Error 13 Interrupt Enable

pub fn ae12ie(&mut self) -> AE12IE_W<'_>

Bit 12 - Acknowledge Error 12 Interrupt Enable

pub fn ae11ie(&mut self) -> AE11IE_W<'_>

Bit 11 - Acknowledge Error 11 Interrupt Enable

pub fn ae10ie(&mut self) -> AE10IE_W<'_>

Bit 10 - Acknowledge Error 10 Interrupt Enable

pub fn ae9ie(&mut self) -> AE9IE_W<'_>

Bit 9 - Acknowledge Error 9 Interrupt Enable

pub fn ae8ie(&mut self) -> AE8IE_W<'_>

Bit 8 - Acknowledge Error 8 Interrupt Enable

pub fn ae7ie(&mut self) -> AE7IE_W<'_>

Bit 7 - Acknowledge Error 7 Interrupt Enable

pub fn ae6ie(&mut self) -> AE6IE_W<'_>

Bit 6 - Acknowledge Error 6 Interrupt Enable

pub fn ae5ie(&mut self) -> AE5IE_W<'_>

Bit 5 - Acknowledge Error 5 Interrupt Enable

pub fn ae4ie(&mut self) -> AE4IE_W<'_>

Bit 4 - Acknowledge Error 4 Interrupt Enable

pub fn ae3ie(&mut self) -> AE3IE_W<'_>

Bit 3 - Acknowledge Error 3 Interrupt Enable

pub fn ae2ie(&mut self) -> AE2IE_W<'_>

Bit 2 - Acknowledge Error 2 Interrupt Enable

pub fn ae1ie(&mut self) -> AE1IE_W<'_>

Bit 1 - Acknowledge Error 1 Interrupt Enable

pub fn ae0ie(&mut self) -> AE0IE_W<'_>

Bit 0 - Acknowledge Error 0 Interrupt Enable

impl W<u32, Reg<u32, _DSI_IER1>>

pub fn gprxeie(&mut self) -> GPRXEIE_W<'_>

Bit 12 - Generic Payload Receive Error Interrupt Enable

pub fn gprdeie(&mut self) -> GPRDEIE_W<'_>

Bit 11 - Generic Payload Read Error Interrupt Enable

pub fn gptxeie(&mut self) -> GPTXEIE_W<'_>

Bit 10 - Generic Payload Transmit Error Interrupt Enable

pub fn gpwreie(&mut self) -> GPWREIE_W<'_>

Bit 9 - Generic Payload Write Error Interrupt Enable

pub fn gcwreie(&mut self) -> GCWREIE_W<'_>

Bit 8 - Generic Command Write Error Interrupt Enable

pub fn lpwreie(&mut self) -> LPWREIE_W<'_>

Bit 7 - LTDC Payload Write Error Interrupt Enable

pub fn eotpeie(&mut self) -> EOTPEIE_W<'_>

Bit 6 - EoTp Error Interrupt Enable

pub fn pseie(&mut self) -> PSEIE_W<'_>

Bit 5 - Packet Size Error Interrupt Enable

pub fn crceie(&mut self) -> CRCEIE_W<'_>

Bit 4 - CRC Error Interrupt Enable

pub fn eccmeie(&mut self) -> ECCMEIE_W<'_>

Bit 3 - ECC Multi-bit Error Interrupt Enable

pub fn eccseie(&mut self) -> ECCSEIE_W<'_>

Bit 2 - ECC Single-bit Error Interrupt Enable

pub fn tolprxie(&mut self) -> TOLPRXIE_W<'_>

Bit 1 - Timeout Low-Power Reception Interrupt Enable

pub fn tohstxie(&mut self) -> TOHSTXIE_W<'_>

Bit 0 - Timeout High-Speed Transmission Interrupt Enable

impl W<u32, Reg<u32, _DSI_FIR0>>

pub fn fpe4(&mut self) -> FPE4_W<'_>

Bit 20 - Force PHY Error 4

pub fn fpe3(&mut self) -> FPE3_W<'_>

Bit 19 - Force PHY Error 3

pub fn fpe2(&mut self) -> FPE2_W<'_>

Bit 18 - Force PHY Error 2

pub fn fpe1(&mut self) -> FPE1_W<'_>

Bit 17 - Force PHY Error 1

pub fn fpe0(&mut self) -> FPE0_W<'_>

Bit 16 - Force PHY Error 0

pub fn fae15(&mut self) -> FAE15_W<'_>

Bit 15 - Force Acknowledge Error 15

pub fn fae14(&mut self) -> FAE14_W<'_>

Bit 14 - Force Acknowledge Error 14

pub fn fae13(&mut self) -> FAE13_W<'_>

Bit 13 - Force Acknowledge Error 13

pub fn fae12(&mut self) -> FAE12_W<'_>

Bit 12 - Force Acknowledge Error 12

pub fn fae11(&mut self) -> FAE11_W<'_>

Bit 11 - Force Acknowledge Error 11

pub fn fae10(&mut self) -> FAE10_W<'_>

Bit 10 - Force Acknowledge Error 10

pub fn fae9(&mut self) -> FAE9_W<'_>

Bit 9 - Force Acknowledge Error 9

pub fn fae8(&mut self) -> FAE8_W<'_>

Bit 8 - Force Acknowledge Error 8

pub fn fae7(&mut self) -> FAE7_W<'_>

Bit 7 - Force Acknowledge Error 7

pub fn fae6(&mut self) -> FAE6_W<'_>

Bit 6 - Force Acknowledge Error 6

pub fn fae5(&mut self) -> FAE5_W<'_>

Bit 5 - Force Acknowledge Error 5

pub fn fae4(&mut self) -> FAE4_W<'_>

Bit 4 - Force Acknowledge Error 4

pub fn fae3(&mut self) -> FAE3_W<'_>

Bit 3 - Force Acknowledge Error 3

pub fn fae2(&mut self) -> FAE2_W<'_>

Bit 2 - Force Acknowledge Error 2

pub fn fae1(&mut self) -> FAE1_W<'_>

Bit 1 - Force Acknowledge Error 1

pub fn fae0(&mut self) -> FAE0_W<'_>

Bit 0 - Force Acknowledge Error 0

impl W<u32, Reg<u32, _DSI_FIR1>>

pub fn fgprxe(&mut self) -> FGPRXE_W<'_>

Bit 12 - Force Generic Payload Receive Error

pub fn fgprde(&mut self) -> FGPRDE_W<'_>

Bit 11 - Force Generic Payload Read Error

pub fn fgptxe(&mut self) -> FGPTXE_W<'_>

Bit 10 - Force Generic Payload Transmit Error

pub fn fgpwre(&mut self) -> FGPWRE_W<'_>

Bit 9 - Force Generic Payload Write Error

pub fn fgcwre(&mut self) -> FGCWRE_W<'_>

Bit 8 - Force Generic Command Write Error

pub fn flpwre(&mut self) -> FLPWRE_W<'_>

Bit 7 - Force LTDC Payload Write Error

pub fn feotpe(&mut self) -> FEOTPE_W<'_>

Bit 6 - Force EoTp Error

pub fn fpse(&mut self) -> FPSE_W<'_>

Bit 5 - Force Packet Size Error

pub fn fcrce(&mut self) -> FCRCE_W<'_>

Bit 4 - Force CRC Error

pub fn feccme(&mut self) -> FECCME_W<'_>

Bit 3 - Force ECC Multi-bit Error

pub fn feccse(&mut self) -> FECCSE_W<'_>

Bit 2 - Force ECC Single-bit Error

pub fn ftolprx(&mut self) -> FTOLPRX_W<'_>

Bit 1 - Force Timeout Low-Power Reception

pub fn ftohstx(&mut self) -> FTOHSTX_W<'_>

Bit 0 - Force Timeout High-Speed Transmission

impl W<u32, Reg<u32, _DSI_VSCR>>

pub fn ur(&mut self) -> UR_W<'_>

Bit 8 - Update Register

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

impl W<u32, Reg<u32, _DSI_LCVCIDR>>

pub fn vcid(&mut self) -> VCID_W<'_>

Bits 0:1 - Virtual Channel ID

impl W<u32, Reg<u32, _DSI_LCCCR>>

pub fn lpe(&mut self) -> LPE_W<'_>

Bit 8 - Loosely Packed Enable

pub fn colc(&mut self) -> COLC_W<'_>

Bits 0:3 - Color Coding

impl W<u32, Reg<u32, _DSI_LPMCCR>>

pub fn lpsize(&mut self) -> LPSIZE_W<'_>

Bits 16:23 - Largest Packet Size

pub fn vlpsize(&mut self) -> VLPSIZE_W<'_>

Bits 0:7 - VACT Largest Packet Size

impl W<u32, Reg<u32, _DSI_VMCCR>>

pub fn lpce(&mut self) -> LPCE_W<'_>

Bit 15 - Low-Power Command Enable

pub fn fbtaae(&mut self) -> FBTAAE_W<'_>

Bit 14 - Frame BTA Acknowledge Enable

pub fn lphfe(&mut self) -> LPHFE_W<'_>

Bit 13 - Low-Power Horizontal Front-Porch Enable

pub fn lphbpe(&mut self) -> LPHBPE_W<'_>

Bit 12 - Low-power Horizontal Back-Porch Enable

pub fn lvae(&mut self) -> LVAE_W<'_>

Bit 11 - Low-Power Vertical Active Enable

pub fn lpvfpe(&mut self) -> LPVFPE_W<'_>

Bit 10 - Low-power Vertical Front-Porch Enable

pub fn lpvbpe(&mut self) -> LPVBPE_W<'_>

Bit 9 - Low-power Vertical Back-Porch Enable

pub fn lpvsae(&mut self) -> LPVSAE_W<'_>

Bit 8 - Low-Power Vertical Sync time Enable

pub fn vmt(&mut self) -> VMT_W<'_>

Bits 0:1 - Video mode Type

impl W<u32, Reg<u32, _DSI_VPCCR>>

pub fn vpsize(&mut self) -> VPSIZE_W<'_>

Bits 0:14 - Video Packet Size

impl W<u32, Reg<u32, _DSI_VCCCR>>

pub fn numc(&mut self) -> NUMC_W<'_>

Bits 0:13 - Number of Chunks

impl W<u32, Reg<u32, _DSI_VNPCCR>>

pub fn npsize(&mut self) -> NPSIZE_W<'_>

Bits 0:13 - Null Packet Size

impl W<u32, Reg<u32, _DSI_VHSACCR>>

pub fn hsa(&mut self) -> HSA_W<'_>

Bits 0:12 - Horizontal Synchronism Active duration

impl W<u32, Reg<u32, _DSI_VHBPCCR>>

pub fn hbp(&mut self) -> HBP_W<'_>

Bits 0:12 - Horizontal Back-Porch duration

impl W<u32, Reg<u32, _DSI_VLCCR>>

pub fn hline(&mut self) -> HLINE_W<'_>

Bits 0:14 - Horizontal Line duration

impl W<u32, Reg<u32, _DSI_VVSACCR>>

pub fn vsa(&mut self) -> VSA_W<'_>

Bits 0:9 - Vertical Synchronism Active duration

impl W<u32, Reg<u32, _DSI_VVBPCCR>>

pub fn vbp(&mut self) -> VBP_W<'_>

Bits 0:9 - Vertical Back-Porch duration

impl W<u32, Reg<u32, _DSI_VVFPCCR>>

pub fn vfp(&mut self) -> VFP_W<'_>

Bits 0:9 - Vertical Front-Porch duration

impl W<u32, Reg<u32, _DSI_VVACCR>>

pub fn va(&mut self) -> VA_W<'_>

Bits 0:13 - Vertical Active duration

impl W<u32, Reg<u32, _DSI_WCFGR>>

pub fn vspol(&mut self) -> VSPOL_W<'_>

Bit 7 - VSync Polarity

pub fn ar(&mut self) -> AR_W<'_>

Bit 6 - Automatic Refresh

pub fn tepol(&mut self) -> TEPOL_W<'_>

Bit 5 - TE Polarity

pub fn tesrc(&mut self) -> TESRC_W<'_>

Bit 4 - TE Source

pub fn colmux(&mut self) -> COLMUX_W<'_>

Bits 1:3 - Color Multiplexing

pub fn dsim(&mut self) -> DSIM_W<'_>

Bit 0 - DSI Mode

impl W<u32, Reg<u32, _DSI_WCR>>

pub fn dsien(&mut self) -> DSIEN_W<'_>

Bit 3 - DSI Enable

pub fn ltdcen(&mut self) -> LTDCEN_W<'_>

Bit 2 - LTDC Enable

pub fn shtdn(&mut self) -> SHTDN_W<'_>

Bit 1 - Shutdown

pub fn colm(&mut self) -> COLM_W<'_>

Bit 0 - Color Mode

impl W<u32, Reg<u32, _DSI_WIER>>

pub fn rrie(&mut self) -> RRIE_W<'_>

Bit 13 - Regulator Ready Interrupt Enable

pub fn plluie(&mut self) -> PLLUIE_W<'_>

Bit 10 - PLL Unlock Interrupt Enable

pub fn plllie(&mut self) -> PLLLIE_W<'_>

Bit 9 - PLL Lock Interrupt Enable

pub fn erie(&mut self) -> ERIE_W<'_>

Bit 1 - End of Refresh Interrupt Enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 0 - Tearing Effect Interrupt Enable

impl W<u32, Reg<u32, _DSI_WIFCR>>

pub fn crrif(&mut self) -> CRRIF_W<'_>

Bit 13 - Clear Regulator Ready Interrupt Flag

pub fn cplluif(&mut self) -> CPLLUIF_W<'_>

Bit 10 - Clear PLL Unlock Interrupt Flag

pub fn cplllif(&mut self) -> CPLLLIF_W<'_>

Bit 9 - Clear PLL Lock Interrupt Flag

pub fn cerif(&mut self) -> CERIF_W<'_>

Bit 1 - Clear End of Refresh Interrupt Flag

pub fn cteif(&mut self) -> CTEIF_W<'_>

Bit 0 - Clear Tearing Effect Interrupt Flag

impl W<u32, Reg<u32, _DSI_WPCR1>>

pub fn tclkposten(&mut self) -> TCLKPOSTEN_W<'_>

Bit 27 - custom time for tCLK-POST Enable

pub fn tlpxcen(&mut self) -> TLPXCEN_W<'_>

Bit 26 - custom time for tLPX for Clock lane Enable

pub fn thsexiten(&mut self) -> THSEXITEN_W<'_>

Bit 25 - custom time for tHS-EXIT Enable

pub fn tlpxden(&mut self) -> TLPXDEN_W<'_>

Bit 24 - custom time for tLPX for Data lanes Enable

pub fn thszeroen(&mut self) -> THSZEROEN_W<'_>

Bit 23 - custom time for tHS-ZERO Enable

pub fn thstrailen(&mut self) -> THSTRAILEN_W<'_>

Bit 22 - custom time for tHS-TRAIL Enable

pub fn thsprepen(&mut self) -> THSPREPEN_W<'_>

Bit 21 - custom time for tHS-PREPARE Enable

pub fn tclkzeroen(&mut self) -> TCLKZEROEN_W<'_>

Bit 20 - custom time for tCLK-ZERO Enable

pub fn tclkprepen(&mut self) -> TCLKPREPEN_W<'_>

Bit 19 - custom time for tCLK-PREPARE Enable

pub fn pden(&mut self) -> PDEN_W<'_>

Bit 18 - Pull-Down Enable

pub fn tddl(&mut self) -> TDDL_W<'_>

Bit 16 - Turn Disable Data Lanes

pub fn cdoffdl(&mut self) -> CDOFFDL_W<'_>

Bit 14 - Contention Detection OFF on Data Lanes

pub fn ftxsmdl(&mut self) -> FTXSMDL_W<'_>

Bit 13 - Force in TX Stop Mode the Data Lanes

pub fn ftxsmcl(&mut self) -> FTXSMCL_W<'_>

Bit 12 - Force in TX Stop Mode the Clock Lane

pub fn hsidl1(&mut self) -> HSIDL1_W<'_>

Bit 11 - Invert the High-Speed data signal on Data Lane 1

pub fn hsidl0(&mut self) -> HSIDL0_W<'_>

Bit 10 - Invert the Hight-Speed data signal on Data Lane 0

pub fn hsicl(&mut self) -> HSICL_W<'_>

Bit 9 - Invert Hight-Speed data signal on Clock Lane

pub fn swdl1(&mut self) -> SWDL1_W<'_>

Bit 8 - Swap Data Lane 1 pins

pub fn swdl0(&mut self) -> SWDL0_W<'_>

Bit 7 - Swap Data Lane 0 pins

pub fn swcl(&mut self) -> SWCL_W<'_>

Bit 6 - Swap Clock Lane pins

pub fn uix4(&mut self) -> UIX4_W<'_>

Bits 0:5 - Unit Interval multiplied by 4

impl W<u32, Reg<u32, _DSI_WPCR2>>

pub fn lprxft(&mut self) -> LPRXFT_W<'_>

Bits 25:26 - Low-Power RX low-pass Filtering Tuning

pub fn flprxlpm(&mut self) -> FLPRXLPM_W<'_>

Bit 22 - Forces LP Receiver in Low-Power Mode

pub fn hstxsrcdl(&mut self) -> HSTXSRCDL_W<'_>

Bits 18:19 - High-Speed Transmission Slew Rate Control on Data Lanes

pub fn hstxsrccl(&mut self) -> HSTXSRCCL_W<'_>

Bits 16:17 - High-Speed Transmission Slew Rate Control on Clock Lane

pub fn sdcc(&mut self) -> SDCC_W<'_>

Bit 12 - SDD Control

pub fn lpsrdl(&mut self) -> LPSRDL_W<'_>

Bits 8:9 - Low-Power transmission Slew Rate Compensation on Data Lanes

pub fn lpsrcl(&mut self) -> LPSRCL_W<'_>

Bits 6:7 - Low-Power transmission Slew Rate Compensation on Clock Lane

pub fn hstxdll(&mut self) -> HSTXDLL_W<'_>

Bits 2:3 - High-Speed Transmission Delay on Data Lanes

pub fn hstxdcl(&mut self) -> HSTXDCL_W<'_>

Bits 0:1 - High-Speed Transmission Delay on Clock Lane

impl W<u32, Reg<u32, _DSI_WPCR3>>

pub fn thstrail(&mut self) -> THSTRAIL_W<'_>

Bits 24:31 - tHSTRAIL

pub fn thsprep(&mut self) -> THSPREP_W<'_>

Bits 16:23 - tHS-PREPARE

pub fn tclkzeo(&mut self) -> TCLKZEO_W<'_>

Bits 8:15 - tCLK-ZERO

pub fn tclkprep(&mut self) -> TCLKPREP_W<'_>

Bits 0:7 - tCLK-PREPARE

impl W<u32, Reg<u32, _DSI_WPCR4>>

pub fn tlpxc(&mut self) -> TLPXC_W<'_>

Bits 24:31 - tLPXC for Clock lane

pub fn thsexit(&mut self) -> THSEXIT_W<'_>

Bits 16:23 - tHSEXIT

pub fn tlpxd(&mut self) -> TLPXD_W<'_>

Bits 8:15 - tLPX for Data lanes

pub fn thszero(&mut self) -> THSZERO_W<'_>

Bits 0:7 - tHS-ZERO

impl W<u32, Reg<u32, _DSI_WPCR5>>

pub fn thszero(&mut self) -> THSZERO_W<'_>

Bits 0:7 - tCLK-POST

impl W<u32, Reg<u32, _DSI_WRPCR>>

pub fn regen(&mut self) -> REGEN_W<'_>

Bit 24 - Regulator Enable

pub fn odf(&mut self) -> ODF_W<'_>

Bits 16:17 - PLL Output Division Factor

pub fn idf(&mut self) -> IDF_W<'_>

Bits 11:14 - PLL Input Division Factor

pub fn ndiv(&mut self) -> NDIV_W<'_>

Bits 2:8 - PLL Loop Division Factor

pub fn pllen(&mut self) -> PLLEN_W<'_>

Bit 0 - PLL Enable

impl W<u32, Reg<u32, _CR>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 24:31 - Clock prescaler

pub fn pmm(&mut self) -> PMM_W<'_>

Bit 23 - Polling match mode

pub fn apms(&mut self) -> APMS_W<'_>

Bit 22 - Automatic poll mode stop

pub fn toie(&mut self) -> TOIE_W<'_>

Bit 20 - TimeOut interrupt enable

pub fn smie(&mut self) -> SMIE_W<'_>

Bit 19 - Status match interrupt enable

pub fn ftie(&mut self) -> FTIE_W<'_>

Bit 18 - FIFO threshold interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 17 - Transfer complete interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 16 - Transfer error interrupt enable

pub fn fthres(&mut self) -> FTHRES_W<'_>

Bits 8:12 - IFO threshold level

pub fn fsel(&mut self) -> FSEL_W<'_>

Bit 7 - FLASH memory selection

pub fn dfm(&mut self) -> DFM_W<'_>

Bit 6 - Dual-flash mode

pub fn sshift(&mut self) -> SSHIFT_W<'_>

Bit 4 - Sample shift

pub fn tcen(&mut self) -> TCEN_W<'_>

Bit 3 - Timeout counter enable

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 2 - DMA enable

pub fn abort(&mut self) -> ABORT_W<'_>

Bit 1 - Abort request

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

impl W<u32, Reg<u32, _DCR>>

pub fn fsize(&mut self) -> FSIZE_W<'_>

Bits 16:20 - FLASH memory size

pub fn csht(&mut self) -> CSHT_W<'_>

Bits 8:10 - Chip select high time

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bit 0 - Mode 0 / mode 3

impl W<u32, Reg<u32, _FCR>>

pub fn ctof(&mut self) -> CTOF_W<'_>

Bit 4 - Clear timeout flag

pub fn csmf(&mut self) -> CSMF_W<'_>

Bit 3 - Clear status match flag

pub fn ctcf(&mut self) -> CTCF_W<'_>

Bit 1 - Clear transfer complete flag

pub fn ctef(&mut self) -> CTEF_W<'_>

Bit 0 - Clear transfer error flag

impl W<u32, Reg<u32, _DLR>>

pub fn dl(&mut self) -> DL_W<'_>

Bits 0:31 - Data length

impl W<u32, Reg<u32, _CCR>>

pub fn ddrm(&mut self) -> DDRM_W<'_>

Bit 31 - Double data rate mode

pub fn dhhc(&mut self) -> DHHC_W<'_>

Bit 30 - DDR hold half cycle

pub fn sioo(&mut self) -> SIOO_W<'_>

Bit 28 - Send instruction only once mode

pub fn fmode(&mut self) -> FMODE_W<'_>

Bits 26:27 - Functional mode

pub fn dmode(&mut self) -> DMODE_W<'_>

Bits 24:25 - Data mode

pub fn dcyc(&mut self) -> DCYC_W<'_>

Bits 18:22 - Number of dummy cycles

pub fn absize(&mut self) -> ABSIZE_W<'_>

Bits 16:17 - Alternate bytes size

pub fn abmode(&mut self) -> ABMODE_W<'_>

Bits 14:15 - Alternate bytes mode

pub fn adsize(&mut self) -> ADSIZE_W<'_>

Bits 12:13 - Address size

pub fn admode(&mut self) -> ADMODE_W<'_>

Bits 10:11 - Address mode

pub fn imode(&mut self) -> IMODE_W<'_>

Bits 8:9 - Instruction mode

pub fn instruction(&mut self) -> INSTRUCTION_W<'_>

Bits 0:7 - Instruction

impl W<u32, Reg<u32, _AR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:31 - Address

impl W<u32, Reg<u32, _ABR>>

pub fn alternate(&mut self) -> ALTERNATE_W<'_>

Bits 0:31 - ALTERNATE

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _PSMKR>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 0:31 - Status mask

impl W<u32, Reg<u32, _PSMAR>>

pub fn match_(&mut self) -> MATCH_W<'_>

Bits 0:31 - Status match

impl W<u32, Reg<u32, _PIR>>

pub fn interval(&mut self) -> INTERVAL_W<'_>

Bits 0:15 - Polling interval

impl W<u32, Reg<u32, _LPTR>>

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bits 0:15 - Timeout period

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP