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#[doc = "Reader of register CCMR1_Output"] pub type R = crate::R<u32, super::CCMR1_OUTPUT>; #[doc = "Writer for register CCMR1_Output"] pub type W = crate::W<u32, super::CCMR1_OUTPUT>; #[doc = "Register CCMR1_Output `reset()`'s with value 0"] impl crate::ResetValue for super::CCMR1_OUTPUT { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `OC2CE`"] pub type OC2CE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `OC2CE`"] pub struct OC2CE_W<'a> { w: &'a mut W, } impl<'a> OC2CE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); self.w } } #[doc = "OC2M\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum OC2M_A { #[doc = "0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] FROZEN = 0, #[doc = "1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] ACTIVEONMATCH = 1, #[doc = "2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] INACTIVEONMATCH = 2, #[doc = "3: OCyREF toggles when TIMx_CNT=TIMx_CCRy"] TOGGLE = 3, #[doc = "4: OCyREF is forced low"] FORCEINACTIVE = 4, #[doc = "5: OCyREF is forced high"] FORCEACTIVE = 5, #[doc = "6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"] PWMMODE1 = 6, #[doc = "7: Inversely to PwmMode1"] PWMMODE2 = 7, } impl From<OC2M_A> for u8 { #[inline(always)] fn from(variant: OC2M_A) -> Self { variant as _ } } #[doc = "Reader of field `OC2M`"] pub type OC2M_R = crate::R<u8, OC2M_A>; impl OC2M_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> OC2M_A { match self.bits { 0 => OC2M_A::FROZEN, 1 => OC2M_A::ACTIVEONMATCH, 2 => OC2M_A::INACTIVEONMATCH, 3 => OC2M_A::TOGGLE, 4 => OC2M_A::FORCEINACTIVE, 5 => OC2M_A::FORCEACTIVE, 6 => OC2M_A::PWMMODE1, 7 => OC2M_A::PWMMODE2, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `FROZEN`"] #[inline(always)] pub fn is_frozen(&self) -> bool { *self == OC2M_A::FROZEN } #[doc = "Checks if the value of the field is `ACTIVEONMATCH`"] #[inline(always)] pub fn is_active_on_match(&self) -> bool { *self == OC2M_A::ACTIVEONMATCH } #[doc = "Checks if the value of the field is `INACTIVEONMATCH`"] #[inline(always)] pub fn is_inactive_on_match(&self) -> bool { *self == OC2M_A::INACTIVEONMATCH } #[doc = "Checks if the value of the field is `TOGGLE`"] #[inline(always)] pub fn is_toggle(&self) -> bool { *self == OC2M_A::TOGGLE } #[doc = "Checks if the value of the field is `FORCEINACTIVE`"] #[inline(always)] pub fn is_force_inactive(&self) -> bool { *self == OC2M_A::FORCEINACTIVE } #[doc = "Checks if the value of the field is `FORCEACTIVE`"] #[inline(always)] pub fn is_force_active(&self) -> bool { *self == OC2M_A::FORCEACTIVE } #[doc = "Checks if the value of the field is `PWMMODE1`"] #[inline(always)] pub fn is_pwm_mode1(&self) -> bool { *self == OC2M_A::PWMMODE1 } #[doc = "Checks if the value of the field is `PWMMODE2`"] #[inline(always)] pub fn is_pwm_mode2(&self) -> bool { *self == OC2M_A::PWMMODE2 } } #[doc = "Write proxy for field `OC2M`"] pub struct OC2M_W<'a> { w: &'a mut W, } impl<'a> OC2M_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: OC2M_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] #[inline(always)] pub fn frozen(self) -> &'a mut W { self.variant(OC2M_A::FROZEN) } #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] #[inline(always)] pub fn active_on_match(self) -> &'a mut W { self.variant(OC2M_A::ACTIVEONMATCH) } #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] #[inline(always)] pub fn inactive_on_match(self) -> &'a mut W { self.variant(OC2M_A::INACTIVEONMATCH) } #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] #[inline(always)] pub fn toggle(self) -> &'a mut W { self.variant(OC2M_A::TOGGLE) } #[doc = "OCyREF is forced low"] #[inline(always)] pub fn force_inactive(self) -> &'a mut W { self.variant(OC2M_A::FORCEINACTIVE) } #[doc = "OCyREF is forced high"] #[inline(always)] pub fn force_active(self) -> &'a mut W { self.variant(OC2M_A::FORCEACTIVE) } #[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"] #[inline(always)] pub fn pwm_mode1(self) -> &'a mut W { self.variant(OC2M_A::PWMMODE1) } #[doc = "Inversely to PwmMode1"] #[inline(always)] pub fn pwm_mode2(self) -> &'a mut W { self.variant(OC2M_A::PWMMODE2) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12); self.w } } #[doc = "OC2PE\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OC2PE_A { #[doc = "0: Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] DISABLED = 0, #[doc = "1: Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] ENABLED = 1, } impl From<OC2PE_A> for bool { #[inline(always)] fn from(variant: OC2PE_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `OC2PE`"] pub type OC2PE_R = crate::R<bool, OC2PE_A>; impl OC2PE_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> OC2PE_A { match self.bits { false => OC2PE_A::DISABLED, true => OC2PE_A::ENABLED, } } #[doc = "Checks if the value of the field is `DISABLED`"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == OC2PE_A::DISABLED } #[doc = "Checks if the value of the field is `ENABLED`"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == OC2PE_A::ENABLED } } #[doc = "Write proxy for field `OC2PE`"] pub struct OC2PE_W<'a> { w: &'a mut W, } impl<'a> OC2PE_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: OC2PE_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] #[inline(always)] pub fn disabled(self) -> &'a mut W { self.variant(OC2PE_A::DISABLED) } #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] #[inline(always)] pub fn enabled(self) -> &'a mut W { self.variant(OC2PE_A::ENABLED) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); self.w } } #[doc = "Reader of field `OC2FE`"] pub type OC2FE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `OC2FE`"] pub struct OC2FE_W<'a> { w: &'a mut W, } impl<'a> OC2FE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); self.w } } #[doc = "CC2S\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum CC2S_A { #[doc = "0: CC2 channel is configured as output"] OUTPUT = 0, } impl From<CC2S_A> for u8 { #[inline(always)] fn from(variant: CC2S_A) -> Self { variant as _ } } #[doc = "Reader of field `CC2S`"] pub type CC2S_R = crate::R<u8, CC2S_A>; impl CC2S_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<u8, CC2S_A> { use crate::Variant::*; match self.bits { 0 => Val(CC2S_A::OUTPUT), i => Res(i), } } #[doc = "Checks if the value of the field is `OUTPUT`"] #[inline(always)] pub fn is_output(&self) -> bool { *self == CC2S_A::OUTPUT } } #[doc = "Write proxy for field `CC2S`"] pub struct CC2S_W<'a> { w: &'a mut W, } impl<'a> CC2S_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: CC2S_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "CC2 channel is configured as output"] #[inline(always)] pub fn output(self) -> &'a mut W { self.variant(CC2S_A::OUTPUT) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8); self.w } } #[doc = "Reader of field `OC1CE`"] pub type OC1CE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `OC1CE`"] pub struct OC1CE_W<'a> { w: &'a mut W, } impl<'a> OC1CE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); self.w } } #[doc = "OC1M"] pub type OC1M_A = OC2M_A; #[doc = "Reader of field `OC1M`"] pub type OC1M_R = crate::R<u8, OC2M_A>; #[doc = "Write proxy for field `OC1M`"] pub struct OC1M_W<'a> { w: &'a mut W, } impl<'a> OC1M_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: OC1M_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] #[inline(always)] pub fn frozen(self) -> &'a mut W { self.variant(OC2M_A::FROZEN) } #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] #[inline(always)] pub fn active_on_match(self) -> &'a mut W { self.variant(OC2M_A::ACTIVEONMATCH) } #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] #[inline(always)] pub fn inactive_on_match(self) -> &'a mut W { self.variant(OC2M_A::INACTIVEONMATCH) } #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] #[inline(always)] pub fn toggle(self) -> &'a mut W { self.variant(OC2M_A::TOGGLE) } #[doc = "OCyREF is forced low"] #[inline(always)] pub fn force_inactive(self) -> &'a mut W { self.variant(OC2M_A::FORCEINACTIVE) } #[doc = "OCyREF is forced high"] #[inline(always)] pub fn force_active(self) -> &'a mut W { self.variant(OC2M_A::FORCEACTIVE) } #[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"] #[inline(always)] pub fn pwm_mode1(self) -> &'a mut W { self.variant(OC2M_A::PWMMODE1) } #[doc = "Inversely to PwmMode1"] #[inline(always)] pub fn pwm_mode2(self) -> &'a mut W { self.variant(OC2M_A::PWMMODE2) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4); self.w } } #[doc = "OC1PE\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OC1PE_A { #[doc = "0: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately"] DISABLED = 0, #[doc = "1: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event"] ENABLED = 1, } impl From<OC1PE_A> for bool { #[inline(always)] fn from(variant: OC1PE_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `OC1PE`"] pub type OC1PE_R = crate::R<bool, OC1PE_A>; impl OC1PE_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> OC1PE_A { match self.bits { false => OC1PE_A::DISABLED, true => OC1PE_A::ENABLED, } } #[doc = "Checks if the value of the field is `DISABLED`"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == OC1PE_A::DISABLED } #[doc = "Checks if the value of the field is `ENABLED`"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == OC1PE_A::ENABLED } } #[doc = "Write proxy for field `OC1PE`"] pub struct OC1PE_W<'a> { w: &'a mut W, } impl<'a> OC1PE_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: OC1PE_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately"] #[inline(always)] pub fn disabled(self) -> &'a mut W { self.variant(OC1PE_A::DISABLED) } #[doc = "Preload register on CCR1 enabled. Preload value is loaded into active register on each update event"] #[inline(always)] pub fn enabled(self) -> &'a mut W { self.variant(OC1PE_A::ENABLED) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `OC1FE`"] pub type OC1FE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `OC1FE`"] pub struct OC1FE_W<'a> { w: &'a mut W, } impl<'a> OC1FE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); self.w } } #[doc = "CC1S\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum CC1S_A { #[doc = "0: CC1 channel is configured as output"] OUTPUT = 0, } impl From<CC1S_A> for u8 { #[inline(always)] fn from(variant: CC1S_A) -> Self { variant as _ } } #[doc = "Reader of field `CC1S`"] pub type CC1S_R = crate::R<u8, CC1S_A>; impl CC1S_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<u8, CC1S_A> { use crate::Variant::*; match self.bits { 0 => Val(CC1S_A::OUTPUT), i => Res(i), } } #[doc = "Checks if the value of the field is `OUTPUT`"] #[inline(always)] pub fn is_output(&self) -> bool { *self == CC1S_A::OUTPUT } } #[doc = "Write proxy for field `CC1S`"] pub struct CC1S_W<'a> { w: &'a mut W, } impl<'a> CC1S_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: CC1S_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "CC1 channel is configured as output"] #[inline(always)] pub fn output(self) -> &'a mut W { self.variant(CC1S_A::OUTPUT) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); self.w } } impl R { #[doc = "Bit 15 - OC2CE"] #[inline(always)] pub fn oc2ce(&self) -> OC2CE_R { OC2CE_R::new(((self.bits >> 15) & 0x01) != 0) } #[doc = "Bits 12:14 - OC2M"] #[inline(always)] pub fn oc2m(&self) -> OC2M_R { OC2M_R::new(((self.bits >> 12) & 0x07) as u8) } #[doc = "Bit 11 - OC2PE"] #[inline(always)] pub fn oc2pe(&self) -> OC2PE_R { OC2PE_R::new(((self.bits >> 11) & 0x01) != 0) } #[doc = "Bit 10 - OC2FE"] #[inline(always)] pub fn oc2fe(&self) -> OC2FE_R { OC2FE_R::new(((self.bits >> 10) & 0x01) != 0) } #[doc = "Bits 8:9 - CC2S"] #[inline(always)] pub fn cc2s(&self) -> CC2S_R { CC2S_R::new(((self.bits >> 8) & 0x03) as u8) } #[doc = "Bit 7 - OC1CE"] #[inline(always)] pub fn oc1ce(&self) -> OC1CE_R { OC1CE_R::new(((self.bits >> 7) & 0x01) != 0) } #[doc = "Bits 4:6 - OC1M"] #[inline(always)] pub fn oc1m(&self) -> OC1M_R { OC1M_R::new(((self.bits >> 4) & 0x07) as u8) } #[doc = "Bit 3 - OC1PE"] #[inline(always)] pub fn oc1pe(&self) -> OC1PE_R { OC1PE_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 2 - OC1FE"] #[inline(always)] pub fn oc1fe(&self) -> OC1FE_R { OC1FE_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bits 0:1 - CC1S"] #[inline(always)] pub fn cc1s(&self) -> CC1S_R { CC1S_R::new((self.bits & 0x03) as u8) } } impl W { #[doc = "Bit 15 - OC2CE"] #[inline(always)] pub fn oc2ce(&mut self) -> OC2CE_W { OC2CE_W { w: self } } #[doc = "Bits 12:14 - OC2M"] #[inline(always)] pub fn oc2m(&mut self) -> OC2M_W { OC2M_W { w: self } } #[doc = "Bit 11 - OC2PE"] #[inline(always)] pub fn oc2pe(&mut self) -> OC2PE_W { OC2PE_W { w: self } } #[doc = "Bit 10 - OC2FE"] #[inline(always)] pub fn oc2fe(&mut self) -> OC2FE_W { OC2FE_W { w: self } } #[doc = "Bits 8:9 - CC2S"] #[inline(always)] pub fn cc2s(&mut self) -> CC2S_W { CC2S_W { w: self } } #[doc = "Bit 7 - OC1CE"] #[inline(always)] pub fn oc1ce(&mut self) -> OC1CE_W { OC1CE_W { w: self } } #[doc = "Bits 4:6 - OC1M"] #[inline(always)] pub fn oc1m(&mut self) -> OC1M_W { OC1M_W { w: self } } #[doc = "Bit 3 - OC1PE"] #[inline(always)] pub fn oc1pe(&mut self) -> OC1PE_W { OC1PE_W { w: self } } #[doc = "Bit 2 - OC1FE"] #[inline(always)] pub fn oc1fe(&mut self) -> OC1FE_W { OC1FE_W { w: self } } #[doc = "Bits 0:1 - CC1S"] #[inline(always)] pub fn cc1s(&mut self) -> CC1S_W { CC1S_W { w: self } } }