Struct EnumBitfieldStruct Copy item path Source #[repr(transparent)]
pub struct EnumBitfieldStruct<Q: RegNumberT, T>(pub Q, _);Expand description Proxy struct for enumerated bitfields
Disable ADC120_GBADI interrupt generation on group B scan completion.
Enable ADC120_GBADI interrupt generation on group B scan completion.
Deselect double-trigger mode.
Select double-trigger mode.
Start A/D conversion by the synchronous trigger (ELC).
Start A/D conversion by the asynchronous trigger (ADTRG0).
Disable A/D conversion to be started by the synchronous or asynchronous trigger
Enable A/D conversion to be started by the synchronous or asynchronous trigger
High-speed A/D conversion mode
Low-power A/D conversion mode
Stop A/D conversion process.
Start A/D conversion process.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
1-time conversion (no addition, same as normal conversion)
2-time conversion (1 addition)
3-time conversion (2 additions)
4-time conversion (3 additions)
16-time conversion (15 additions)
Disable automatic clearing
Enable automatic clearing
Setting prohibited when self-diagnosis is enabled
Select rotation mode for self-diagnosis voltage
Select mixed mode for self-diagnosis voltage
Disable ADC12 self-diagnosis
Enable ADC12 self-diagnosis
Select right-justified for the A/D data register format
Select left-justified for the A/D data register format
Do not select addition/average mode for temperature sensor output.
Select addition/average mode for temperature sensor output.
Do not select addition/average mode for internal reference voltage.
Select addition/average mode for internal reference voltage.
Disable A/D conversion of temperature sensor output
Enable A/D conversion of temperature sensor output
Disable A/D conversion of internal reference voltage
Enable A/D conversion of internal reference voltage
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Do not select associated input channel.
Select associated input channel.
Self-diagnosis not executed after power-on.
Self-diagnosis was executed using the 0 V voltage.
Self-diagnosis was executed using the reference voltage × 1/2.
Self-diagnosis was executed using the reference voltage .
The disconnection detection assist function is disabled
The number of states for the discharge or precharge period.
Normal conversion mode (default)
Operate without group priority control.
Operate with group priority control.
Disable rescanning of the group that was stopped in group priority operation
Enable rescanning of the group that was stopped in group priority operation.
Single scan is not continuously activated.
Single scan for the group with the lower-priority is continuously activated.
VCC0 is selected as the high-potential reference voltage
VREFH0 is selected as the high-potential reference voltage
Internal reference voltage is selected as the high-potential reference voltage
No reference voltage pin is selected (internal node discharge)
VSS0 is selected as the low-potential reference voltage.
VREFL0 is selected as the low-potential reference voltage.
Window A/B composite conditions are not met.
Window A/B composite conditions are met.
Window A comparison conditions are not met.
Window A comparison conditions are met.
Window B comparison conditions are not met.
Window B comparison conditions are met.
Output ADC120_WCMPM when window A OR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM.
Output ADC120_WCMPM when window A EXOR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM.
Output ADC120_WCMPM when window A AND window B comparison conditions are met. Otherwise, output ADC120_WCMPUM.
Disable compare window B operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs.
Enable compare window B operation.
Disable compare window A operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs.
Enable compare window A operation.
Disable ADC120_CMPBI interrupt when comparison conditions (window B) are met.
Enable ADC120_CMPBI interrupt when comparison conditions (window B) are met.
Disable window function Window A and window B operate as a comparator to compare the single value on the lower side with the A/D conversion result.
Enable window function Window A and window B operate as a comparator to compare the two values on the upper and lower sides with the A/D conversion result.
Disable ADC120_CMPAI interrupt when comparison conditions (window A) are met.
Enable ADC120_CMPAI interrupt when comparison conditions (window A) are met.
Exclude the temperature sensor output from the compare Window A target range.
Include the temperature sensor output in the compare Window A target range.
Exclude the internal reference voltage from the compare Window A target range.
Include the internal reference voltage in the compare Window A target range.
When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted valueCompare Window A Temperature Sensor Output Comparison Condition Select When window function is enabled (ADCMPCR.WCMPE = 1) : Compare Window A Temperature Sensor Output Comparison ConditionA/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1) : ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
Disable compare function for associated input channel
Enable compare function for associated input channel
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
Comparison conditions are not met.
Comparison conditions are met.
When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADWINLLB value, or ADWINULB value < A/D-converted value
When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADWINLLB value < A/D-converted value < ADWINULB value
Comparison conditions are not met.
Comparison conditions are met.
The count is forcibly stopped
Pulse width measurement mode
Pulse period measurement mode
Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register
Underflow event signal from AGTW0
External event input is disabled during Software Standby mode
External event input is enabled during Software Standby mode
AGTOn pin output disabled
Filter sampled at PCLKB/8
Filter sampled at PCLKB/32
Event is counted during polarity period specified for AGTEEn pin
An event is counted during the low-level period
An event is counted during the high-level period
AGT Compare match A register disabled
AGT Compare match A register enabled
AGTOAn pin output disabled
AGTOAn pin output enabled
AGTOAn pin output is started on low. i.e. normal output
AGTOAn pin output is started on high. i.e. inverted output
Compare match B register disabled
Compare match B register enabled
AGTOBn pin output disabled
AGTOBn pin output enabled
AGTOBn pin output is started on low. i.e. normal output
AGTOBn pin output is started on high. i.e. inverted output
A bus error is not reported.
A bus error is not reported.
Peripheral module clock B (PCLKB)
Both rising and falling edges
Internal clock (internally generated signal)
Peripheral module clock B (PCLKB)
Disable digital filtering
Use sampling clock for the digital filter as the frequency measuring clock
Use sampling clock for the digital filter as the frequency measuring clock divided by 4
Use sampling clock for the digital filter as the frequency measuring clock divided by 16.
The CASTR.FERRF flag is cleared
The CASTR.MENDF flag is cleared
The CASTR.OVFF flag is cleared.
Clock frequency is within the allowable range
Clock frequency has deviated beyond the allowable range (frequency error).
Measurement is in progress
Counter has not overflowed
8-bit CRC-8 (X8 + X2 + X + 1)
16-bit CRC-16 (X16 + X15 + X2 + 1)
16-bit CRC-CCITT (X16 + X12 + X5 + 1)
32-bit CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 +X10 + X8 + X7 + X5 + X4 + X2 + X + 1)
32-bit CRC-32C (X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1)
No calculation is executed
Generate CRC code for LSB-first communication
Generate CRC code for MSB-first communication
Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register
OCD is not requesting debug power up
OCD is requesting debug power up
Debug power-up request is not acknowledged
Debug power-up request is acknowledged
Enable IWDT reset/interrupt
Mask IWDT reset/interrupt and stop IWDT counter
Enable WDT reset/interrupt
Mask WDT reset/interrupt and stop WDT counter
Enable LVD1 reset/interrupt
Mask LVD1 reset/interrupt
Enable LVD2 reset/interrupt
Mask LVD2 reset/interrupt
Enable SRAM parity error reset/interrupt
Mask SRAM parity error reset/interrupt
Set DOPCF flag when data mismatch is detected
Set DOPCF flag when data match is detected
Transfer information read is not skipped
Transfer information read is skipped when vector numbers match
DTC transfer operation is not in progress.
DTC transfer operation is in progress.
ELC function is disabled.
Software event is generated.
Write to SEG bit disabled.
Write to SEG bit enabled.
Write to ELSEGR register enabled.
Write to ELSEGR register disabled.
Access to the data flash is disabled
Access to the data flash is enabled
FMS1 = 0: Read mode FMS1 = 1: Data flash P/E mode.
FMS1 = 0: Code flash P/E mode FMS1 = 1: Setting prohibited.
Programming of the code flash is enabled
Programming of the code flash is disabled.
Data is not read or next data is requested
Data reading is complete.
The registers related to the flash programming are not reset
The registers related to the flash programming are reset.
The read processing of the consecutive read command at each address is not terminated.
The read processing of the consecutive read command at each address is terminated and read data is stored to the FRBH and FRBL registers.
The software command of the FCR register is not terminated.
The software command of the FCR register is terminated.
The software command of the FEXCR register is not terminated.
The software command of the FEXCR register is terminated.
Setting to start up using the alternative area
Setting to start up using the default area
Access window setting disabled.
Access window setting enabled.
The startup area is switched to the default area temporarily
The startup area is switched to the alternate area temporarily.
The startup area is selected according to the settings of the extra area.
Access window information program Startup area selection and security setting
Erasure terminates normally
An error occurs during erasure
Programming terminates normally
An error occurs during programming.
Programming by the FEXCR register terminates normally
An error occurs during programming.
Blank checking terminates normally
An error occurs during blank checking.
No illegal software command or illegal access is detected
An illegal command or illegal access is detected.
No illegal command or illegal access to the extra area is detected
An illegal command or illegal access to the extra area is detected.
The code flash is the read mode
The code flash is the P/E mode.
The data flash is the read mode
The data flash is the P/E mode.
Prefetch buffer is disabled
Prefetch buffer is enabled
Write to the register enabled
Write to the register disabled
GTCNT counter is not cleared
GTCNT counter is not cleared
GTCNT counter is not cleared
GTCNT counter is not cleared
GTCNT counter is not cleared
GTCNT counter is not cleared
GTCNT counter is not cleared
GTCNT counter is not cleared
GTCNT counter is not cleared
GTCNT counter is not cleared
Counter start disabled on the rising edge of GTETRGA input
Counter start enabled on the rising edge of GTETRGA input
Counter start disabled on the falling edge of GTETRGA input
Counter start enabled on the falling edge of GTETRGA input
Counter start disabled on the rising edge of GTETRGB input
Counter start enabled on the rising edge of GTETRGB input
Counter start disabled on the falling edge of GTETRGB input
Counter start enabled on the falling edge of GTETRGB input
Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
Counter start disabled at the ELC_GPTA input
Counter start enabled at the ELC_GPTA input
Counter start disabled at the ELC_GPTB input
Counter start enabled at the ELC_GPTB input
Counter start disabled at the ELC_GPTC input
Counter start enabled at the ELC_GPTC input
Counter start disabled at the ELC_GPTD input
Counter start enabled at the ELC_GPTD input
Counter start disabled by the GTSTR register
Counter start enabled by the GTSTR register
Counter stop disabled on the rising edge of GTETRGA input
Counter stop enabled on the rising edge of GTETRGA input
Counter stop disabled on the falling edge of GTETRGA input
Counter stop enabled on the falling edge of GTETRGA input
Counter stop disabled on the rising edge of GTETRGB input
Counter stop enabled on the rising edge of GTETRGB input
Counter stop disabled on the falling edge of GTETRGB input
Counter stop enabled on the falling edge of GTETRGB input
Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
Counter stop disabled at the ELC_GPTA input
Counter stop enabled at the ELC_GPTA input
Counter stop disabled at the ELC_GPTB input
Counter stop enabled at the ELC_GPTB input
Counter stop disabled at the ELC_GPTC input
Counter stop enabled at the ELC_GPTC input
Counter stop disabled at the ELC_GPTD input
Counter stop enabled at the ELC_GPTD input
Counter stop disabled by the GTSTP register
Counter stop enabled by the GTSTP register
Counter clear disabled on the rising edge of GTETRGA input
Counter clear enabled on the rising edge of GTETRGA input
Counter clear disabled on the falling edge of GTETRGA input
Counter clear enabled on the falling edge of GTETRGA input
Disable counter clear on the rising edge of GTETRGB input
Enable counter clear on the rising edge of GTETRGB input
Counter clear disabled on the falling edge of GTETRGB input
Counter clear enabled on the falling edge of GTETRGB input
Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
Counter clear disabled at the ELC_GPTA input
Counter clear enabled at the ELC_GPTA input
Counter clear disabled at the ELC_GPTB input
Counter clear enabled at the ELC_GPTB input
Counter clear disabled at the ELC_GPTC input
Counter clear enabled at the ELC_GPTC input
Counter clear disabled at the ELC_GPTD input
Counter clear enabled at the ELC_GPTD input
Counter clear disabled by the GTCLR register
Counter clear enabled by the GTCLR register
Counter count up disabled on the rising edge of GTETRGA input
Counter count up enabled on the rising edge of GTETRGA input
Counter count up disabled on the falling edge of GTETRGA input
Counter count up enabled on the falling edge of GTETRGA input
Counter count up disabled on the rising edge of GTETRGB input
Counter count up enabled on the rising edge of GTETRGB input
Counter count up disabled on the falling edge of GTETRGB input
Counter count up enabled on the falling edge of GTETRGB input
Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
Counter count up disabled at the ELC_GPTA input
Counter count up enabled at the ELC_GPTA input
Counter count up disabled at the ELC_GPTB input
Counter count up enabled at the ELC_GPTB input
Counter count up disabled at the ELC_GPTC input
Counter count up enabled at the ELC_GPTC input
Counter count up disabled at the ELC_GPTD input
Counter count up enabled at the ELC_GPTD input
Counter count down disabled on the rising edge of GTETRGA input
Counter count down enabled on the rising edge of GTETRGA input
Counter count down disabled on the falling edge of GTETRGA input
Counter count down enabled on the falling edge of GTETRGA input
Counter count down disabled on the rising edge of GTETRGB input
Counter count down enabled on the rising edge of GTETRGB input
Counter count down disabled on the falling edge of GTETRGB input
Counter count down enabled on the falling edge of GTETRGB input
Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
Counter count down disabled at the ELC_GPTA input
Counter count down enabled at the ELC_GPTA input
Counter count down disabled at the ELC_GPTB input
Counter count down enabled at the ELC_GPTB input
Counter count down disabled at the ELC_GPTC input
Counter count down enabled at the ELC_GPTC input
Counter count down disabled at the ELC_GPTD input
Counter count down enabled at the ELC_GPTD input
GTCCRA input capture disabled on the rising edge of GTETRGA input
GTCCRA input capture enabled on the rising edge of GTETRGA input
GTCCRA input capture disabled on the falling edge of GTETRGA input
GTCCRA input capture enabled on the falling edge of GTETRGA input
GTCCRA input capture disabled on the rising edge of GTETRGB input
GTCCRA input capture enabled on the rising edge of GTETRGB input
GTCCRA input capture disabled on the falling edge of GTETRGB input
GTCCRA input capture enabled on the falling edge of GTETRGB input
GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
GTCCRA input capture disabled at the ELC_GPTA input
GTCCRA input capture enabled at the ELC_GPTA input
GTCCRA input capture disabled at the ELC_GPTB input
GTCCRA input capture enabled at the ELC_GPTB input
GTCCRA input capture disabled at the ELC_GPTC input
GTCCRA input capture enabled at the ELC_GPTC input
GTCCRA input capture disabled at the ELC_GPTD input
GTCCRA input capture enabled at the ELC_GPTD input
GTCCRB input capture disabled on the rising edge of GTETRGA input
GTCCRB input capture enabled on the rising edge of GTETRGA input
GTCCRB input capture disabled on the falling edge of GTETRGA input
GTCCRB input capture enabled on the falling edge of GTETRGA input
GTCCRB input capture disabled on the rising edge of GTETRGB input
GTCCRB input capture enabled on the rising edge of GTETRGB input
GTCCRB input capture disabled on the falling edge of GTETRGB input
GTCCRB input capture enabled on the falling edge of GTETRGB input
GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
GTCCRB input capture disabled at the ELC_GPTA input
GTCCRB input capture enabled at the ELC_GPTA input
GTCCRB input capture disabled at the ELC_GPTB input
GTCCRB input capture enabled at the ELC_GPTB input
GTCCRB input capture disabled at the ELC_GPTC input
GTCCRB input capture enabled at the ELC_GPTC input
GTCCRB input capture disabled at the ELC_GPTD input
GTCCRB input capture enabled at the ELC_GPTD input
Count operation is stopped
Count operation is performed
Saw-wave PWM mode (single buffer or double buffer possible)
Saw-wave one-shot pulse mode (fixed buffer operation)
Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible)
Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible)
Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation)
GTIOCnA pin duty depends on the compare match
GTIOCnA pin duty depends on the compare match
The function selected by the GTIOA[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting.
The function selected by the GTIOA[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting.
GTIOCnB pin duty depends on the compare match
GTIOCnB pin duty depends on the compare match
The function selected by the GTIOB[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting.
The function selected by the GTIOB[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting.
The GTIOCnA pin outputs low when counting stops
The GTIOCnA pin outputs high when counting stops
The GTIOCnA pin output level at the start or stop of counting depends on the register setting
The GTIOCnA pin output level is retained at the start or stop of counting
None of the below options are specified
GTIOCnA pin is set to Hi-Z in response to controlling the output negation
GTIOCnA pin is set to 0 in response to controlling the output negation
GTIOCnA pin is set to 1 in response to controlling the output negation
The noise filter for the GTIOCnA pin is disabled
The noise filter for the GTIOCnA pin is enabled
The GTIOCnB pin outputs low when counting stops
The GTIOCnB pin outputs high when counting stops
The GTIOCnB pin output level at the start/stop of counting depends on the register setting
The GTIOCnB pin output level is retained at the start/stop of counting
None of the below options are specified
GTIOCnB pin is set to Hi-Z in response to controlling the output negation
GTIOCnB pin is set to 0 in response to controlling the output negation
GTIOCnB pin is set to 1 in response to controlling the output negation
The noise filter for the GTIOCnB pin is disabled
The noise filter for the GTIOCnB pin is enabled
Group A output disable request is selected
Group B output disable request is selected
Same time output level high disable request disabled
Same time output level high disable request enabled
Same time output level low disable request disabled
Same time output level low disable request enabled
No input capture/compare match of GTCCRA is generated
An input capture/compare match of GTCCRA is generated
No input capture/compare match of GTCCRB is generated
An input capture/compare match of GTCCRB is generated
No compare match of GTCCRC is generated
A compare match of GTCCRC is generated
No compare match of GTCCRD is generated
A compare match of GTCCRD is generated
No compare match of GTCCRE is generated
A compare match of GTCCRE is generated
No compare match of GTCCRF is generated
A compare match of GTCCRF is generated
No overflow (crest) occurred
An overflow (crest) occurred
No underflow (trough) occurred
An underflow (trough) occurred
GTCNT counter counts downward
GTCNT counter counts upward
No output disable request is generated
An output disable request is generated
No simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred.
A simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred.
No simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred.
A simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred.
Buffer operation is enabled
Buffer operation is disabled
Buffer operation is enabled
Buffer operation is disabled
Single buffer operation (GTCCRA <––>GTCCRC)
Double buffer operation (GTCCRA <––> GTCCRC <––> GTCCRD)
Single buffer operation (GTCCRB <––> GTCCRE)
Double buffer operation (GTCCRB <––> GTCCRE <––> GTCCRF)
Single buffer operation (GTPBR –> GTPR)
GTCCRB is set without using GTDVU
GTDVU is used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB
Do not output (Hi-Z external pin)
Select the soft setting (OPSCR.UF, VF, WF)
Positive logic (active-high) output
Negative logic (active-low) output
Input phase aligned to PCLKD
Input phase aligned to the falling edge of PWM
This bit function is ignored
Group disable clears the OPSCR.EN bit
Do not use a noise filter on the external input
Use a noise filter on the external input
Do not include I3C broadcast address for private transfers
Include I3C broadcast address for private transfers
NACK and send broadcast CCC to disable Hot-Join
I3C has aborted a transfer.
I3C bus operation is disabled.
I3C bus operation is enabled.
The master dynamic address field is not valid.
The master dynamic address field is valid.
The Command Queues in I3C is not flushed.
The Command Queues in I3C is flushed.
The Response Queues in I3C is not flushed.
The Response Queues in I3C is flushed.
The Transmit Queues in I3C is not flushed.
The Transmit Queues in I3C is flushed.
The Receive Queues in I3C is not flushed.
The Receive Queues in I3C is flushed.
The IBI Queues in I3C is not flushed.
The IBI Queues in I3C is flushed.
The Receive Status Queue in I3C is not flushed.
The Receive Status Queue in I3C is flushed.
Releases of some registers and internal state.
Resets of some registers and internal state.
The Master is not the Current Master, and must request and acquire bus ownership before initiating any transfer.
The Master is the Current Master, and as a result can initiate transfers.
CRMS bit can be written when writing simultaneously with the value of the target bit.
I3C Internal Error has not detected.
I3C Internal Error has detected.
Disables Non-recoverable Internal Error Interrupt Signal.
Enables Non-recoverable Internal Error Interrupt Signal.
Not force a specific interrupt
Force a specific interrupt
Do not pass rejected IBI Status to IBI Queue, if the incoming HotJoin request is NACKed and is autodisabled based on field HJACKCTL of BCTL.
Pass rejected IBI Status to the IBI Queue, if the incoming Hot Join request is NACKed and is autodisabled based on field HJACKCTL of BCTL.
Do not pass rejected IBI Status to IBI Queue/Ring, if the incoming Master Request is NACKed and is auto-disabled based on DVMRRJ field in relevant DAT entry.
Pass rejected IBI Status to the IBI Queue, if the incoming Master Request is NACKed and is autodisabled based on DVMRRJ field in relevant DAT entry.
Do not pass rejected IBI Status to the IBI Queue/Rings, if the incoming SIR is NACKed and is auto-disabled based on DVSIRRJ field in relevant DAT entry.
Pass rejected IBI Status to the IBI Queue/Rings, if the incoming SIR is NACKed and is auto-disabled based on DVSIRRJ field in relevant DAT entry.
Master arbitration-lost detection disables. Disables the arbitration-lost detection function and does not clear the CRMS and TRMD bits in PRSST automatically when arbitration is lost.
Master arbitration-lost detection enables. Enables the arbitration-lost detection function and clears the CRMS and TRMD bits in PRSST automatically when arbitration is lost.
NACK transmission arbitration-lost detection disables.
NACK transmission arbitration-lost detection enables.
Slave arbitration-lost detection disables.
Slave arbitration-lost detection enables.
No SCL synchronous circuit uses.
An SCL synchronous circuit uses.
No Fm+ slope control circuit uses for the SCLn pin and SDAn pin. (n = 0)
An Fm+ slope control circuit uses for the SCLn pin and SDAn pin. (n = 0)
General call address detection disables.
General call address detection enables.
Hs-mode Master Code Detection disables.
Hs-mode Master Code Detection enables.
Device-ID address detection disables.
Device-ID address detection enables.
Host address detection disables.
Host address detection enables.
The time period set for SBRHO[7:0] and SBRLO[7:0] is not doubled.
The time period set for SBRHO[7:0] and SBRLO[7:0] is doubled.
I3C drives the SDAn pin low.
I3C releases the SDAn pin.
I3C drives the SCLn pin low.
I3C releases the SCLn pin.
Bits SCOC and SDOC are protected.
Bits SCOC and SDOC can be written (When writing simultaneously with the value of the target bit). This bit is read as 0.
Does not output an extra SCL clock cycle (default).
Outputs an extra SCL clock cycle.
1 I3Cφ cycle (When OUTCTL.SDODCS = 0 (I3Cφ)) 1 or 2 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
2 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 3 or 4 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
3 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 5 or 6 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
4 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 7 or 8 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
5 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 9 or 10 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
6 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 11 or 12 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
7 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 13 or 14 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
The internal reference clock (I3Cφ) is selected as the clock source of the SDA output delay counter.
The internal reference clock divided by 2 (I3Cφ/2) is selected as the clock source of the SDA output delay counter.
No digital noise filter circuit is used.
A digital noise filter circuit is used.
Count is disabled while the SCLn line is at a low level.
Count is enabled while the SCLn line is at a low level.
Count is disabled while the SCLn line is at a high level.
Count is enabled while the SCLn line is at a high level.
Timeout is detected during the following conditions: The bus is busy (BCST.BFREF = 0) in master mode.I3C’s own slave address is detected and the bus is busy in slave mode.The bus is free (BCST.BFREF = 1) while generation of a START condition is requested (CNDCTL.STCND = 1).
Timeout is detected while the bus is busy.
Timeout is detected while the bus is free.
A 0 is received as the acknowledge bit (ACK reception).
A 1 is received as the acknowledge bit (NACK reception).
A 0 is sent as the acknowledge bit (ACK transmission).
A 1 is sent as the acknowledge bit (NACK transmission).
The ACKT bit are protected.
The ACKT bit can be written (when writing simultaneously with the value of the target bit). This bit is read as 0.
NTST.RDBFF0 is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.)
NTST.RDBFF0 is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) Low-hold is released by writing a value to the ACKCTL.ACKT bit.
No WAIT (The period between ninth clock cycle and first clock cycle is not held low.)
WAIT (The period between ninth clock cycle and first clock cycle is held low.) Low-hold is released by reading NTDTBP0.
Does not stall the SCL clock during the address assignment phase.
Stall the SCL clock during address assignment phase.
Does not stall the SCL clock during the transition bit in read transfer.
Stall the SCL clock during the transition bit in read transfer.
Does not stall the SCL clock during the parity bit period.
Stall the SCL clock during the parity bit period.
Does not stall the SCL clock during the ACK/NACK phase.
Stall the SCL clock during the ACK/NACK phase.
Does not request to issue a START condition.
Requests to issue a START condition.
Does not request to issue a Repeated START condition.
Requests to issue a Repeated START condition.
Does not request to issue a STOP condition.
Requests to issue a STOP condition.
Interrupt is issued when Command Queue is completely empty.
Interrupt is issued when Command Queue contains N empties. (N = CMDQTH[7:0])
Interrupt is issued when Response Queue contains 1 entry (DWORD).
Interrupt is triggered when Response Queue contains N+1 entries (DWORD). (N = CMDQTH[7:0])
I3C Protocol mode (Master): Interrupt is generated when the Outstanding IBI Status count is 1 or more. I3C Protocol mode (Slave): Interrupt is issued when IBI Data Buffer is completely empty.
I3C Protocol mode (Master): Interrupt is generated when the Outstanding IBI Status count is N + 1 or more. (N = CMDQTH[7:0]) I3C Protocol mode (Slave): Interrupt is issued when IBI Data Buffer contains N empties.
Interrupt triggers at 2 Tx Buffer empties, DWORDs
Interrupt triggers at 2 Rx Buffer entries, DWORDs
Interrupt is issued when Receive Status Queue contains 1 entry (DWORD).
Interrupt is triggered when Receive Status Queue contains N+1 entries (DWORD). (N = RSQTH[7:0])
START condition is not detected.
START condition is detected.
STOP condition is not detected.
STOP condition is detected.
HDR Exit Pattern Detection Interrupt does not occur.
HDR Exit Pattern Detection Interrupt occurs.
Data is being transmitted.
Data has been transmitted.
Disables START condition Detection Interrupt Status logging.
Enables START condition Detection Interrupt Status logging.
Disables STOP condition Detection Interrupt Status logging.
Enables STOP condition Detection Interrupt Status logging.
Disables HDR Exit Pattern Detection Interrupt Status logging.
Enables HDR Exit Pattern Detection Interrupt Status logging.
Disables NACK Detection Interrupt Status logging.
Enables NACK Detection Interrupt Status logging.
Disables Transmit End Interrupt Status logging.
Enables Transmit End Interrupt Status logging.
Disables Arbitration Lost Interrupt Status logging.
Enables Arbitration Lost Interrupt Status logging.
Disables Timeout Detection Interrupt Status logging.
Enables Timeout Detection Interrupt Status logging.
Disables START condition Detection Interrupt Signal.
Enables START condition Detection Interrupt Signal.
Disables STOP condition Detection Interrupt Signal.
Enables STOP condition Detection Interrupt Signal.
Disables HDR Exit Pattern Detection Interrupt Signal.
Enables HDR Exit Pattern Detection Interrupt Signal.
Disables NACK Detection Interrupt Signal.
Enables NACK Detection Interrupt Signal.
Disables Transmit End Interrupt Signal.
Enables Transmit End Interrupt Signal.
Disables Arbitration Lost Interrupt Signal.
Enables Arbitration Lost Interrupt Signal.
Disables Timeout Detection Interrupt Signal.
Enables Timeout Detection Interrupt Signal.
Not Force START condition Detection Interrupt for software testing.
Force START condition Detection Interrupt for software testing.
Not Force STOP condition Detection Interrupt for software testing.
Force STOP condition Detection Interrupt for software testing.
Not Force HDR Exit Pattern Detection Interrupt for software testing.
Force HDR Exit Pattern Detection Interrupt for software testing.
Not Force NACK Detection Interrupt for software testing.
Force NACK Detection Interrupt for software testing.
Not Force Transmit End Interrupt for software testing.
Force Transmit End Interrupt for software testing.
Not Force Arbitration Lost Interrupt for software testing.
Force Arbitration Lost Interrupt for software testing.
Not Force Timeout Detection Interrupt for software testing.
Force Timeout Detection Interrupt for software testing.
For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Transmit Data Buffer 0 contains transmit data. For I3C protocol mode: PRTS.PRTMD bit = 0. The number of empties in the Normal Transmit Data Buffer 0 is less than the NTBTHCTL0.TXDBTH[2:0] threshold.
For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Transmit Data Buffer 0 contains no transmit data. For I3C protocol mode: PRTS.PRTMD bit = 0. The number of empties in the Normal Transmit Data Buffer 0 is the NTBTHCTL0.TXDBTH[2:0] threshold or more.
For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Receive Data Buffer0 contains no receive data. For I3C Protocol mode: PRTS.PRTMD bit = 0. The number of entries in the Normal Receive Data Buffer 0 is less than the NTBTHCTL0.RXDBTH[2:0] threshold.
For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Receive Data Buffer0 contains receive data. For I3C Protocol mode: PRTS.PRTMD bit = 0. The number of entries in the Normal Receive Data Buffer 0 is the NTBTHCTL0.RXDBTH[2:0] threshold or more.
For I3C protocol mode (Master): PRTS.PRTMD bit = 0, PRSST.CRMS bit = 1. The number of IBI Status Queue entries is the NQTHCTL.IBIQTH threshold or less. For I3C protocol mode (Slave) : PRTS.PRTMD bit = 0, PRSST.CRMS bit = 0. If the NQTHCTL.IBIQTH = 0: The number of IBI Data Buffer empties is less than the IBI Data Buffer size. If the NQTHCTL.IBIQTH is other than 0: The number of IBI Data Buffer empties is less than the NQTHCTL.IBIQTH threshold.
For I3C protocol mode (Master): PRTS.PRTMD bit = 0, PRSST.CRMS bit = 1. The number of IBI Status Queue entries is more than the NQTHCTL.IBIQTH threshold. For I3C protocol mode (Slave) : PRTS.PRTMD bit = 0, PRSST.CRMS bit = 0. If the NQTHCTL.IBIQTH = 0: The number of IBI Data Buffer empties is the IBI Data Buffer size. If the NQTHCTL.IBIQTH is other than 0: The number of IBI Data Buffer empties is the NQTHCTL.IBIQTH threshold or more.
If the NQTHCTL.CMDQTH = 0: The number of Command Queue empties is less than the Command Queue size. If the NQTHCTL.CMDQTH is other than 0: The number of Command Queue empties is less than the NQTHCTL.CMDQTH threshold.
If the NQTHCTL.CMDQTH = 0: The number of Command Queue empties is the Command Queue size. If the NQTHCTL.CMDQTH is other than 0: 1: The number of Command Queue empties is the NQTHCTL.CMDQTH threshold or more.
The number of Response Queue entries is the NQTHCTL.RSPQTH threshold or less.
The number of Response Queue entries is more than the NQTHCTL.RSPQTH threshold.
Transfer Abort does not occur.
Transfer Abort occur. To clear, write 0 to this bit after 1 state is read.
Transfer Error does not occur.
Transfer Error occurs. To clear, write 0 to this bit after 1 state is read.
The number of Receive Status Queue entries is the NRQTHCTL.RSQTH threshold or less.
The number of Receive Status Queue entries is more than the NRQTHCTL.RSQTH threshold.
Disables Tx0 Data Buffer Empty Interrupt Status logging.
Enables Tx0 Data Buffer Empty Interrupt Status logging.
Disables Rx0 Data Buffer Full Interrupt Status logging.
Enables Rx0 Data Buffer Full Interrupt Status logging.
Disables IBI Status Buffer Empty/Full Interrupt Status logging.
Enables IBI Status Buffer Empty/Full Interrupt Status logging.
Disables Command Buffer Empty Interrupt Status logging.
Enables Command Buffer Empty Interrupt Status logging.
Disables Response Buffer Full Interrupt Status logging.
Enables Response Buffer Full Interrupt Status logging.
Disables Transfer Abort Interrupt Status logging.
Enables Transfer Abort Interrupt Status logging.
Disables Transfer Error Interrupt Status logging.
Enables Transfer Error Interrupt Status logging.
Disables Receive Status Buffer Full Interrupt Status logging.
Enables Receive Status Buffer Full Interrupt Status logging.
Disables Tx0 Data Buffer Empty Interrupt Signal.
Enables Tx0 Data Buffer Empty Interrupt Signal.
Disables Rx0 Data Buffer Full Interrupt Signal.
Enables Rx0 Data Buffer Full Interrupt Signal.
Disables IBI Status Buffer Empty/Full Interrupt Signal.
Enables IBI Status Buffer Empty/Full Interrupt Signal.
Disables Command Buffer Empty Interrupt Signal.
Enables Command Buffer Empty Interrupt Signal.
Disables Response Buffer Full Interrupt Signal.
Enables Response Buffer Full Interrupt Signal.
Disables Transfer Abort Interrupt Signal.
Enables Transfer Abort Interrupt Signal.
Disables Transfer Error Interrupt Signal.
Enables Transfer Error Interrupt Signal.
Disables Receive Status Buffer Full Interrupt Signal.
Enables Receive Status Buffer Full Interrupt Signal.
Not Force Tx0 Data Buffer Empty Interrupt for software testing.
Force Tx0 Data Buffer Empty Interrupt for software testing.
Not Force Rx0 Data Buffer Full Interrupt for software testing.
Force Rx0 Data Buffer Full Interrupt for software testing.
Not Force IBI Status Buffer Full Interrupt for software testing.
Force IBI Status Buffer Full Interrupt for software testing.
Not Force Command Buffer Empty Interrupt for software testing.
Force Command Buffer Empty Interrupt for software testing.
Not Force Response Buffer Full Interrupt for software testing.
Force Response Buffer Full Interrupt for software testing.
Not Force Transfer Abort Interrupt for software testing.
Force Transfer Abort Interrupt for software testing.
Not Force Transfer Error Interrupt for software testing.
Force Transfer Error Interrupt for software testing.
Not Force Receive Status Buffer Full Interrupt for software testing.
Force Receive Status Buffer Full Interrupt for software testing.
Have not Detected Bus Free
Have not Detected Bus Available
Have Detected Bus Available
Have not Detected Bus Idle
General call address does not detect.
General call address detects.
Hs-mode Master Code does not detect.
Hs-mode Master Code detects.
Device-ID command does not detect.
Device-ID command detects. This bit set to 1 when the first frame received immediately after a START condition is detected matches a value of (device ID (1111 100) + 0[W]).
Host address does not detect.
Host address detects. This bit set to 1 when the received slave address matches the host address (0001 000).
IBIs from this Device do not carry a Data Payload.
IBIs from this Device do carry a Data Payload.
This Device shall ACK the SIR.
This Device shall NACK the SIR and send the auto-disable CCC.
This Device shall ACK Master Requests.
This Device shall NACK Master Requests and send the auto-disable command.
Slave device address length 7 bits selected.
Slave device address length 10 bits selected. (I2C device only)
IBIs from this device do not carry a data payload.
IBIs from this device carry a data payload.
No data byte follows the accepted IBI.
Mandatory one or more data bytes follow the accepted IBI. Data byte continuation is indicated by T-Bit.
Device will always respond to I3C bus commands.
Device will not always respond to I3C bus commands.
No data byte follows the accepted IBI.
Mandatory one or more data bytes follow the accepted IBI. Data byte continuation is indicated by T-Bit.
Device will always respond to I3C bus commands.
Device will not always respond to I3C bus commands.
Reserved for future definition by MIPI Sensor WG
Reserved for future definition by MIPI Sensor WG
The 7-bit address format is selected.
The 10-bit address format is selected.
Slave address is disabled.
Slave address is enabled.
Dynamic Address is disabled.
Dynamic Address is enabled.
DISABLED: Slave-initiated Interrupts is Disabled by the Master to control.
ENABLED: Slave-initiated Interrupts is Enabled by the Master to control.
DISABLED: Mastership requests from Secondary Masters is Disabled by the Current Master to control.
ENABLED: Mastership requests from Secondary Masters is Enabled by the Current Master to control.
DISABLED: Slave-initiated Hot-Join is Disabled by the Master to control.
ENABLED: Slave-initiated Hot-Join is Enabled by the Master to control.
ENTAS0 (1µs: Latency-free operation)
ENTAS3 (50 ms: Lowest-activity operation)
Exit Test Mode This value removes all I3C devices from Test Mode.
Vendor Test Mode This value indicates that I3C devices shall return a random 32bit value in the provisional ID during the Dynamic Address Assignment procedure.
MIPI reserved Reserved for future use by the MIPI Alliance
The Slave has not detected a protocol error since the last Status read.
The Slave has detected a protocol error since the last Status read.
8 ns or less (default value)
TSCO is more than 12 ns, and is reported by private agreement.
Disables transmission of the Maximum Read Turnaround Time. (GETMXDS Format 1: Without Turnaround)
Enables transmission of the Maximum Read Turnaround Time. (GETMXDS Format 2: With Turnaround)
I3C has driven the SCL pin low.
I3C has released the SCL pin.
I3C has driven the SDA pin low.
I3C has released the SDA pin.
Digital filter is disabled
Digital filter is enabled.
Clear the NMISR.IWDTST flag
Clear the NMISR.WDTST flag
Clear the NMISR.LVD1ST flag
Clear the NMISR.LVD2ST flag.
Clear the NMISR.NMIST flag
Clear the NMISR.RPEST flag
Clear the NMISR.BUSSST flag
Clear the NMISR.BUSMST flag
Clear the NMISR.SPEST flag
Software Standby/Snooze Mode returns by IRQn interrupt disabled
Software Standby/Snooze Mode returns by IRQn interrupt enabled
Software Standby/Snooze Mode returns by IWDT interrupt disabled
Software Standby/Snooze Mode returns by IWDT interrupt enabled
Software Standby/Snooze Mode returns by KEY interrupt disabled
Software Standby/Snooze Mode returns by KEY interrupt enabled
Software Standby/Snooze Mode returns by LVD1 interrupt disabled
Software Standby/Snooze Mode returns by LVD1 interrupt enabled
Software Standby/Snooze Mode returns by LVD2 interrupt disabled
Software Standby/Snooze Mode returns by LVD2 interrupt enabled
Software Standby/Snooze Mode returns by AGT1 underflow interrupt disabled
Software Standby/Snooze Mode returns by AGT1 underflow
Software Standby/Snooze Mode returns by AGT1 compare match A interrupt disabled.
Software Standby/Snooze Mode returns by AGT1 compare match A interrupt enabled.
Software Standby/Snooze Mode returns by AGT1 compare match B interrupt disabled.
Software Standby/Snooze Mode returns by AGT1 compare match B interrupt enabled.
No refresh error occurred
Do not use key interrupt flags
Do not detect key interrupt signals
Detect key interrupt signals
Do not detect key interrupt signals
Detect key interrupt signals
Do not detect key interrupt signals
Detect key interrupt signals
Do not detect key interrupt signals
Detect key interrupt signals
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Cancel the module-stop state
Enter the module-stop state
Stop the WDT clock and register R/W clock
Stop the IWDT register R/W clock
Write protect for bits [2:0]
Write enable for bits [2:0]
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Use as I/O port for peripheral functions
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Use as I/O port for peripheral functions
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Use as I/O port for peripheral functions
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Use as I/O port for peripheral functions
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Use as I/O port for peripheral functions
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Use as I/O port for peripheral functions
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Use as I/O port for peripheral functions
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Use as I/O port for peripheral functions
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Use as I/O port for peripheral functions
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Use as I/O port for peripheral functions
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Use as I/O port for peripheral functions
Input (functions as an input pin)
Output (functions as an output pin)
Do not use as IRQn input pin
Input (functions as an input pin)
Output (functions as an output pin)
Writing to the PmnPFS register is disabled
Writing to the PmnPFS register is enabled
Writing to the PFSWE bit is enabled
Writing to the PFSWE bit is disabled
No output-disable request from the GTETRGn pin occurred
Output-disable request from the GTETRGn pin occurred.
No output-disable request from GPT occurred.
Output-disable request from GPT occurred.
No output-disable request from software occurred
Output-disable request from software occurred
Disable output-disable requests from the GTETRGn pins
Enable output-disable requests from the GTETRGn pins
Disable output-disable requests from GPT
Enable output-disable requests from GPT
GTETRGn input after filtering was 0
GTETRGn input after filtering was 1
Sample GTETRGn pin input level three times every PCLKB
Sample GTETRGn pin input level three times every PCLKB/8
Sample GTETRGn pin input level three times every PCLKB/32
Sample GTETRGn pin input level three times every PCLKB/128
No output-disable request from the GTETRGn pin occurred
Output-disable request from the GTETRGn pin occurred.
No output-disable request from GPT occurred.
Output-disable request from GPT occurred.
No output-disable request from software occurred
Output-disable request from software occurred
Disable output-disable requests from the GTETRGn pins
Enable output-disable requests from the GTETRGn pins
Disable output-disable requests from GPT
Enable output-disable requests from GPT
GTETRGn input after filtering was 0
GTETRGn input after filtering was 1
Sample GTETRGn pin input level three times every PCLKB
Sample GTETRGn pin input level three times every PCLKB/8
Sample GTETRGn pin input level three times every PCLKB/32
Sample GTETRGn pin input level three times every PCLKB/128
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
Input (functions as an input pin)
Output (functions as an output pin)
All bus master MPU group A register writes are permitted.
All bus master MPU group A register writes are protected. Reads are permitted.
Group A region n disabled
All bus slave register writes are permitted
All bus slave register writes are protected. Reads are permitted
Memory protection read for master MPU group A disabled
Memory protection read for master MPU group A enabled
Memory protection write for master MPU group A disabled
Memory protection write for master MPU group A enabled
Memory protection for CPU read disabled
Memory protection for CPU read enabled
Memory protection for CPU write disabled
Memory protection for CPU write enabled
Memory protection for master MPU group A read disabled
Memory protection for master MPU group A read enabled
Memory protection for master MPU group A write disabled
Memory protection for master MPU group A write enabled
Memory protection for CPU read disabled
Memory protection for CPU read enabled
Memory protection for CPU write disabled
Memory protection for CPU write enabled
Memory protection for master MPU group A read disabled
Memory protection for master MPU group A read enabled
Memory protection for master MPU group A write disabled
Memory protection for master MPU group A write enabled
Memory protection for CPU read disabled
Memory protection for CPU read enabled
Memory protection for CPU write disabled
Memory protection for CPU write enabled
Memory protection for master MPU group A read disabled
Memory protection for master MPU group A read enabled
Memory protection for master MPU group A write disabled
Memory protection for master MPU group A write enabled
Memory protection for CPU read disabled
Memory protection for CPU read enabled
Memory protection for CPU write disabled
Memory protection for CPU write enabled
Memory protection for master MPU group A read disabled
Memory protection for master MPU group A read enabled
Memory protection for master MPU group A write disabled
Memory protection for master MPU group A write enabled
CPU read of memory protection disabled
CPU read of memory protection enabled
CPU write of memory protection disabled
CPU write of memory protection enabled
Master MPU group A read of memory protection disabled
Master MPU group A read of memory protection enabled
Master MPU group A write of memory protection disabled
Master MPU group A write of memory protection enabled
Stack pointer monitor is disabled
Stack pointer monitor is enabled
Stack pointer has not overflowed or underflowed
Stack pointer has overflowed or underflowed
Stack pointer monitor register writes are permitted.
Stack pointer monitor register writes are protected. Reads are permitted
Stack pointer monitor is disabled
Stack pointer monitor is enabled
Stack pointer has not overflowed or underflowed
Stack pointer has overflowed or underflowed
Stack pointer monitor register writes are permitted.
Stack pointer monitor register writes are protected. Reads are permitted
Disable multi-processor communications function
Enable multi-processor communications function
When transmitting: Do not add parity bit When receiving: Do not check parity bit
When transmitting: Add parity bit When receiving: Check parity bit
SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value)
SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length
Asynchronous mode or simple IIC mode
Clock synchronous mode or simple SPI mode
Block transfer mode operation
In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin.
In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin.
In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin.
Disable SCIn_TEI interrupt requests
Enable SCIn_TEI interrupt requests
When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed.
Disable serial transmission
Enable serial transmission
Disable SCIn_RXI and SCIn_ERI interrupt requests
Enable SCIn_RXI and SCIn_ERI interrupt requests
Disable SCIn_TXI interrupt requests
Enable SCIn_TXI interrupt requests
When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low
When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock
When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high
When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock
Disable serial transmission
Enable serial transmission
Disable SCIn_RXI and SCIn_ERI interrupt requests
Enable SCIn_RXI and SCIn_ERI interrupt requests
Disable SCIn_TXI interrupt requests
Enable SCIn_TXI interrupt requests
A character is being transmitted
Character transfer is complete
No framing error occurred
No overrun error occurred
No received data in RDR register
Received data in RDR register
Transmit data in TDR register
No transmit data in TDR register
A character is being transmitted
Character transfer is complete
No low error signal response
Low error signal response occurred
No overrun error occurred
No received data in RDR register
Received data in RDR register
Transmit data in TDR register
No transmit data in TDR register
Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode)
Smart card interface mode
TDR contents are transmitted as they are. Received data is stored as received in the RDR register.
TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register.
SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length
SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length
Disable bit rate modulation function
Enable bit rate modulation function
Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register
Baud rate is 6 base clock cycles for 1-bit period
Select 16 base clock cycles for 1-bit period
Select 8 base clock cycles for 1-bit period
In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple I2C mode: Disable noise cancellation function for SCLn and SDAn input signals
In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple I2C mode: Enable noise cancellation function for SCLn and SDAn input signals
Output clock from baud rate generator with normal frequency
Output clock from baud rate generator with doubled frequency
Detect low level on RXDn pin as start bit
Detect falling edge of RXDn pin as start bit
In asynchronous mode: Use clock signal divided by 1 with noise filter In simple I2C mode: Setting prohibited
In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 1 with noise filter
In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 2 with noise filter
In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 4 with noise filter
In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 8 with noise filter
SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode
SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited
(IICDL - 1) to (IICDL) cycles
Use reception and transmission interrupts
Do not synchronize with clock signal
Synchronize with clock signal
NACK transmission and ACK/NACK reception
Do not generate start condition
Do not generate restart condition
Generate restart condition
Do not generate stop condition
No requests are being made for generating conditions, or a condition is being generated
Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0
Generate start, restart, or stop condition
Drive SDAn pin to high-impedance state
Generate start, restart, or stop condition
Drive SCLn pin to high-impedance state
Disable CTS function (enable RTS output function)
Transmit through TXDn pin and receive through RXDn pin (master mode)
Receive through TXDn pin and transmit through RXDn pin (slave mode)
Do not invert clock polarity
No framing error occurred
Always compare data regardless of the MPB bit value
Only compare data when MPB bit = 1 (ID frame)
Disable address match function
Enable address match function
Do not output value of SPB2DT bit on TXDn pin
Output value of SPB2DT bit on TXDn pin
Select SPI operation (4-wire method)
Select clock synchronous operation (3-wire method)
Select full-duplex synchronous serial communications
Select serial communications with transmit-only
Disable detection of mode fault errors
Enable detection of mode fault errors
Disable SPI error interrupt requests
Enable SPI error interrupt requests
Disable transmit buffer empty interrupt requests
Enable transmit buffer empty interrupt requests
Disable SPI receive buffer full interrupt requests
Enable SPI receive buffer full interrupt requests
Set SSLn0 signal to active-low
Set SSLn0 signal to active-high
Loopback mode (receive data = inverted transmit data)
Loopback mode (receive data = transmit data)
Set level output on MOSIn pin during MOSI idling to low
Set level output on MOSIn pin during MOSI idling to high
Set MOSI output value to equal final data from previous transfer
Set MOSI output value to equal value set in the MOIFV bit
No overrun error occurred
SPI is in the transfer state
No mode fault or underrun error occurred
Mode fault error or underrun error occurred
Mode fault error occurred (MODF = 1)
Underrun error occurred (MODF = 1)
Data is in the transmit buffer
No data is in the transmit buffer
No valid data is in SPDR/SPDR_HA
Valid data is in SPDR/SPDR_HA
Read SPDR/SPDR_HA values from receive buffer
Read SPDR/SPDR_HA values from transmit buffer, but only if the transmit buffer is empty
Set SPDR_HA to valid for halfword access
Set SPDR to valid for word access
SPDR/SPDR_HA is accessed in halfword or word (SPLW is valid)
SPDR_BY is accessed in byte (SPLW is invalid)
Do not add parity bit to transmit data and do not check parity bit of receive data
When SPCR.TXMD = 0: Add parity bit to transmit data and check parity bit of receive data When SPCR.TXMD = 1: Add parity bit to transmit data but do not check parity bit of receive data
Select even parity for transmission and reception
Select odd parity for transmission and reception
Disable idle interrupt requests
Enable idle interrupt requests
Disable self-diagnosis function of the parity circuit
Enable self-diagnosis function of the parity circuit
Disable RSPCK auto-stop function
Enable RSPCK auto-stop function
Select data sampling on leading edge, data change on trailing edge
Select data change on leading edge, data sampling on trailing edge
Set RSPCK low during idle
Set RSPCK high during idle
Base bit rate divided by 2
Base bit rate divided by 4
Base bit rate divided by 8
Select next-access delay of 1 RSPCK + 2 PCLKB
Select next-access delay equal to the setting in the SPI Next-Access Delay Register (SPND)
Select SSL negation delay of 1 RSPCK
Select SSL negation delay equal to the setting in the SPI Slave Select Negation Delay Register (SSLND)
Select RSPCK delay of 1 RSPCK
Select RSPCK delay equal to the setting in the SPI Clock Delay Register (SPCKD)
Disable writes to protected registers
Enable writes to protected registers
Cancel the module-stop state
Enter the module-stop state
The HOCO clock is stopped or is not yet stable
The HOCO clock is stable, so is available for use as the system clock
MPU operate clock stops (MPU function disable).
Debug clock does not stop
Debug clock stops (valid only when LPOPT.LPOPTEN = 1)
Flash register R/W clock operates as normal
Flash register R/W clock stops.
All lower power counter measure disable
All lower power counter measure enable
Disable the snooze end request
Enable the snooze end request
Disable the snooze end request
Enable the snooze end request
Disable the snooze end request
Enable the snooze end request
Disable the snooze end request
Enable the snooze end request
Disable the snooze end request
Enable the snooze end request
Disable the snooze request
Enable the snooze request
Disable the snooze request
Enable the snooze request
Disable the snooze request
Enable the snooze request
Disable the snooze request
Enable the snooze request
Disable the snooze request
Enable the snooze request
Disable the snooze request
Enable the snooze request
Disable the snooze request
Enable the snooze request
Disable the snooze request
Enable the snooze request
Disable the snooze request
Enable the snooze request
Disable the snooze request
Enable the snooze request
Disable the snooze request
Enable the snooze request
Disable the snooze request
Enable the snooze request
All SRAMs are on in Software Standby mode
4 KB SRAM (0x2000_4000 to 0x2000_4FFF) is on in Software Standby mode
Before starting high-speed on-chip oscillator by setting HOCOCR.HCSTP bit, the HSTS[2:0] bits must be set to 011b beforehand. Wait time = 46 cycles (5.75 µs) Wait time is calculated at MOCO = 8 MHz (typically 0.125 µs).
Other than Subosc-speed mode
Independent watchdog timer reset not detected
Independent watchdog timer reset detected
Watchdog timer reset not detected
Watchdog timer reset detected
Software reset not detected
SRAM parity error reset not detected
SRAM parity error reset detected
Bus slave MPU error reset not detected
Bus slave MPU error reset detected
Bus master MPU error reset not detected
Bus master MPU error reset detected
CPU stack pointer error reset not detected
CPU stack pointer error reset detected
When VCC >= Vdet1 (rise) is detected
When VCC < Vdet1 (fall) is detected
When fall and rise are detected
Vdet1 crossing is detected
VCC >= Vdet1 or MON is disabled
When VCC>= Vdet2 (rise) is detected
When VCC < Vdet2 (fall) is detected
When fall and rise are detected
Vdet2 crossing is detected
VCC>= Vdet2 or MON is disabled
On-chip debugger is disabled
On-chip debugger is enabled
Power-on reset not detected
Voltage monitor 0 reset not detected
Voltage monitor 0 reset detected
Voltage monitor 1 reset not detected
Voltage monitor 1 reset detected
Voltage monitor 2 reset not detected
Voltage monitor 2 reset detected
Voltage detection 1 circuit disabled
Voltage detection 1 circuit enabled
Voltage detection 2 circuit disabled
Voltage detection 2 circuit enabled
Disable voltage monitor 1 circuit comparison result output
Enable voltage monitor 1 circuit comparison result output
Generate voltage monitor 1 interrupt on Vdet1 crossing
Enable voltage monitor 1 reset when the voltage falls to and below Vdet1
Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected
Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset
Disable voltage monitor 2 circuit comparison result output
Enable voltage monitor 2 circuit comparison result output
Generate voltage monitor 2 interrupt on Vdet2 crossing
Enable voltage monitor 2 reset when the voltage falls to and below Vdet2
Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected
Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset
0% (do not specify window end position).
100% (do not specify window start position).
No refresh error occurred
Stop count on transition to Sleep mode
Performs copy-assignment from
source.
Read more Converts to this type from the input type.
Converts to this type from the input type.
Compares and returns the maximum of two values.
Read more Compares and returns the minimum of two values.
Read more Restrict a value to a certain interval.
Read more Tests for self and other values to be equal, and is used by ==.
Tests for !=. The default implementation is almost always sufficient,
and should not be overridden without very good reason.
This method returns an ordering between
self and
other values if one exists.
Read more Tests less than (for
self and
other) and is used by the
< operator.
Read more Tests less than or equal to (for
self and
other) and is used by the
<= operator.
Read more Tests greater than (for
self and
other) and is used by the
>
operator.
Read more Tests greater than or equal to (for
self and
other) and is used by
the
>= operator.
Read more Immutably borrows from an owned value.
Read more Mutably borrows from an owned value.
Read more 🔬 This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from
self to
dest.
Read more Returns the argument unchanged.
Calls U::from(self).
That is, this conversion is whatever the implementation of
From <T> for U chooses to do.
The type returned in the event of a conversion error.
Performs the conversion.
The type returned in the event of a conversion error.
Performs the conversion.