#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! TIM13
//!
//! Used by: stm32mp153, stm32mp157
use crate::{RWRegister, WORegister};
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;
/// TIM13 control register 1
pub mod TIM13_CR1 {
/// CEN
pub mod CEN {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// UDIS
pub mod UDIS {
/// Offset (1 bits)
pub const offset: u16 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// URS
pub mod URS {
/// Offset (2 bits)
pub const offset: u16 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// OPM
pub mod OPM {
/// Offset (3 bits)
pub const offset: u16 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ARPE
pub mod ARPE {
/// Offset (7 bits)
pub const offset: u16 = 7;
/// Mask (1 bit: 1 << 7)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CKD
pub mod CKD {
/// Offset (8 bits)
pub const offset: u16 = 8;
/// Mask (2 bits: 0b11 << 8)
pub const mask: u16 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// UIFREMAP
pub mod UIFREMAP {
/// Offset (11 bits)
pub const offset: u16 = 11;
/// Mask (1 bit: 1 << 11)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM13 Interrupt enable register
pub mod TIM13_DIER {
/// UIE
pub mod UIE {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1IE
pub mod CC1IE {
/// Offset (1 bits)
pub const offset: u16 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM13 status register
pub mod TIM13_SR {
/// UIF
pub mod UIF {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1IF
pub mod CC1IF {
/// Offset (1 bits)
pub const offset: u16 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1OF
pub mod CC1OF {
/// Offset (9 bits)
pub const offset: u16 = 9;
/// Mask (1 bit: 1 << 9)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM13 event generation register
pub mod TIM13_EGR {
/// UG
pub mod UG {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1G
pub mod CC1G {
/// Offset (1 bits)
pub const offset: u16 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode
pub mod TIM13_CCMR1 {
/// CC1S
pub mod CC1S {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (2 bits: 0b11 << 0)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// OC1FE
pub mod OC1FE {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// OC1PE
pub mod OC1PE {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// OC1M
pub mod OC1M {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (3 bits: 0b111 << 4)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// OC1M3
pub mod OC1M3 {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (1 bit: 1 << 16)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM13 capture/compare enable register
pub mod TIM13_CCER {
/// CC1E
pub mod CC1E {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1P
pub mod CC1P {
/// Offset (1 bits)
pub const offset: u16 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CC1NP
pub mod CC1NP {
/// Offset (3 bits)
pub const offset: u16 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u16 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM13 counter
pub mod TIM13_CNT {
/// CNT
pub mod CNT {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// UIFCPY
pub mod UIFCPY {
/// Offset (31 bits)
pub const offset: u32 = 31;
/// Mask (1 bit: 1 << 31)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM13 prescaler
pub mod TIM13_PSC {
/// PSC
pub mod PSC {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u16 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM13 auto-reload register
pub mod TIM13_ARR {
/// ARR
pub mod ARR {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u16 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM13 capture/compare register 1
pub mod TIM13_CCR1 {
/// CCR1
pub mod CCR1 {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u16 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// TIM13 timer input selection register
pub mod TIM13_TISEL {
/// TI1SEL
pub mod TI1SEL {
/// Offset (0 bits)
pub const offset: u16 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u16 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
#[repr(C)]
pub struct RegisterBlock {
/// TIM13 control register 1
pub TIM13_CR1: RWRegister<u16>,
_reserved1: [u8; 10],
/// TIM13 Interrupt enable register
pub TIM13_DIER: RWRegister<u16>,
_reserved2: [u8; 2],
/// TIM13 status register
pub TIM13_SR: RWRegister<u16>,
_reserved3: [u8; 2],
/// TIM13 event generation register
pub TIM13_EGR: WORegister<u16>,
_reserved4: [u8; 2],
/// The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode
pub TIM13_CCMR1: RWRegister<u32>,
_reserved5: [u8; 4],
/// TIM13 capture/compare enable register
pub TIM13_CCER: RWRegister<u16>,
_reserved6: [u8; 2],
/// TIM13 counter
pub TIM13_CNT: RWRegister<u32>,
/// TIM13 prescaler
pub TIM13_PSC: RWRegister<u16>,
_reserved7: [u8; 2],
/// TIM13 auto-reload register
pub TIM13_ARR: RWRegister<u16>,
_reserved8: [u8; 6],
/// TIM13 capture/compare register 1
pub TIM13_CCR1: RWRegister<u16>,
_reserved9: [u8; 50],
/// TIM13 timer input selection register
pub TIM13_TISEL: RWRegister<u16>,
}
pub struct ResetValues {
pub TIM13_CR1: u16,
pub TIM13_DIER: u16,
pub TIM13_SR: u16,
pub TIM13_EGR: u16,
pub TIM13_CCMR1: u32,
pub TIM13_CCER: u16,
pub TIM13_CNT: u32,
pub TIM13_PSC: u16,
pub TIM13_ARR: u16,
pub TIM13_CCR1: u16,
pub TIM13_TISEL: u16,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
pub(crate) addr: u32,
pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
type Target = RegisterBlock;
#[inline(always)]
fn deref(&self) -> &RegisterBlock {
unsafe { &*(self.addr as *const _) }
}
}
#[cfg(feature = "rtic")]
unsafe impl Send for Instance {}