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#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! DLYBQS
//!
//! Used by: stm32mp153, stm32mp157
use crate::{RORegister, RWRegister};
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;
/// DLYB control register
pub mod DLYB_CR {
/// DEN
pub mod DEN {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SEN
pub mod SEN {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// DLYB configuration register
pub mod DLYB_CFGR {
/// SEL
pub mod SEL {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// UNIT
pub mod UNIT {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (7 bits: 0x7f << 8)
pub const mask: u32 = 0x7f << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// LNG
pub mod LNG {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (12 bits: 0xfff << 16)
pub const mask: u32 = 0xfff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// LNGF
pub mod LNGF {
/// Offset (31 bits)
pub const offset: u32 = 31;
/// Mask (1 bit: 1 << 31)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// DLYB IP version register
pub mod DLYB_VERR {
/// MINREV
pub mod MINREV {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// MAJREV
pub mod MAJREV {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// DLYB IP identification register
pub mod DLYB_IPIDR {
/// ID
pub mod ID {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (32 bits: 0xffffffff << 0)
pub const mask: u32 = 0xffffffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// DLYB size ID register
pub mod DLYB_SIDR {
/// SID
pub mod SID {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (32 bits: 0xffffffff << 0)
pub const mask: u32 = 0xffffffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
#[repr(C)]
pub struct RegisterBlock {
/// DLYB control register
pub DLYB_CR: RWRegister<u32>,
/// DLYB configuration register
pub DLYB_CFGR: RWRegister<u32>,
_reserved1: [u8; 1004],
/// DLYB IP version register
pub DLYB_VERR: RORegister<u32>,
/// DLYB IP identification register
pub DLYB_IPIDR: RORegister<u32>,
/// DLYB size ID register
pub DLYB_SIDR: RORegister<u32>,
}
pub struct ResetValues {
pub DLYB_CR: u32,
pub DLYB_CFGR: u32,
pub DLYB_VERR: u32,
pub DLYB_IPIDR: u32,
pub DLYB_SIDR: u32,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
pub(crate) addr: u32,
pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
type Target = RegisterBlock;
#[inline(always)]
fn deref(&self) -> &RegisterBlock {
unsafe { &*(self.addr as *const _) }
}
}
#[cfg(feature = "rtic")]
unsafe impl Send for Instance {}