#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! FMC register block
//!
//! Used by: stm32mp153, stm32mp157
use crate::{RORegister, RWRegister, WORegister};
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
pub mod FMC_BCR1 {
/// MBKEN
pub mod MBKEN {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// MUXEN
pub mod MUXEN {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// MTYP
pub mod MTYP {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (2 bits: 0b11 << 2)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// MWID
pub mod MWID {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (2 bits: 0b11 << 4)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// FACCEN
pub mod FACCEN {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (1 bit: 1 << 6)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// BURSTEN
pub mod BURSTEN {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (1 bit: 1 << 8)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WAITPOL
pub mod WAITPOL {
/// Offset (9 bits)
pub const offset: u32 = 9;
/// Mask (1 bit: 1 << 9)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WAITCFG
pub mod WAITCFG {
/// Offset (11 bits)
pub const offset: u32 = 11;
/// Mask (1 bit: 1 << 11)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WREN
pub mod WREN {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (1 bit: 1 << 12)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WAITEN
pub mod WAITEN {
/// Offset (13 bits)
pub const offset: u32 = 13;
/// Mask (1 bit: 1 << 13)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTMOD
pub mod EXTMOD {
/// Offset (14 bits)
pub const offset: u32 = 14;
/// Mask (1 bit: 1 << 14)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ASYNCWAIT
pub mod ASYNCWAIT {
/// Offset (15 bits)
pub const offset: u32 = 15;
/// Mask (1 bit: 1 << 15)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CPSIZE
pub mod CPSIZE {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (3 bits: 0b111 << 16)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CBURSTRW
pub mod CBURSTRW {
/// Offset (19 bits)
pub const offset: u32 = 19;
/// Mask (1 bit: 1 << 19)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CCLKEN
pub mod CCLKEN {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (1 bit: 1 << 20)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// NBLSET
pub mod NBLSET {
/// Offset (22 bits)
pub const offset: u32 = 22;
/// Mask (2 bits: 0b11 << 22)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// FMCEN
pub mod FMCEN {
/// Offset (31 bits)
pub const offset: u32 = 31;
/// Mask (1 bit: 1 << 31)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
pub mod FMC_BTR1 {
/// ADDSET
pub mod ADDSET {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ADDHLD
pub mod ADDHLD {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DATAST
pub mod DATAST {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (8 bits: 0xff << 8)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// BUSTURN
pub mod BUSTURN {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (4 bits: 0b1111 << 16)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CLKDIV
pub mod CLKDIV {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (4 bits: 0b1111 << 20)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DATLAT
pub mod DATLAT {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (4 bits: 0b1111 << 24)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ACCMOD
pub mod ACCMOD {
/// Offset (28 bits)
pub const offset: u32 = 28;
/// Mask (2 bits: 0b11 << 28)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DATAHLD
pub mod DATAHLD {
/// Offset (30 bits)
pub const offset: u32 = 30;
/// Mask (2 bits: 0b11 << 30)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
pub mod FMC_BCR2 {
pub use super::FMC_BCR1::ASYNCWAIT;
pub use super::FMC_BCR1::BURSTEN;
pub use super::FMC_BCR1::CBURSTRW;
pub use super::FMC_BCR1::CCLKEN;
pub use super::FMC_BCR1::CPSIZE;
pub use super::FMC_BCR1::EXTMOD;
pub use super::FMC_BCR1::FACCEN;
pub use super::FMC_BCR1::FMCEN;
pub use super::FMC_BCR1::MBKEN;
pub use super::FMC_BCR1::MTYP;
pub use super::FMC_BCR1::MUXEN;
pub use super::FMC_BCR1::MWID;
pub use super::FMC_BCR1::NBLSET;
pub use super::FMC_BCR1::WAITCFG;
pub use super::FMC_BCR1::WAITEN;
pub use super::FMC_BCR1::WAITPOL;
pub use super::FMC_BCR1::WREN;
}
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
pub mod FMC_BTR2 {
pub use super::FMC_BTR1::ACCMOD;
pub use super::FMC_BTR1::ADDHLD;
pub use super::FMC_BTR1::ADDSET;
pub use super::FMC_BTR1::BUSTURN;
pub use super::FMC_BTR1::CLKDIV;
pub use super::FMC_BTR1::DATAHLD;
pub use super::FMC_BTR1::DATAST;
pub use super::FMC_BTR1::DATLAT;
}
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
pub mod FMC_BCR3 {
pub use super::FMC_BCR1::ASYNCWAIT;
pub use super::FMC_BCR1::BURSTEN;
pub use super::FMC_BCR1::CBURSTRW;
pub use super::FMC_BCR1::CCLKEN;
pub use super::FMC_BCR1::CPSIZE;
pub use super::FMC_BCR1::EXTMOD;
pub use super::FMC_BCR1::FACCEN;
pub use super::FMC_BCR1::FMCEN;
pub use super::FMC_BCR1::MBKEN;
pub use super::FMC_BCR1::MTYP;
pub use super::FMC_BCR1::MUXEN;
pub use super::FMC_BCR1::MWID;
pub use super::FMC_BCR1::NBLSET;
pub use super::FMC_BCR1::WAITCFG;
pub use super::FMC_BCR1::WAITEN;
pub use super::FMC_BCR1::WAITPOL;
pub use super::FMC_BCR1::WREN;
}
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
pub mod FMC_BTR3 {
pub use super::FMC_BTR1::ACCMOD;
pub use super::FMC_BTR1::ADDHLD;
pub use super::FMC_BTR1::ADDSET;
pub use super::FMC_BTR1::BUSTURN;
pub use super::FMC_BTR1::CLKDIV;
pub use super::FMC_BTR1::DATAHLD;
pub use super::FMC_BTR1::DATAST;
pub use super::FMC_BTR1::DATLAT;
}
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
pub mod FMC_BCR4 {
pub use super::FMC_BCR1::ASYNCWAIT;
pub use super::FMC_BCR1::BURSTEN;
pub use super::FMC_BCR1::CBURSTRW;
pub use super::FMC_BCR1::CCLKEN;
pub use super::FMC_BCR1::CPSIZE;
pub use super::FMC_BCR1::EXTMOD;
pub use super::FMC_BCR1::FACCEN;
pub use super::FMC_BCR1::FMCEN;
pub use super::FMC_BCR1::MBKEN;
pub use super::FMC_BCR1::MTYP;
pub use super::FMC_BCR1::MUXEN;
pub use super::FMC_BCR1::MWID;
pub use super::FMC_BCR1::NBLSET;
pub use super::FMC_BCR1::WAITCFG;
pub use super::FMC_BCR1::WAITEN;
pub use super::FMC_BCR1::WAITPOL;
pub use super::FMC_BCR1::WREN;
}
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
pub mod FMC_BTR4 {
pub use super::FMC_BTR1::ACCMOD;
pub use super::FMC_BTR1::ADDHLD;
pub use super::FMC_BTR1::ADDSET;
pub use super::FMC_BTR1::BUSTURN;
pub use super::FMC_BTR1::CLKDIV;
pub use super::FMC_BTR1::DATAHLD;
pub use super::FMC_BTR1::DATAST;
pub use super::FMC_BTR1::DATLAT;
}
/// This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h
pub mod FMC_PCSCNTR {
/// CSCOUNT
pub mod CSCOUNT {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CNTB1EN
pub mod CNTB1EN {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (1 bit: 1 << 16)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CNTB2EN
pub mod CNTB2EN {
/// Offset (17 bits)
pub const offset: u32 = 17;
/// Mask (1 bit: 1 << 17)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CNTB3EN
pub mod CNTB3EN {
/// Offset (18 bits)
pub const offset: u32 = 18;
/// Mask (1 bit: 1 << 18)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CNTB4EN
pub mod CNTB4EN {
/// Offset (19 bits)
pub const offset: u32 = 19;
/// Mask (1 bit: 1 << 19)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// NAND Flash Programmable control register
pub mod FMC_PCR {
/// PWAITEN
pub mod PWAITEN {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// PBKEN
pub mod PBKEN {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// PWID
pub mod PWID {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (2 bits: 0b11 << 4)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ECCEN
pub mod ECCEN {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (1 bit: 1 << 6)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ECCALG
pub mod ECCALG {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (1 bit: 1 << 8)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// TCLR
pub mod TCLR {
/// Offset (9 bits)
pub const offset: u32 = 9;
/// Mask (4 bits: 0b1111 << 9)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// TAR
pub mod TAR {
/// Offset (13 bits)
pub const offset: u32 = 13;
/// Mask (4 bits: 0b1111 << 13)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ECCSS
pub mod ECCSS {
/// Offset (17 bits)
pub const offset: u32 = 17;
/// Mask (3 bits: 0b111 << 17)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// TCEH
pub mod TCEH {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (4 bits: 0b1111 << 20)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// BCHECC
pub mod BCHECC {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (1 bit: 1 << 24)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WEN
pub mod WEN {
/// Offset (25 bits)
pub const offset: u32 = 25;
/// Mask (1 bit: 1 << 25)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits.
pub mod FMC_SR {
/// ISOST
pub mod ISOST {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (2 bits: 0b11 << 0)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// PEF
pub mod PEF {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// NWRF
pub mod NWRF {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (1 bit: 1 << 6)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses.
pub mod FMC_PMEM {
/// MEMSET
pub mod MEMSET {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (8 bits: 0xff << 0)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// MEMWAIT
pub mod MEMWAIT {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (8 bits: 0xff << 8)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// MEMHOLD
pub mod MEMHOLD {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (8 bits: 0xff << 16)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// MEMHIZ
pub mod MEMHIZ {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (8 bits: 0xff << 24)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function).
pub mod FMC_PATT {
/// ATTSET
pub mod ATTSET {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (8 bits: 0xff << 0)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ATTWAIT
pub mod ATTWAIT {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (8 bits: 0xff << 8)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ATTHOLD
pub mod ATTHOLD {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (8 bits: 0xff << 16)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ATTHIZ
pub mod ATTHIZ {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (8 bits: 0xff << 24)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
pub mod FMC_HPR {
/// HPR
pub mod HPR {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (32 bits: 0xffffffff << 0)
pub const mask: u32 = 0xffffffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
pub mod FMC_HECCR {
/// HECC
pub mod HECC {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (32 bits: 0xffffffff << 0)
pub const mask: u32 = 0xffffffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
pub mod FMC_BWTR1 {
/// ADDSET
pub mod ADDSET {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ADDHLD
pub mod ADDHLD {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DATAST
pub mod DATAST {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (8 bits: 0xff << 8)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// BUSTURN
pub mod BUSTURN {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (4 bits: 0b1111 << 16)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ACCMOD
pub mod ACCMOD {
/// Offset (28 bits)
pub const offset: u32 = 28;
/// Mask (2 bits: 0b11 << 28)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DATAHLD
pub mod DATAHLD {
/// Offset (30 bits)
pub const offset: u32 = 30;
/// Mask (2 bits: 0b11 << 30)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
pub mod FMC_BWTR2 {
pub use super::FMC_BWTR1::ACCMOD;
pub use super::FMC_BWTR1::ADDHLD;
pub use super::FMC_BWTR1::ADDSET;
pub use super::FMC_BWTR1::BUSTURN;
pub use super::FMC_BWTR1::DATAHLD;
pub use super::FMC_BWTR1::DATAST;
}
/// This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
pub mod FMC_BWTR3 {
pub use super::FMC_BWTR1::ACCMOD;
pub use super::FMC_BWTR1::ADDHLD;
pub use super::FMC_BWTR1::ADDSET;
pub use super::FMC_BWTR1::BUSTURN;
pub use super::FMC_BWTR1::DATAHLD;
pub use super::FMC_BWTR1::DATAST;
}
/// This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
pub mod FMC_BWTR4 {
pub use super::FMC_BWTR1::ACCMOD;
pub use super::FMC_BWTR1::ADDHLD;
pub use super::FMC_BWTR1::ADDSET;
pub use super::FMC_BWTR1::BUSTURN;
pub use super::FMC_BWTR1::DATAHLD;
pub use super::FMC_BWTR1::DATAST;
}
/// FMC NAND Command Sequencer Control Register
pub mod FMC_CSQCR {
/// CSQSTART
pub mod CSQSTART {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC NAND Command Sequencer Configuration Register 1
pub mod FMC_CSQCFGR1 {
/// CMD2EN
pub mod CMD2EN {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DMADEN
pub mod DMADEN {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ACYNBR
pub mod ACYNBR {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (3 bits: 0b111 << 4)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CMD1
pub mod CMD1 {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (8 bits: 0xff << 8)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CMD2
pub mod CMD2 {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (8 bits: 0xff << 16)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CMD1T
pub mod CMD1T {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (1 bit: 1 << 24)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CMD2T
pub mod CMD2T {
/// Offset (25 bits)
pub const offset: u32 = 25;
/// Mask (1 bit: 1 << 25)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written. .
pub mod FMC_CSQCFGR2 {
/// SQSDTEN
pub mod SQSDTEN {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RCMD2EN
pub mod RCMD2EN {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DMASEN
pub mod DMASEN {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RCMD1
pub mod RCMD1 {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (8 bits: 0xff << 8)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RCMD2
pub mod RCMD2 {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (8 bits: 0xff << 16)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RCMD1T
pub mod RCMD1T {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (1 bit: 1 << 24)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RCMD2T
pub mod RCMD2T {
/// Offset (25 bits)
pub const offset: u32 = 25;
/// Mask (1 bit: 1 << 25)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC NAND sequencer configuration register 3
pub mod FMC_CSQCFGR3 {
/// SNBR
pub mod SNBR {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (6 bits: 0x3f << 8)
pub const mask: u32 = 0x3f << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// AC1T
pub mod AC1T {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (1 bit: 1 << 16)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// AC2T
pub mod AC2T {
/// Offset (17 bits)
pub const offset: u32 = 17;
/// Mask (1 bit: 1 << 17)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// AC3T
pub mod AC3T {
/// Offset (18 bits)
pub const offset: u32 = 18;
/// Mask (1 bit: 1 << 18)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// AC4T
pub mod AC4T {
/// Offset (19 bits)
pub const offset: u32 = 19;
/// Mask (1 bit: 1 << 19)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// AC5T
pub mod AC5T {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (1 bit: 1 << 20)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SDT
pub mod SDT {
/// Offset (21 bits)
pub const offset: u32 = 21;
/// Mask (1 bit: 1 << 21)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RAC1T
pub mod RAC1T {
/// Offset (22 bits)
pub const offset: u32 = 22;
/// Mask (1 bit: 1 << 22)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RAC2T
pub mod RAC2T {
/// Offset (23 bits)
pub const offset: u32 = 23;
/// Mask (1 bit: 1 << 23)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer.
pub mod FMC_CSQAR1 {
/// ADDC1
pub mod ADDC1 {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (8 bits: 0xff << 0)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ADDC2
pub mod ADDC2 {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (8 bits: 0xff << 8)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ADDC3
pub mod ADDC3 {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (8 bits: 0xff << 16)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ADDC4
pub mod ADDC4 {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (8 bits: 0xff << 24)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable.
pub mod FMC_CSQAR2 {
/// ADDC5
pub mod ADDC5 {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (8 bits: 0xff << 0)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// NANDCEN0
pub mod NANDCEN0 {
/// Offset (10 bits)
pub const offset: u32 = 10;
/// Mask (1 bit: 1 << 10)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// NANDCEN1
pub mod NANDCEN1 {
/// Offset (11 bits)
pub const offset: u32 = 11;
/// Mask (1 bit: 1 << 11)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SAO
pub mod SAO {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (16 bits: 0xffff << 16)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC NAND Command Sequencer Interrupt Enable Register
pub mod FMC_CSQIER {
/// TCIE
pub mod TCIE {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SCIE
pub mod SCIE {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SEIE
pub mod SEIE {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SUEIE
pub mod SUEIE {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CMDTCIE
pub mod CMDTCIE {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC NAND Command Sequencer Interrupt Status Register
pub mod FMC_CSQISR {
/// TCF
pub mod TCF {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SCF
pub mod SCF {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SEF
pub mod SEF {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SUEF
pub mod SUEF {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CMDTCF
pub mod CMDTCF {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC NAND Command Sequencer Interrupt Clear Register
pub mod FMC_CSQICR {
/// CTCF
pub mod CTCF {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CSCF
pub mod CSCF {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CSEF
pub mod CSEF {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CSUEF
pub mod CSUEF {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CCMDTCF
pub mod CCMDTCF {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register holds a sector error mapping status when the whole transfer is complete.
pub mod FMC_CSQEMSR {
/// SEM
pub mod SEM {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC BCH Interrupt enable register
pub mod FMC_BCHIER {
/// DUEIE
pub mod DUEIE {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DERIE
pub mod DERIE {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DEFIE
pub mod DEFIE {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DSRIE
pub mod DSRIE {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EPBRIE
pub mod EPBRIE {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared.
pub mod FMC_BCHISR {
/// DUEF
pub mod DUEF {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DERF
pub mod DERF {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DEFF
pub mod DEFF {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DSRF
pub mod DSRF {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EPBRF
pub mod EPBRF {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC BCH Interrupt Clear Register
pub mod FMC_BCHICR {
/// CDUEF
pub mod CDUEF {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CDERF
pub mod CDERF {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CDEFF
pub mod CDEFF {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CDSRF
pub mod CDSRF {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CEPBRF
pub mod CEPBRF {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB\[51:0\] are significant and for the BCH 8-bit BCHPB\[103:0\] are significant.
pub mod FMC_BCHPBR1 {
/// BCHPB
pub mod BCHPB {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (32 bits: 0xffffffff << 0)
pub const mask: u32 = 0xffffffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC BCH Parity Bits Register 2
pub mod FMC_BCHPBR2 {
pub use super::FMC_BCHPBR1::BCHPB;
}
/// FMC BCH Parity Bits Register 3
pub mod FMC_BCHPBR3 {
pub use super::FMC_BCHPBR1::BCHPB;
}
/// FMC BCH Parity Bits Register 4
pub mod FMC_BCHPBR4 {
/// BCHPB
pub mod BCHPB {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (8 bits: 0xff << 0)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer. .
pub mod FMC_BCHDSR0 {
/// DUE
pub mod DUE {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DEF
pub mod DEF {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DEN
pub mod DEN {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// The maximum error correction capability of the BCH block embedded in the FMC is 8 errors
pub mod FMC_BCHDSR1 {
/// EBP1
pub mod EBP1 {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (13 bits: 0x1fff << 0)
pub const mask: u32 = 0x1fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EBP2
pub mod EBP2 {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (13 bits: 0x1fff << 16)
pub const mask: u32 = 0x1fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively.
pub mod FMC_BCHDSR2 {
/// EBP3
pub mod EBP3 {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (13 bits: 0x1fff << 0)
pub const mask: u32 = 0x1fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EBP4
pub mod EBP4 {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (13 bits: 0x1fff << 16)
pub const mask: u32 = 0x1fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// The maximum error correction capability of the BCH block embedded in the FMC is 8 errors.
pub mod FMC_BCHDSR3 {
/// EBP5
pub mod EBP5 {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (13 bits: 0x1fff << 0)
pub const mask: u32 = 0x1fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EBP6
pub mod EBP6 {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (13 bits: 0x1fff << 16)
pub const mask: u32 = 0x1fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively. .
pub mod FMC_BCHDSR4 {
/// EBP7
pub mod EBP7 {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (13 bits: 0x1fff << 0)
pub const mask: u32 = 0x1fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EBP8
pub mod EBP8 {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (13 bits: 0x1fff << 16)
pub const mask: u32 = 0x1fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC Hardware configuration register 2
pub mod FMC_HWCFGR2 {
/// RD_LN2DPTH
pub mod RD_LN2DPTH {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// NOR_BASE
pub mod NOR_BASE {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SDRAM_RBASE
pub mod SDRAM_RBASE {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (4 bits: 0b1111 << 8)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// NAND_BASE
pub mod NAND_BASE {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (4 bits: 0b1111 << 12)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SDRAM1_BASE
pub mod SDRAM1_BASE {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (4 bits: 0b1111 << 16)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SDRAM2_BASE
pub mod SDRAM2_BASE {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (4 bits: 0b1111 << 20)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC Hardware configuration register 1
pub mod FMC_HWCFGR1 {
/// NAND_SEL
pub mod NAND_SEL {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// NAND_ECC
pub mod NAND_ECC {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// SDRAM_SEL
pub mod SDRAM_SEL {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (1 bit: 1 << 8)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ID_SIZE
pub mod ID_SIZE {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (4 bits: 0b1111 << 12)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WA_LN2DPTH
pub mod WA_LN2DPTH {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (4 bits: 0b1111 << 16)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WD_LN2DPTH
pub mod WD_LN2DPTH {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (4 bits: 0b1111 << 20)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WR_LN2DPTH
pub mod WR_LN2DPTH {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (4 bits: 0b1111 << 24)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RA_LN2DPTH
pub mod RA_LN2DPTH {
/// Offset (28 bits)
pub const offset: u32 = 28;
/// Mask (4 bits: 0b1111 << 28)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC Version register
pub mod FMC_VERR {
/// MINREV
pub mod MINREV {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// MAJREV
pub mod MAJREV {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC Identification register
pub mod FMC_IPIDR {
/// ID
pub mod ID {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (32 bits: 0xffffffff << 0)
pub const mask: u32 = 0xffffffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// FMC Size Identification register
pub mod FMC_SIDR {
/// SID
pub mod SID {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (32 bits: 0xffffffff << 0)
pub const mask: u32 = 0xffffffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
#[repr(C)]
pub struct RegisterBlock {
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
pub FMC_BCR1: RWRegister<u32>,
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
pub FMC_BTR1: RWRegister<u32>,
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
pub FMC_BCR2: RWRegister<u32>,
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
pub FMC_BTR2: RWRegister<u32>,
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
pub FMC_BCR3: RWRegister<u32>,
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
pub FMC_BTR3: RWRegister<u32>,
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
pub FMC_BCR4: RWRegister<u32>,
/// This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
pub FMC_BTR4: RWRegister<u32>,
/// This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h
pub FMC_PCSCNTR: RWRegister<u32>,
_reserved1: [u8; 92],
/// NAND Flash Programmable control register
pub FMC_PCR: RWRegister<u32>,
/// This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits.
pub FMC_SR: RORegister<u32>,
/// The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses.
pub FMC_PMEM: RWRegister<u32>,
/// The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function).
pub FMC_PATT: RWRegister<u32>,
/// This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
pub FMC_HPR: RORegister<u32>,
/// This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
pub FMC_HECCR: RORegister<u32>,
_reserved2: [u8; 108],
/// This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
pub FMC_BWTR1: RWRegister<u32>,
_reserved3: [u8; 4],
/// This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
pub FMC_BWTR2: RWRegister<u32>,
_reserved4: [u8; 4],
/// This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
pub FMC_BWTR3: RWRegister<u32>,
_reserved5: [u8; 4],
/// This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
pub FMC_BWTR4: RWRegister<u32>,
_reserved6: [u8; 224],
/// FMC NAND Command Sequencer Control Register
pub FMC_CSQCR: WORegister<u32>,
/// FMC NAND Command Sequencer Configuration Register 1
pub FMC_CSQCFGR1: RWRegister<u32>,
/// This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written. .
pub FMC_CSQCFGR2: RWRegister<u32>,
/// FMC NAND sequencer configuration register 3
pub FMC_CSQCFGR3: RWRegister<u32>,
/// This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer.
pub FMC_CSQAR1: RWRegister<u32>,
/// This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable.
pub FMC_CSQAR2: RWRegister<u32>,
_reserved7: [u8; 8],
/// FMC NAND Command Sequencer Interrupt Enable Register
pub FMC_CSQIER: RWRegister<u32>,
/// FMC NAND Command Sequencer Interrupt Status Register
pub FMC_CSQISR: RWRegister<u32>,
/// FMC NAND Command Sequencer Interrupt Clear Register
pub FMC_CSQICR: WORegister<u32>,
_reserved8: [u8; 4],
/// This register holds a sector error mapping status when the whole transfer is complete.
pub FMC_CSQEMSR: RORegister<u32>,
_reserved9: [u8; 28],
/// FMC BCH Interrupt enable register
pub FMC_BCHIER: RWRegister<u32>,
/// This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared.
pub FMC_BCHISR: RORegister<u32>,
/// FMC BCH Interrupt Clear Register
pub FMC_BCHICR: WORegister<u32>,
_reserved10: [u8; 4],
/// These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB\[51:0\] are significant and for the BCH 8-bit BCHPB\[103:0\] are significant.
pub FMC_BCHPBR1: RORegister<u32>,
/// FMC BCH Parity Bits Register 2
pub FMC_BCHPBR2: RORegister<u32>,
/// FMC BCH Parity Bits Register 3
pub FMC_BCHPBR3: RORegister<u32>,
/// FMC BCH Parity Bits Register 4
pub FMC_BCHPBR4: RORegister<u32>,
_reserved11: [u8; 12],
/// This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer. .
pub FMC_BCHDSR0: RORegister<u32>,
/// The maximum error correction capability of the BCH block embedded in the FMC is 8 errors
pub FMC_BCHDSR1: RORegister<u32>,
/// The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively.
pub FMC_BCHDSR2: RORegister<u32>,
/// The maximum error correction capability of the BCH block embedded in the FMC is 8 errors.
pub FMC_BCHDSR3: RORegister<u32>,
/// The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively. .
pub FMC_BCHDSR4: RORegister<u32>,
_reserved12: [u8; 348],
/// FMC Hardware configuration register 2
pub FMC_HWCFGR2: RORegister<u32>,
/// FMC Hardware configuration register 1
pub FMC_HWCFGR1: RORegister<u32>,
/// FMC Version register
pub FMC_VERR: RORegister<u32>,
/// FMC Identification register
pub FMC_IPIDR: RORegister<u32>,
/// FMC Size Identification register
pub FMC_SIDR: RORegister<u32>,
}
pub struct ResetValues {
pub FMC_BCR1: u32,
pub FMC_BTR1: u32,
pub FMC_BCR2: u32,
pub FMC_BTR2: u32,
pub FMC_BCR3: u32,
pub FMC_BTR3: u32,
pub FMC_BCR4: u32,
pub FMC_BTR4: u32,
pub FMC_PCSCNTR: u32,
pub FMC_PCR: u32,
pub FMC_SR: u32,
pub FMC_PMEM: u32,
pub FMC_PATT: u32,
pub FMC_HPR: u32,
pub FMC_HECCR: u32,
pub FMC_BWTR1: u32,
pub FMC_BWTR2: u32,
pub FMC_BWTR3: u32,
pub FMC_BWTR4: u32,
pub FMC_CSQCR: u32,
pub FMC_CSQCFGR1: u32,
pub FMC_CSQCFGR2: u32,
pub FMC_CSQCFGR3: u32,
pub FMC_CSQAR1: u32,
pub FMC_CSQAR2: u32,
pub FMC_CSQIER: u32,
pub FMC_CSQISR: u32,
pub FMC_CSQICR: u32,
pub FMC_CSQEMSR: u32,
pub FMC_BCHIER: u32,
pub FMC_BCHISR: u32,
pub FMC_BCHICR: u32,
pub FMC_BCHPBR1: u32,
pub FMC_BCHPBR2: u32,
pub FMC_BCHPBR3: u32,
pub FMC_BCHPBR4: u32,
pub FMC_BCHDSR0: u32,
pub FMC_BCHDSR1: u32,
pub FMC_BCHDSR2: u32,
pub FMC_BCHDSR3: u32,
pub FMC_BCHDSR4: u32,
pub FMC_HWCFGR2: u32,
pub FMC_HWCFGR1: u32,
pub FMC_VERR: u32,
pub FMC_IPIDR: u32,
pub FMC_SIDR: u32,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
pub(crate) addr: u32,
pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
type Target = RegisterBlock;
#[inline(always)]
fn deref(&self) -> &RegisterBlock {
unsafe { &*(self.addr as *const _) }
}
}
#[cfg(feature = "rtic")]
unsafe impl Send for Instance {}