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#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! IWDG1
//!
//! Used by: stm32mp153, stm32mp157
use crate::{RORegister, RWRegister, WORegister};
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;
/// Key register
pub mod IWDG_KR {
/// KEY
pub mod KEY {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Prescaler register
pub mod IWDG_PR {
/// PR
pub mod PR {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (3 bits: 0b111 << 0)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Reload register
pub mod IWDG_RLR {
/// RL
pub mod RL {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (12 bits: 0xfff << 0)
pub const mask: u32 = 0xfff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Status register
pub mod IWDG_SR {
/// PVU
pub mod PVU {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RVU
pub mod RVU {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WVU
pub mod WVU {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Window register
pub mod IWDG_WINR {
/// WIN
pub mod WIN {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (12 bits: 0xfff << 0)
pub const mask: u32 = 0xfff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// IWDG hardware configuration register
pub mod IWDG_HWCFGR {
/// WINDOW
pub mod WINDOW {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// PR_DEFAULT
pub mod PR_DEFAULT {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// IWDG version register
pub mod IWDG_VERR {
/// MINREV
pub mod MINREV {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// MAJREV
pub mod MAJREV {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// IWDG identification register
pub mod IWDG_IDR {
/// ID
pub mod ID {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (32 bits: 0xffffffff << 0)
pub const mask: u32 = 0xffffffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// IWDG size identification register
pub mod IWDG_SIDR {
/// SID
pub mod SID {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (32 bits: 0xffffffff << 0)
pub const mask: u32 = 0xffffffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
#[repr(C)]
pub struct RegisterBlock {
/// Key register
pub IWDG_KR: WORegister<u32>,
/// Prescaler register
pub IWDG_PR: RWRegister<u32>,
/// Reload register
pub IWDG_RLR: RWRegister<u32>,
/// Status register
pub IWDG_SR: RORegister<u32>,
/// Window register
pub IWDG_WINR: RWRegister<u32>,
_reserved1: [u8; 988],
/// IWDG hardware configuration register
pub IWDG_HWCFGR: RORegister<u32>,
/// IWDG version register
pub IWDG_VERR: RORegister<u32>,
/// IWDG identification register
pub IWDG_IDR: RORegister<u32>,
/// IWDG size identification register
pub IWDG_SIDR: RORegister<u32>,
}
pub struct ResetValues {
pub IWDG_KR: u32,
pub IWDG_PR: u32,
pub IWDG_RLR: u32,
pub IWDG_SR: u32,
pub IWDG_WINR: u32,
pub IWDG_HWCFGR: u32,
pub IWDG_VERR: u32,
pub IWDG_IDR: u32,
pub IWDG_SIDR: u32,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
pub(crate) addr: u32,
pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
type Target = RegisterBlock;
#[inline(always)]
fn deref(&self) -> &RegisterBlock {
unsafe { &*(self.addr as *const _) }
}
}
#[cfg(feature = "rtic")]
unsafe impl Send for Instance {}