Struct lpc55s6x_pac::syscon::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub memoryremap: MEMORYREMAP,
    pub ahbmatprio: AHBMATPRIO,
    pub cpu0stckcal: CPU0STCKCAL,
    pub cpu0nstckcal: CPU0NSTCKCAL,
    pub cpu1tckcal: CPU1TCKCAL,
    pub nmisrc: NMISRC,
    pub presetctrlset: [PRESETCTRLSET; 3],
    pub presetctrlclr: [PRESETCTRLCLR; 3],
    pub swr_reset: SWR_RESET,
    pub ahbclkctrlset: [AHBCLKCTRLSET; 3],
    pub ahbclkctrlclr: [AHBCLKCTRLCLR; 3],
    pub traceclksel: TRACECLKSEL,
    pub mainclksela: MAINCLKSELA,
    pub mainclkselb: MAINCLKSELB,
    pub clkoutsel: CLKOUTSEL,
    pub pll0clksel: PLL0CLKSEL,
    pub pll1clksel: PLL1CLKSEL,
    pub adcclksel: ADCCLKSEL,
    pub usb0clksel: USB0CLKSEL,
    pub usb1clksel: USB1CLKSEL,
    pub hslspiclksel: HSLSPICLKSEL,
    pub mclkclksel: MCLKCLKSEL,
    pub sctclksel: SCTCLKSEL,
    pub sdioclksel: SDIOCLKSEL,
    pub systickclkdiv0: SYSTICKCLKDIV0,
    pub systickclkdiv1: SYSTICKCLKDIV1,
    pub traceclkdiv: TRACECLKDIV,
    pub ahbclkdiv: AHBCLKDIV,
    pub clkoutdiv: CLKOUTDIV,
    pub frohfdiv: FROHFDIV,
    pub wdtclkdiv: WDTCLKDIV,
    pub adcclkdiv: ADCCLKDIV,
    pub usb0clkdiv: USB0CLKDIV,
    pub mclkdiv: MCLKDIV,
    pub sctclkdiv: SCTCLKDIV,
    pub sdioclkdiv: SDIOCLKDIV,
    pub pll0clkdiv: PLL0CLKDIV,
    pub clockgenupdatelockout: CLOCKGENUPDATELOCKOUT,
    pub fmccr: FMCCR,
    pub usb0clkctrl: USB0CLKCTRL,
    pub usb0clkstat: USB0CLKSTAT,
    pub fmcflush: FMCFLUSH,
    pub mclkio: MCLKIO,
    pub usb1clkctrl: USB1CLKCTRL,
    pub usb1clkstat: USB1CLKSTAT,
    pub flashbankenable: FLASHBANKENABLE,
    pub sdioclkctrl: SDIOCLKCTRL,
    pub pll1ctrl: PLL1CTRL,
    pub pll1stat: PLL1STAT,
    pub pll1ndec: PLL1NDEC,
    pub pll1mdec: PLL1MDEC,
    pub pll1pdec: PLL1PDEC,
    pub pll0ctrl: PLL0CTRL,
    pub pll0stat: PLL0STAT,
    pub pll0ndec: PLL0NDEC,
    pub pll0pdec: PLL0PDEC,
    pub pll0sscg0: PLL0SSCG0,
    pub pll0sscg1: PLL0SSCG1,
    pub efuseclkctrl: EFUSECLKCTRL,
    pub starter0: STARTER0,
    pub starter1: STARTER1,
    pub starterset0: STARTERSET0,
    pub starterset1: STARTERSET1,
    pub starterclr0: STARTERCLR0,
    pub starterclr1: STARTERCLR1,
    pub hardwaresleep: HARDWARESLEEP,
    pub cpuctrl: CPUCTRL,
    pub cpboot: CPBOOT,
    pub cpstack: CPSTACK,
    pub cpstat: CPSTAT,
    pub dice_reg0: DICE_REG0,
    pub dice_reg1: DICE_REG1,
    pub dice_reg2: DICE_REG2,
    pub dice_reg3: DICE_REG3,
    pub dice_reg4: DICE_REG4,
    pub dice_reg5: DICE_REG5,
    pub dice_reg6: DICE_REG6,
    pub dice_reg7: DICE_REG7,
    pub clock_ctrl: CLOCK_CTRL,
    pub comp_int_ctrl: COMP_INT_CTRL,
    pub comp_int_status: COMP_INT_STATUS,
    pub autoclkgateoverride: AUTOCLKGATEOVERRIDE,
    pub gpiopsync: GPIOPSYNC,
    pub debug_lock_en: DEBUG_LOCK_EN,
    pub debug_features: DEBUG_FEATURES,
    pub debug_features_dp: DEBUG_FEATURES_DP,
    pub codesecurityprottest: CODESECURITYPROTTEST,
    pub codesecurityprotcpu0: CODESECURITYPROTCPU0,
    pub codesecurityprotcpu1: CODESECURITYPROTCPU1,
    pub key_block: KEY_BLOCK,
    pub debug_auth_scratch: DEBUG_AUTH_SCRATCH,
    pub cpucfg: CPUCFG,
    pub periphencfg: PERIPHENCFG,
    pub device_id0: DEVICE_ID0,
    pub dieid: DIEID,
    // some fields omitted
}

Register block

Fields

memoryremap: MEMORYREMAP

0x00 - Memory Remap control register

ahbmatprio: AHBMATPRIO

0x10 - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest

cpu0stckcal: CPU0STCKCAL

0x38 - System tick calibration for secure part of CPU0

cpu0nstckcal: CPU0NSTCKCAL

0x3c - System tick calibration for non-secure part of CPU0

cpu1tckcal: CPU1TCKCAL

0x40 - System tick calibration for CPU1

nmisrc: NMISRC

0x48 - NMI Source Select

presetctrlset: [PRESETCTRLSET; 3]

0x120 - Peripheral reset control set register

presetctrlclr: [PRESETCTRLCLR; 3]

0x140 - Peripheral reset contro clearl register

swr_reset: SWR_RESET

0x160 - generate a software_reset

ahbclkctrlset: [AHBCLKCTRLSET; 3]

0x220 - Peripheral reset control register

ahbclkctrlclr: [AHBCLKCTRLCLR; 3]

0x240 - Peripheral reset control register

traceclksel: TRACECLKSEL

0x268 - Trace clock source select

mainclksela: MAINCLKSELA

0x280 - Main clock A source select

mainclkselb: MAINCLKSELB

0x284 - Main clock source select

clkoutsel: CLKOUTSEL

0x288 - CLKOUT clock source select

pll0clksel: PLL0CLKSEL

0x290 - PLL0 clock source select

pll1clksel: PLL1CLKSEL

0x294 - PLL1 clock source select

adcclksel: ADCCLKSEL

0x2a4 - ADC clock source select

usb0clksel: USB0CLKSEL

0x2a8 - FS USB clock source select

usb1clksel: USB1CLKSEL

0x2ac - HS USB clock source select - NOT USED

hslspiclksel: HSLSPICLKSEL

0x2d0 - HS LSPI clock source select

mclkclksel: MCLKCLKSEL

0x2e0 - MCLK clock source select

sctclksel: SCTCLKSEL

0x2f0 - SCTimer/PWM clock source select

sdioclksel: SDIOCLKSEL

0x2f8 - SDIO clock source select

systickclkdiv0: SYSTICKCLKDIV0

0x300 - System Tick Timer divider for CPU0

systickclkdiv1: SYSTICKCLKDIV1

0x304 - System Tick Timer divider for CPU1

traceclkdiv: TRACECLKDIV

0x308 - TRACE clock divider

ahbclkdiv: AHBCLKDIV

0x380 - System clock divider

clkoutdiv: CLKOUTDIV

0x384 - CLKOUT clock divider

frohfdiv: FROHFDIV

0x388 - FRO_HF (96MHz) clock divider

wdtclkdiv: WDTCLKDIV

0x38c - WDT clock divider

adcclkdiv: ADCCLKDIV

0x394 - ADC clock divider

usb0clkdiv: USB0CLKDIV

0x398 - USB0 Clock divider

mclkdiv: MCLKDIV

0x3ac - I2S MCLK clock divider

sctclkdiv: SCTCLKDIV

0x3b4 - SCT/PWM clock divider

sdioclkdiv: SDIOCLKDIV

0x3bc - SDIO clock divider

pll0clkdiv: PLL0CLKDIV

0x3c4 - PLL0 clock divider

clockgenupdatelockout: CLOCKGENUPDATELOCKOUT

0x3fc - Control clock configuration registers access (like xxxDIV, xxxSEL)

fmccr: FMCCR

0x400 - FMC configuration register - INTERNAL USE ONLY

usb0clkctrl: USB0CLKCTRL

0x40c - USB0 clock control

usb0clkstat: USB0CLKSTAT

0x410 - USB0 clock status

fmcflush: FMCFLUSH

0x41c - FMCflush control

mclkio: MCLKIO

0x420 - MCLK control

usb1clkctrl: USB1CLKCTRL

0x424 - USB1 clock control

usb1clkstat: USB1CLKSTAT

0x428 - USB1 clock status

flashbankenable: FLASHBANKENABLE

0x450 - Flash Banks control

sdioclkctrl: SDIOCLKCTRL

0x460 - SDIO CCLKIN phase and delay control

pll1ctrl: PLL1CTRL

0x560 - PLL1 550m control

pll1stat: PLL1STAT

0x564 - PLL1 550m status

pll1ndec: PLL1NDEC

0x568 - PLL1 550m N divider

pll1mdec: PLL1MDEC

0x56c - PLL1 550m M divider

pll1pdec: PLL1PDEC

0x570 - PLL1 550m P divider

pll0ctrl: PLL0CTRL

0x580 - PLL0 550m control

pll0stat: PLL0STAT

0x584 - PLL0 550m status

pll0ndec: PLL0NDEC

0x588 - PLL0 550m N divider

pll0pdec: PLL0PDEC

0x58c - PLL0 550m P divider

pll0sscg0: PLL0SSCG0

0x590 - PLL0 Spread Spectrum Wrapper control register 0

pll0sscg1: PLL0SSCG1

0x594 - PLL0 Spread Spectrum Wrapper control register 1

efuseclkctrl: EFUSECLKCTRL

0x5cc - eFUSE controller clock enable

starter0: STARTER0

0x680 - Start logic wake-up enable register

starter1: STARTER1

0x684 - Start logic wake-up enable register

starterset0: STARTERSET0

0x6a0 - Set bits in STARTER

starterset1: STARTERSET1

0x6a4 - Set bits in STARTER

starterclr0: STARTERCLR0

0x6c0 - Clear bits in STARTER

starterclr1: STARTERCLR1

0x6c4 - Clear bits in STARTER

hardwaresleep: HARDWARESLEEP

0x780 - Hardware Sleep control

cpuctrl: CPUCTRL

0x800 - CPU Control for multiple processors

cpboot: CPBOOT

0x804 - Coprocessor Boot Address

cpstack: CPSTACK

0x808 - Coprocessor Stack Address

cpstat: CPSTAT

0x80c - CPU Status

dice_reg0: DICE_REG0

0x900 - Composite Device Identifier

dice_reg1: DICE_REG1

0x904 - Composite Device Identifier

dice_reg2: DICE_REG2

0x908 - Composite Device Identifier

dice_reg3: DICE_REG3

0x90c - Composite Device Identifier

dice_reg4: DICE_REG4

0x910 - Composite Device Identifier

dice_reg5: DICE_REG5

0x914 - Composite Device Identifier

dice_reg6: DICE_REG6

0x918 - Composite Device Identifier

dice_reg7: DICE_REG7

0x91c - Composite Device Identifier

clock_ctrl: CLOCK_CTRL

0xa18 - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures

comp_int_ctrl: COMP_INT_CTRL

0xb10 - Comparator Interrupt control

comp_int_status: COMP_INT_STATUS

0xb14 - Comparator Interrupt status

autoclkgateoverride: AUTOCLKGATEOVERRIDE

0xe04 - Control automatic clock gating

gpiopsync: GPIOPSYNC

0xe08 - Enable bypass of the first stage of synchonization inside GPIO_INT module

debug_lock_en: DEBUG_LOCK_EN

0xfa0 - Control write access to security registers -- FOR INTERNAl USE ONLY

debug_features: DEBUG_FEATURES

0xfa4 - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY

debug_features_dp: DEBUG_FEATURES_DP

0xfa8 - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY

codesecurityprottest: CODESECURITYPROTTEST

0xfb0 - Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY

codesecurityprotcpu0: CODESECURITYPROTCPU0

0xfb4 - Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY

codesecurityprotcpu1: CODESECURITYPROTCPU1

0xfb8 - Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY

key_block: KEY_BLOCK

0xfbc - block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY

debug_auth_scratch: DEBUG_AUTH_SCRATCH

0xfc0 - Debug authentication scratch registers -- FOR INTERNAL USE ONLY

cpucfg: CPUCFG

0xfd4 - CPUs configuration register

periphencfg: PERIPHENCFG

0xfec - peripheral enable configuration -- FOR INTERNAL USE ONLY

device_id0: DEVICE_ID0

0xff8 - Device ID

dieid: DIEID

0xffc - Chip revision ID and Number

Methods

impl RegisterBlock

pub fn presetctrlx0(&self) -> &PRESETCTRLX0

0x100 - Peripheral reset control register

pub fn presetctrlx0_mut(&self) -> &mut PRESETCTRLX0

0x100 - Peripheral reset control register

pub fn presetctrl0(&self) -> &PRESETCTRL0

0x100 - Peripheral reset control 0

pub fn presetctrl0_mut(&self) -> &mut PRESETCTRL0

0x100 - Peripheral reset control 0

pub fn presetctrlx1(&self) -> &PRESETCTRLX1

0x104 - Peripheral reset control register

pub fn presetctrlx1_mut(&self) -> &mut PRESETCTRLX1

0x104 - Peripheral reset control register

pub fn presetctrl1(&self) -> &PRESETCTRL1

0x104 - Peripheral reset control 1

pub fn presetctrl1_mut(&self) -> &mut PRESETCTRL1

0x104 - Peripheral reset control 1

pub fn presetctrlx2(&self) -> &PRESETCTRLX2

0x108 - Peripheral reset control register

pub fn presetctrlx2_mut(&self) -> &mut PRESETCTRLX2

0x108 - Peripheral reset control register

pub fn presetctrl2(&self) -> &PRESETCTRL2

0x108 - Peripheral reset control 2

pub fn presetctrl2_mut(&self) -> &mut PRESETCTRL2

0x108 - Peripheral reset control 2

pub fn ahbclkctrlx0(&self) -> &AHBCLKCTRLX0

0x200 - Peripheral reset control register

pub fn ahbclkctrlx0_mut(&self) -> &mut AHBCLKCTRLX0

0x200 - Peripheral reset control register

pub fn ahbclkctrl0(&self) -> &AHBCLKCTRL0

0x200 - AHB Clock control 0

pub fn ahbclkctrl0_mut(&self) -> &mut AHBCLKCTRL0

0x200 - AHB Clock control 0

pub fn ahbclkctrlx1(&self) -> &AHBCLKCTRLX1

0x204 - Peripheral reset control register

pub fn ahbclkctrlx1_mut(&self) -> &mut AHBCLKCTRLX1

0x204 - Peripheral reset control register

pub fn ahbclkctrl1(&self) -> &AHBCLKCTRL1

0x204 - AHB Clock control 1

pub fn ahbclkctrl1_mut(&self) -> &mut AHBCLKCTRL1

0x204 - AHB Clock control 1

pub fn ahbclkctrlx2(&self) -> &AHBCLKCTRLX2

0x208 - Peripheral reset control register

pub fn ahbclkctrlx2_mut(&self) -> &mut AHBCLKCTRLX2

0x208 - Peripheral reset control register

pub fn ahbclkctrl2(&self) -> &AHBCLKCTRL2

0x208 - AHB Clock control 2

pub fn ahbclkctrl2_mut(&self) -> &mut AHBCLKCTRL2

0x208 - AHB Clock control 2

pub fn systickclkselx0(&self) -> &SYSTICKCLKSELX0

0x260 - Peripheral reset control register

pub fn systickclkselx0_mut(&self) -> &mut SYSTICKCLKSELX0

0x260 - Peripheral reset control register

pub fn systickclksel0(&self) -> &SYSTICKCLKSEL0

0x260 - System Tick Timer for CPU0 source select

pub fn systickclksel0_mut(&self) -> &mut SYSTICKCLKSEL0

0x260 - System Tick Timer for CPU0 source select

pub fn systickclkselx1(&self) -> &SYSTICKCLKSELX1

0x264 - Peripheral reset control register

pub fn systickclkselx1_mut(&self) -> &mut SYSTICKCLKSELX1

0x264 - Peripheral reset control register

pub fn systickclksel1(&self) -> &SYSTICKCLKSEL1

0x264 - System Tick Timer for CPU1 source select

pub fn systickclksel1_mut(&self) -> &mut SYSTICKCLKSEL1

0x264 - System Tick Timer for CPU1 source select

pub fn ctimerclkselx0(&self) -> &CTIMERCLKSELX0

0x26c - Peripheral reset control register

pub fn ctimerclkselx0_mut(&self) -> &mut CTIMERCLKSELX0

0x26c - Peripheral reset control register

pub fn ctimerclksel0(&self) -> &CTIMERCLKSEL0

0x26c - CTimer 0 clock source select

pub fn ctimerclksel0_mut(&self) -> &mut CTIMERCLKSEL0

0x26c - CTimer 0 clock source select

pub fn ctimerclkselx1(&self) -> &CTIMERCLKSELX1

0x270 - Peripheral reset control register

pub fn ctimerclkselx1_mut(&self) -> &mut CTIMERCLKSELX1

0x270 - Peripheral reset control register

pub fn ctimerclksel1(&self) -> &CTIMERCLKSEL1

0x270 - CTimer 1 clock source select

pub fn ctimerclksel1_mut(&self) -> &mut CTIMERCLKSEL1

0x270 - CTimer 1 clock source select

pub fn ctimerclkselx2(&self) -> &CTIMERCLKSELX2

0x274 - Peripheral reset control register

pub fn ctimerclkselx2_mut(&self) -> &mut CTIMERCLKSELX2

0x274 - Peripheral reset control register

pub fn ctimerclksel2(&self) -> &CTIMERCLKSEL2

0x274 - CTimer 2 clock source select

pub fn ctimerclksel2_mut(&self) -> &mut CTIMERCLKSEL2

0x274 - CTimer 2 clock source select

pub fn ctimerclkselx3(&self) -> &CTIMERCLKSELX3

0x278 - Peripheral reset control register

pub fn ctimerclkselx3_mut(&self) -> &mut CTIMERCLKSELX3

0x278 - Peripheral reset control register

pub fn ctimerclksel3(&self) -> &CTIMERCLKSEL3

0x278 - CTimer 3 clock source select

pub fn ctimerclksel3_mut(&self) -> &mut CTIMERCLKSEL3

0x278 - CTimer 3 clock source select

pub fn ctimerclkselx4(&self) -> &CTIMERCLKSELX4

0x27c - Peripheral reset control register

pub fn ctimerclkselx4_mut(&self) -> &mut CTIMERCLKSELX4

0x27c - Peripheral reset control register

pub fn ctimerclksel4(&self) -> &CTIMERCLKSEL4

0x27c - CTimer 4 clock source select

pub fn ctimerclksel4_mut(&self) -> &mut CTIMERCLKSEL4

0x27c - CTimer 4 clock source select

pub fn fcclkselx0(&self) -> &FCCLKSELX0

0x2b0 - Peripheral reset control register

pub fn fcclkselx0_mut(&self) -> &mut FCCLKSELX0

0x2b0 - Peripheral reset control register

pub fn fcclksel0(&self) -> &FCCLKSEL0

0x2b0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider

pub fn fcclksel0_mut(&self) -> &mut FCCLKSEL0

0x2b0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider

pub fn fcclkselx1(&self) -> &FCCLKSELX1

0x2b4 - Peripheral reset control register

pub fn fcclkselx1_mut(&self) -> &mut FCCLKSELX1

0x2b4 - Peripheral reset control register

pub fn fcclksel1(&self) -> &FCCLKSEL1

0x2b4 - Flexcomm Interface 1 clock source select for Fractional Rate Divider

pub fn fcclksel1_mut(&self) -> &mut FCCLKSEL1

0x2b4 - Flexcomm Interface 1 clock source select for Fractional Rate Divider

pub fn fcclkselx2(&self) -> &FCCLKSELX2

0x2b8 - Peripheral reset control register

pub fn fcclkselx2_mut(&self) -> &mut FCCLKSELX2

0x2b8 - Peripheral reset control register

pub fn fcclksel2(&self) -> &FCCLKSEL2

0x2b8 - Flexcomm Interface 2 clock source select for Fractional Rate Divider

pub fn fcclksel2_mut(&self) -> &mut FCCLKSEL2

0x2b8 - Flexcomm Interface 2 clock source select for Fractional Rate Divider

pub fn fcclkselx3(&self) -> &FCCLKSELX3

0x2bc - Peripheral reset control register

pub fn fcclkselx3_mut(&self) -> &mut FCCLKSELX3

0x2bc - Peripheral reset control register

pub fn fcclksel3(&self) -> &FCCLKSEL3

0x2bc - Flexcomm Interface 3 clock source select for Fractional Rate Divider

pub fn fcclksel3_mut(&self) -> &mut FCCLKSEL3

0x2bc - Flexcomm Interface 3 clock source select for Fractional Rate Divider

pub fn fcclkselx4(&self) -> &FCCLKSELX4

0x2c0 - Peripheral reset control register

pub fn fcclkselx4_mut(&self) -> &mut FCCLKSELX4

0x2c0 - Peripheral reset control register

pub fn fcclksel4(&self) -> &FCCLKSEL4

0x2c0 - Flexcomm Interface 4 clock source select for Fractional Rate Divider

pub fn fcclksel4_mut(&self) -> &mut FCCLKSEL4

0x2c0 - Flexcomm Interface 4 clock source select for Fractional Rate Divider

pub fn fcclkselx5(&self) -> &FCCLKSELX5

0x2c4 - Peripheral reset control register

pub fn fcclkselx5_mut(&self) -> &mut FCCLKSELX5

0x2c4 - Peripheral reset control register

pub fn fcclksel5(&self) -> &FCCLKSEL5

0x2c4 - Flexcomm Interface 5 clock source select for Fractional Rate Divider

pub fn fcclksel5_mut(&self) -> &mut FCCLKSEL5

0x2c4 - Flexcomm Interface 5 clock source select for Fractional Rate Divider

pub fn fcclkselx6(&self) -> &FCCLKSELX6

0x2c8 - Peripheral reset control register

pub fn fcclkselx6_mut(&self) -> &mut FCCLKSELX6

0x2c8 - Peripheral reset control register

pub fn fcclksel6(&self) -> &FCCLKSEL6

0x2c8 - Flexcomm Interface 6 clock source select for Fractional Rate Divider

pub fn fcclksel6_mut(&self) -> &mut FCCLKSEL6

0x2c8 - Flexcomm Interface 6 clock source select for Fractional Rate Divider

pub fn fcclkselx7(&self) -> &FCCLKSELX7

0x2cc - Peripheral reset control register

pub fn fcclkselx7_mut(&self) -> &mut FCCLKSELX7

0x2cc - Peripheral reset control register

pub fn fcclksel7(&self) -> &FCCLKSEL7

0x2cc - Flexcomm Interface 7 clock source select for Fractional Rate Divider

pub fn fcclksel7_mut(&self) -> &mut FCCLKSEL7

0x2cc - Flexcomm Interface 7 clock source select for Fractional Rate Divider

pub fn flexfrgxctrl0(&self) -> &FLEXFRGXCTRL0

0x320 - Peripheral reset control register

pub fn flexfrgxctrl0_mut(&self) -> &mut FLEXFRGXCTRL0

0x320 - Peripheral reset control register

pub fn flexfrg0ctrl(&self) -> &FLEXFRG0CTRL

0x320 - Fractional rate divider for flexcomm 0

pub fn flexfrg0ctrl_mut(&self) -> &mut FLEXFRG0CTRL

0x320 - Fractional rate divider for flexcomm 0

pub fn flexfrgxctrl1(&self) -> &FLEXFRGXCTRL1

0x324 - Peripheral reset control register

pub fn flexfrgxctrl1_mut(&self) -> &mut FLEXFRGXCTRL1

0x324 - Peripheral reset control register

pub fn flexfrg1ctrl(&self) -> &FLEXFRG1CTRL

0x324 - Fractional rate divider for flexcomm 1

pub fn flexfrg1ctrl_mut(&self) -> &mut FLEXFRG1CTRL

0x324 - Fractional rate divider for flexcomm 1

pub fn flexfrgxctrl2(&self) -> &FLEXFRGXCTRL2

0x328 - Peripheral reset control register

pub fn flexfrgxctrl2_mut(&self) -> &mut FLEXFRGXCTRL2

0x328 - Peripheral reset control register

pub fn flexfrg2ctrl(&self) -> &FLEXFRG2CTRL

0x328 - Fractional rate divider for flexcomm 2

pub fn flexfrg2ctrl_mut(&self) -> &mut FLEXFRG2CTRL

0x328 - Fractional rate divider for flexcomm 2

pub fn flexfrgxctrl3(&self) -> &FLEXFRGXCTRL3

0x32c - Peripheral reset control register

pub fn flexfrgxctrl3_mut(&self) -> &mut FLEXFRGXCTRL3

0x32c - Peripheral reset control register

pub fn flexfrg3ctrl(&self) -> &FLEXFRG3CTRL

0x32c - Fractional rate divider for flexcomm 3

pub fn flexfrg3ctrl_mut(&self) -> &mut FLEXFRG3CTRL

0x32c - Fractional rate divider for flexcomm 3

pub fn flexfrgxctrl4(&self) -> &FLEXFRGXCTRL4

0x330 - Peripheral reset control register

pub fn flexfrgxctrl4_mut(&self) -> &mut FLEXFRGXCTRL4

0x330 - Peripheral reset control register

pub fn flexfrg4ctrl(&self) -> &FLEXFRG4CTRL

0x330 - Fractional rate divider for flexcomm 4

pub fn flexfrg4ctrl_mut(&self) -> &mut FLEXFRG4CTRL

0x330 - Fractional rate divider for flexcomm 4

pub fn flexfrgxctrl5(&self) -> &FLEXFRGXCTRL5

0x334 - Peripheral reset control register

pub fn flexfrgxctrl5_mut(&self) -> &mut FLEXFRGXCTRL5

0x334 - Peripheral reset control register

pub fn flexfrg5ctrl(&self) -> &FLEXFRG5CTRL

0x334 - Fractional rate divider for flexcomm 5

pub fn flexfrg5ctrl_mut(&self) -> &mut FLEXFRG5CTRL

0x334 - Fractional rate divider for flexcomm 5

pub fn flexfrgxctrl6(&self) -> &FLEXFRGXCTRL6

0x338 - Peripheral reset control register

pub fn flexfrgxctrl6_mut(&self) -> &mut FLEXFRGXCTRL6

0x338 - Peripheral reset control register

pub fn flexfrg6ctrl(&self) -> &FLEXFRG6CTRL

0x338 - Fractional rate divider for flexcomm 6

pub fn flexfrg6ctrl_mut(&self) -> &mut FLEXFRG6CTRL

0x338 - Fractional rate divider for flexcomm 6

pub fn flexfrgxctrl7(&self) -> &FLEXFRGXCTRL7

0x33c - Peripheral reset control register

pub fn flexfrgxctrl7_mut(&self) -> &mut FLEXFRGXCTRL7

0x33c - Peripheral reset control register

pub fn flexfrg7ctrl(&self) -> &FLEXFRG7CTRL

0x33c - Fractional rate divider for flexcomm 7

pub fn flexfrg7ctrl_mut(&self) -> &mut FLEXFRG7CTRL

0x33c - Fractional rate divider for flexcomm 7