[−][src]Type Definition lpc55s6x_pac::syscon::FCCLKSEL1
type FCCLKSEL1 = Reg<u32, _FCCLKSEL1>;
Flexcomm Interface 1 clock source select for Fractional Rate Divider
This register you can read
, reset
, write
, write_with_zero
, modify
. See API.
For information about avaliable fields see fcclksel1 module
Trait Implementations
impl Readable for FCCLKSEL1
[src]
read()
method returns fcclksel1::R reader structure
impl Writable for FCCLKSEL1
[src]
write(|w| ..)
method takes fcclksel1::W writer structure
impl ResetValue for FCCLKSEL1
[src]
Register FCCLKSEL1 reset()
's with value 0x07