Module lpc55s6x_pac::syscon

SYSCON

Modules

adcclkdiv	ADC clock divider
adcclksel	ADC clock source select
ahbclkctrl0	AHB Clock control 0
ahbclkctrl1	AHB Clock control 1
ahbclkctrl2	AHB Clock control 2
ahbclkctrlclr	Peripheral reset control register
ahbclkctrlset	Peripheral reset control register
ahbclkctrlx0	Peripheral reset control register
ahbclkctrlx1	Peripheral reset control register
ahbclkctrlx2	Peripheral reset control register
ahbclkdiv	System clock divider
ahbmatprio	AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest
autoclkgateoverride	Control automatic clock gating
clkoutdiv	CLKOUT clock divider
clkoutsel	CLKOUT clock source select
clock_ctrl	Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures
clockgenupdatelockout	Control clock configuration registers access (like xxxDIV, xxxSEL)
codesecurityprotcpu0	Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY
codesecurityprotcpu1	Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY
codesecurityprottest	Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY
comp_int_ctrl	Comparator Interrupt control
comp_int_status	Comparator Interrupt status
cpboot	Coprocessor Boot Address
cpstack	Coprocessor Stack Address
cpstat	CPU Status
cpu0stckcal	System tick calibration for secure part of CPU0
cpu0nstckcal	System tick calibration for non-secure part of CPU0
cpu1tckcal	System tick calibration for CPU1
cpucfg	CPUs configuration register
cpuctrl	CPU Control for multiple processors
ctimerclksel0	CTimer 0 clock source select
ctimerclksel1	CTimer 1 clock source select
ctimerclksel2	CTimer 2 clock source select
ctimerclksel3	CTimer 3 clock source select
ctimerclksel4	CTimer 4 clock source select
ctimerclkselx0	Peripheral reset control register
ctimerclkselx1	Peripheral reset control register
ctimerclkselx2	Peripheral reset control register
ctimerclkselx3	Peripheral reset control register
ctimerclkselx4	Peripheral reset control register
debug_auth_scratch	Debug authentication scratch registers -- FOR INTERNAL USE ONLY
debug_features	Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY
debug_features_dp	Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY
debug_lock_en	Control write access to security registers -- FOR INTERNAl USE ONLY
device_id0	Device ID
dice_reg0	Composite Device Identifier
dice_reg1	Composite Device Identifier
dice_reg2	Composite Device Identifier
dice_reg3	Composite Device Identifier
dice_reg4	Composite Device Identifier
dice_reg5	Composite Device Identifier
dice_reg6	Composite Device Identifier
dice_reg7	Composite Device Identifier
dieid	Chip revision ID and Number
efuseclkctrl	eFUSE controller clock enable
fcclksel0	Flexcomm Interface 0 clock source select for Fractional Rate Divider
fcclksel1	Flexcomm Interface 1 clock source select for Fractional Rate Divider
fcclksel2	Flexcomm Interface 2 clock source select for Fractional Rate Divider
fcclksel3	Flexcomm Interface 3 clock source select for Fractional Rate Divider
fcclksel4	Flexcomm Interface 4 clock source select for Fractional Rate Divider
fcclksel5	Flexcomm Interface 5 clock source select for Fractional Rate Divider
fcclksel6	Flexcomm Interface 6 clock source select for Fractional Rate Divider
fcclksel7	Flexcomm Interface 7 clock source select for Fractional Rate Divider
fcclkselx0	Peripheral reset control register
fcclkselx1	Peripheral reset control register
fcclkselx2	Peripheral reset control register
fcclkselx3	Peripheral reset control register
fcclkselx4	Peripheral reset control register
fcclkselx5	Peripheral reset control register
fcclkselx6	Peripheral reset control register
fcclkselx7	Peripheral reset control register
flashbankenable	Flash Banks control
flexfrg0ctrl	Fractional rate divider for flexcomm 0
flexfrg1ctrl	Fractional rate divider for flexcomm 1
flexfrg2ctrl	Fractional rate divider for flexcomm 2
flexfrg3ctrl	Fractional rate divider for flexcomm 3
flexfrg4ctrl	Fractional rate divider for flexcomm 4
flexfrg5ctrl	Fractional rate divider for flexcomm 5
flexfrg6ctrl	Fractional rate divider for flexcomm 6
flexfrg7ctrl	Fractional rate divider for flexcomm 7
flexfrgxctrl0	Peripheral reset control register
flexfrgxctrl1	Peripheral reset control register
flexfrgxctrl2	Peripheral reset control register
flexfrgxctrl3	Peripheral reset control register
flexfrgxctrl4	Peripheral reset control register
flexfrgxctrl5	Peripheral reset control register
flexfrgxctrl6	Peripheral reset control register
flexfrgxctrl7	Peripheral reset control register
fmccr	FMC configuration register - INTERNAL USE ONLY
fmcflush	FMCflush control
frohfdiv	FRO_HF (96MHz) clock divider
gpiopsync	Enable bypass of the first stage of synchonization inside GPIO_INT module
hardwaresleep	Hardware Sleep control
hslspiclksel	HS LSPI clock source select
key_block	block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY
mainclksela	Main clock A source select
mainclkselb	Main clock source select
mclkclksel	MCLK clock source select
mclkdiv	I2S MCLK clock divider
mclkio	MCLK control
memoryremap	Memory Remap control register
nmisrc	NMI Source Select
periphencfg	peripheral enable configuration -- FOR INTERNAL USE ONLY
pll0ctrl	PLL0 550m control
pll0stat	PLL0 550m status
pll0ndec	PLL0 550m N divider
pll0pdec	PLL0 550m P divider
pll0clksel	PLL0 clock source select
pll0clkdiv	PLL0 clock divider
pll1clksel	PLL1 clock source select
pll1ctrl	PLL1 550m control
pll1stat	PLL1 550m status
pll1ndec	PLL1 550m N divider
pll1mdec	PLL1 550m M divider
pll1pdec	PLL1 550m P divider
pll0sscg0	PLL0 Spread Spectrum Wrapper control register 0
pll0sscg1	PLL0 Spread Spectrum Wrapper control register 1
presetctrl0	Peripheral reset control 0
presetctrl1	Peripheral reset control 1
presetctrl2	Peripheral reset control 2
presetctrlclr	Peripheral reset contro clearl register
presetctrlset	Peripheral reset control set register
presetctrlx0	Peripheral reset control register
presetctrlx1	Peripheral reset control register
presetctrlx2	Peripheral reset control register
sctclkdiv	SCT/PWM clock divider
sctclksel	SCTimer/PWM clock source select
sdioclkctrl	SDIO CCLKIN phase and delay control
sdioclkdiv	SDIO clock divider
sdioclksel	SDIO clock source select
starter0	Start logic wake-up enable register
starter1	Start logic wake-up enable register
starterclr0	Clear bits in STARTER
starterclr1	Clear bits in STARTER
starterset0	Set bits in STARTER
starterset1	Set bits in STARTER
swr_reset	generate a software_reset
systickclkdiv0	System Tick Timer divider for CPU0
systickclkdiv1	System Tick Timer divider for CPU1
systickclksel0	System Tick Timer for CPU0 source select
systickclksel1	System Tick Timer for CPU1 source select
systickclkselx0	Peripheral reset control register
systickclkselx1	Peripheral reset control register
traceclkdiv	TRACE clock divider
traceclksel	Trace clock source select
usb0clksel	FS USB clock source select
usb0clkdiv	USB0 Clock divider
usb0clkctrl	USB0 clock control
usb0clkstat	USB0 clock status
usb1clksel	HS USB clock source select - NOT USED
usb1clkctrl	USB1 clock control
usb1clkstat	USB1 clock status
wdtclkdiv	WDT clock divider

Structs

RegisterBlock

Register block

Type Definitions

ADCCLKDIV	ADC clock divider
ADCCLKSEL	ADC clock source select
AHBCLKCTRL0	AHB Clock control 0
AHBCLKCTRL1	AHB Clock control 1
AHBCLKCTRL2	AHB Clock control 2
AHBCLKCTRLCLR	Peripheral reset control register
AHBCLKCTRLSET	Peripheral reset control register
AHBCLKCTRLX0	Peripheral reset control register
AHBCLKCTRLX1	Peripheral reset control register
AHBCLKCTRLX2	Peripheral reset control register
AHBCLKDIV	System clock divider
AHBMATPRIO	AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest
AUTOCLKGATEOVERRIDE	Control automatic clock gating
CLKOUTDIV	CLKOUT clock divider
CLKOUTSEL	CLKOUT clock source select
CLOCKGENUPDATELOCKOUT	Control clock configuration registers access (like xxxDIV, xxxSEL)
CLOCK_CTRL	Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures
CODESECURITYPROTCPU0	Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY
CODESECURITYPROTCPU1	Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY
CODESECURITYPROTTEST	Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY
COMP_INT_CTRL	Comparator Interrupt control
COMP_INT_STATUS	Comparator Interrupt status
CPBOOT	Coprocessor Boot Address
CPSTACK	Coprocessor Stack Address
CPSTAT	CPU Status
CPU0STCKCAL	System tick calibration for secure part of CPU0
CPU0NSTCKCAL	System tick calibration for non-secure part of CPU0
CPU1TCKCAL	System tick calibration for CPU1
CPUCFG	CPUs configuration register
CPUCTRL	CPU Control for multiple processors
CTIMERCLKSEL0	CTimer 0 clock source select
CTIMERCLKSEL1	CTimer 1 clock source select
CTIMERCLKSEL2	CTimer 2 clock source select
CTIMERCLKSEL3	CTimer 3 clock source select
CTIMERCLKSEL4	CTimer 4 clock source select
CTIMERCLKSELX0	Peripheral reset control register
CTIMERCLKSELX1	Peripheral reset control register
CTIMERCLKSELX2	Peripheral reset control register
CTIMERCLKSELX3	Peripheral reset control register
CTIMERCLKSELX4	Peripheral reset control register
DEBUG_AUTH_SCRATCH	Debug authentication scratch registers -- FOR INTERNAL USE ONLY
DEBUG_FEATURES	Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY
DEBUG_FEATURES_DP	Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY
DEBUG_LOCK_EN	Control write access to security registers -- FOR INTERNAl USE ONLY
DEVICE_ID0	Device ID
DICE_REG0	Composite Device Identifier
DICE_REG1	Composite Device Identifier
DICE_REG2	Composite Device Identifier
DICE_REG3	Composite Device Identifier
DICE_REG4	Composite Device Identifier
DICE_REG5	Composite Device Identifier
DICE_REG6	Composite Device Identifier
DICE_REG7	Composite Device Identifier
DIEID	Chip revision ID and Number
EFUSECLKCTRL	eFUSE controller clock enable
FCCLKSEL0	Flexcomm Interface 0 clock source select for Fractional Rate Divider
FCCLKSEL1	Flexcomm Interface 1 clock source select for Fractional Rate Divider
FCCLKSEL2	Flexcomm Interface 2 clock source select for Fractional Rate Divider
FCCLKSEL3	Flexcomm Interface 3 clock source select for Fractional Rate Divider
FCCLKSEL4	Flexcomm Interface 4 clock source select for Fractional Rate Divider
FCCLKSEL5	Flexcomm Interface 5 clock source select for Fractional Rate Divider
FCCLKSEL6	Flexcomm Interface 6 clock source select for Fractional Rate Divider
FCCLKSEL7	Flexcomm Interface 7 clock source select for Fractional Rate Divider
FCCLKSELX0	Peripheral reset control register
FCCLKSELX1	Peripheral reset control register
FCCLKSELX2	Peripheral reset control register
FCCLKSELX3	Peripheral reset control register
FCCLKSELX4	Peripheral reset control register
FCCLKSELX5	Peripheral reset control register
FCCLKSELX6	Peripheral reset control register
FCCLKSELX7	Peripheral reset control register
FLASHBANKENABLE	Flash Banks control
FLEXFRG0CTRL	Fractional rate divider for flexcomm 0
FLEXFRG1CTRL	Fractional rate divider for flexcomm 1
FLEXFRG2CTRL	Fractional rate divider for flexcomm 2
FLEXFRG3CTRL	Fractional rate divider for flexcomm 3
FLEXFRG4CTRL	Fractional rate divider for flexcomm 4
FLEXFRG5CTRL	Fractional rate divider for flexcomm 5
FLEXFRG6CTRL	Fractional rate divider for flexcomm 6
FLEXFRG7CTRL	Fractional rate divider for flexcomm 7
FLEXFRGXCTRL0	Peripheral reset control register
FLEXFRGXCTRL1	Peripheral reset control register
FLEXFRGXCTRL2	Peripheral reset control register
FLEXFRGXCTRL3	Peripheral reset control register
FLEXFRGXCTRL4	Peripheral reset control register
FLEXFRGXCTRL5	Peripheral reset control register
FLEXFRGXCTRL6	Peripheral reset control register
FLEXFRGXCTRL7	Peripheral reset control register
FMCCR	FMC configuration register - INTERNAL USE ONLY
FMCFLUSH	FMCflush control
FROHFDIV	FRO_HF (96MHz) clock divider
GPIOPSYNC	Enable bypass of the first stage of synchonization inside GPIO_INT module
HARDWARESLEEP	Hardware Sleep control
HSLSPICLKSEL	HS LSPI clock source select
KEY_BLOCK	block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY
MAINCLKSELA	Main clock A source select
MAINCLKSELB	Main clock source select
MCLKCLKSEL	MCLK clock source select
MCLKDIV	I2S MCLK clock divider
MCLKIO	MCLK control
MEMORYREMAP	Memory Remap control register
NMISRC	NMI Source Select
PERIPHENCFG	peripheral enable configuration -- FOR INTERNAL USE ONLY
PLL0CTRL	PLL0 550m control
PLL0STAT	PLL0 550m status
PLL0NDEC	PLL0 550m N divider
PLL0PDEC	PLL0 550m P divider
PLL0CLKSEL	PLL0 clock source select
PLL0CLKDIV	PLL0 clock divider
PLL1CLKSEL	PLL1 clock source select
PLL1CTRL	PLL1 550m control
PLL1STAT	PLL1 550m status
PLL1NDEC	PLL1 550m N divider
PLL1MDEC	PLL1 550m M divider
PLL1PDEC	PLL1 550m P divider
PLL0SSCG0	PLL0 Spread Spectrum Wrapper control register 0
PLL0SSCG1	PLL0 Spread Spectrum Wrapper control register 1
PRESETCTRL0	Peripheral reset control 0
PRESETCTRL1	Peripheral reset control 1
PRESETCTRL2	Peripheral reset control 2
PRESETCTRLCLR	Peripheral reset contro clearl register
PRESETCTRLSET	Peripheral reset control set register
PRESETCTRLX0	Peripheral reset control register
PRESETCTRLX1	Peripheral reset control register
PRESETCTRLX2	Peripheral reset control register
SCTCLKDIV	SCT/PWM clock divider
SCTCLKSEL	SCTimer/PWM clock source select
SDIOCLKCTRL	SDIO CCLKIN phase and delay control
SDIOCLKDIV	SDIO clock divider
SDIOCLKSEL	SDIO clock source select
STARTER0	Start logic wake-up enable register
STARTER1	Start logic wake-up enable register
STARTERCLR0	Clear bits in STARTER
STARTERCLR1	Clear bits in STARTER
STARTERSET0	Set bits in STARTER
STARTERSET1	Set bits in STARTER
SWR_RESET	generate a software_reset
SYSTICKCLKDIV0	System Tick Timer divider for CPU0
SYSTICKCLKDIV1	System Tick Timer divider for CPU1
SYSTICKCLKSEL0	System Tick Timer for CPU0 source select
SYSTICKCLKSEL1	System Tick Timer for CPU1 source select
SYSTICKCLKSELX0	Peripheral reset control register
SYSTICKCLKSELX1	Peripheral reset control register
TRACECLKDIV	TRACE clock divider
TRACECLKSEL	Trace clock source select
USB0CLKSEL	FS USB clock source select
USB0CLKDIV	USB0 Clock divider
USB0CLKCTRL	USB0 clock control
USB0CLKSTAT	USB0 clock status
USB1CLKSEL	HS USB clock source select - NOT USED
USB1CLKCTRL	USB1 clock control
USB1CLKSTAT	USB1 clock status
WDTCLKDIV	WDT clock divider