[−][src]Type Definition lpc55s6x_pac::syscon::FCCLKSEL2
type FCCLKSEL2 = Reg<u32, _FCCLKSEL2>;
Flexcomm Interface 2 clock source select for Fractional Rate Divider
This register you can read
, reset
, write
, write_with_zero
, modify
. See API.
For information about avaliable fields see fcclksel2 module
Trait Implementations
impl Readable for FCCLKSEL2
[src]
read()
method returns fcclksel2::R reader structure
impl Writable for FCCLKSEL2
[src]
write(|w| ..)
method takes fcclksel2::W writer structure
impl ResetValue for FCCLKSEL2
[src]
Register FCCLKSEL2 reset()
's with value 0x07