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;; GENERATED BY `isaspec`. DO NOT EDIT!!!
(attr MInst.IntToFpu (tag isaspec_generated))
(spec
(MInst.IntToFpu op rd rn)
(provide
(match
op
((I64ToF64)
(with
(t1 t4)
(and
(= t1 (zero_ext 4 (extract 23 22 fpcr)))
(= t4 (FixedToFP! rn 0 false fpcr (bv2nat t1) 64 64))
(= rd (zero_ext 128 t4))
)
)
)
((U64ToF64)
(with
(t1 t4)
(and
(= t1 (zero_ext 4 (extract 23 22 fpcr)))
(= t4 (FixedToFP! rn 0 true fpcr (bv2nat t1) 64 64))
(= rd (zero_ext 128 t4))
)
)
)
((I64ToF32)
(with
(t1 t4)
(and
(= t1 (zero_ext 4 (extract 23 22 fpcr)))
(= t4 (FixedToFP! rn 0 false fpcr (bv2nat t1) 64 32))
(= rd (zero_ext 128 t4))
)
)
)
((U64ToF32)
(with
(t1 t4)
(and
(= t1 (zero_ext 4 (extract 23 22 fpcr)))
(= t4 (FixedToFP! rn 0 true fpcr (bv2nat t1) 64 32))
(= rd (zero_ext 128 t4))
)
)
)
((I32ToF64)
(with
(t1 t4)
(and
(= t1 (zero_ext 4 (extract 23 22 fpcr)))
(= t4 (FixedToFP! (extract 31 0 rn) 0 false fpcr (bv2nat t1) 32 64))
(= rd (zero_ext 128 t4))
)
)
)
((U32ToF64)
(with
(t1 t4)
(and
(= t1 (zero_ext 4 (extract 23 22 fpcr)))
(= t4 (FixedToFP! (extract 31 0 rn) 0 true fpcr (bv2nat t1) 32 64))
(= rd (zero_ext 128 t4))
)
)
)
((I32ToF32)
(with
(t1 t4)
(and
(= t1 (zero_ext 4 (extract 23 22 fpcr)))
(= t4 (FixedToFP! (extract 31 0 rn) 0 false fpcr (bv2nat t1) 32 32))
(= rd (zero_ext 128 t4))
)
)
)
((U32ToF32)
(with
(t1 t4)
(and
(= t1 (zero_ext 4 (extract 23 22 fpcr)))
(= t4 (FixedToFP! (extract 31 0 rn) 0 true fpcr (bv2nat t1) 32 32))
(= rd (zero_ext 128 t4))
)
)
)
)
)
(require
(match
op
((I64ToF64) true)
((U64ToF64) true)
((I64ToF32) true)
((U64ToF32) true)
((I32ToF64) true)
((U32ToF64) true)
((I32ToF32) true)
((U32ToF32) true)
)
)
)