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;; GENERATED BY `isaspec`. DO NOT EDIT!!!
(attr MInst.FpuRR (tag isaspec_generated))
(spec
(MInst.FpuRR fpu_op size rd rn)
(provide
(match
size
((Size64)
(match
fpu_op
((Neg)
(=
(conv_to 128 (as rd (bv 64)))
(zero_ext
128
(concat (bvnot (extract 63 63 (conv_to 128 (as rn (bv 64))))) (extract 62 0 (conv_to 128 (as rn (bv 64)))))
)
)
)
((Abs) (= (conv_to 128 (as rd (bv 64))) (zero_ext 128 (extract 62 0 (conv_to 128 (as rn (bv 64)))))))
((Sqrt)
(with
(t2)
(and
(= t2 (FPSqrt! (extract 63 0 (conv_to 128 (as rn (bv 64)))) fpcr))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t2))
)
)
)
((Cvt64To32)
(with
(t1 t3)
(and
(= t1 (zero_ext 4 (extract 23 22 fpcr)))
(= t3 (FPConvert! (extract 63 0 (conv_to 128 (as rn (bv 64)))) fpcr (bv2nat t1) 32 64))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t3))
)
)
)
)
)
((Size32)
(match
fpu_op
((Neg)
(=
(conv_to 128 (as rd (bv 64)))
(zero_ext
128
(concat (bvnot (extract 31 31 (conv_to 128 (as rn (bv 64))))) (extract 30 0 (conv_to 128 (as rn (bv 64)))))
)
)
)
((Abs) (= (conv_to 128 (as rd (bv 64))) (zero_ext 128 (extract 30 0 (conv_to 128 (as rn (bv 64)))))))
((Sqrt)
(with
(t2)
(and
(= t2 (FPSqrt! (extract 31 0 (conv_to 128 (as rn (bv 64)))) fpcr))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t2))
)
)
)
((Cvt32To64)
(with
(t1 t3)
(and
(= t1 (zero_ext 4 (extract 23 22 fpcr)))
(= t3 (FPConvert! (extract 31 0 (conv_to 128 (as rn (bv 64)))) fpcr (bv2nat t1) 64 32))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t3))
)
)
)
)
)
)
)
(require
(match
size
((Size64) (match fpu_op ((Neg) true) ((Abs) true) ((Sqrt) true) ((Cvt64To32) true)))
((Size32) (match fpu_op ((Neg) true) ((Abs) true) ((Sqrt) true) ((Cvt32To64) true)))
)
)
)