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;; GENERATED BY `isaspec`. DO NOT EDIT!!!
(attr MInst.AluRRR (tag isaspec_generated))
(spec
(MInst.AluRRR alu_op size rd rn rm)
(provide
(match
size
((Size64)
(match
alu_op
((Add) (= rd (bvadd rn rm)))
((Sub) (= rd (bvadd (bvadd rn (bvnot rm)) #x0000000000000001)))
((Orr) (= rd (bvor rn rm)))
((OrrNot) (= rd (bvor rn (bvnot rm))))
((And) (= rd (bvand rn rm)))
((AndNot) (= rd (bvand rn (bvnot rm))))
((Eor) (= rd (bvxor rn rm)))
((EorNot) (= rd (bvxor rn (bvnot rm))))
((AddS)
(with
(t2)
(and
(= t2 (bvadd rn rm))
(= (:V (:flags_out result)) (bvnot (if (= (sign_ext 128 t2) (bvadd (sign_ext 128 rn) (sign_ext 128 rm))) #b1 #b0)))
(= (:C (:flags_out result)) (bvnot (if (= (zero_ext 128 t2) (bvadd (zero_ext 128 rn) (zero_ext 128 rm))) #b1 #b0)))
(= (:Z (:flags_out result)) (if (= t2 #x0000000000000000) #b1 #b0))
(= (:N (:flags_out result)) (extract 63 63 t2))
(= rd t2)
)
)
)
((SubS)
(with
(t1 t3)
(and
(= t1 (bvnot rm))
(= t3 (bvadd rn (bvnot rm)))
(=
(:V (:flags_out result))
(bvnot
(if
(=
(sign_ext 128 (bvadd t3 #x0000000000000001))
(bvadd (bvadd (sign_ext 128 rn) (sign_ext 128 t1)) #x00000000000000000000000000000001)
)
#b1
#b0
)
)
)
(=
(:C (:flags_out result))
(bvnot
(if
(=
(zero_ext 128 (bvadd t3 #x0000000000000001))
(bvadd (bvadd (zero_ext 128 rn) (zero_ext 128 t1)) #x00000000000000000000000000000001)
)
#b1
#b0
)
)
)
(= (:Z (:flags_out result)) (if (= (bvadd t3 #x0000000000000001) #x0000000000000000) #b1 #b0))
(= (:N (:flags_out result)) (extract 63 63 (bvadd t3 #x0000000000000001)))
(= rd (bvadd t3 #x0000000000000001))
)
)
)
((SMulH) (= rd (extract 127 64 (bvmul (sign_ext 128 rn) (sign_ext 128 rm)))))
((UMulH) (= rd (extract 127 64 (bvmul (zero_ext 128 rn) (zero_ext 128 rm)))))
((SDiv)
(with
(t1 t2 t4)
(and (= t1 (= rm #x0000000000000000)) (if t1 (= t2 #x0000000000000000) (= t4 (bvsdiv rn rm))) (= rd (if t1 t2 t4)))
)
)
((UDiv)
(with
(t1 t2 t4)
(and
(= t1 (= rm #x0000000000000000))
(if t1 (= t2 #x0000000000000000) (= t4 (extract 63 0 (bvsdiv (zero_ext 128 rn) (zero_ext 128 rm)))))
(= rd (if t1 t2 t4))
)
)
)
((Extr)
(with
(t1 t3 t4 t5)
(and
(= t1 (= (extract 5 0 rm) #b000000))
(if
t1
(= t3 rn)
(and
(not (= (extract 5 0 rm) #b000000))
(=
t4
(bvor (bvlshr rn (zero_ext 64 (extract 5 0 rm))) (bvshl rn (zero_ext 64 (bvsub #x40 (zero_ext 8 (extract 5 0 rm))))))
)
)
)
(= t5 (if t1 t3 t4))
(= rd t5)
)
)
)
((Lsr) (= rd (bvlshr rn (zero_ext 64 (extract 5 0 rm)))))
((Asr) (= rd (bvashr rn (zero_ext 64 (extract 5 0 rm)))))
((Lsl) (= rd (bvshl rn (zero_ext 64 (extract 5 0 rm)))))
((Adc) (= rd (bvadd (bvadd rn rm) (zero_ext 64 (extract 0 0 (:C (:flags_in result)))))))
)
)
((Size32)
(match
alu_op
((Add) (= rd (zero_ext 64 (bvadd (extract 31 0 rn) (extract 31 0 rm)))))
((Sub) (= rd (zero_ext 64 (bvadd (bvadd (extract 31 0 rn) (bvnot (extract 31 0 rm))) #x00000001))))
((Orr) (= rd (zero_ext 64 (bvor (extract 31 0 rn) (extract 31 0 rm)))))
((OrrNot) (= rd (zero_ext 64 (bvor (extract 31 0 rn) (bvnot (extract 31 0 rm))))))
((And) (= rd (zero_ext 64 (bvand (extract 31 0 rn) (extract 31 0 rm)))))
((AndNot) (= rd (zero_ext 64 (bvand (extract 31 0 rn) (bvnot (extract 31 0 rm))))))
((Eor) (= rd (zero_ext 64 (bvxor (extract 31 0 rn) (extract 31 0 rm)))))
((EorNot) (= rd (zero_ext 64 (bvxor (extract 31 0 rn) (bvnot (extract 31 0 rm))))))
((AddS)
(with
(t2 t3)
(and
(= t2 (bvadd (extract 31 0 rn) (extract 31 0 rm)))
(= t3 (zero_ext 64 (bvadd (extract 31 0 rn) (extract 31 0 rm))))
(=
(:V (:flags_out result))
(bvnot (if (= (sign_ext 64 t2) (bvadd (sign_ext 64 (extract 31 0 rn)) (sign_ext 64 (extract 31 0 rm)))) #b1 #b0))
)
(=
(:C (:flags_out result))
(bvnot (if (= t3 (bvadd (zero_ext 64 (extract 31 0 rn)) (zero_ext 64 (extract 31 0 rm)))) #b1 #b0))
)
(= (:Z (:flags_out result)) (if (= t2 #x00000000) #b1 #b0))
(= (:N (:flags_out result)) (extract 31 31 t2))
(= rd t3)
)
)
)
((SubS)
(with
(t1 t3 t4)
(and
(= t1 (bvnot (extract 31 0 rm)))
(= t3 (bvadd (extract 31 0 rn) (bvnot (extract 31 0 rm))))
(= t4 (zero_ext 64 (bvadd (bvadd (extract 31 0 rn) (bvnot (extract 31 0 rm))) #x00000001)))
(=
(:V (:flags_out result))
(bvnot
(if
(=
(sign_ext 64 (bvadd t3 #x00000001))
(bvadd (bvadd (sign_ext 64 (extract 31 0 rn)) (sign_ext 64 t1)) #x0000000000000001)
)
#b1
#b0
)
)
)
(=
(:C (:flags_out result))
(bvnot (if (= t4 (bvadd (bvadd (zero_ext 64 (extract 31 0 rn)) (zero_ext 64 t1)) #x0000000000000001)) #b1 #b0))
)
(= (:Z (:flags_out result)) (if (= (bvadd t3 #x00000001) #x00000000) #b1 #b0))
(= (:N (:flags_out result)) (extract 31 31 (bvadd t3 #x00000001)))
(= rd t4)
)
)
)
((SDiv)
(with
(t1 t2 t4)
(and
(= t1 (= (extract 31 0 rm) #x00000000))
(if t1 (= t2 #x0000000000000000) (= t4 (zero_ext 64 (bvsdiv (extract 31 0 rn) (extract 31 0 rm)))))
(= rd (if t1 t2 t4))
)
)
)
((UDiv)
(with
(t1 t2 t4)
(and
(= t1 (= (extract 31 0 rm) #x00000000))
(if
t1
(= t2 #x0000000000000000)
(= t4 (zero_ext 64 (extract 31 0 (bvsdiv (zero_ext 64 (extract 31 0 rn)) (zero_ext 64 (extract 31 0 rm))))))
)
(= rd (if t1 t2 t4))
)
)
)
((Extr)
(with
(t1 t3 t4 t5)
(and
(= t1 (= (extract 4 0 rm) #b00000))
(if
t1
(= t3 (extract 31 0 rn))
(and
(not (= (extract 4 0 rm) #b00000))
(=
t4
(bvor
(bvlshr (extract 31 0 rn) (zero_ext 32 (extract 4 0 rm)))
(bvshl (extract 31 0 rn) (zero_ext 32 (bvsub #x20 (zero_ext 8 (extract 4 0 rm)))))
)
)
)
)
(= t5 (if t1 t3 t4))
(= rd (zero_ext 64 t5))
)
)
)
((Lsr) (= rd (zero_ext 64 (bvlshr (extract 31 0 rn) (zero_ext 32 (extract 4 0 rm))))))
((Asr) (= rd (zero_ext 64 (bvashr (extract 31 0 rn) (zero_ext 32 (extract 4 0 rm))))))
((Lsl) (= rd (zero_ext 64 (bvshl (extract 31 0 rn) (zero_ext 32 (extract 4 0 rm))))))
((Adc)
(=
rd
(zero_ext 64 (bvadd (bvadd (extract 31 0 rn) (extract 31 0 rm)) (zero_ext 32 (extract 0 0 (:C (:flags_in result))))))
)
)
)
)
)
)
(require
(match
size
((Size64)
(match
alu_op
((Add) true)
((Sub) true)
((Orr) true)
((OrrNot) true)
((And) true)
((AndNot) true)
((Eor) true)
((EorNot) true)
((AddS) true)
((SubS) true)
((SMulH) true)
((UMulH) true)
((SDiv) true)
((UDiv) true)
((Extr) true)
((Lsr) true)
((Asr) true)
((Lsl) true)
((Adc) true)
)
)
((Size32)
(match
alu_op
((Add) true)
((Sub) true)
((Orr) true)
((OrrNot) true)
((And) true)
((AndNot) true)
((Eor) true)
((EorNot) true)
((AddS) true)
((SubS) true)
((SDiv) true)
((UDiv) true)
((Extr) true)
((Lsr) true)
((Asr) true)
((Lsl) true)
((Adc) true)
)
)
)
)
)