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;; GENERATED BY `isaspec`. DO NOT EDIT!!!
(attr MInst.FpuRound (tag isaspec_generated))
(spec
(MInst.FpuRound op rd rn)
(provide
(match
op
((Nearest64)
(with
(t3)
(and
(= t3 (FPRoundInt! (extract 63 0 (conv_to 128 (as rn (bv 64)))) fpcr 0 false))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t3))
)
)
)
((Nearest32)
(with
(t3)
(and
(= t3 (FPRoundInt! (extract 31 0 (conv_to 128 (as rn (bv 64)))) fpcr 0 false))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t3))
)
)
)
((Zero64)
(with
(t3)
(and
(= t3 (FPRoundInt! (extract 63 0 (conv_to 128 (as rn (bv 64)))) fpcr 3 false))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t3))
)
)
)
((Zero32)
(with
(t3)
(and
(= t3 (FPRoundInt! (extract 31 0 (conv_to 128 (as rn (bv 64)))) fpcr 3 false))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t3))
)
)
)
((Plus64)
(with
(t3)
(and
(= t3 (FPRoundInt! (extract 63 0 (conv_to 128 (as rn (bv 64)))) fpcr 1 false))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t3))
)
)
)
((Plus32)
(with
(t3)
(and
(= t3 (FPRoundInt! (extract 31 0 (conv_to 128 (as rn (bv 64)))) fpcr 1 false))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t3))
)
)
)
((Minus64)
(with
(t3)
(and
(= t3 (FPRoundInt! (extract 63 0 (conv_to 128 (as rn (bv 64)))) fpcr 2 false))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t3))
)
)
)
((Minus32)
(with
(t3)
(and
(= t3 (FPRoundInt! (extract 31 0 (conv_to 128 (as rn (bv 64)))) fpcr 2 false))
(= (conv_to 128 (as rd (bv 64))) (zero_ext 128 t3))
)
)
)
)
)
(require
(match
op
((Nearest64) true)
((Nearest32) true)
((Zero64) true)
((Zero32) true)
((Plus64) true)
((Plus32) true)
((Minus64) true)
((Minus32) true)
)
)
)