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//! # PRFM (immediate)
//!
//! This instruction signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The address for data memory accesses is calculated from a base register value and an immediate offset. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as making the cache line containing the specified address available at the level of cache specified by the instruction.
#![allow(non_snake_case)]
#![allow(unused)]
use crate::error::Result;
use crate::utils::*;
use super::super::formatter::*;
use super::super::instruction::*;
use super::super::operand::*;
use super::super::consts::*;
use super::super::config::*;
use super::super::decoder::*;
// ---------------------------------------------------------------------------
// Iclass IclassPrfmPLdstPos
// ---------------------------------------------------------------------------
/// Type that represents the IclassPrfmPLdstPos instruction class.
pub(crate) struct IclassPrfmPLdstPos;
impl IclassPrfmPLdstPos {
/// Tries to decode the instruction in `data`.
pub(crate) fn decode(data: u32, decoder: &mut Decoder) -> Result<Instruction> {
let size = (data >> 30) & 3;
let size_post = size;
let imm12 = (data >> 10) & 4095;
let imm12_post = imm12;
let field_27 = (data >> 27) & 1;
let field_27_post = field_27;
let Rt = (data >> 0) & 31;
let Rt_post = Rt;
let VR = (data >> 26) & 1;
let VR_post = VR;
let Rn = (data >> 5) & 31;
let Rn_post = Rn;
let field_25 = (data >> 25) & 1;
let field_25_post = field_25;
let field_29 = (data >> 28) & 3;
let field_29_post = field_29;
let opc = (data >> 22) & 3;
let opc_post = opc;
let field_24 = (data >> 24) & 1;
let field_24_post = field_24;
return PrfmPLdstPos::decode(data as u32, decoder);
unreachable!()
}
}
/// None-bit encoding.
///
/// # Encoding
///
/// <table style="font-family: courier, monospace">
/// <tr>
/// <td style="border: none">31</td>
/// <td style="border: none">30</td>
/// <td style="border: none">29</td>
/// <td style="border: none">28</td>
/// <td style="border: none">27</td>
/// <td style="border: none">26</td>
/// <td style="border: none">25</td>
/// <td style="border: none">24</td>
/// <td style="border: none">23</td>
/// <td style="border: none">22</td>
/// <td style="border: none">21</td>
/// <td style="border: none">20</td>
/// <td style="border: none">19</td>
/// <td style="border: none">18</td>
/// <td style="border: none">17</td>
/// <td style="border: none">16</td>
/// <td style="border: none">15</td>
/// <td style="border: none">14</td>
/// <td style="border: none">13</td>
/// <td style="border: none">12</td>
/// <td style="border: none">11</td>
/// <td style="border: none">10</td>
/// <td style="border: none">9</td>
/// <td style="border: none">8</td>
/// <td style="border: none">7</td>
/// <td style="border: none">6</td>
/// <td style="border: none">5</td>
/// <td style="border: none">4</td>
/// <td style="border: none">3</td>
/// <td style="border: none">2</td>
/// <td style="border: none">1</td>
/// <td style="border: none">0</td>
/// </tr>
/// <tr>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-left: none" colspan="1">1</td>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-left: none" colspan="1">1</td>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-right: none" colspan="1">0</td>
/// <td style="text-align: center; border-right: none" colspan="1">0</td>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-left: none" colspan="1">0</td>
/// <td style="text-align: center" colspan="12">imm12</td>
/// <td style="text-align: center" colspan="5">Rn</td>
/// <td style="text-align: center" colspan="5">Rt</td>
/// </tr>
/// <tr>
/// <td style="text-align: center; border: none" colspan="2">size</td>
/// <td style="text-align: center; border: none" colspan="2"></td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="1">VR</td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="2">opc</td>
/// <td style="text-align: center; border: none" colspan="12"></td>
/// <td style="text-align: center; border: none" colspan="5"></td>
/// <td style="text-align: center; border: none" colspan="5"></td>
/// </tr>
/// </table>
pub struct PrfmPLdstPos;
impl PrfmPLdstPos {
/// Returns the instruction mnemonic.
pub fn mnemonic(_instr: &Instruction) -> Mnemonic {
Mnemonic::PRFM
}
/// Returns the instruction size.
pub fn size(_instr: &Instruction) -> usize {
4
}
/// Decodes the instruction in `data`.
pub fn decode(data: u32, decoder: &mut Decoder) -> Result<Instruction> {
// Fields are extracted from the input value.
let imm12 = (data >> 10) & 4095;
let imm12_post = imm12;
let Rn = (data >> 5) & 31;
let Rn_post = Rn;
let Rt = (data >> 0) & 31;
let Rt_post = Rt;
// Operand values are computed from the base fields.
let Rt_post = Rt;
let op_0 = match (Rt) {
(0) => PrefetchOp::PLDL1KEEP,
(1) => PrefetchOp::PLDL1STRM,
(2) => PrefetchOp::PLDL2KEEP,
(3) => PrefetchOp::PLDL2STRM,
(4) => PrefetchOp::PLDL3KEEP,
(5) => PrefetchOp::PLDL3STRM,
(6) => PrefetchOp::PLDSLCKEEP,
(7) => PrefetchOp::PLDSLCSTRM,
(8) => PrefetchOp::PLIL1KEEP,
(9) => PrefetchOp::PLIL1STRM,
(10) => PrefetchOp::PLIL2KEEP,
(11) => PrefetchOp::PLIL2STRM,
(12) => PrefetchOp::PLIL3KEEP,
(13) => PrefetchOp::PLIL3STRM,
(14) => PrefetchOp::PLISLCKEEP,
(15) => PrefetchOp::PLISLCSTRM,
(16) => PrefetchOp::PSTL1KEEP,
(17) => PrefetchOp::PSTL1STRM,
(18) => PrefetchOp::PSTL2KEEP,
(19) => PrefetchOp::PSTL2STRM,
(20) => PrefetchOp::PSTL3KEEP,
(21) => PrefetchOp::PSTL3STRM,
(22) => PrefetchOp::PSTSLCKEEP,
(23) => PrefetchOp::PSTSLCSTRM,
(24) => PrefetchOp::IR,
_ => PrefetchOp::Other(Rt),
};
let Rn_post = Rn;
let op_1 = Register::aarch64(Rn_post, true)?;
let imm12_post = (imm12) * 8;
let op_2 = imm12_post as u32;
// Instruction creation from the operands.
let mut instr = Instruction::builder(Code::PRFM_P_ldst_pos)
.operand(0, op_0)?
.operand(1, op_1)?
.operand(2, op_2)?
.build();
Ok(instr)
}
/// Encodes the instruction into `buf`.
pub fn encode(instr: &Instruction, buf: &mut Vec<u8>) -> Result<usize> {
// Retrieve all operand values.
let (Rt_pre) = match instr.op0().as_prefetch_op()? {
PrefetchOp::PLDL1KEEP => (0),
PrefetchOp::PLDL1STRM => (1),
PrefetchOp::PLDL2KEEP => (2),
PrefetchOp::PLDL2STRM => (3),
PrefetchOp::PLDL3KEEP => (4),
PrefetchOp::PLDL3STRM => (5),
PrefetchOp::PLDSLCKEEP => (6),
PrefetchOp::PLDSLCSTRM => (7),
PrefetchOp::PLIL1KEEP => (8),
PrefetchOp::PLIL1STRM => (9),
PrefetchOp::PLIL2KEEP => (10),
PrefetchOp::PLIL2STRM => (11),
PrefetchOp::PLIL3KEEP => (12),
PrefetchOp::PLIL3STRM => (13),
PrefetchOp::PLISLCKEEP => (14),
PrefetchOp::PLISLCSTRM => (15),
PrefetchOp::PSTL1KEEP => (16),
PrefetchOp::PSTL1STRM => (17),
PrefetchOp::PSTL2KEEP => (18),
PrefetchOp::PSTL2STRM => (19),
PrefetchOp::PSTL3KEEP => (20),
PrefetchOp::PSTL3STRM => (21),
PrefetchOp::PSTSLCKEEP => (22),
PrefetchOp::PSTSLCSTRM => (23),
PrefetchOp::IR => (24),
PrefetchOp::Other(Rt_pre) => {
let Rt = (Rt_pre & 31);
(Rt)
}
_ => todo!()
};
let Rn_pre = instr.op1().as_register()?.encode();
let imm12_pre = instr.op2().as_unsigned_immediate()? as u32;
// Compute all instruction fields from the operand values.
let Rt = (Rt_pre & 31);
let Rn = (Rn_pre & 31);
let imm12_pre = (imm12_pre) / 8;
let imm12 = (imm12_pre & 4095);
// Add all fields to the base instruction encoding.
let mut instr: u32 = 0b11111001100000000000000000000000;
instr |= (Rt & 31) << 0;
instr |= (Rn & 31) << 5;
instr |= (imm12 & 4095) << 10;
let bytes = instr.to_le_bytes();
let len = bytes.len();
buf.extend(bytes);
Ok(len)
}
/// Encode an instruction part of an instruction block into `buf`.
pub fn encode_block(instr: &mut Instruction, buf: &mut Vec<u8>, labels: &std::collections::HashMap<u64, u64>) -> Result<usize> {
Self::encode(instr, buf)
}
/// Verifies that operand #0 is valid.
pub fn check_op0(instr: &Instruction, op: &Operand) -> Result<()> {
match op.as_prefetch_op()? {
PrefetchOp::PLDL1KEEP => {},
PrefetchOp::PLDL1STRM => {},
PrefetchOp::PLDL2KEEP => {},
PrefetchOp::PLDL2STRM => {},
PrefetchOp::PLDL3KEEP => {},
PrefetchOp::PLDL3STRM => {},
PrefetchOp::PLDSLCKEEP => {},
PrefetchOp::PLDSLCSTRM => {},
PrefetchOp::PLIL1KEEP => {},
PrefetchOp::PLIL1STRM => {},
PrefetchOp::PLIL2KEEP => {},
PrefetchOp::PLIL2STRM => {},
PrefetchOp::PLIL3KEEP => {},
PrefetchOp::PLIL3STRM => {},
PrefetchOp::PLISLCKEEP => {},
PrefetchOp::PLISLCSTRM => {},
PrefetchOp::PSTL1KEEP => {},
PrefetchOp::PSTL1STRM => {},
PrefetchOp::PSTL2KEEP => {},
PrefetchOp::PSTL2STRM => {},
PrefetchOp::PSTL3KEEP => {},
PrefetchOp::PSTL3STRM => {},
PrefetchOp::PSTSLCKEEP => {},
PrefetchOp::PSTSLCSTRM => {},
PrefetchOp::IR => {},
PrefetchOp::Other(value) => if !(0..=31).contains(&value) {
todo!()
}
_ => todo!()
}
Ok(())
}
/// Verifies that operand #1 is valid.
pub fn check_op1(instr: &Instruction, op: &Operand) -> Result<()> {
if let Operand::Register(r) = op {
if !r.is_aarch64() {
todo!()
}
if *r == Register::XZR {
todo!()
}
return Ok(())
}
todo!()
}
/// Verifies that operand #2 is valid.
pub fn check_op2(instr: &Instruction, op: &Operand) -> Result<()> {
if let Operand::UnsignedImmediate(i) = op {
if !(0..=32760).contains(i) {
todo!()
}
return Ok(())
}
todo!()
}
/// Verifies that operand #3 is valid.
pub fn check_op3(instr: &Instruction, op: &Operand) -> Result<()> {
todo!()
}
/// Verifies that operand #4 is valid.
pub fn check_op4(instr: &Instruction, op: &Operand) -> Result<()> {
todo!()
}
/// Verifies that operand #5 is valid.
pub fn check_op5(instr: &Instruction, op: &Operand) -> Result<()> {
todo!()
}
/// Verifies that operand #6 is valid.
pub fn check_op6(instr: &Instruction, op: &Operand) -> Result<()> {
todo!()
}
/// Formats the instruction.
pub fn format(instr: &Instruction, fmt: &mut impl Formatter, output: &mut impl FormatterOutput, config: &Config) -> Result<()> {
fmt.format_mnemonic(output, &config.global, &config.instructions.prfm_p_ldst_pos, instr)?;
fmt.format_punctuation(output, &config.global, &config.instructions.prfm_p_ldst_pos, instr, FormatterTextKind::Space)?;
fmt.format_operand(output, &config.global, &config.instructions.prfm_p_ldst_pos, instr, 0)?;
fmt.format_punctuation(output, &config.global, &config.instructions.prfm_p_ldst_pos, instr, FormatterTextKind::Comma)?;
fmt.format_punctuation(output, &config.global, &config.instructions.prfm_p_ldst_pos, instr, FormatterTextKind::BracketLeft)?;
fmt.format_operand(output, &config.global, &config.instructions.prfm_p_ldst_pos, instr, 1)?;
if instr.op2().as_unsigned_immediate()? != 0 {
fmt.format_punctuation(output, &config.global, &config.instructions.prfm_p_ldst_pos, instr, FormatterTextKind::Comma)?;
fmt.format_punctuation(output, &config.global, &config.instructions.prfm_p_ldst_pos, instr, FormatterTextKind::NumSign)?;
fmt.format_operand(output, &config.global, &config.instructions.prfm_p_ldst_pos, instr, 2)?;
};
fmt.format_punctuation(output, &config.global, &config.instructions.prfm_p_ldst_pos, instr, FormatterTextKind::BracketRight)?;;
Ok(())
}
}
/// Type that represents alias identifiers for [`PrfmPLdstPos`].
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug, Hash)]
pub enum PrfmPLdstPosAliases {
None,
}