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//! # LDTNP
//!
//! This instruction calculates an address from a base register value and an immediate offset, loads two 64-bit doublewords from memory, and writes them to two registers. For information about addressing modes, see *Load/Store addressing modes* . For information about non-temporal pair instructions, see *Load/Store non-temporal pair* .
#![allow(non_snake_case)]
#![allow(unused)]
use crate::error::Result;
use crate::utils::*;
use super::super::formatter::*;
use super::super::instruction::*;
use super::super::operand::*;
use super::super::consts::*;
use super::super::config::*;
use super::super::decoder::*;
// ---------------------------------------------------------------------------
// Iclass IclassLdtnp64LdstnapairOffs
// ---------------------------------------------------------------------------
/// Type that represents the IclassLdtnp64LdstnapairOffs instruction class.
pub(crate) struct IclassLdtnp64LdstnapairOffs;
impl IclassLdtnp64LdstnapairOffs {
/// Tries to decode the instruction in `data`.
pub(crate) fn decode(data: u32, decoder: &mut Decoder) -> Result<Instruction> {
let Rt2 = (data >> 10) & 31;
let Rt2_post = Rt2;
let field_27 = (data >> 27) & 1;
let field_27_post = field_27;
let Rt = (data >> 0) & 31;
let Rt_post = Rt;
let imm7 = (data >> 15) & 127;
let imm7_post = imm7;
let VR = (data >> 26) & 1;
let VR_post = VR;
let Rn = (data >> 5) & 31;
let Rn_post = Rn;
let field_25 = (data >> 25) & 1;
let field_25_post = field_25;
let field_29 = (data >> 28) & 3;
let field_29_post = field_29;
let opc = (data >> 30) & 3;
let opc_post = opc;
let field_24 = (data >> 23) & 3;
let field_24_post = field_24;
let L = (data >> 22) & 1;
let L_post = L;
return Ldtnp64LdstnapairOffs::decode(data as u32, decoder);
unreachable!()
}
}
/// None-bit encoding.
///
/// # Encoding
///
/// <table style="font-family: courier, monospace">
/// <tr>
/// <td style="border: none">31</td>
/// <td style="border: none">30</td>
/// <td style="border: none">29</td>
/// <td style="border: none">28</td>
/// <td style="border: none">27</td>
/// <td style="border: none">26</td>
/// <td style="border: none">25</td>
/// <td style="border: none">24</td>
/// <td style="border: none">23</td>
/// <td style="border: none">22</td>
/// <td style="border: none">21</td>
/// <td style="border: none">20</td>
/// <td style="border: none">19</td>
/// <td style="border: none">18</td>
/// <td style="border: none">17</td>
/// <td style="border: none">16</td>
/// <td style="border: none">15</td>
/// <td style="border: none">14</td>
/// <td style="border: none">13</td>
/// <td style="border: none">12</td>
/// <td style="border: none">11</td>
/// <td style="border: none">10</td>
/// <td style="border: none">9</td>
/// <td style="border: none">8</td>
/// <td style="border: none">7</td>
/// <td style="border: none">6</td>
/// <td style="border: none">5</td>
/// <td style="border: none">4</td>
/// <td style="border: none">3</td>
/// <td style="border: none">2</td>
/// <td style="border: none">1</td>
/// <td style="border: none">0</td>
/// </tr>
/// <tr>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-left: none" colspan="1">1</td>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-left: none" colspan="1">0</td>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-right: none" colspan="1">0</td>
/// <td style="text-align: center; border-right: none" colspan="1">0</td>
/// <td style="text-align: center; border-right: none" colspan="1">0</td>
/// <td style="text-align: center; border-left: none" colspan="1">0</td>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center" colspan="7">imm7</td>
/// <td style="text-align: center" colspan="5">Rt2</td>
/// <td style="text-align: center" colspan="5">Rn</td>
/// <td style="text-align: center" colspan="5">Rt</td>
/// </tr>
/// <tr>
/// <td style="text-align: center; border: none" colspan="2">opc</td>
/// <td style="text-align: center; border: none" colspan="2"></td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="1">VR</td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="2"></td>
/// <td style="text-align: center; border: none" colspan="1">L</td>
/// <td style="text-align: center; border: none" colspan="7"></td>
/// <td style="text-align: center; border: none" colspan="5"></td>
/// <td style="text-align: center; border: none" colspan="5"></td>
/// <td style="text-align: center; border: none" colspan="5"></td>
/// </tr>
/// </table>
pub struct Ldtnp64LdstnapairOffs;
impl Ldtnp64LdstnapairOffs {
/// Returns the instruction mnemonic.
pub fn mnemonic(_instr: &Instruction) -> Mnemonic {
Mnemonic::LDTNP
}
/// Returns the instruction size.
pub fn size(_instr: &Instruction) -> usize {
4
}
/// Decodes the instruction in `data`.
pub fn decode(data: u32, decoder: &mut Decoder) -> Result<Instruction> {
// Fields are extracted from the input value.
let imm7 = (data >> 15) & 127;
let imm7_post = imm7;
let Rt2 = (data >> 10) & 31;
let Rt2_post = Rt2;
let Rn = (data >> 5) & 31;
let Rn_post = Rn;
let Rt = (data >> 0) & 31;
let Rt_post = Rt;
// Operand values are computed from the base fields.
let Rt_post = Rt;
let op_0 = Register::aarch64(Rt_post, false)?;
let Rt2_post = Rt2;
let op_1 = Register::aarch64(Rt2_post, false)?;
let Rn_post = Rn;
let op_2 = Register::aarch64(Rn_post, true)?;
let imm7_post = ((((imm7) as i32) * 8) << 22) >> 22;
let op_3 = imm7_post as i32;
// Instruction creation from the operands.
let mut instr = Instruction::builder(Code::LDTNP_64_ldstnapair_offs)
.operand(0, op_0)?
.operand(1, op_1)?
.operand(2, op_2)?
.operand(3, op_3)?
.build();
Ok(instr)
}
/// Encodes the instruction into `buf`.
pub fn encode(instr: &Instruction, buf: &mut Vec<u8>) -> Result<usize> {
// Retrieve all operand values.
let Rt_pre = instr.op0().as_register()?.encode();
let Rt2_pre = instr.op1().as_register()?.encode();
let Rn_pre = instr.op2().as_register()?.encode();
let imm7_pre = instr.op3().as_signed_immediate()? as u32;
// Compute all instruction fields from the operand values.
let Rt = (Rt_pre & 31);
let Rt2 = (Rt2_pre & 31);
let Rn = (Rn_pre & 31);
let imm7_pre = ((imm7_pre) / 8) as u32;
let imm7 = (imm7_pre & 127);
// Add all fields to the base instruction encoding.
let mut instr: u32 = 0b11101000010000000000000000000000;
instr |= (Rt & 31) << 0;
instr |= (Rt2 & 31) << 10;
instr |= (Rn & 31) << 5;
instr |= (imm7 & 127) << 15;
let bytes = instr.to_le_bytes();
let len = bytes.len();
buf.extend(bytes);
Ok(len)
}
/// Encode an instruction part of an instruction block into `buf`.
pub fn encode_block(instr: &mut Instruction, buf: &mut Vec<u8>, labels: &std::collections::HashMap<u64, u64>) -> Result<usize> {
Self::encode(instr, buf)
}
/// Verifies that operand #0 is valid.
pub fn check_op0(instr: &Instruction, op: &Operand) -> Result<()> {
if let Operand::Register(r) = op {
if !r.is_aarch64() {
todo!()
}
if *r == Register::SP {
todo!()
}
return Ok(())
}
todo!()
}
/// Verifies that operand #1 is valid.
pub fn check_op1(instr: &Instruction, op: &Operand) -> Result<()> {
if let Operand::Register(r) = op {
if !r.is_aarch64() {
todo!()
}
if *r == Register::SP {
todo!()
}
return Ok(())
}
todo!()
}
/// Verifies that operand #2 is valid.
pub fn check_op2(instr: &Instruction, op: &Operand) -> Result<()> {
if let Operand::Register(r) = op {
if !r.is_aarch64() {
todo!()
}
if *r == Register::XZR {
todo!()
}
return Ok(())
}
todo!()
}
/// Verifies that operand #3 is valid.
pub fn check_op3(instr: &Instruction, op: &Operand) -> Result<()> {
if let Operand::SignedImmediate(i) = op {
if !(-512..=504).contains(i) {
todo!()
}
return Ok(())
}
todo!()
}
/// Verifies that operand #4 is valid.
pub fn check_op4(instr: &Instruction, op: &Operand) -> Result<()> {
todo!()
}
/// Verifies that operand #5 is valid.
pub fn check_op5(instr: &Instruction, op: &Operand) -> Result<()> {
todo!()
}
/// Verifies that operand #6 is valid.
pub fn check_op6(instr: &Instruction, op: &Operand) -> Result<()> {
todo!()
}
/// Formats the instruction.
pub fn format(instr: &Instruction, fmt: &mut impl Formatter, output: &mut impl FormatterOutput, config: &Config) -> Result<()> {
fmt.format_mnemonic(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr)?;
fmt.format_punctuation(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr, FormatterTextKind::Space)?;
fmt.format_operand(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr, 0)?;
fmt.format_punctuation(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr, FormatterTextKind::Comma)?;
fmt.format_operand(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr, 1)?;
fmt.format_punctuation(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr, FormatterTextKind::Comma)?;
fmt.format_punctuation(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr, FormatterTextKind::BracketLeft)?;
fmt.format_operand(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr, 2)?;
if instr.op3().as_unsigned_immediate()? != 0 {
fmt.format_punctuation(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr, FormatterTextKind::Comma)?;
fmt.format_punctuation(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr, FormatterTextKind::NumSign)?;
fmt.format_operand(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr, 3)?;
};
fmt.format_punctuation(output, &config.global, &config.instructions.ldtnp_64_ldstnapair_offs, instr, FormatterTextKind::BracketRight)?;;
Ok(())
}
}
/// Type that represents alias identifiers for [`Ldtnp64LdstnapairOffs`].
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug, Hash)]
pub enum Ldtnp64LdstnapairOffsAliases {
None,
}