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//! # LDG
//!
//! This instruction loads an Allocation Tag from a memory address, generates a Logical Address Tag from the Allocation Tag and merges it into the destination register. The address used for the load is calculated from the base register and an immediate signed offset scaled by the Tag Granule.
#![allow(non_snake_case)]
#![allow(unused)]
use crate::error::Result;
use crate::utils::*;
use super::super::formatter::*;
use super::super::instruction::*;
use super::super::operand::*;
use super::super::consts::*;
use super::super::config::*;
use super::super::decoder::*;
// ---------------------------------------------------------------------------
// Iclass IclassLdg64loffsetLdsttags
// ---------------------------------------------------------------------------
/// Type that represents the IclassLdg64loffsetLdsttags instruction class.
pub(crate) struct IclassLdg64loffsetLdsttags;
impl IclassLdg64loffsetLdsttags {
/// Tries to decode the instruction in `data`.
pub(crate) fn decode(data: u32, decoder: &mut Decoder) -> Result<Instruction> {
let field_31 = (data >> 28) & 15;
let field_31_post = field_31;
let field_27 = (data >> 27) & 1;
let field_27_post = field_27;
let Rt = (data >> 0) & 31;
let Rt_post = Rt;
let field_26 = (data >> 26) & 1;
let field_26_post = field_26;
let op2 = (data >> 10) & 3;
let op2_post = op2;
let Rn = (data >> 5) & 31;
let Rn_post = Rn;
let field_21 = (data >> 21) & 1;
let field_21_post = field_21;
let field_25 = (data >> 25) & 1;
let field_25_post = field_25;
let imm9 = (data >> 12) & 511;
let imm9_post = imm9;
let opc = (data >> 22) & 3;
let opc_post = opc;
let field_24 = (data >> 24) & 1;
let field_24_post = field_24;
return Ldg64loffsetLdsttags::decode(data as u32, decoder);
unreachable!()
}
}
/// None-bit encoding.
///
/// # Encoding
///
/// <table style="font-family: courier, monospace">
/// <tr>
/// <td style="border: none">31</td>
/// <td style="border: none">30</td>
/// <td style="border: none">29</td>
/// <td style="border: none">28</td>
/// <td style="border: none">27</td>
/// <td style="border: none">26</td>
/// <td style="border: none">25</td>
/// <td style="border: none">24</td>
/// <td style="border: none">23</td>
/// <td style="border: none">22</td>
/// <td style="border: none">21</td>
/// <td style="border: none">20</td>
/// <td style="border: none">19</td>
/// <td style="border: none">18</td>
/// <td style="border: none">17</td>
/// <td style="border: none">16</td>
/// <td style="border: none">15</td>
/// <td style="border: none">14</td>
/// <td style="border: none">13</td>
/// <td style="border: none">12</td>
/// <td style="border: none">11</td>
/// <td style="border: none">10</td>
/// <td style="border: none">9</td>
/// <td style="border: none">8</td>
/// <td style="border: none">7</td>
/// <td style="border: none">6</td>
/// <td style="border: none">5</td>
/// <td style="border: none">4</td>
/// <td style="border: none">3</td>
/// <td style="border: none">2</td>
/// <td style="border: none">1</td>
/// <td style="border: none">0</td>
/// </tr>
/// <tr>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-left: none; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-left: none; border-right: none" colspan="1">0</td>
/// <td style="text-align: center; border-left: none" colspan="1">1</td>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-right: none" colspan="1">0</td>
/// <td style="text-align: center; border-right: none" colspan="1">0</td>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center; border-right: none" colspan="1">0</td>
/// <td style="text-align: center; border-left: none" colspan="1">1</td>
/// <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center" colspan="9">imm9</td>
/// <td style="text-align: center; border-right: none" colspan="1">0</td>
/// <td style="text-align: center; border-left: none" colspan="1">0</td>
/// <td style="text-align: center" colspan="5">Rn</td>
/// <td style="text-align: center" colspan="5">Rt</td>
/// </tr>
/// <tr>
/// <td style="text-align: center; border: none" colspan="4"></td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="2">opc</td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="9"></td>
/// <td style="text-align: center; border: none" colspan="2">op2</td>
/// <td style="text-align: center; border: none" colspan="5"></td>
/// <td style="text-align: center; border: none" colspan="5"></td>
/// </tr>
/// </table>
pub struct Ldg64loffsetLdsttags;
impl Ldg64loffsetLdsttags {
/// Returns the instruction mnemonic.
pub fn mnemonic(_instr: &Instruction) -> Mnemonic {
Mnemonic::LDG
}
/// Returns the instruction size.
pub fn size(_instr: &Instruction) -> usize {
4
}
/// Decodes the instruction in `data`.
pub fn decode(data: u32, decoder: &mut Decoder) -> Result<Instruction> {
// Fields are extracted from the input value.
let imm9 = (data >> 12) & 511;
let imm9_post = imm9;
let Rn = (data >> 5) & 31;
let Rn_post = Rn;
let Rt = (data >> 0) & 31;
let Rt_post = Rt;
// Operand values are computed from the base fields.
let Rt_post = Rt;
let op_0 = Register::aarch64(Rt_post, false)?;
let Rn_post = Rn;
let op_1 = Register::aarch64(Rn_post, true)?;
let imm9_post = ((((imm9) as i32) * 16) << 19) >> 19;
let op_2 = imm9_post as i32;
// Instruction creation from the operands.
let mut instr = Instruction::builder(Code::LDG_64Loffset_ldsttags)
.operand(0, op_0)?
.operand(1, op_1)?
.operand(2, op_2)?
.build();
Ok(instr)
}
/// Encodes the instruction into `buf`.
pub fn encode(instr: &Instruction, buf: &mut Vec<u8>) -> Result<usize> {
// Retrieve all operand values.
let Rt_pre = instr.op0().as_register()?.encode();
let Rn_pre = instr.op1().as_register()?.encode();
let imm9_pre = instr.op2().as_signed_immediate()? as u32;
// Compute all instruction fields from the operand values.
let Rt = (Rt_pre & 31);
let Rn = (Rn_pre & 31);
let imm9_pre = ((imm9_pre) / 16) as u32;
let imm9 = (imm9_pre & 511);
// Add all fields to the base instruction encoding.
let mut instr: u32 = 0b11011001011000000000000000000000;
instr |= (Rt & 31) << 0;
instr |= (Rn & 31) << 5;
instr |= (imm9 & 511) << 12;
let bytes = instr.to_le_bytes();
let len = bytes.len();
buf.extend(bytes);
Ok(len)
}
/// Encode an instruction part of an instruction block into `buf`.
pub fn encode_block(instr: &mut Instruction, buf: &mut Vec<u8>, labels: &std::collections::HashMap<u64, u64>) -> Result<usize> {
Self::encode(instr, buf)
}
/// Verifies that operand #0 is valid.
pub fn check_op0(instr: &Instruction, op: &Operand) -> Result<()> {
if let Operand::Register(r) = op {
if !r.is_aarch64() {
todo!()
}
if *r == Register::SP {
todo!()
}
return Ok(())
}
todo!()
}
/// Verifies that operand #1 is valid.
pub fn check_op1(instr: &Instruction, op: &Operand) -> Result<()> {
if let Operand::Register(r) = op {
if !r.is_aarch64() {
todo!()
}
if *r == Register::XZR {
todo!()
}
return Ok(())
}
todo!()
}
/// Verifies that operand #2 is valid.
pub fn check_op2(instr: &Instruction, op: &Operand) -> Result<()> {
if let Operand::SignedImmediate(i) = op {
if !(-4096..=4080).contains(i) {
todo!()
}
return Ok(())
}
todo!()
}
/// Verifies that operand #3 is valid.
pub fn check_op3(instr: &Instruction, op: &Operand) -> Result<()> {
todo!()
}
/// Verifies that operand #4 is valid.
pub fn check_op4(instr: &Instruction, op: &Operand) -> Result<()> {
todo!()
}
/// Verifies that operand #5 is valid.
pub fn check_op5(instr: &Instruction, op: &Operand) -> Result<()> {
todo!()
}
/// Verifies that operand #6 is valid.
pub fn check_op6(instr: &Instruction, op: &Operand) -> Result<()> {
todo!()
}
/// Formats the instruction.
pub fn format(instr: &Instruction, fmt: &mut impl Formatter, output: &mut impl FormatterOutput, config: &Config) -> Result<()> {
fmt.format_mnemonic(output, &config.global, &config.instructions.ldg_64loffset_ldsttags, instr)?;
fmt.format_punctuation(output, &config.global, &config.instructions.ldg_64loffset_ldsttags, instr, FormatterTextKind::Space)?;
fmt.format_operand(output, &config.global, &config.instructions.ldg_64loffset_ldsttags, instr, 0)?;
fmt.format_punctuation(output, &config.global, &config.instructions.ldg_64loffset_ldsttags, instr, FormatterTextKind::Comma)?;
fmt.format_punctuation(output, &config.global, &config.instructions.ldg_64loffset_ldsttags, instr, FormatterTextKind::BracketLeft)?;
fmt.format_operand(output, &config.global, &config.instructions.ldg_64loffset_ldsttags, instr, 1)?;
if instr.op2().as_unsigned_immediate()? != 0 {
fmt.format_punctuation(output, &config.global, &config.instructions.ldg_64loffset_ldsttags, instr, FormatterTextKind::Comma)?;
fmt.format_punctuation(output, &config.global, &config.instructions.ldg_64loffset_ldsttags, instr, FormatterTextKind::NumSign)?;
fmt.format_operand(output, &config.global, &config.instructions.ldg_64loffset_ldsttags, instr, 2)?;
};
fmt.format_punctuation(output, &config.global, &config.instructions.ldg_64loffset_ldsttags, instr, FormatterTextKind::BracketRight)?;;
Ok(())
}
}
/// Type that represents alias identifiers for [`Ldg64loffsetLdsttags`].
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug, Hash)]
pub enum Ldg64loffsetLdsttagsAliases {
None,
}