charm 0.0.1

//! # LDRSW (register)
//!
//! This instruction calculates an address from a base register value and an offset register value, loads a word from memory, sign-extends it to form a 64-bit value, and writes it to a register. The offset register value can be shifted left by 0 or 2 bits. For information about addressing modes, see *Load/Store addressing modes* .

#![allow(non_snake_case)]
#![allow(unused)]
use crate::error::Result;
use crate::utils::*;
use super::super::formatter::*;
use super::super::instruction::*;
use super::super::operand::*;
use super::super::consts::*;
use super::super::config::*;
use super::super::decoder::*;

// ---------------------------------------------------------------------------
// Iclass IclassLdrsw64LdstRegoff
// ---------------------------------------------------------------------------

/// Type that represents the IclassLdrsw64LdstRegoff instruction class.
pub(crate) struct IclassLdrsw64LdstRegoff;

impl IclassLdrsw64LdstRegoff {
    /// Tries to decode the instruction in `data`.
    pub(crate) fn decode(data: u32, decoder: &mut Decoder) -> Result<Instruction> {
        let size = (data >> 30) & 3;
        let size_post = size;
        let Rm = (data >> 16) & 31;
        let Rm_post = Rm;
        let field_27 = (data >> 27) & 1;
        let field_27_post = field_27;
        let Rt = (data >> 0) & 31;
        let Rt_post = Rt;
        let S = (data >> 12) & 1;
        let S_post = S;
        let VR = (data >> 26) & 1;
        let VR_post = VR;
        let Rn = (data >> 5) & 31;
        let Rn_post = Rn;
        let field_21 = (data >> 21) & 1;
        let field_21_post = field_21;
        let field_25 = (data >> 25) & 1;
        let field_25_post = field_25;
        let field_29 = (data >> 28) & 3;
        let field_29_post = field_29;
        let option = (data >> 13) & 7;
        let option_post = option;
        let opc = (data >> 22) & 3;
        let opc_post = opc;
        let field_11 = (data >> 10) & 3;
        let field_11_post = field_11;
        let field_24 = (data >> 24) & 1;
        let field_24_post = field_24;


        return Ldrsw64LdstRegoff::decode(data as u32, decoder);

        unreachable!()
    }
}

/// 64-bit encoding.
///
/// # Encoding
///
/// <table style="font-family: courier, monospace">
///     <tr>
///         <td style="border: none">31</td>
///         <td style="border: none">30</td>
///         <td style="border: none">29</td>
///         <td style="border: none">28</td>
///         <td style="border: none">27</td>
///         <td style="border: none">26</td>
///         <td style="border: none">25</td>
///         <td style="border: none">24</td>
///         <td style="border: none">23</td>
///         <td style="border: none">22</td>
///         <td style="border: none">21</td>
///         <td style="border: none">20</td>
///         <td style="border: none">19</td>
///         <td style="border: none">18</td>
///         <td style="border: none">17</td>
///         <td style="border: none">16</td>
///         <td style="border: none">15</td>
///         <td style="border: none">14</td>
///         <td style="border: none">13</td>
///         <td style="border: none">12</td>
///         <td style="border: none">11</td>
///         <td style="border: none">10</td>
///         <td style="border: none">9</td>
///         <td style="border: none">8</td>
///         <td style="border: none">7</td>
///         <td style="border: none">6</td>
///         <td style="border: none">5</td>
///         <td style="border: none">4</td>
///         <td style="border: none">3</td>
///         <td style="border: none">2</td>
///         <td style="border: none">1</td>
///         <td style="border: none">0</td>
///     </tr>
///     <tr>
///          <td style="text-align: center; border-right: none" colspan="1">1</td>
///          <td style="text-align: center; border-left: none" colspan="1">0</td>
///          <td style="text-align: center; border-right: none" colspan="1">1</td>
///          <td style="text-align: center; border-left: none" colspan="1">1</td>
///          <td style="text-align: center; border-right: none" colspan="1">1</td>
///          <td style="text-align: center; border-right: none" colspan="1">0</td>
///          <td style="text-align: center; border-right: none" colspan="1">0</td>
///          <td style="text-align: center; border-right: none" colspan="1">0</td>
///          <td style="text-align: center; border-right: none" colspan="1">1</td>
///          <td style="text-align: center; border-left: none" colspan="1">0</td>
///          <td style="text-align: center; border-right: none" colspan="1">1</td>
/// <td style="text-align: center" colspan="5">Rm</td>
/// <td style="text-align: center" colspan="3">option</td>
/// <td style="text-align: center" colspan="1">S</td>
///          <td style="text-align: center; border-right: none" colspan="1">1</td>
///          <td style="text-align: center; border-left: none" colspan="1">0</td>
/// <td style="text-align: center" colspan="5">Rn</td>
/// <td style="text-align: center" colspan="5">Rt</td>
///     </tr>
///     <tr>
/// <td style="text-align: center; border: none" colspan="2">size</td>
/// <td style="text-align: center; border: none" colspan="2"></td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="1">VR</td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="2">opc</td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="5"></td>
/// <td style="text-align: center; border: none" colspan="3"></td>
/// <td style="text-align: center; border: none" colspan="1"></td>
/// <td style="text-align: center; border: none" colspan="2"></td>
/// <td style="text-align: center; border: none" colspan="5"></td>
/// <td style="text-align: center; border: none" colspan="5"></td>
///     </tr>
/// </table>
pub struct Ldrsw64LdstRegoff;

impl Ldrsw64LdstRegoff {
    /// Returns the instruction mnemonic.
    pub fn mnemonic(_instr: &Instruction) -> Mnemonic {
        Mnemonic::LDRSW
    }

    /// Returns the instruction size.
    pub fn size(_instr: &Instruction) -> usize {
        4
    }

    /// Decodes the instruction in `data`.
    pub fn decode(data: u32, decoder: &mut Decoder) -> Result<Instruction> {
        // Fields are extracted from the input value.
        let Rm = (data >> 16) & 31;
        let Rm_post = Rm;
        let option = (data >> 13) & 7;
        let option_post = option;
        let S = (data >> 12) & 1;
        let S_post = S;
        let Rn = (data >> 5) & 31;
        let Rn_post = Rn;
        let Rt = (data >> 0) & 31;
        let Rt_post = Rt;
        

        // Operand values are computed from the base fields.
        let Rt_post = Rt;
        let op_0 = Register::aarch64(Rt_post, false)?;
        let Rn_post = Rn;
        let op_1 = Register::aarch64(Rn_post, true)?;
        let Rm_post = Rm;
        let op_2 = match (option >> 0) & 1 {
            0 => Register::aarch32(Rm_post, false)?,
            1 => Register::aarch64(Rm_post, false)?,
            _ => todo!(),
        };
        let S_post = S;
        let option_post = option;
        let op_3 = {
            let value = match S_post {
                0 => 0,
                1 => 2,
                _ => todo!(),
            };
            match option_post {
                2 => Extension::Uxtw(value),
                3 => Extension::Lsl(value),
                6 => Extension::Sxtw(value),
                7 => Extension::Sxtx(value),
                _ => todo!(),
            }
        };

        // Instruction creation from the operands.
        let mut instr = Instruction::builder(Code::LDRSW_64_ldst_regoff)
            .operand(0, op_0)?
            .operand(1, op_1)?
            .operand(2, op_2)?
            .operand(3, op_3)?
            .build();
        
        Ok(instr)
    }

    /// Encodes the instruction into `buf`.
    pub fn encode(instr: &Instruction, buf: &mut Vec<u8>) -> Result<usize> {
        // Retrieve all operand values.
        let Rt_pre = instr.op0().as_register()?.encode();
        let Rn_pre = instr.op1().as_register()?.encode();
        let Rm_pre = instr.op2().as_register()?.encode();
        let (S_pre, option_pre) = {
            let (extension, value) = match instr.op3().as_extension()? {
                Extension::Uxtw(value) => (2, value),
                Extension::Lsl(value) => (3, value),
                Extension::Sxtw(value) => (6, value),
                Extension::Sxtx(value) => (7, value),
                _ => todo!(),
            };
            let amount = match value {
                0 => 0,
                2 => 1,
                _ => todo!(),
            };
            (amount, extension)
        };

        // Compute all instruction fields from the operand values.
        let Rt = (Rt_pre & 31);
        let Rn = (Rn_pre & 31);
        let Rm = (Rm_pre & 31);
        let S_pre = S_pre;
        let S = (S_pre & 1);
        let option = (option_pre & 7);

        // Add all fields to the base instruction encoding.
        let mut instr: u32 = 0b10111000101000000000100000000000;
        instr |= (Rt & 31) << 0;
        instr |= (Rn & 31) << 5;
        instr |= (Rm & 31) << 16;
        instr |= (S & 1) << 12;
        instr |= (option & 7) << 13;

        let bytes = instr.to_le_bytes();
        let len = bytes.len();
        buf.extend(bytes);
        Ok(len)
    }

    /// Encode an instruction part of an instruction block into `buf`.
    pub fn encode_block(instr: &mut Instruction, buf: &mut Vec<u8>, labels: &std::collections::HashMap<u64, u64>) -> Result<usize> {
        Self::encode(instr, buf)
    }
    
    /// Verifies that operand #0 is valid.
    pub fn check_op0(instr: &Instruction, op: &Operand) -> Result<()> {
        if let Operand::Register(r) = op {
            if !r.is_aarch64() {
                todo!()
            }
            
            if *r == Register::SP {
                todo!()
            }
            return Ok(())
        }
        todo!()
    }
    
    /// Verifies that operand #1 is valid.
    pub fn check_op1(instr: &Instruction, op: &Operand) -> Result<()> {
        if let Operand::Register(r) = op {
            if !r.is_aarch64() {
                todo!()
            }
            
            if *r == Register::XZR {
                todo!()
            }
            return Ok(())
        }
        todo!()
    }
    
    /// Verifies that operand #2 is valid.
    pub fn check_op2(instr: &Instruction, op: &Operand) -> Result<()> {
        if let Operand::Register(r) = op {
            match instr.op3() {
                Operand::None => {
                    if r.is_aarch32() {
                        if *r == Register::WSP {
                            todo!()
                        }
                    } else if r.is_aarch64() {
                        if *r == Register::SP {
                            todo!()
                        }
                    }
                }
                Operand::Extension(Extension::Uxtw(_)) => {
                    if r.is_aarch64() {
                        todo!()
                    }
                    if *r == Register::WSP {
                        todo!()
                    }
                }
                Operand::Extension(Extension::Lsl(_)) => {
                    if r.is_aarch32() {
                        todo!()
                    }
                    if *r == Register::SP {
                        todo!()
                    }
                }
                Operand::Extension(Extension::Sxtw(_)) => {
                    if r.is_aarch64() {
                        todo!()
                    }
                    if *r == Register::WSP {
                        todo!()
                    }
                }
                Operand::Extension(Extension::Sxtx(_)) => {
                    if r.is_aarch32() {
                        todo!()
                    }
                    if *r == Register::SP {
                        todo!()
                    }
                }
                _ => todo!(),
            }
            return Ok(())
        }
        todo!()
    }
    
    /// Verifies that operand #3 is valid.
    pub fn check_op3(instr: &Instruction, op: &Operand) -> Result<()> {
        match op.as_extension()? {
            Extension::Uxtw(_) => {}
            Extension::Lsl(_) => {}
            Extension::Sxtw(_) => {}
            Extension::Sxtx(_) => {}
            _ => todo!(),
        }
        Ok(())
    }
    
    /// Verifies that operand #4 is valid.
    pub fn check_op4(instr: &Instruction, op: &Operand) -> Result<()> {
        todo!()
    }
    
    /// Verifies that operand #5 is valid.
    pub fn check_op5(instr: &Instruction, op: &Operand) -> Result<()> {
        todo!()
    }
    
    /// Verifies that operand #6 is valid.
    pub fn check_op6(instr: &Instruction, op: &Operand) -> Result<()> {
        todo!()
    }

    /// Formats the instruction.
    pub fn format(instr: &Instruction, fmt: &mut impl Formatter, output: &mut impl FormatterOutput, config: &Config) -> Result<()> {
        fmt.format_mnemonic(output, &config.global, &config.instructions.ldrsw_64_ldst_regoff, instr)?;
        fmt.format_punctuation(output, &config.global, &config.instructions.ldrsw_64_ldst_regoff, instr, FormatterTextKind::Space)?;
        fmt.format_operand(output, &config.global, &config.instructions.ldrsw_64_ldst_regoff, instr, 0)?;
        fmt.format_punctuation(output, &config.global, &config.instructions.ldrsw_64_ldst_regoff, instr, FormatterTextKind::Comma)?;
        fmt.format_punctuation(output, &config.global, &config.instructions.ldrsw_64_ldst_regoff, instr, FormatterTextKind::BracketLeft)?;
        fmt.format_operand(output, &config.global, &config.instructions.ldrsw_64_ldst_regoff, instr, 1)?;
        fmt.format_punctuation(output, &config.global, &config.instructions.ldrsw_64_ldst_regoff, instr, FormatterTextKind::Comma)?;
        fmt.format_operand(output, &config.global, &config.instructions.ldrsw_64_ldst_regoff, instr, 2)?;
        if (!instr.op3().as_extension()?.is_lsl() || instr.op3().as_extension()?.value() != 0) {
            fmt.format_punctuation(output, &config.global, &config.instructions.ldrsw_64_ldst_regoff, instr, FormatterTextKind::Comma)?;
            fmt.format_operand(output, &config.global, &config.instructions.ldrsw_64_ldst_regoff, instr, 3)?;
        };
        fmt.format_punctuation(output, &config.global, &config.instructions.ldrsw_64_ldst_regoff, instr, FormatterTextKind::BracketRight)?;;
        Ok(())
    }
}

/// Type that represents alias identifiers for [`Ldrsw64LdstRegoff`].
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug, Hash)]
pub enum Ldrsw64LdstRegoffAliases {
    None,
}