calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    r1 = std_reg(32);
    lt = std_lt(32);
  }
  wires {
    static<2> group A {
      r1.write_en = 1'd1;
      r1.in = 32'd2;
    }
    lt.left = r1.out;
    lt.right = 32'd4;
  }
  control {
    while lt.out {
      A;
    }
  }
}
---STDERR---
[WARN  calyx_opt::passes::well_formed] tests/errors/while-unstable.futil
    20 |    while lt.out {
       |    ^^^^^^^^^^^^^^ While loop has no comb group and its condition port lt.out is unstable