calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

import "primitives/core.futil";
import "primitives/memories/comb.futil";
comb static<1> component custom_lt(left: 4, right: 4) -> (out: 1) {
  cells {
    lt = std_lt(4);
  }
  wires {
    comb group g {
      lt.left = left;
      lt.right = right;
      out = lt.out;
    }
  }
}

component main(@go go: 1, @clk clk: 1, @reset reset: 1, a: 4, b: 4, c: 1) -> (@done done: 1) {
  cells {
    lt = custom_lt();
  }
  wires {
  }
  control {
  }
}