asmkit-rs 0.3.1

#![allow(unused_imports, dead_code, non_snake_case, clippy::all)]
extern crate alloc;
use crate::x86::assembler::Assembler;
use crate::x86::operands::*;
use super::super::opcodes::*;
use crate::core::emitter::*;
use crate::core::operand::*;
use crate::AsmError;

const NOREG: Operand = Operand::new();

/// A dynamically typed x86 instruction.
///
/// Build instructions with runtime operand-type checking via the associated
/// constructor methods (e.g. [`Instruction::mov`], [`Instruction::add`]),
/// or build from a mnemonic string with [`Instruction::from_mnem`].
pub struct Instruction {
    /// Encoded opcode constant (matches those in `opcodes.rs`).
    pub opcode: i64,
    pub op0: Operand,
    pub op1: Operand,
    pub op2: Operand,
    pub op3: Operand,
}

impl Instruction {
    /// Emit this instruction into the given assembler.
    #[inline]
    pub fn emit(&self, asm: &mut Assembler<'_>) {
        asm.emit(self.opcode, &self.op0, &self.op1, &self.op2, &self.op3);
    }

    /// Construct a dynamically typed `3DNOW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn _3dnow(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) && op2.is_imm() {
            return Ok(Self { opcode: _3DNOWRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: _3DNOWRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aadd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: AADD32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: AADD64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AAND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aand(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: AAND32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: AAND64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ADC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn adc(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ADC8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ADC8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: ADC16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: ADC16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: ADC32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: ADC32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: ADC64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: ADC64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_mem() {
            return Ok(Self { opcode: ADC8RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: ADC16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: ADC32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: ADC64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: ADC8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: ADC16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: ADC32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: ADC64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: ADC8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ADCX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn adcx(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: ADCX32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: ADCX32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: ADCX64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: ADCX64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn add(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ADD8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ADD8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: ADD16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: ADD16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: ADD32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: ADD32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: ADD64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: ADD64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_mem() {
            return Ok(Self { opcode: ADD8RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: ADD16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: ADD32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: ADD64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: ADD8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: ADD16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: ADD32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: ADD64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: ADD8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ADOX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn adox(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: ADOX32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: ADOX32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: ADOX64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: ADOX64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESDEC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesdec(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: AESDECRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: AESDECRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESDEC128KL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesdec128kl(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: AESDEC128KLRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESDEC256KL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesdec256kl(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: AESDEC256KLRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESDECLAST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesdeclast(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: AESDECLASTRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: AESDECLASTRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESDECWIDE128KL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesdecwide128kl(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: AESDECWIDE128KLM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESDECWIDE256KL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesdecwide256kl(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: AESDECWIDE256KLM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESENC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesenc(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: AESENCRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: AESENCRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESENC128KL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesenc128kl(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: AESENC128KLRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESENC256KL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesenc256kl(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: AESENC256KLRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESENCLAST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesenclast(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: AESENCLASTRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: AESENCLASTRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESENCWIDE128KL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesencwide128kl(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: AESENCWIDE128KLM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESENCWIDE256KL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesencwide256kl(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: AESENCWIDE256KLM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESIMC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aesimc(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: AESIMCRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: AESIMCRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AESKEYGENASSIST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aeskeygenassist(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: AESKEYGENASSISTRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: AESKEYGENASSISTRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn and(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: AND8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: AND8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: AND16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: AND16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: AND32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: AND32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: AND64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: AND64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_mem() {
            return Ok(Self { opcode: AND8RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: AND16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: AND32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: AND64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: AND8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: AND16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: AND32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: AND64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: AND8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ANDN` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn andn(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: ANDN32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() && op2.is_mem() {
            return Ok(Self { opcode: ANDN32RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: ANDN64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_mem() {
            return Ok(Self { opcode: ANDN64RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn aor(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: AOR32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: AOR64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `AXOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn axor(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: AXOR32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: AXOR64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BEXTR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn bextr(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: BEXTR32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() && op2.is_gp32() {
            return Ok(Self { opcode: BEXTR32RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: BEXTR64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() && op2.is_gp64() {
            return Ok(Self { opcode: BEXTR64RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BLSI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn blsi(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: BLSI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: BLSI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: BLSI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: BLSI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BLSMSK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn blsmsk(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: BLSMSK32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: BLSMSK32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: BLSMSK64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: BLSMSK64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BLSR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn blsr(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: BLSR32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: BLSR32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: BLSR64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: BLSR64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BSF` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn bsf(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: BSF16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: BSF16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: BSF32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: BSF32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: BSF64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: BSF64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BSR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn bsr(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: BSR16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: BSR16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: BSR32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: BSR32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: BSR64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: BSR64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BSWAP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn bswap(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: BSWAP16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: BSWAP32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: BSWAP64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn bt(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: BT16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: BT16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: BT32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: BT32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: BT64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: BT64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: BT16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: BT16MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: BT32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: BT64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BTC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn btc(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: BTC16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: BTC16MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: BTC32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: BTC64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: BTC16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: BTC16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: BTC32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: BTC32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: BTC64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: BTC64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BTR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn btr(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: BTR16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: BTR16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: BTR32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: BTR32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: BTR64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: BTR64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: BTR16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: BTR16MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: BTR32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: BTR64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BTS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn bts(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: BTS16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: BTS16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: BTS32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: BTS32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: BTS64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: BTS64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: BTS16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: BTS16MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: BTS32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: BTS64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `BZHI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn bzhi(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: BZHI32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() && op2.is_gp32() {
            return Ok(Self { opcode: BZHI32RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: BZHI64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() && op2.is_gp64() {
            return Ok(Self { opcode: BZHI64RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CALL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn call(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: CALL, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: CALL, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: CALL, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: CALLR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: CALLM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CALLF` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn callf(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: CALLF16M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cbw() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CBW, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cdq() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CDQ, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CDQE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cdqe() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CDQE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CLAC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn clac() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CLAC, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CLC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn clc() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CLC, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cld() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CLD, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CLDEMOTE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cldemote(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: CLDEMOTEM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CLFLUSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn clflush(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: CLFLUSHM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CLFLUSHOPT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn clflushopt(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: CLFLUSHOPTM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CLGI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn clgi() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CLGI, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CLI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cli() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CLI, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CLRSSBSY` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn clrssbsy(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: CLRSSBSYM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CLTS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn clts() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CLTS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CLUI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn clui() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CLUI, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CLWB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn clwb(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: CLWBM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CLZERO` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn clzero(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CLZERO16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: CLZERO32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: CLZERO64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmc() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CMC, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CMOVA` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmova(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVA16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVA16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVA32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVA32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVA64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVA64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVBE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovbe(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVBE16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVBE16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVBE32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVBE32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVBE64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVBE64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovc(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVC16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVC16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVC32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVC32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVC64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVC64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovg(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVG16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVG16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVG32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVG32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVG64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVG64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVGE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovge(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVGE16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVGE16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVGE32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVGE32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVGE64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVGE64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovl(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVL16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVL16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVL32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVL32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVL64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVL64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVLE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovle(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVLE16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVLE16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVLE32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVLE32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVLE64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVLE64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVNC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovnc(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVNC16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVNC16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVNC32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVNC32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVNC64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVNC64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVNO` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovno(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVNO16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVNO16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVNO32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVNO32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVNO64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVNO64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVNP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovnp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVNP16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVNP16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVNP32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVNP32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVNP64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVNP64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVNS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovns(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVNS16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVNS16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVNS32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVNS32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVNS64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVNS64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVNZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovnz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVNZ16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVNZ16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVNZ32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVNZ32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVNZ64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVNZ64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVO` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovo(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVO16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVO16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVO32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVO32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVO64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVO64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVP16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVP16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVP32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVP32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVP64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVP64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovs(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVS16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVS16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVS32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVS32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVS64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVS64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVZ16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVZ16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVZ32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVZ32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVZ64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVZ64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMOVCC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmovcc(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMOVCC16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMOVCC16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMOVCC32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMOVCC32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMOVCC64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMOVCC64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: CMP8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: CMP8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMP16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMP16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMP32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: CMP32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMP64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: CMP64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_mem() {
            return Ok(Self { opcode: CMP8RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: CMP16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CMP32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: CMP64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: CMP8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: CMP16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: CMP32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: CMP64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: CMP8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPBEXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpbexadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPBEXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPBEXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPBXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpbxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPBXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPBXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPLEXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmplexadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPLEXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPLEXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPLXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmplxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPLXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPLXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPNBEXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpnbexadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPNBEXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPNBEXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPNBXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpnbxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPNBXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPNBXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPNLEXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpnlexadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPNLEXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPNLEXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPNLXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpnlxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPNLXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPNLXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPNOXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpnoxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPNOXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPNOXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPNPXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpnpxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPNPXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPNPXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPNSXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpnsxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPNSXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPNSXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPNZXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpnzxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPNZXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPNZXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPOXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpoxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPOXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPOXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPPXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmppxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPPXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPPXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmps() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CMPS8, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CMPSXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpsxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPSXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPSXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPXCHG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpxchg(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: CMPXCHG8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: CMPXCHG8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMPXCHG16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CMPXCHG16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CMPXCHG32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: CMPXCHG32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: CMPXCHG64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: CMPXCHG64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPXCHG16BM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpxchg16bm(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: CMPXCHG16BM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPXCHG8BM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpxchg8bm(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: CMPXCHG8BM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPXCHGD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpxchgd(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: CMPXCHGD32M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPZXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpzxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPZXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPZXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CMPCCXADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cmpccxadd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: CMPCCXADD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: CMPCCXADD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CPUID` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cpuid() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CPUID, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CQO` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cqo() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CQO, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CRC32` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn crc32(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: CRC32_8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: CRC32_8RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: CRC32_16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: CRC32_32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp64() {
            return Ok(Self { opcode: CRC32_64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `CWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cwd() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CWD, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `CWDE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn cwde() -> Result<Self, AsmError> {
        return Ok(Self { opcode: CWDE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `C_EX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn c_ex() -> Result<Self, AsmError> {
        return Ok(Self { opcode: C_EX16, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `C_SEP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn c_sep() -> Result<Self, AsmError> {
        return Ok(Self { opcode: C_SEP16, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `DEC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn dec(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: DEC8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: DEC8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: DEC16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: DEC32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: DEC64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `DIV` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn div(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: DIV8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: DIV8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: DIV16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: DIV32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: DIV64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ENCLS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn encls() -> Result<Self, AsmError> {
        return Ok(Self { opcode: ENCLS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `ENCLU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn enclu() -> Result<Self, AsmError> {
        return Ok(Self { opcode: ENCLU, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `ENCLV` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn enclv() -> Result<Self, AsmError> {
        return Ok(Self { opcode: ENCLV, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `ENCODEKEY128` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn encodekey128(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: ENCODEKEY128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ENCODEKEY256` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn encodekey256(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: ENCODEKEY256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ENDBR32` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn endbr32() -> Result<Self, AsmError> {
        return Ok(Self { opcode: ENDBR32, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `ENDBR64` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn endbr64() -> Result<Self, AsmError> {
        return Ok(Self { opcode: ENDBR64, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `ENQCMD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn enqcmd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: ENQCMD32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: ENQCMD64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ENQCMDS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn enqcmds(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: ENQCMDS32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: ENQCMDS64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ENTER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn enter(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: ENTER16I, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ERETS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn erets() -> Result<Self, AsmError> {
        return Ok(Self { opcode: ERETS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `ERETU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn eretu() -> Result<Self, AsmError> {
        return Ok(Self { opcode: ERETU, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `F2XM1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn f2xm1() -> Result<Self, AsmError> {
        return Ok(Self { opcode: F2XM1, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FABS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fabs() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FABS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fadd_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FADDM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fadd_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FADDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FADDP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn faddp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FADDPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FBLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fbld(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FBLDM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FBSTP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fbstp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FBSTPM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCHS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fchs() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FCHS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FCLEX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fclex() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FCLEX, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FCMOVB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcmovb(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCMOVBR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCMOVBE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcmovbe(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCMOVBER, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCMOVE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcmove(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCMOVER, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCMOVNB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcmovnb(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCMOVNBR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCMOVNBE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcmovnbe(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCMOVNBER, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCMOVNE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcmovne(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCMOVNER, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCMOVNU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcmovnu(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCMOVNUR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCMOVU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcmovu(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCMOVUR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCOM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcom_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FCOMM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCOM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcom_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCOMRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCOMI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcomi(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCOMIR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCOMIP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcomip(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCOMIPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCOMP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcomp_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FCOMPM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCOMP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcomp_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FCOMPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FCOMPP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcompp() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FCOMPP, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FCOS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fcos() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FCOS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FDECSTP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fdecstp() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FDECSTP, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FDIV` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fdiv_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FDIVM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FDIV` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fdiv_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FDIVRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FDIVP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fdivp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FDIVPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FDIVR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fdivr_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FDIVRM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FDIVR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fdivr_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FDIVRRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FDIVRP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fdivrp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FDIVRPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FEMMS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn femms() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FEMMS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FFREE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ffree(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FFREER, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FIADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fiadd(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FIADDM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FICOM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ficom(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FICOMM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FICOMP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ficomp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FICOMPM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FIDIV` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fidiv(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FIDIVM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FIDIVR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fidivr(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FIDIVRM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FILD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fild(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FILDM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FIMUL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fimul(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FIMULM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FINCSTP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fincstp() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FINCSTP, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FINIT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn finit() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FINIT, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FIST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fist(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FISTM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FISTP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fistp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FISTPM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FISTTP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fisttp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FISTTPM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FISUB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fisub(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FISUBM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FISUBR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fisubr(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FISUBRM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fld(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FLDM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FLDR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FLD1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fld1() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FLD1, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FLDCW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fldcw(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FLDCWM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FLDENV` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fldenv(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FLDENVM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FLDL2E` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fldl2e() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FLDL2E, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FLDL2T` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fldl2t() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FLDL2T, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FLDLG2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fldlg2() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FLDLG2, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FLDLN2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fldln2() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FLDLN2, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FLDPI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fldpi() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FLDPI, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FLDZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fldz() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FLDZ, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FMUL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fmul_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FMULM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FMUL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fmul_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FMULRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FMULP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fmulp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FMULPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FNOP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fnop() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FNOP, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FPATAN` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fpatan() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FPATAN, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FPREM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fprem() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FPREM, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FPREM1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fprem1() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FPREM1, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FPTAN` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fptan() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FPTAN, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FRNDINT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn frndint() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FRNDINT, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FRSTOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn frstor(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FRSTORM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSAVE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fsave(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FSAVEM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSCALE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fscale() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FSCALE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FSIN` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fsin() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FSIN, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FSINCOS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fsincos() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FSINCOS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FSQRT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fsqrt() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FSQRT, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fst(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FSTM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FSTR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSTCW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fstcw(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FSTCWM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSTENV` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fstenv(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FSTENVM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSTP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fstp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FSTPM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FSTPR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSTSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fstsw(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FSTSWM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: FSTSWR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSUB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fsub_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FSUBM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSUB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fsub_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FSUBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSUBP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fsubp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FSUBPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSUBR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fsubr_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FSUBRM32, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSUBR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fsubr_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FSUBRRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FSUBRP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fsubrp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FSUBRPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FTST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ftst() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FTST, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FUCOM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fucom(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FUCOMR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FUCOMI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fucomi(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FUCOMIR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FUCOMIP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fucomip(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) && op1.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FUCOMIPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FUCOMP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fucomp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FUCOMPR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FUCOMPP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fucompp() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FUCOMPP, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FWAIT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fwait() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FWAIT, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FXAM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fxam() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FXAM, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FXCH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fxch(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86St) {
            return Ok(Self { opcode: FXCHR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FXRSTOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fxrstor(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FXRSTOR32M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FXSAVE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fxsave(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: FXSAVE32M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `FXTRACT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fxtract() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FXTRACT, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FYL2X` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fyl2x() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FYL2X, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `FYL2XP1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn fyl2xp1() -> Result<Self, AsmError> {
        return Ok(Self { opcode: FYL2XP1, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `GETSEC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn getsec() -> Result<Self, AsmError> {
        return Ok(Self { opcode: GETSEC, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `GF2P8AFFINEINVQB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn gf2p8affineinvqb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: GF2P8AFFINEINVQBRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: GF2P8AFFINEINVQBRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `GF2P8AFFINEQB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn gf2p8affineqb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: GF2P8AFFINEQBRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: GF2P8AFFINEQBRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `GF2P8MULB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn gf2p8mulb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: GF2P8MULBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: GF2P8MULBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `HLT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn hlt() -> Result<Self, AsmError> {
        return Ok(Self { opcode: HLT, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `HRESET` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn hreset(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: HRESETI, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `IDIV` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn idiv(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: IDIV8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: IDIV8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: IDIV16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: IDIV32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: IDIV64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `IMUL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn imul_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: IMUL8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: IMUL8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: IMUL16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: IMUL32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: IMUL64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `IMUL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn imul_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: IMUL16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: IMUL16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: IMUL32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: IMUL32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: IMUL64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: IMUL64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `IMUL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn imul_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) && op2.is_imm() {
            return Ok(Self { opcode: IMUL16RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: IMUL16RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() && op2.is_imm() {
            return Ok(Self { opcode: IMUL32RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: IMUL32RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_imm() {
            return Ok(Self { opcode: IMUL64RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: IMUL64RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `IN` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn in_instr() -> Result<Self, AsmError> {
        return Ok(Self { opcode: IN8, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `IN` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn in_instr_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: IN8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: IN16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: IN32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: IN64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `INC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn inc(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: INC8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: INC8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: INC16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: INC32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: INC64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `INCSSP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn incssp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: INCSSP32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: INCSSP64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `INS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ins() -> Result<Self, AsmError> {
        return Ok(Self { opcode: INS8, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `INT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn int(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: INTI, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `INT1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn int1() -> Result<Self, AsmError> {
        return Ok(Self { opcode: INT1, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `INT3` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn int3() -> Result<Self, AsmError> {
        return Ok(Self { opcode: INT3, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `INVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn invd() -> Result<Self, AsmError> {
        return Ok(Self { opcode: INVD, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `INVEPT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn invept(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: INVEPTRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `INVLPG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn invlpg(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: INVLPG8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `INVLPGA` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn invlpga() -> Result<Self, AsmError> {
        return Ok(Self { opcode: INVLPGA, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `INVLPGB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn invlpgb() -> Result<Self, AsmError> {
        return Ok(Self { opcode: INVLPGB, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `INVPCID` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn invpcid(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: INVPCIDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `INVVPID` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn invvpid(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: INVVPIDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `IRET` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn iret() -> Result<Self, AsmError> {
        return Ok(Self { opcode: IRET16, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `JA` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ja(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JA, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JA, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JA, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JBE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jbe(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JBE, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JBE, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JBE, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jc(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JC, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JC, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JC, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JCXZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jcxz(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JCXZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JCXZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JCXZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jg(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JG, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JG, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JG, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JGE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jge(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JGE, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JGE, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JGE, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jl(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JL, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JL, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JL, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JLE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jle(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JLE, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JLE, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JLE, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JMP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jmp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JMP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JMP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JMP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: JMPR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: JMPM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JMPF` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jmpf(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: JMPF16M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JNC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jnc(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JNC, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JNC, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JNC, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JNO` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jno(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JNO, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JNO, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JNO, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JNP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jnp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JNP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JNP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JNP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JNS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jns(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JNS, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JNS, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JNS, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JNZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jnz(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JNZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JNZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JNZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JO` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jo(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JO, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JO, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JO, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn js(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JS, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JS, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JS, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jz(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `JCC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn jcc(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: JCC, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: JCC, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: JCC, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KADDB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kaddb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KADDBKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KADDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kaddd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KADDDKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KADDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kaddq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KADDQKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KADDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kaddw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KADDWKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KANDB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kandb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KANDBKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KANDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kandd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KANDDKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KANDNB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kandnb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KANDNBKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KANDND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kandnd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KANDNDKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KANDNQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kandnq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KANDNQKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KANDNW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kandnw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KANDNWKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KANDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kandq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KANDQKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KANDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kandw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KANDWKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KMOVB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kmovb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KMOVBKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() {
            return Ok(Self { opcode: KMOVBKM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_mask() {
            return Ok(Self { opcode: KMOVBMK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_gp32() {
            return Ok(Self { opcode: KMOVBKR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mask() {
            return Ok(Self { opcode: KMOVBRK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KMOVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kmovd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KMOVDKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() {
            return Ok(Self { opcode: KMOVDKM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_mask() {
            return Ok(Self { opcode: KMOVDMK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_gp32() {
            return Ok(Self { opcode: KMOVDKR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mask() {
            return Ok(Self { opcode: KMOVDRK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KMOVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kmovq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KMOVQKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() {
            return Ok(Self { opcode: KMOVQKM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_mask() {
            return Ok(Self { opcode: KMOVQMK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_gp32() {
            return Ok(Self { opcode: KMOVQKR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mask() {
            return Ok(Self { opcode: KMOVQRK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KMOVW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kmovw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KMOVWKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() {
            return Ok(Self { opcode: KMOVWKM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_mask() {
            return Ok(Self { opcode: KMOVWMK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_gp32() {
            return Ok(Self { opcode: KMOVWKR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mask() {
            return Ok(Self { opcode: KMOVWRK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KNOTB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn knotb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KNOTBKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KNOTD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn knotd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KNOTDKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KNOTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn knotq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KNOTQKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KNOTW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn knotw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KNOTWKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KORB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn korb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KORBKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KORD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kord(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KORDKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KORQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn korq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KORQKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KORTESTB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kortestb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KORTESTBKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KORTESTD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kortestd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KORTESTDKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KORTESTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kortestq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KORTESTQKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KORTESTW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kortestw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KORTESTWKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KORW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn korw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KORWKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KSHIFTLB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kshiftlb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_imm() {
            return Ok(Self { opcode: KSHIFTLBKKI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KSHIFTLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kshiftld(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_imm() {
            return Ok(Self { opcode: KSHIFTLDKKI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KSHIFTLQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kshiftlq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_imm() {
            return Ok(Self { opcode: KSHIFTLQKKI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KSHIFTLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kshiftlw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_imm() {
            return Ok(Self { opcode: KSHIFTLWKKI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KSHIFTRB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kshiftrb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_imm() {
            return Ok(Self { opcode: KSHIFTRBKKI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KSHIFTRD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kshiftrd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_imm() {
            return Ok(Self { opcode: KSHIFTRDKKI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KSHIFTRQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kshiftrq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_imm() {
            return Ok(Self { opcode: KSHIFTRQKKI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KSHIFTRW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kshiftrw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_imm() {
            return Ok(Self { opcode: KSHIFTRWKKI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KTESTB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ktestb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KTESTBKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KTESTD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ktestd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KTESTDKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KTESTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ktestq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KTESTQKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KTESTW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ktestw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() {
            return Ok(Self { opcode: KTESTWKK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KUNPCKBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kunpckbw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KUNPCKBWKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KUNPCKDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kunpckdq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KUNPCKDQKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KUNPCKWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kunpckwd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KUNPCKWDKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KXNORB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kxnorb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KXNORBKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KXNORD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kxnord(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KXNORDKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KXNORQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kxnorq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KXNORQKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KXNORW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kxnorw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KXNORWKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KXORB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kxorb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KXORBKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KXORD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kxord(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KXORDKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KXORQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kxorq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KXORQKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `KXORW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn kxorw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_mask() && op2.is_mask() {
            return Ok(Self { opcode: KXORWKKK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LAHF` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lahf() -> Result<Self, AsmError> {
        return Ok(Self { opcode: LAHF, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `LAR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lar(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: LAR16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: LAR16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: LAR32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: LAR32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: LAR64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: LAR64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LDMXCSR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ldmxcsr(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: LDMXCSRM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LDTILECFG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ldtilecfg(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: LDTILECFGM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LEA` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lea(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: LEA16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: LEA32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: LEA64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LEAVE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn leave() -> Result<Self, AsmError> {
        return Ok(Self { opcode: LEAVE16, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `LFENCE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lfence() -> Result<Self, AsmError> {
        return Ok(Self { opcode: LFENCE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `LFS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lfs(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: LFS16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: LFS32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: LFS64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LGDT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lgdt(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: LGDTM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LGS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lgs(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: LGS16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: LGS32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: LGS64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LIDT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lidt(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: LIDTM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LKGS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lkgs(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: LKGSR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: LKGSM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LLDT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lldt(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: LLDTR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: LLDTM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LMSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lmsw(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: LMSWR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: LMSWM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LOADIWKEY` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn loadiwkey(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: LOADIWKEYRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LODS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lods() -> Result<Self, AsmError> {
        return Ok(Self { opcode: LODS8, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `LOOP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn loop_instr(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: LOOP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: LOOP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: LOOP, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LOOPNZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn loopnz(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: LOOPNZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: LOOPNZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: LOOPNZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LOOPZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn loopz(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: LOOPZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: LOOPZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: LOOPZ, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LSL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lsl(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: LSL16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: LSL16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: LSL32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: LSL32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: LSL64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: LSL64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: LSS16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: LSS32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: LSS64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LTR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ltr(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: LTRR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: LTRM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `LZCNT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn lzcnt(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: LZCNT16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: LZCNT16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: LZCNT32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: LZCNT32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: LZCNT64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: LZCNT64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MCOMMIT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mcommit() -> Result<Self, AsmError> {
        return Ok(Self { opcode: MCOMMIT, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `MFENCE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mfence() -> Result<Self, AsmError> {
        return Ok(Self { opcode: MFENCE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `MMX_CVTPD2PI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_cvtpd2pi(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_vec128() {
            return Ok(Self { opcode: MMX_CVTPD2PIRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_CVTPD2PIRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_CVTPI2PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_cvtpi2pd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_CVTPI2PDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: MMX_CVTPI2PDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_CVTPI2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_cvtpi2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_CVTPI2PSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: MMX_CVTPI2PSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_CVTPS2PI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_cvtps2pi(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_vec128() {
            return Ok(Self { opcode: MMX_CVTPS2PIRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_CVTPS2PIRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_CVTTPD2PI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_cvttpd2pi(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_vec128() {
            return Ok(Self { opcode: MMX_CVTTPD2PIRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_CVTTPD2PIRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_CVTTPS2PI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_cvttps2pi(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_vec128() {
            return Ok(Self { opcode: MMX_CVTTPS2PIRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_CVTTPS2PIRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_EMMS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_emms() -> Result<Self, AsmError> {
        return Ok(Self { opcode: MMX_EMMS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `MMX_MASKMOVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_maskmovq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_MASKMOVQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_MOVDQ2Q` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_movdq2q(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_vec128() {
            return Ok(Self { opcode: MMX_MOVDQ2QRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_MOVD_G2M` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_movd_g2m(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_gp32() {
            return Ok(Self { opcode: MMX_MOVD_G2MRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_MOVD_G2MRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_MOVD_M2G` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_movd_m2g(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_MOVD_M2GRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_MOVD_M2GMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_MOVNTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_movntq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_MOVNTQMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_MOVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_movq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_MOVQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_MOVQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_MOVQMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_MOVQ2DQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_movq2dq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_MOVQ2DQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_MOVQ_G2M` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_movq_g2m(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_gp32() {
            return Ok(Self { opcode: MMX_MOVQ_G2MRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_MOVQ_G2MRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_MOVQ_M2G` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_movq_m2g(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_MOVQ_M2GRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_MOVQ_M2GMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PABSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pabsb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PABSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PABSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PABSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pabsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PABSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PABSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PABSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pabsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PABSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PABSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PACKSSDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_packssdw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PACKSSDWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PACKSSDWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PACKSSWB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_packsswb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PACKSSWBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PACKSSWBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PACKUSWB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_packuswb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PACKUSWBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PACKUSWBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PADDB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_paddb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PADDBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PADDBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PADDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_paddd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PADDDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PADDDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PADDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_paddq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PADDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PADDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PADDSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_paddsb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PADDSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PADDSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PADDSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_paddsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PADDSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PADDSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PADDUSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_paddusb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PADDUSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PADDUSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PADDUSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_paddusw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PADDUSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PADDUSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PADDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_paddw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PADDWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PADDWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PALIGNR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_palignr(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) && op2.is_imm() {
            return Ok(Self { opcode: MMX_PALIGNRRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: MMX_PALIGNRRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PAND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pand(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PANDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PANDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PANDN` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pandn(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PANDNRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PANDNRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PAVGB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pavgb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PAVGBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PAVGBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PAVGW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pavgw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PAVGWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PAVGWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PCMPEQB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pcmpeqb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PCMPEQBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PCMPEQBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PCMPEQD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pcmpeqd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PCMPEQDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PCMPEQDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PCMPEQW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pcmpeqw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PCMPEQWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PCMPEQWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PCMPGTB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pcmpgtb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PCMPGTBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PCMPGTBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PCMPGTD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pcmpgtd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PCMPGTDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PCMPGTDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PCMPGTW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pcmpgtw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PCMPGTWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PCMPGTWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PEXTRW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pextrw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_reg_group_of(RegGroup::X86MM) && op2.is_imm() {
            return Ok(Self { opcode: MMX_PEXTRWRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PHADDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_phaddd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PHADDDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PHADDDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PHADDSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_phaddsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PHADDSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PHADDSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PHADDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_phaddw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PHADDWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PHADDWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PHSUBD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_phsubd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PHSUBDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PHSUBDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PHSUBSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_phsubsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PHSUBSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PHSUBSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PHSUBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_phsubw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PHSUBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PHSUBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PINSRW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pinsrw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_gp32() && op2.is_imm() {
            return Ok(Self { opcode: MMX_PINSRWRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: MMX_PINSRWRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMADDUBSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pmaddubsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMADDUBSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PMADDUBSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMADDWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pmaddwd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMADDWDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PMADDWDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMAXSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pmaxsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMAXSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PMAXSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMAXUB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pmaxub(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMAXUBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PMAXUBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMINSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pminsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMINSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PMINSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMINUB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pminub(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMINUBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PMINUBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMOVMSKB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pmovmskb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMOVMSKBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMULHRSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pmulhrsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMULHRSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PMULHRSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMULHUW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pmulhuw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMULHUWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PMULHUWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMULHW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pmulhw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMULHWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PMULHWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMULLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pmullw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMULLWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PMULLWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PMULUDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pmuludq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PMULUDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PMULUDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_POR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_por(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PORRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PORRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSADBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psadbw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSADBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSADBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSHUFB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pshufb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSHUFBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSHUFBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSHUFW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pshufw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) && op2.is_imm() {
            return Ok(Self { opcode: MMX_PSHUFWRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: MMX_PSHUFWRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSIGNB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psignb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSIGNBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSIGNBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSIGND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psignd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSIGNDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSIGNDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSIGNW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psignw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSIGNWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSIGNWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSLLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pslld(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_imm() {
            return Ok(Self { opcode: MMX_PSLLDRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSLLDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSLLDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSLLQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psllq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_imm() {
            return Ok(Self { opcode: MMX_PSLLQRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSLLQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSLLQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSLLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psllw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_imm() {
            return Ok(Self { opcode: MMX_PSLLWRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSLLWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSLLWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSRAD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psrad(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_imm() {
            return Ok(Self { opcode: MMX_PSRADRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSRADRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSRADRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSRAW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psraw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_imm() {
            return Ok(Self { opcode: MMX_PSRAWRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSRAWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSRAWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSRLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psrld(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_imm() {
            return Ok(Self { opcode: MMX_PSRLDRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSRLDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSRLDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSRLQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psrlq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_imm() {
            return Ok(Self { opcode: MMX_PSRLQRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSRLQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSRLQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSRLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psrlw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_imm() {
            return Ok(Self { opcode: MMX_PSRLWRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSRLWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSRLWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSUBB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psubb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSUBBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSUBBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSUBD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psubd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSUBDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSUBDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSUBQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psubq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSUBQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSUBQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSUBSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psubsb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSUBSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSUBSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSUBSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psubsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSUBSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSUBSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSUBUSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psubusb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSUBUSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSUBUSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSUBUSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psubusw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSUBUSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSUBUSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PSUBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_psubw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PSUBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PSUBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PUNPCKHBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_punpckhbw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PUNPCKHBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PUNPCKHBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PUNPCKHDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_punpckhdq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PUNPCKHDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PUNPCKHDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PUNPCKHWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_punpckhwd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PUNPCKHWDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PUNPCKHWDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PUNPCKLBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_punpcklbw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PUNPCKLBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PUNPCKLBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PUNPCKLDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_punpckldq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PUNPCKLDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PUNPCKLDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PUNPCKLWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_punpcklwd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PUNPCKLWDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PUNPCKLWDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MMX_PXOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mmx_pxor(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_reg_group_of(RegGroup::X86MM) {
            return Ok(Self { opcode: MMX_PXORRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86MM) && op1.is_mem() {
            return Ok(Self { opcode: MMX_PXORRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MONITOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn monitor() -> Result<Self, AsmError> {
        return Ok(Self { opcode: MONITOR, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `MONITORX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn monitorx() -> Result<Self, AsmError> {
        return Ok(Self { opcode: MONITORX, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `MOV` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mov(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: MOV8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: MOV8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: MOV16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: MOV16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: MOV32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: MOV32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: MOV64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: MOV64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_mem() {
            return Ok(Self { opcode: MOV8RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: MOV16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: MOV32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: MOV64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_mem() {
            return Ok(Self { opcode: MOV8RA, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: MOV16RA, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: MOV32RA, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: MOV64RA, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: MOV8AR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: MOV16AR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: MOV32AR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: MOV64AR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: MOV8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: MOV16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: MOV32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: MOV64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: MOV8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOVBE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn movbe(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: MOVBE16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: MOVBE32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: MOVBE64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: MOVBE16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: MOVBE32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: MOVBE64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOVDIR64B` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn movdir64b(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: MOVDIR64BRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOVDIRI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn movdiri(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: MOVDIRI32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: MOVDIRI64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOVNTI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn movnti(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: MOVNTI32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: MOVNTI64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOVS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn movs() -> Result<Self, AsmError> {
        return Ok(Self { opcode: MOVS8, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `MOVSX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn movsx(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_gp32() {
            return Ok(Self { opcode: MOVSXR16R32, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: MOVSXR16M32, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: MOVSXR32R32, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: MOVSXR32M32, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp32() {
            return Ok(Self { opcode: MOVSXR64R32, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: MOVSXR64M32, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: MOVSXR16R8, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: MOVSXR32R8, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: MOVSXR64R8, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: MOVSXR16R16, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: MOVSXR32R16, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: MOVSXR64R16, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOVZX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn movzx(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: MOVZXR16R8, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: MOVZXR16M8, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: MOVZXR32R8, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: MOVZXR32M8, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: MOVZXR64R8, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: MOVZXR64M8, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: MOVZXR16R16, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: MOVZXR32R16, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: MOVZXR64R16, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOV_CR2G` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mov_cr2g(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_reg_group_of(RegGroup::X86CReg) {
            return Ok(Self { opcode: MOV_CR2GRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOV_DR2G` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mov_dr2g(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_reg_group_of(RegGroup::X86DReg) {
            return Ok(Self { opcode: MOV_DR2GRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOV_G2CR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mov_g2cr(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86CReg) && op1.is_gp64() {
            return Ok(Self { opcode: MOV_G2CRRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOV_G2DR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mov_g2dr(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86DReg) && op1.is_gp64() {
            return Ok(Self { opcode: MOV_G2DRRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOV_G2S` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mov_g2s(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86SReg) && op1.is_gp32() {
            return Ok(Self { opcode: MOV_G2SRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_group_of(RegGroup::X86SReg) && op1.is_mem() {
            return Ok(Self { opcode: MOV_G2SRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MOV_S2G` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mov_s2g(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_reg_group_of(RegGroup::X86SReg) {
            return Ok(Self { opcode: MOV_S2GRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_group_of(RegGroup::X86SReg) {
            return Ok(Self { opcode: MOV_S2GMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MUL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mul(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: MUL8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: MUL8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: MUL16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: MUL32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: MUL64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MULX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mulx(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: MULX32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() && op2.is_mem() {
            return Ok(Self { opcode: MULX32RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: MULX64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_mem() {
            return Ok(Self { opcode: MULX64RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `MWAIT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mwait() -> Result<Self, AsmError> {
        return Ok(Self { opcode: MWAIT, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `MWAITX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn mwaitx() -> Result<Self, AsmError> {
        return Ok(Self { opcode: MWAITX, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `NEG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn neg(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: NEG8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: NEG8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: NEG16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: NEG32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: NEG64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `NOP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn nop() -> Result<Self, AsmError> {
        return Ok(Self { opcode: NOP, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `NOP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn nop_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: NOP16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: NOP16M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: NOP32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: NOP64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `NOT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn not(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: NOT8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: NOT8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: NOT16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: NOT32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: NOT64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `OR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn or(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: OR8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: OR8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: OR16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: OR16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: OR32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: OR32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: OR64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: OR64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_mem() {
            return Ok(Self { opcode: OR8RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: OR16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: OR32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: OR64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: OR8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: OR16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: OR32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: OR64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: OR8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `OUT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn out_instr() -> Result<Self, AsmError> {
        return Ok(Self { opcode: OUT8, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `OUT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn out_instr_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: OUT8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: OUT16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: OUT32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: OUT64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `OUTS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn outs() -> Result<Self, AsmError> {
        return Ok(Self { opcode: OUTS8, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `PAUSE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn pause() -> Result<Self, AsmError> {
        return Ok(Self { opcode: PAUSE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `PBNDKB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn pbndkb() -> Result<Self, AsmError> {
        return Ok(Self { opcode: PBNDKB, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `PCONFIG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn pconfig() -> Result<Self, AsmError> {
        return Ok(Self { opcode: PCONFIG, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `PDEP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn pdep(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: PDEP32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() && op2.is_mem() {
            return Ok(Self { opcode: PDEP32RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: PDEP64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_mem() {
            return Ok(Self { opcode: PDEP64RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PEXT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn pext(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: PEXT32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() && op2.is_mem() {
            return Ok(Self { opcode: PEXT32RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: PEXT64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_mem() {
            return Ok(Self { opcode: PEXT64RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `POP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn pop(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: POP16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: POPR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: POP16M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `POPCNT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn popcnt(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: POPCNT16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: POPCNT16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: POPCNT32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: POPCNT32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: POPCNT64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: POPCNT64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `POPF` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn popf() -> Result<Self, AsmError> {
        return Ok(Self { opcode: POPF16, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `POP_SEG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn pop_seg(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86SReg) {
            return Ok(Self { opcode: POP_SEG16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PREFETCH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn prefetch(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: PREFETCHM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PREFETCHIT0` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn prefetchit0(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: PREFETCHIT0M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PREFETCHIT1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn prefetchit1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: PREFETCHIT1M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PREFETCHNTA` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn prefetchnta(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: PREFETCHNTAM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PREFETCHT0` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn prefetcht0(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: PREFETCHT0M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PREFETCHT1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn prefetcht1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: PREFETCHT1M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PREFETCHT2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn prefetcht2(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: PREFETCHT2M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PREFETCHW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn prefetchw(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: PREFETCHWM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PREFETCHWT1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn prefetchwt1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: PREFETCHWT1M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PSMASH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn psmash() -> Result<Self, AsmError> {
        return Ok(Self { opcode: PSMASH, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `PTWRITE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ptwrite(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: PTWRITE32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: PTWRITE32M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: PTWRITE64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PUSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn push(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: PUSH16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: PUSHR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_imm() {
            return Ok(Self { opcode: PUSH16I, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: PUSH16M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PUSHF` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn pushf() -> Result<Self, AsmError> {
        return Ok(Self { opcode: PUSHF16, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `PUSH_SEG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn push_seg(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86SReg) {
            return Ok(Self { opcode: PUSH_SEG16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `PVALIDATE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn pvalidate() -> Result<Self, AsmError> {
        return Ok(Self { opcode: PVALIDATE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RCL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rcl(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: RCL8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: RCL8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: RCL16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: RCL32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: RCL64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: RCL8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: RCL8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: RCL16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: RCL32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: RCL64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RCR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rcr(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: RCR8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: RCR8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: RCR16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: RCR32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: RCR64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: RCR8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: RCR8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: RCR16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: RCR32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: RCR64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RDFSBASE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdfsbase(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: RDFSBASE32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: RDFSBASE64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RDGSBASE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdgsbase(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: RDGSBASE32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: RDGSBASE64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RDMSR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdmsr() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RDMSR, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RDMSR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdmsr_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: RDMSRRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RDMSRLIST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdmsrlist() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RDMSRLIST, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RDPID` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdpid(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() {
            return Ok(Self { opcode: RDPIDR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RDPKRU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdpkru() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RDPKRU, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RDPMC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdpmc() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RDPMC, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RDPRU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdpru() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RDPRU, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RDRAND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdrand(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: RDRAND16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: RDRAND32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: RDRAND64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RDSEED` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdseed(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: RDSEED16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: RDSEED32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: RDSEED64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RDSSP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdssp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: RDSSP32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: RDSSP64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RDTSC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdtsc() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RDTSC, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RDTSCP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rdtscp() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RDTSCP, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RET` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ret() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RET, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RET` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ret_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: RETI, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RETF` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn retf() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RETF16, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RETF` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn retf_1(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: RETF16I, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RMPADJUST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rmpadjust() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RMPADJUST, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RMPQUERY` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rmpquery() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RMPQUERY, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RMPREAD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rmpread() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RMPREAD, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RMPUPDATE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rmpupdate() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RMPUPDATE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `ROL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rol(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: ROL8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: ROL8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: ROL16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: ROL32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: ROL64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ROL8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ROL8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ROL16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ROL32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ROL64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `ROR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ror(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: ROR8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: ROR8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: ROR16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: ROR32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: ROR64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ROR8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ROR8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ROR16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ROR32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: ROR64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RORX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rorx(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() && op2.is_imm() {
            return Ok(Self { opcode: RORX32RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: RORX32RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_imm() {
            return Ok(Self { opcode: RORX64RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: RORX64RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `RSM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rsm() -> Result<Self, AsmError> {
        return Ok(Self { opcode: RSM, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `RSTORSSP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn rstorssp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: RSTORSSPM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SAHF` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sahf() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SAHF, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SAR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sar(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: SAR8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: SAR8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: SAR16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: SAR32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: SAR64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SAR8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SAR8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SAR16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SAR32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SAR64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SARX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sarx(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: SARX32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() && op2.is_gp32() {
            return Ok(Self { opcode: SARX32RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: SARX64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() && op2.is_gp64() {
            return Ok(Self { opcode: SARX64RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SAVEPREVSSP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn saveprevssp() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SAVEPREVSSP, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SBB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sbb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SBB8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SBB8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: SBB16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: SBB16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: SBB32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: SBB32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: SBB64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: SBB64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_mem() {
            return Ok(Self { opcode: SBB8RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: SBB16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: SBB32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: SBB64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: SBB8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: SBB16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: SBB32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: SBB64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: SBB8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SCAS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn scas() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SCAS8, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SEAMCALL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn seamcall() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SEAMCALL, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SEAMOPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn seamops() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SEAMOPS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SEAMRET` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn seamret() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SEAMRET, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SENDUIPI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn senduipi(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() {
            return Ok(Self { opcode: SENDUIPIR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SERIALIZE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn serialize() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SERIALIZE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SETA` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn seta(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETA8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETA8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETBE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setbe(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETBE8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETBE8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setc(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETC8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETC8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setg(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETG8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETG8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETGE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setge(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETGE8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETGE8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setl(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETL8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETL8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETLE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setle(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETLE8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETLE8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETNC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setnc(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETNC8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETNC8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETNO` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setno(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETNO8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETNO8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETNP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setnp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETNP8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETNP8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETNS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setns(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETNS8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETNS8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETNZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setnz(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETNZ8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETNZ8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETO` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn seto(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETO8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETO8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setp(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETP8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETP8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sets(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETS8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETS8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETSSBSY` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setssbsy() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SETSSBSY, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SETZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setz(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETZ8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETZ8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SETCC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn setcc(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SETCC8R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SETCC8M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SFENCE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sfence() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SFENCE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SGDT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sgdt(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: SGDTM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHA1MSG1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sha1msg1(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SHA1MSG1RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SHA1MSG1RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHA1MSG2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sha1msg2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SHA1MSG2RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SHA1MSG2RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHA1NEXTE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sha1nexte(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SHA1NEXTERR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SHA1NEXTERM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHA1RNDS4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sha1rnds4(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SHA1RNDS4RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SHA1RNDS4RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHA256MSG1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sha256msg1(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SHA256MSG1RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SHA256MSG1RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHA256MSG2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sha256msg2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SHA256MSG2RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SHA256MSG2RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHA256RNDS2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sha256rnds2(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: SHA256RNDS2RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_vec128() {
            return Ok(Self { opcode: SHA256RNDS2RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn shl(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: SHL8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: SHL8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: SHL16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: SHL32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: SHL64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHL8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHL8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHL16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHL32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHL64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn shld(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) && op2.is_imm() {
            return Ok(Self { opcode: SHLD16RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) && op2.is_imm() {
            return Ok(Self { opcode: SHLD16MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() && op2.is_imm() {
            return Ok(Self { opcode: SHLD32RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() && op2.is_imm() {
            return Ok(Self { opcode: SHLD32MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_imm() {
            return Ok(Self { opcode: SHLD64RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_imm() {
            return Ok(Self { opcode: SHLD64MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHLD16RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHLD16MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHLD32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHLD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHLD64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHLD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHLX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn shlx(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: SHLX32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() && op2.is_gp32() {
            return Ok(Self { opcode: SHLX32RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: SHLX64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() && op2.is_gp64() {
            return Ok(Self { opcode: SHLX64RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn shr(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: SHR8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: SHR8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: SHR16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: SHR32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: SHR64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHR8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHR8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHR16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHR32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHR64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHRD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn shrd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) && op2.is_imm() {
            return Ok(Self { opcode: SHRD16RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) && op2.is_imm() {
            return Ok(Self { opcode: SHRD16MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() && op2.is_imm() {
            return Ok(Self { opcode: SHRD32RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() && op2.is_imm() {
            return Ok(Self { opcode: SHRD32MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_imm() {
            return Ok(Self { opcode: SHRD64RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_imm() {
            return Ok(Self { opcode: SHRD64MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHRD16RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHRD16MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHRD32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHRD32MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHRD64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() && op2.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SHRD64MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SHRX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn shrx(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() && op2.is_gp32() {
            return Ok(Self { opcode: SHRX32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() && op2.is_gp32() {
            return Ok(Self { opcode: SHRX32RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() && op2.is_gp64() {
            return Ok(Self { opcode: SHRX64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() && op2.is_gp64() {
            return Ok(Self { opcode: SHRX64RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SIDT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sidt(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: SIDTM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SKINIT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn skinit() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SKINIT, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SLDT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sldt(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: SLDTR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: SLDTM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SMSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn smsw(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: SMSWM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: SMSW16R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() {
            return Ok(Self { opcode: SMSW32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: SMSW64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ADDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_addpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ADDPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ADDPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ADDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_addps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ADDPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ADDPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ADDSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_addsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ADDSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ADDSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ADDSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_addss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ADDSSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ADDSSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ADDSUBPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_addsubpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ADDSUBPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ADDSUBPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ADDSUBPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_addsubps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ADDSUBPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ADDSUBPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ANDNPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_andnpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ANDNPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ANDNPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ANDNPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_andnps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ANDNPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ANDNPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ANDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_andpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ANDPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ANDPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ANDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_andps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ANDPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ANDPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_BLENDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_blendpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_BLENDPDRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_BLENDPDRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_BLENDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_blendps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_BLENDPSRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_BLENDPSRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_BLENDVPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_blendvpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: SSE_BLENDVPDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_vec128() {
            return Ok(Self { opcode: SSE_BLENDVPDRMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_BLENDVPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_blendvps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: SSE_BLENDVPSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_vec128() {
            return Ok(Self { opcode: SSE_BLENDVPSRMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CMPPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cmppd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_CMPPDRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_CMPPDRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CMPPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cmpps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_CMPPSRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_CMPPSRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CMPSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cmpsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_CMPSDRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_CMPSDRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CMPSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cmpss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_CMPSSRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_CMPSSRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_COMISD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_comisd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_COMISDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_COMISDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_COMISS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_comiss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_COMISSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_COMISSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTDQ2PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtdq2pd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTDQ2PDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTDQ2PDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTDQ2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtdq2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTDQ2PSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTDQ2PSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTPD2DQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtpd2dq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTPD2DQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTPD2DQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTPD2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtpd2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTPD2PSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTPD2PSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTPS2DQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtps2dq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTPS2DQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTPS2DQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTPS2PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtps2pd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTPS2PDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTPS2PDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTSD2SI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtsd2si(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTSD2SI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTSD2SI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTSD2SI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTSD2SI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTSD2SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtsd2ss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTSD2SSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTSD2SSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTSI2SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtsi2sd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: SSE_CVTSI2SD32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTSI2SD32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_gp64() {
            return Ok(Self { opcode: SSE_CVTSI2SD64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTSI2SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtsi2ss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: SSE_CVTSI2SS32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTSI2SS32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_gp64() {
            return Ok(Self { opcode: SSE_CVTSI2SS64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTSS2SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtss2sd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTSS2SDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTSS2SDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTSS2SI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvtss2si(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTSS2SI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTSS2SI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTSS2SI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTSS2SI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTTPD2DQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvttpd2dq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTTPD2DQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTTPD2DQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTTPS2DQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvttps2dq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTTPS2DQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTTPS2DQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTTSD2SI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvttsd2si(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTTSD2SI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTTSD2SI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTTSD2SI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTTSD2SI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_CVTTSS2SI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_cvttss2si(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTTSS2SI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTTSS2SI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_CVTTSS2SI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: SSE_CVTTSS2SI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_DIVPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_divpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_DIVPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_DIVPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_DIVPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_divps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_DIVPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_DIVPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_DIVSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_divsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_DIVSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_DIVSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_DIVSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_divss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_DIVSSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_DIVSSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_DPPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_dppd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_DPPDRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_DPPDRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_DPPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_dpps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_DPPSRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_DPPSRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_EXTRACTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_extractps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_EXTRACTPSRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_EXTRACTPSMRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_EXTRQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_extrq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_imm() {
            return Ok(Self { opcode: SSE_EXTRQRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_EXTRQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_HADDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_haddpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_HADDPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_HADDPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_HADDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_haddps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_HADDPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_HADDPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_HSUBPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_hsubpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_HSUBPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_HSUBPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_HSUBPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_hsubps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_HSUBPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_HSUBPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_INSERTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_insertps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_INSERTPSRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_INSERTPSRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_INSERTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_insertq_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_INSERTQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_INSERTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_insertq_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_INSERTQRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_LDDQU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_lddqu(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_LDDQURM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MASKMOVDQU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_maskmovdqu(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MASKMOVDQURR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MAXPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_maxpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MAXPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MAXPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MAXPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_maxps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MAXPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MAXPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MAXSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_maxsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MAXSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MAXSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MAXSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_maxss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MAXSSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MAXSSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MINPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_minpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MINPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MINPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MINPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_minps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MINPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MINPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MINSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_minsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MINSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MINSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MINSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_minss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MINSSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MINSSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVAPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movapd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVAPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVAPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVAPDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVAPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movaps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVAPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVAPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVAPSMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVDDUP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movddup(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVDDUPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVDDUPRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVDQA` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movdqa(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVDQARR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVDQARM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVDQAMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVDQU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movdqu(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVDQURR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVDQURM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVDQUMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVD_G2X` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movd_g2x(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: SSE_MOVD_G2XRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVD_G2XRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVD_X2G` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movd_x2g(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVD_X2GRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVD_X2GMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVHLPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movhlps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVHLPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVHPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movhpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVHPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVHPDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVHPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movhps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVHPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVHPSMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVLHPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movlhps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVLHPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVLPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movlpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVLPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVLPDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVLPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movlps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVLPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVLPSMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVMSKPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movmskpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVMSKPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVMSKPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movmskps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVMSKPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVNTDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movntdq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVNTDQMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVNTDQA` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movntdqa(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVNTDQARM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVNTPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movntpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVNTPDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVNTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movntps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVNTPSMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVNTSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movntsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVNTSDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVNTSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movntss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVNTSSMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVQMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVQ_G2X` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movq_g2x(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: SSE_MOVQ_G2XRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVQ_G2XRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVQ_X2G` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movq_x2g(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVQ_X2GRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVQ_X2GMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVSDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVSHDUP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movshdup(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVSHDUPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVSHDUPRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVSLDUP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movsldup(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVSLDUPRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVSLDUPRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVSSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVSSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVSSMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVUPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movupd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVUPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVUPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVUPDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MOVUPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_movups(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVUPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MOVUPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MOVUPSMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MPSADBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_mpsadbw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_MPSADBWRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_MPSADBWRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MULPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_mulpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MULPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MULPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MULPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_mulps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MULPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MULPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MULSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_mulsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MULSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MULSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_MULSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_mulss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_MULSSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_MULSSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ORPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_orpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ORPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ORPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ORPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_orps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_ORPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_ORPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PABSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pabsb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PABSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PABSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PABSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pabsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PABSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PABSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PABSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pabsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PABSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PABSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PACKSSDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_packssdw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PACKSSDWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PACKSSDWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PACKSSWB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_packsswb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PACKSSWBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PACKSSWBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PACKUSDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_packusdw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PACKUSDWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PACKUSDWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PACKUSWB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_packuswb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PACKUSWBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PACKUSWBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PADDB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_paddb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PADDBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PADDBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PADDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_paddd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PADDDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PADDDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PADDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_paddq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PADDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PADDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PADDSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_paddsb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PADDSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PADDSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PADDSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_paddsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PADDSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PADDSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PADDUSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_paddusb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PADDUSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PADDUSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PADDUSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_paddusw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PADDUSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PADDUSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PADDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_paddw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PADDWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PADDWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PALIGNR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_palignr(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PALIGNRRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PALIGNRRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PAND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pand(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PANDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PANDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PANDN` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pandn(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PANDNRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PANDNRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PAVGB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pavgb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PAVGBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PAVGBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PAVGW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pavgw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PAVGWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PAVGWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PBLENDVB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pblendvb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PBLENDVBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PBLENDVBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PBLENDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pblendw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PBLENDWRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PBLENDWRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCLMULQDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pclmulqdq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PCLMULQDQRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PCLMULQDQRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPEQB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpeqb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PCMPEQBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PCMPEQBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPEQD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpeqd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PCMPEQDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PCMPEQDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPEQQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpeqq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PCMPEQQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PCMPEQQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPEQW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpeqw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PCMPEQWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PCMPEQWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPESTRI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpestri(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PCMPESTRIRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PCMPESTRIRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPESTRM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpestrm(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PCMPESTRMRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PCMPESTRMRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPGTB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpgtb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PCMPGTBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PCMPGTBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPGTD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpgtd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PCMPGTDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PCMPGTDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPGTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpgtq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PCMPGTQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PCMPGTQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPGTW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpgtw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PCMPGTWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PCMPGTWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPISTRI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpistri(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PCMPISTRIRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PCMPISTRIRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PCMPISTRM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pcmpistrm(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PCMPISTRMRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PCMPISTRMRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PEXTRB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pextrb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PEXTRBMRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PEXTRBRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PEXTRD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pextrd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PEXTRDRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PEXTRDMRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PEXTRQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pextrq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PEXTRQRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PEXTRQMRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PEXTRW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pextrw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PEXTRWRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PEXTRWMRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PHADDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_phaddd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PHADDDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PHADDDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PHADDSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_phaddsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PHADDSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PHADDSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PHADDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_phaddw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PHADDWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PHADDWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PHMINPOSUW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_phminposuw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PHMINPOSUWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PHMINPOSUWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PHSUBD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_phsubd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PHSUBDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PHSUBDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PHSUBSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_phsubsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PHSUBSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PHSUBSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PHSUBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_phsubw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PHSUBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PHSUBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PINSRB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pinsrb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PINSRBRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PINSRBRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PINSRD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pinsrd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PINSRDRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PINSRDRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PINSRQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pinsrq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PINSRQRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PINSRQRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PINSRW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pinsrw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PINSRWRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PINSRWRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMADDUBSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmaddubsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMADDUBSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMADDUBSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMADDWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmaddwd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMADDWDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMADDWDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMAXSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmaxsb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMAXSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMAXSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMAXSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmaxsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMAXSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMAXSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMAXSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmaxsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMAXSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMAXSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMAXUB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmaxub(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMAXUBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMAXUBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMAXUD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmaxud(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMAXUDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMAXUDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMAXUW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmaxuw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMAXUWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMAXUWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMINSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pminsb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMINSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMINSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMINSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pminsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMINSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMINSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMINSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pminsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMINSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMINSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMINUB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pminub(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMINUBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMINUBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMINUD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pminud(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMINUDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMINUDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMINUW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pminuw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMINUWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMINUWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVMSKB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovmskb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVMSKBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVSXBD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovsxbd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVSXBDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVSXBDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVSXBQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovsxbq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVSXBQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVSXBQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVSXBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovsxbw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVSXBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVSXBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVSXDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovsxdq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVSXDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVSXDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVSXWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovsxwd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVSXWDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVSXWDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVSXWQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovsxwq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVSXWQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVSXWQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVZXBD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovzxbd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVZXBDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVZXBDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVZXBQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovzxbq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVZXBQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVZXBQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVZXBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovzxbw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVZXBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVZXBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVZXDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovzxdq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVZXDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVZXDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVZXWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovzxwd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVZXWDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVZXWDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMOVZXWQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmovzxwq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMOVZXWQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMOVZXWQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMULDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmuldq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMULDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMULDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMULHRSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmulhrsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMULHRSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMULHRSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMULHUW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmulhuw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMULHUWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMULHUWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMULHW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmulhw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMULHWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMULHWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMULLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmulld(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMULLDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMULLDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMULLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmullw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMULLWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMULLWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PMULUDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pmuludq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PMULUDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PMULUDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_POR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_por(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PORRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PORRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSADBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psadbw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSADBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSADBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSHUFB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pshufb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSHUFBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSHUFBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSHUFD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pshufd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PSHUFDRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PSHUFDRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSHUFHW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pshufhw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PSHUFHWRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PSHUFHWRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSHUFLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pshuflw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PSHUFLWRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_PSHUFLWRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSIGNB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psignb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSIGNBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSIGNBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSIGND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psignd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSIGNDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSIGNDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSIGNW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psignw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSIGNWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSIGNWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSLLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pslld(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_imm() {
            return Ok(Self { opcode: SSE_PSLLDRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSLLDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSLLDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSLLDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pslldq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_imm() {
            return Ok(Self { opcode: SSE_PSLLDQRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSLLQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psllq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_imm() {
            return Ok(Self { opcode: SSE_PSLLQRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSLLQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSLLQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSLLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psllw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_imm() {
            return Ok(Self { opcode: SSE_PSLLWRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSLLWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSLLWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSRAD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psrad(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_imm() {
            return Ok(Self { opcode: SSE_PSRADRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSRADRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSRADRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSRAW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psraw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_imm() {
            return Ok(Self { opcode: SSE_PSRAWRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSRAWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSRAWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSRLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psrld(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_imm() {
            return Ok(Self { opcode: SSE_PSRLDRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSRLDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSRLDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSRLDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psrldq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_imm() {
            return Ok(Self { opcode: SSE_PSRLDQRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSRLQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psrlq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_imm() {
            return Ok(Self { opcode: SSE_PSRLQRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSRLQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSRLQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSRLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psrlw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_imm() {
            return Ok(Self { opcode: SSE_PSRLWRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSRLWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSRLWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSUBB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psubb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSUBBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSUBBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSUBD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psubd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSUBDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSUBDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSUBQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psubq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSUBQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSUBQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSUBSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psubsb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSUBSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSUBSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSUBSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psubsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSUBSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSUBSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSUBUSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psubusb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSUBUSBRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSUBUSBRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSUBUSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psubusw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSUBUSWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSUBUSWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PSUBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_psubw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PSUBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PSUBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PTEST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_ptest(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PTESTRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PTESTRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PUNPCKHBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_punpckhbw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PUNPCKHBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PUNPCKHBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PUNPCKHDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_punpckhdq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PUNPCKHDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PUNPCKHDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PUNPCKHQDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_punpckhqdq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PUNPCKHQDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PUNPCKHQDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PUNPCKHWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_punpckhwd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PUNPCKHWDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PUNPCKHWDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PUNPCKLBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_punpcklbw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PUNPCKLBWRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PUNPCKLBWRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PUNPCKLDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_punpckldq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PUNPCKLDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PUNPCKLDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PUNPCKLQDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_punpcklqdq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PUNPCKLQDQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PUNPCKLQDQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PUNPCKLWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_punpcklwd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PUNPCKLWDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PUNPCKLWDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_PXOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_pxor(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_PXORRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_PXORRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_RCPPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_rcpps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_RCPPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_RCPPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_RCPSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_rcpss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_RCPSSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_RCPSSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ROUNDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_roundpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_ROUNDPDRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_ROUNDPDRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ROUNDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_roundps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_ROUNDPSRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_ROUNDPSRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ROUNDSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_roundsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_ROUNDSDRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_ROUNDSDRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_ROUNDSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_roundss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_ROUNDSSRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_ROUNDSSRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_RSQRTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_rsqrtps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_RSQRTPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_RSQRTPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_RSQRTSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_rsqrtss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_RSQRTSSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_RSQRTSSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_SHUFPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_shufpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_SHUFPDRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_SHUFPDRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_SHUFPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_shufps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: SSE_SHUFPSRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: SSE_SHUFPSRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_SQRTPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_sqrtpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_SQRTPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_SQRTPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_SQRTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_sqrtps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_SQRTPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_SQRTPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_SQRTSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_sqrtsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_SQRTSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_SQRTSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_SQRTSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_sqrtss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_SQRTSSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_SQRTSSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_SUBPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_subpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_SUBPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_SUBPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_SUBPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_subps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_SUBPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_SUBPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_SUBSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_subsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_SUBSDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_SUBSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_SUBSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_subss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_SUBSSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_SUBSSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_UCOMISD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_ucomisd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_UCOMISDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_UCOMISDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_UCOMISS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_ucomiss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_UCOMISSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_UCOMISSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_UNPCKHPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_unpckhpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_UNPCKHPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_UNPCKHPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_UNPCKHPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_unpckhps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_UNPCKHPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_UNPCKHPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_UNPCKLPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_unpcklpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_UNPCKLPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_UNPCKLPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_UNPCKLPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_unpcklps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_UNPCKLPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_UNPCKLPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_XORPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_xorpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_XORPDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_XORPDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SSE_XORPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sse_xorps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: SSE_XORPSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: SSE_XORPSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `STAC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn stac() -> Result<Self, AsmError> {
        return Ok(Self { opcode: STAC, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `STC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn stc() -> Result<Self, AsmError> {
        return Ok(Self { opcode: STC, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `STD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn std() -> Result<Self, AsmError> {
        return Ok(Self { opcode: STD, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `STGI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn stgi() -> Result<Self, AsmError> {
        return Ok(Self { opcode: STGI, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `STI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sti() -> Result<Self, AsmError> {
        return Ok(Self { opcode: STI, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `STMXCSR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn stmxcsr(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: STMXCSRM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `STOS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn stos() -> Result<Self, AsmError> {
        return Ok(Self { opcode: STOS8, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `STR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn str(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: STRR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: STRM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `STTILECFG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sttilecfg(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: STTILECFGM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `STUI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn stui() -> Result<Self, AsmError> {
        return Ok(Self { opcode: STUI, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SUB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sub(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SUB8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: SUB8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: SUB16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: SUB16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: SUB32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: SUB32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: SUB64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: SUB64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_mem() {
            return Ok(Self { opcode: SUB8RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: SUB16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: SUB32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: SUB64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: SUB8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: SUB16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: SUB32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: SUB64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: SUB8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `SWAPGS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn swapgs() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SWAPGS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SYSCALL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn syscall() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SYSCALL, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SYSENTER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sysenter() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SYSENTER, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SYSEXIT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sysexit() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SYSEXIT, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `SYSRET` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn sysret() -> Result<Self, AsmError> {
        return Ok(Self { opcode: SYSRET, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `TCMMIMFP16PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tcmmimfp16ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86Tmm) && op1.is_reg_group_of(RegGroup::X86Tmm) && op2.is_reg_group_of(RegGroup::X86Tmm) {
            return Ok(Self { opcode: TCMMIMFP16PSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TCMMRLFP16PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tcmmrlfp16ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86Tmm) && op1.is_reg_group_of(RegGroup::X86Tmm) && op2.is_reg_group_of(RegGroup::X86Tmm) {
            return Ok(Self { opcode: TCMMRLFP16PSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TDCALL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tdcall() -> Result<Self, AsmError> {
        return Ok(Self { opcode: TDCALL, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `TDPBF16PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tdpbf16ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86Tmm) && op1.is_reg_group_of(RegGroup::X86Tmm) && op2.is_reg_group_of(RegGroup::X86Tmm) {
            return Ok(Self { opcode: TDPBF16PSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TDPBSSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tdpbssd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86Tmm) && op1.is_reg_group_of(RegGroup::X86Tmm) && op2.is_reg_group_of(RegGroup::X86Tmm) {
            return Ok(Self { opcode: TDPBSSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TDPBSUD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tdpbsud(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86Tmm) && op1.is_reg_group_of(RegGroup::X86Tmm) && op2.is_reg_group_of(RegGroup::X86Tmm) {
            return Ok(Self { opcode: TDPBSUDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TDPBUSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tdpbusd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86Tmm) && op1.is_reg_group_of(RegGroup::X86Tmm) && op2.is_reg_group_of(RegGroup::X86Tmm) {
            return Ok(Self { opcode: TDPBUSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TDPBUUD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tdpbuud(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86Tmm) && op1.is_reg_group_of(RegGroup::X86Tmm) && op2.is_reg_group_of(RegGroup::X86Tmm) {
            return Ok(Self { opcode: TDPBUUDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TDPFP16PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tdpfp16ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86Tmm) && op1.is_reg_group_of(RegGroup::X86Tmm) && op2.is_reg_group_of(RegGroup::X86Tmm) {
            return Ok(Self { opcode: TDPFP16PSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TEST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn test(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: TEST8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: TEST8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: TEST16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: TEST16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: TEST32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: TEST32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: TEST64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: TEST64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: TEST8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: TEST16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: TEST32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: TEST64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: TEST8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TESTUI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn testui() -> Result<Self, AsmError> {
        return Ok(Self { opcode: TESTUI, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `TILELOADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tileloadd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86Tmm) && op1.is_mem() {
            return Ok(Self { opcode: TILELOADDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TILELOADDT1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tileloaddt1(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86Tmm) && op1.is_mem() {
            return Ok(Self { opcode: TILELOADDT1RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TILERELEASE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tilerelease() -> Result<Self, AsmError> {
        return Ok(Self { opcode: TILERELEASE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `TILESTORED` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tilestored(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_reg_group_of(RegGroup::X86Tmm) {
            return Ok(Self { opcode: TILESTOREDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TILEZERO` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tilezero(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_group_of(RegGroup::X86Tmm) {
            return Ok(Self { opcode: TILEZEROR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TLBSYNC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tlbsync() -> Result<Self, AsmError> {
        return Ok(Self { opcode: TLBSYNC, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `TPAUSE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tpause(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: TPAUSER, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `TZCNT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn tzcnt(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: TZCNT16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: TZCNT16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: TZCNT32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: TZCNT32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: TZCNT64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: TZCNT64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `UD0` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ud0(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: UD0_16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: UD0_16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: UD0_32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: UD0_32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: UD0_64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: UD0_64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `UD1` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ud1(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: UD1_16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: UD1_16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: UD1_32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: UD1_32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: UD1_64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: UD1_64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `UD2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn ud2() -> Result<Self, AsmError> {
        return Ok(Self { opcode: UD2, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `UIRET` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn uiret() -> Result<Self, AsmError> {
        return Ok(Self { opcode: UIRET, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `UMONITOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn umonitor(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: UMONITOR32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: UMONITOR64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `UMWAIT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn umwait(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: UMWAITR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `URDMSR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn urdmsr(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: URDMSRRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: URDMSRRI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `UWRMSR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn uwrmsr(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: UWRMSRRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_imm() && op1.is_gp32() {
            return Ok(Self { opcode: UWRMSRIR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VADDPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VADDPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VADDPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddpd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VADDPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VADDPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VADDPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddpd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VADDPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VADDPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VADDPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddpd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDPH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDPH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VADDPH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VADDPH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VADDPH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDPH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDPH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VADDPH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VADDPH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VADDPH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDPH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDPH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VADDPH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VADDPH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VADDPH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VADDPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VADDPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VADDPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VADDPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VADDPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VADDPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VADDPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VADDPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VADDPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDPS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VADDPS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDSDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDSDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDSDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDSSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDSSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDSSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSUBPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsubpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSUBPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDSUBPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VADDSUBPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VADDSUBPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VADDSUBPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaddsubps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VADDSUBPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VADDSUBPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VADDSUBPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VADDSUBPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VAESDEC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaesdec(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VAESDEC128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VAESDEC128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VAESDEC256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VAESDEC256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VAESDEC512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VAESDEC512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VAESDECLAST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaesdeclast(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VAESDECLAST128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VAESDECLAST128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VAESDECLAST256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VAESDECLAST256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VAESDECLAST512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VAESDECLAST512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VAESENC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaesenc(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VAESENC128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VAESENC128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VAESENC256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VAESENC256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VAESENC512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VAESENC512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VAESENCLAST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaesenclast(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VAESENCLAST128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VAESENCLAST128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VAESENCLAST256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VAESENCLAST256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VAESENCLAST512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VAESENCLAST512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VAESIMC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaesimc(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VAESIMCRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VAESIMCRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VAESKEYGENASSIST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vaeskeygenassist(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VAESKEYGENASSISTRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VAESKEYGENASSISTRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VALIGND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn valignd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VALIGND_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn valignd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VALIGND_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn valignd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGND512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VALIGNQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn valignq(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VALIGNQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn valignq_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VALIGNQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn valignq_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VALIGNQ512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDNPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandnpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDNPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDNPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDNPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDNPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandnpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDNPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDNPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDNPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDNPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandnpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDNPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDNPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDNPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDNPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandnps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDNPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDNPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDNPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDNPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandnps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDNPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDNPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDNPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDNPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandnps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDNPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDNPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDNPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDNPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VANDPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vandps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VANDPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VANDPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VANDPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VANDPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VANDPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VANDPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBCSTNEBF162PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbcstnebf162ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VBCSTNEBF162PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBCSTNEBF162PS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBCSTNESH2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbcstnesh2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VBCSTNESH2PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBCSTNESH2PS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBLENDMPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vblendmpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VBLENDMPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VBLENDMPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VBLENDMPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBLENDMPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vblendmpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VBLENDMPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VBLENDMPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VBLENDMPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBLENDMPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vblendmpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VBLENDMPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VBLENDMPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VBLENDMPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBLENDMPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vblendmps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VBLENDMPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VBLENDMPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VBLENDMPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBLENDMPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vblendmps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VBLENDMPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VBLENDMPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VBLENDMPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBLENDMPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vblendmps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VBLENDMPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VBLENDMPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VBLENDMPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VBLENDMPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBLENDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vblendpd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VBLENDPD128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VBLENDPD128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VBLENDPD256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VBLENDPD256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBLENDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vblendps(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VBLENDPS128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VBLENDPS128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VBLENDPS256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VBLENDPS256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBLENDVPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vblendvpd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_vec128() {
            return Ok(Self { opcode: VBLENDVPD128RRRR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_vec128() {
            return Ok(Self { opcode: VBLENDVPD128RRMR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_vec256() {
            return Ok(Self { opcode: VBLENDVPD256RRRR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_vec256() {
            return Ok(Self { opcode: VBLENDVPD256RRMR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBLENDVPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vblendvps(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_vec128() {
            return Ok(Self { opcode: VBLENDVPS128RRRR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_vec128() {
            return Ok(Self { opcode: VBLENDVPS128RRMR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_vec256() {
            return Ok(Self { opcode: VBLENDVPS256RRRR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_vec256() {
            return Ok(Self { opcode: VBLENDVPS256RRMR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF128` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf128(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTF128_256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF128_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF32X2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf32x2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTF32X2_256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X2_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTF32X2_512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X2_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF32X2_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf32x2_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTF32X2_256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X2_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTF32X2_512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X2_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF32X2_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf32x2_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTF32X2_256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X2_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTF32X2_512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X2_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF32X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf32x4(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X4_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X4_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF32X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf32x4_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X4_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X4_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF32X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf32x4_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X4_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X4_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF32X8` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf32x8(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X8_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF32X8_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf32x8_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X8_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF32X8_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf32x8_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF32X8_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF64X2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf64x2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF64X2_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF64X2_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF64X2_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf64x2_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF64X2_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF64X2_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF64X2_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf64x2_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF64X2_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF64X2_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF64X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf64x4(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF64X4_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF64X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf64x4_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF64X4_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTF64X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastf64x4_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTF64X4_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI128` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti128(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI32X2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti32x2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTI32X2_128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X2_128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTI32X2_256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X2_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTI32X2_512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X2_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI32X2_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti32x2_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTI32X2_128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X2_128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTI32X2_256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X2_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTI32X2_512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X2_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI32X2_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti32x2_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTI32X2_128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X2_128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTI32X2_256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X2_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTI32X2_512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X2_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI32X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti32x4(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X4_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X4_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI32X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti32x4_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X4_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X4_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI32X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti32x4_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X4_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X4_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI32X8` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti32x8(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X8_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI32X8_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti32x8_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X8_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI32X8_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti32x8_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI32X8_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI64X2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti64x2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI64X2_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI64X2_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI64X2_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti64x2_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI64X2_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI64X2_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI64X2_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti64x2_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI64X2_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI64X2_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI64X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti64x4(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI64X4_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI64X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti64x4_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI64X4_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTI64X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcasti64x4_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTI64X4_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastsd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastsd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastss_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSS256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VBROADCASTSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vbroadcastss_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSS256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VBROADCASTSS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VBROADCASTSS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmppd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD128KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD128KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD256KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD256KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD512KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD512KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmppd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD128KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD128KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD256KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD256KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD512KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD512KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmppd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD512KRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmppd_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPD512KRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpph(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH128KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH128KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH256KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH256KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH512KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH512KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpph_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH128KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH128KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH256KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH256KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH512KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH512KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpph_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH512KRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpph_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPH512KRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpps(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS128KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS128KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS256KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS256KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS512KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS512KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpps_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS128KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS128KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS256KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS256KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS512KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS512KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpps_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS512KRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPPS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpps_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VCMPPS512KRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpsd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSDRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSDRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSDKRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSDKRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpsd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSDKRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSDKRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpsd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSDKRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpsd_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSDKRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpsh(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSHKRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSHKRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpsh_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSHKRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSHKRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpsh_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSHKRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpsh_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSHKRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpss(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSSRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSSRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSSKRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSSKRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpss_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSSKRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSSKRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpss_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSSKRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCMPSS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcmpss_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VCMPSSKRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMISD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcomisd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMISDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCOMISDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMISD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcomisd_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMISDRR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMISH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcomish(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMISHRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCOMISHRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMISH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcomish_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMISHRR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMISS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcomiss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMISSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCOMISSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMISS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcomiss_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMISSRR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMPRESSPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcompresspd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMPRESSPD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VCOMPRESSPD256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VCOMPRESSPD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMPRESSPD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCOMPRESSPD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCOMPRESSPD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMPRESSPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcompresspd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMPRESSPD128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VCOMPRESSPD256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VCOMPRESSPD512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMPRESSPD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCOMPRESSPD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCOMPRESSPD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMPRESSPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcompresspd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMPRESSPD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCOMPRESSPD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCOMPRESSPD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMPRESSPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcompressps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMPRESSPS128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VCOMPRESSPS256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VCOMPRESSPS512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMPRESSPS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCOMPRESSPS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCOMPRESSPS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMPRESSPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcompressps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMPRESSPS128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VCOMPRESSPS256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VCOMPRESSPS512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMPRESSPS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCOMPRESSPS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCOMPRESSPS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCOMPRESSPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcompressps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCOMPRESSPS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCOMPRESSPS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCOMPRESSPS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2pd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2pd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2pd_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PD512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2pd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2pd_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PD512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2pd_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PD512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ph(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PH128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PH128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PH256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PH512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PH512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ph_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PH512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ph_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PH128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PH128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PH256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PH512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PH512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ph_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PH512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ph_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PH128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PH128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PH256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PH512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PH512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ph_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PH512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ps_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PS512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PS256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ps_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PS512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTDQ2PS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTDQ2PS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PS256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTDQ2PS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTDQ2PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtdq2ps_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTDQ2PS512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTNE2PS2BF16` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtne2ps2bf16(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTNE2PS2BF16_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtne2ps2bf16_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTNE2PS2BF16_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtne2ps2bf16_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VCVTNE2PS2BF16_512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTNEEBF162PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtneebf162ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEEBF162PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEEBF162PS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTNEEPH2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtneeph2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEEPH2PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEEPH2PS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTNEOBF162PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtneobf162ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEOBF162PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEOBF162PS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTNEOPH2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtneoph2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEOPH2PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEOPH2PS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTNEPS2BF16` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtneps2bf16(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTNEPS2BF16_128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEPS2BF16_128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTNEPS2BF16_256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTNEPS2BF16_512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEPS2BF16_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTNEPS2BF16_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtneps2bf16_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTNEPS2BF16_128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEPS2BF16_128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTNEPS2BF16_256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTNEPS2BF16_512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEPS2BF16_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTNEPS2BF16_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtneps2bf16_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTNEPS2BF16_128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEPS2BF16_128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTNEPS2BF16_256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTNEPS2BF16_512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTNEPS2BF16_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2DQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2dq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2DQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2DQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2DQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2DQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2DQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2DQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2dq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2DQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2DQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2dq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2DQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2DQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2DQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2DQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2DQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2DQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2dq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2DQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2DQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2dq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2DQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2DQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2DQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2DQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2DQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2DQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2dq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2DQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ph(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2PH128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2PH128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2PH256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PH512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ph_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PH512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ph_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2PH128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2PH128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2PH256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PH512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ph_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PH512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ph_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2PH128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2PH128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2PH256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PH512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ph_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PH512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2PS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2PS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2PS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ps_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PS512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2PS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2PS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2PS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2PS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ps_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PS512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2PS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2PS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2PS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2PS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2ps_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2PS512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2QQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2qq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2QQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2QQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2QQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2QQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2QQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2QQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2QQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2qq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2QQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2QQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2qq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2QQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2QQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2QQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2QQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2QQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2QQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2QQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2qq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2QQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2QQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2qq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2QQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2QQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2QQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2QQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2QQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2QQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2QQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2qq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2QQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2udq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2UDQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UDQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2UDQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UDQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UDQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UDQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2udq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UDQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2udq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2UDQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UDQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2UDQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UDQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UDQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UDQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2udq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UDQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2udq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2UDQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UDQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2UDQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UDQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UDQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UDQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2udq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UDQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UQQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2uqq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2UQQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UQQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2UQQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UQQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UQQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UQQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UQQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2uqq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UQQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UQQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2uqq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2UQQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UQQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2UQQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UQQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UQQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UQQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UQQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2uqq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UQQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UQQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2uqq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPD2UQQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UQQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPD2UQQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UQQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UQQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPD2UQQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPD2UQQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtpd2uqq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPD2UQQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2DQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2dq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2DQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2DQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2DQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2DQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2DQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2DQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2DQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2dq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2DQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2DQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2dq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2DQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2DQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2DQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2DQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2DQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2DQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2DQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2dq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2DQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2DQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2dq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2DQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2DQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2DQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2DQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2DQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2DQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2DQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2dq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2DQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2pd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2pd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2pd_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2pd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2pd_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2pd_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PD512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PSX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2psx(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PSX128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PSX128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PSX256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PSX256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PSX512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PSX512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PSX_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2psx_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PSX128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PSX128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PSX256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PSX256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PSX512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PSX512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PSX_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2psx_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PSX512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PSX_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2psx_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PSX128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PSX128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PSX256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PSX256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PSX512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PSX512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PSX_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2psx_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PSX512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PSX_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2psx_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PSX512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2ps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PS256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2ps_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PS512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2ps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2PS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PS256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2PS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2ps_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PS512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2PS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2ps_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2PS512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2QQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2qq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2QQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2QQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2QQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2QQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2qq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2QQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2qq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2QQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2QQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2QQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2QQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2qq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2QQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2qq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2QQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2QQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2QQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2QQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2qq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2QQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2udq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UDQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UDQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UDQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UDQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2UDQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UDQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UDQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2udq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2UDQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2udq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UDQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UDQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UDQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UDQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2UDQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UDQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UDQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2udq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2UDQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2udq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UDQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UDQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UDQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UDQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2UDQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UDQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UDQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2udq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2UDQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UQQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uqq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UQQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UQQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UQQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UQQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uqq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UQQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uqq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UQQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UQQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UQQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UQQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uqq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UQQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uqq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UQQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UQQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UQQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UQQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uqq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UQQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UW128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2UW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UW256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2UW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UW512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UW_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uw_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2UW512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UW128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2UW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UW256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2UW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UW512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UW_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uw_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2UW512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2UW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UW128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2UW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UW256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2UW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2UW512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2UW_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2uw_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2UW512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2W` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2w(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2W128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2W128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2W256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2W256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2W512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2W512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2W_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2w_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2W512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2W_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2w_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2W128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2W128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2W256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2W256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2W512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2W512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2W_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2w_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2W512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2W_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2w_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPH2W128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2W128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPH2W256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2W256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2W512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPH2W512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPH2W_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtph2w_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPH2W512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2DQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2dq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2DQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2DQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2DQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2DQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2DQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2DQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2DQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2dq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2DQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2DQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2dq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2DQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2DQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2DQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2DQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2DQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2DQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2DQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2dq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2DQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2DQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2dq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2DQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2DQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2DQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2DQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2DQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2DQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2DQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2dq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2DQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2pd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2PD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2PD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2PD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2pd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2PD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2PD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2PD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2pd_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2PD512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2pd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2PD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2PD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2PD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2pd_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2PD512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2pd_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2PD512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH128MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH256MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH512MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PHX` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2phx(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2PHX128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PHX128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2PHX256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2PHX512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PHX512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PHX_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2phx_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2PHX512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PHX_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2phx_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2PHX128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PHX128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2PHX256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2PHX512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PHX512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PHX_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2phx_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2PHX512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PHX_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2phx_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2PHX128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PHX128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2PHX256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2PHX512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2PHX512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PHX_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2phx_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2PHX512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH128MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH256MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH512MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2ph_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH512RRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2ph_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH512RRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2PH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2ph_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VCVTPS2PH512RRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2QQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2qq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2QQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2QQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2QQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2QQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2QQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2QQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2QQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2qq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2QQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2QQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2qq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2QQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2QQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2QQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2QQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2QQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2QQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2QQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2qq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2QQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2QQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2qq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2QQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2QQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2QQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2QQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2QQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2QQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2QQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2qq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2QQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2udq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2UDQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UDQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2UDQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UDQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2UDQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UDQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UDQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2udq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2UDQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2udq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2UDQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UDQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2UDQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UDQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2UDQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UDQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UDQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2udq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2UDQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2udq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2UDQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UDQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2UDQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UDQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2UDQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UDQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UDQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2udq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTPS2UDQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UQQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2uqq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2UQQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UQQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2UQQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UQQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2UQQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UQQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UQQ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2uqq_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2UQQ512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UQQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2uqq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2UQQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UQQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2UQQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UQQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2UQQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UQQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UQQ_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2uqq_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2UQQ512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UQQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2uqq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2UQQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UQQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTPS2UQQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UQQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2UQQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTPS2UQQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTPS2UQQ_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtps2uqq_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTPS2UQQ512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2pd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTQQ2PD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTQQ2PD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2pd_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PD512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2pd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTQQ2PD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTQQ2PD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2pd_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PD512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2pd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTQQ2PD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTQQ2PD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2pd_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PD512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ph(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTQQ2PH128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PH128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTQQ2PH256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PH512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ph_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PH512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ph_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTQQ2PH128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PH128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTQQ2PH256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PH512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ph_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PH512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ph_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTQQ2PH128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PH128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTQQ2PH256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PH512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ph_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PH512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTQQ2PS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTQQ2PS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ps_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PS512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTQQ2PS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTQQ2PS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ps_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PS512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTQQ2PS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTQQ2PS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTQQ2PS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTQQ2PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtqq2ps_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTQQ2PS512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSD2SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSD2SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSD2SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2si(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSD2SI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSD2SI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SI_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2si_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SI32RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SI64RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSD2SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSD2SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSD2SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSD2SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2USI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2usi(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSD2USI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSD2USI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSD2USI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSD2USI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSD2USI_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsd2usi_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSD2USI32RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSD2USI64RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSH2SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSH2SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2sd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SDRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSH2SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2sd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SDRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2sd_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SDRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2si(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSH2SI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSH2SI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SI_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2si_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SI32RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SI64RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSH2SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSH2SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2ss_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SSRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSH2SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2ss_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SSRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2SS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2ss_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSH2SSRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2USI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2usi(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSH2USI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSH2USI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSH2USI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSH2USI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSH2USI_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsh2usi_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSH2USI32RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSH2USI64RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSI2SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsi2sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTSI2SD32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSI2SD32RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTSI2SD64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSI2SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsi2sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTSI2SD32RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTSI2SD64RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSI2SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsi2sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTSI2SH32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSI2SH32RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTSI2SH64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSI2SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsi2sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTSI2SH32RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTSI2SH64RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSI2SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsi2ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTSI2SS32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSI2SS32RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTSI2SS64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSI2SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtsi2ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTSI2SS32RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTSI2SS64RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSS2SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSS2SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SDRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSS2SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SDRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sd_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SDRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSS2SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSS2SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTSS2SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2si(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSS2SI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSS2SI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2SI_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2si_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SI32RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSS2SI64RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2USI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2usi(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSS2USI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSS2USI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSS2USI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTSS2USI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTSS2USI_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtss2usi_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSS2USI32RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTSS2USI64RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2DQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2dq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2DQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2DQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2DQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2DQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2DQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2DQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2dq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2DQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2DQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2DQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2DQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2DQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2DQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2dq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2DQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2DQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2dq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2DQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2DQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2DQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2DQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2DQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2DQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2dq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2DQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2DQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2dq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2DQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2QQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2qq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2QQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2QQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2QQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2QQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2QQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2QQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2QQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2qq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2QQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2QQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2QQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2QQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2QQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2QQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2QQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2qq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2QQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2QQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2qq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2QQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2QQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2QQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2QQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2QQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2QQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2QQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2qq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2QQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2QQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2qq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2QQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2udq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2UDQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UDQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2UDQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UDQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UDQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2udq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2UDQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UDQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2UDQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UDQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UDQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UDQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2udq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UDQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2udq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2UDQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UDQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2UDQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UDQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UDQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UDQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2udq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UDQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UDQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2udq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UDQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UQQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2uqq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2UQQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UQQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2UQQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UQQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UQQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UQQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UQQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2uqq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2UQQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UQQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2UQQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UQQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UQQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UQQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UQQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2uqq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UQQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UQQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2uqq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPD2UQQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UQQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPD2UQQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UQQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UQQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPD2UQQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UQQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2uqq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UQQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPD2UQQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttpd2uqq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPD2UQQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2DQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2dq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2DQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2DQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2DQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2DQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2DQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2DQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2DQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2dq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2DQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2DQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2DQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2DQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2DQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2DQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2DQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2dq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2DQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2DQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2dq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2DQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2DQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2DQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2DQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2DQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2DQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2DQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2dq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2DQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2DQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2dq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2DQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2QQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2qq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2QQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2QQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2QQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2QQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2qq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2QQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2QQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2QQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2QQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2qq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2QQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2qq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2QQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2QQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2QQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2QQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2qq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2QQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2qq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2QQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2udq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UDQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UDQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UDQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UDQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2UDQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UDQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2udq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UDQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UDQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UDQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UDQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2UDQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UDQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UDQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2udq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2UDQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2udq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UDQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UDQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UDQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UDQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2UDQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UDQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UDQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2udq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2UDQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UDQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2udq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2UDQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UQQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uqq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UQQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UQQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UQQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UQQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uqq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UQQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UQQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UQQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UQQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uqq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UQQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uqq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UQQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UQQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UQQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UQQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uqq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UQQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uqq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UQQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UW128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2UW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UW256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2UW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UW512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UW128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2UW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UW256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2UW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UW512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UW_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uw_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2UW512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2UW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UW128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2UW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UW256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2UW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2UW512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UW_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uw_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2UW512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2UW_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2uw_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2UW512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2W` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2w(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2W128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2W128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2W256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2W256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2W512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2W512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2W_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2w_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2W128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2W128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2W256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2W256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2W512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2W512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2W_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2w_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2W512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2W_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2w_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPH2W128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2W128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPH2W256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2W256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2W512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPH2W512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2W_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2w_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2W512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPH2W_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttph2w_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPH2W512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2DQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2dq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2DQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2DQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2DQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2DQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2DQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2DQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2DQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2dq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2DQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2DQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2DQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2DQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2DQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2DQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2DQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2dq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2DQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2DQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2dq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2DQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2DQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2DQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2DQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2DQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2DQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2DQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2dq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2DQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2DQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2dq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2DQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2QQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2qq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2QQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2QQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2QQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2QQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2QQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2QQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2QQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2qq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2QQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2QQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2QQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2QQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2QQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2QQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2QQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2qq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2QQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2QQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2qq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2QQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2QQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2QQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2QQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2QQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2QQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2QQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2qq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2QQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2QQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2qq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2QQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2udq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2UDQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UDQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2UDQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UDQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2UDQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UDQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2udq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2UDQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UDQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2UDQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UDQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2UDQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UDQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UDQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2udq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2UDQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2udq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2UDQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UDQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2UDQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UDQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2UDQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UDQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UDQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2udq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2UDQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UDQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2udq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTTPS2UDQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UQQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2uqq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2UQQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UQQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2UQQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UQQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2UQQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UQQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UQQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2uqq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2UQQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UQQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2UQQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UQQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2UQQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UQQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UQQ_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2uqq_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2UQQ512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UQQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2uqq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2UQQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UQQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTPS2UQQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UQQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2UQQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTPS2UQQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UQQ_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2uqq_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2UQQ512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTPS2UQQ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttps2uqq_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTTPS2UQQ512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSD2SI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttsd2si(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSD2SI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSD2SI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSD2SI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSD2SI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSD2SI_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttsd2si_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSD2SI32RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSD2SI64RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSD2USI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttsd2usi(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSD2USI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSD2USI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSD2USI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSD2USI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSD2USI_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttsd2usi_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSD2USI32RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSD2USI64RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSH2SI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttsh2si(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSH2SI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSH2SI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSH2SI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSH2SI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSH2SI_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttsh2si_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSH2SI32RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSH2SI64RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSH2USI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttsh2usi(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSH2USI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSH2USI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSH2USI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSH2USI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSH2USI_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttsh2usi_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSH2USI32RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSH2USI64RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSS2SI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttss2si(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSS2SI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSS2SI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSS2SI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSS2SI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSS2SI_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttss2si_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSS2SI32RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSS2SI64RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSS2USI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttss2usi(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSS2USI32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSS2USI32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSS2USI64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VCVTTSS2USI64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTTSS2USI_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvttss2usi_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSS2USI32RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTTSS2USI64RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2pd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2pd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2pd_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PD512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2pd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2pd_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PD512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2pd_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PD512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ph(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PH128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PH128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PH256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PH512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PH512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ph_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PH512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ph_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PH128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PH128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PH256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PH512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PH512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ph_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PH512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ph_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PH128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PH128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PH256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PH512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PH512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ph_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PH512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ps_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PS512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PS256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ps_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PS512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUDQ2PS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUDQ2PS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PS256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUDQ2PS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUDQ2PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtudq2ps_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUDQ2PS512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2pd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUQQ2PD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUQQ2PD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2pd_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PD512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2pd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUQQ2PD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUQQ2PD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2pd_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PD512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2pd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUQQ2PD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUQQ2PD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2pd_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PD512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ph(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUQQ2PH128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PH128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUQQ2PH256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PH512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ph_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PH512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ph_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUQQ2PH128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PH128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUQQ2PH256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PH512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ph_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PH512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ph_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUQQ2PH128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PH128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUQQ2PH256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PH512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ph_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PH512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUQQ2PS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUQQ2PS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ps_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PS512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUQQ2PS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUQQ2PS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ps_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PS512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUQQ2PS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUQQ2PS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUQQ2PS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUQQ2PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuqq2ps_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUQQ2PS512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUSI2SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtusi2sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTUSI2SD32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTUSI2SD32RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTUSI2SD64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUSI2SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtusi2sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTUSI2SD32RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTUSI2SD64RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUSI2SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtusi2sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTUSI2SH32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTUSI2SH32RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTUSI2SH64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUSI2SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtusi2sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTUSI2SH32RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTUSI2SH64RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUSI2SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtusi2ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTUSI2SS32RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VCVTUSI2SS32RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTUSI2SS64RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUSI2SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtusi2ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() {
            return Ok(Self { opcode: VCVTUSI2SS32RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() {
            return Ok(Self { opcode: VCVTUSI2SS64RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUW2PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuw2ph(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUW2PH128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUW2PH128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUW2PH256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUW2PH256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUW2PH512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUW2PH512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUW2PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuw2ph_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUW2PH512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUW2PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuw2ph_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUW2PH128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUW2PH128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUW2PH256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUW2PH256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUW2PH512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUW2PH512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUW2PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuw2ph_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUW2PH512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUW2PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuw2ph_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTUW2PH128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUW2PH128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTUW2PH256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUW2PH256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUW2PH512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTUW2PH512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTUW2PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtuw2ph_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTUW2PH512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTW2PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtw2ph(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTW2PH128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTW2PH128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTW2PH256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTW2PH256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTW2PH512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTW2PH512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTW2PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtw2ph_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTW2PH512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTW2PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtw2ph_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTW2PH128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTW2PH128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTW2PH256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTW2PH256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTW2PH512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTW2PH512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTW2PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtw2ph_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTW2PH512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTW2PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtw2ph_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VCVTW2PH128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VCVTW2PH128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VCVTW2PH256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VCVTW2PH256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTW2PH512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VCVTW2PH512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VCVTW2PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vcvtw2ph_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VCVTW2PH512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDBPSADBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdbpsadbw(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDBPSADBW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdbpsadbw_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDBPSADBW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdbpsadbw_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDBPSADBW512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDIVPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivpd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDIVPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivpd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDIVPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivpd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVPH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDIVPH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVPH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDIVPH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVPH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDIVPH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDIVPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDIVPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDIVPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDIVPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVPS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDIVPS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVSDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVSDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVSDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivsh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVSSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVSSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDIVSSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDIVSS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdivss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDIVSSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDPBF16PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdpbf16ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDPBF16PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDPBF16PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDPBF16PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDPBF16PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDPBF16PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDPBF16PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDPBF16PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdpbf16ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDPBF16PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDPBF16PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDPBF16PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDPBF16PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDPBF16PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDPBF16PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDPBF16PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdpbf16ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VDPBF16PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VDPBF16PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VDPBF16PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VDPBF16PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VDPBF16PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VDPBF16PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDPPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdppd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VDPPD128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDPPD128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VDPPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vdpps(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VDPPS128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDPPS128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VDPPS256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VDPPS256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VERR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn verr(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: VERRR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: VERRM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VERW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn verw(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: VERWR, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() {
            return Ok(Self { opcode: VERWM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXPANDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vexpandpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VEXPANDPD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VEXPANDPD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VEXPANDPD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXPANDPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vexpandpd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VEXPANDPD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VEXPANDPD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VEXPANDPD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXPANDPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vexpandpd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VEXPANDPD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VEXPANDPD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VEXPANDPD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXPANDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vexpandps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VEXPANDPS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VEXPANDPS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VEXPANDPS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXPANDPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vexpandps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPS256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VEXPANDPS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VEXPANDPS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VEXPANDPS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXPANDPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vexpandps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPS256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VEXPANDPS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VEXPANDPS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VEXPANDPS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VEXPANDPS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF128` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf128(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF128MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF32X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf32x4(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X4_256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X4_256MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X4_512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X4_512MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF32X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf32x4_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X4_256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X4_256MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X4_512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X4_512MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF32X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf32x4_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X4_256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X4_512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF32X8` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf32x8(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X8_512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X8_512MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF32X8_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf32x8_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X8_512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X8_512MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF32X8_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf32x8_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF32X8_512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF64X2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf64x2(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X2_256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X2_256MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X2_512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X2_512MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF64X2_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf64x2_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X2_256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X2_256MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X2_512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X2_512MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF64X2_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf64x2_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X2_256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X2_512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF64X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf64x4(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X4_512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X4_512MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF64X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf64x4_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X4_512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X4_512MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTF64X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractf64x4_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTF64X4_512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI128` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti128(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI128MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI32X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti32x4(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X4_256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X4_256MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X4_512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X4_512MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI32X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti32x4_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X4_256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X4_256MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X4_512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X4_512MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI32X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti32x4_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X4_256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X4_512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI32X8` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti32x8(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X8_512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X8_512MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI32X8_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti32x8_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X8_512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X8_512MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI32X8_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti32x8_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI32X8_512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI64X2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti64x2(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X2_256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X2_256MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X2_512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X2_512MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI64X2_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti64x2_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X2_256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X2_256MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X2_512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X2_512MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI64X2_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti64x2_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X2_256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X2_512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI64X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti64x4(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X4_512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X4_512MRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI64X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti64x4_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X4_512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X4_512MRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTI64X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextracti64x4_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTI64X4_512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VEXTRACTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vextractps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTPSRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VEXTRACTPSMRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMADDCPH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCPH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFCMADDCPH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCPH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMADDCPH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCPH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCPH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMADDCPH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMADDCPH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCPH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFCMADDCPH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCPH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMADDCPH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCPH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCPH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMADDCPH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMADDCPH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCPH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFCMADDCPH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCPH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMADDCPH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCPH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCPH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMADDCPH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMADDCSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCSH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcsh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMADDCSHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMADDCSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCSH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcsh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMADDCSHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMADDCSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMADDCSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMADDCSH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmaddcsh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMADDCSHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMULCPH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCPH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFCMULCPH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCPH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMULCPH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCPH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCPH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMULCPH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMULCPH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCPH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFCMULCPH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCPH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMULCPH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCPH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCPH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMULCPH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMULCPH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCPH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFCMULCPH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCPH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMULCPH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCPH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCPH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFCMULCPH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMULCSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCSH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcsh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMULCSHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMULCSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCSH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcsh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMULCSHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMULCSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFCMULCSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFCMULCSH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfcmulcsh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFCMULCSHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmpd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmpd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmpd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD512RRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmpd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD512RRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmpd_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPD512RRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmps(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmps_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmps_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS512RRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmps_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmps_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS512RRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMPS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmps_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMPS512RRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmsd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSDRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSDRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmsd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSDRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSDRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmsd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSDRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSDRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSDRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmsd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSDRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmsd_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSDRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmss(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSSRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSSRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmss_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSSRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSSRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmss_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSSRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmss_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSSRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSSRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmss_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSSRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFIXUPIMMSS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfixupimmss_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VFIXUPIMMSSRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD132PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD132PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD132PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD132PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD132PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD132PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD132PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD132PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD132PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD132PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD132SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD132SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd132ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD132SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD213PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD213PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD213PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD213PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD213PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD213PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD213PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD213PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD213PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD213PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD213SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD213SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd213ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD213SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD231PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD231PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD231PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD231PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD231PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD231PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD231PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD231PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADD231PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADD231PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADD231SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADD231SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmadd231ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADD231SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDCPH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCPH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDCPH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCPH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDCPH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCPH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCPH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDCPH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDCPH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCPH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDCPH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCPH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDCPH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCPH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCPH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDCPH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDCPH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCPH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDCPH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCPH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDCPH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCPH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCPH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDCPH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDCSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCSH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcsh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDCSHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDCSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCSH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcsh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDCSHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDCSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDCSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDCSH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddcsh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDCSHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB132PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB132PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB132PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB132PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB132PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB132PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB132PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB132PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB132PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB132PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB132PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB132PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB132PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB132PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB132PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB132PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB132PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB132PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB132PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB132PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub132ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB132PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB213PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB213PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB213PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB213PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB213PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB213PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB213PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB213PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB213PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB213PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB213PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB213PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB213PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB213PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB213PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB213PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB213PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB213PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB213PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB213PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub213ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB213PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB231PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB231PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB231PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB231PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB231PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB231PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB231PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB231PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB231PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB231PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB231PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB231PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB231PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB231PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB231PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB231PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMADDSUB231PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMADDSUB231PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMADDSUB231PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMADDSUB231PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmaddsub231ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMADDSUB231PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB132PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB132PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB132PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB132PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB132PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB132PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB132PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB132PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB132PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB132PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB132SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB132SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub132ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB132SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB213PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB213PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB213PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB213PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB213PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB213PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB213PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB213PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB213PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB213PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB213SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB213SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub213ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB213SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB231PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB231PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB231PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB231PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB231PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB231PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB231PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB231PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUB231PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUB231PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUB231SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUB231SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsub231ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUB231SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD132PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD132PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD132PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD132PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD132PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD132PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD132PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD132PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD132PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD132PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD132PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD132PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD132PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD132PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD132PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD132PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD132PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD132PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD132PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD132PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd132ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD132PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD213PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD213PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD213PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD213PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD213PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD213PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD213PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD213PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD213PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD213PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD213PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD213PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD213PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD213PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD213PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD213PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD213PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD213PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD213PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD213PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd213ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD213PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD231PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD231PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD231PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD231PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD231PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD231PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD231PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD231PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD231PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD231PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD231PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD231PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD231PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD231PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD231PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD231PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMSUBADD231PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMSUBADD231PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMSUBADD231PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMSUBADD231PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmsubadd231ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMSUBADD231PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMULCPH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCPH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMULCPH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCPH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMULCPH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCPH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCPH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMULCPH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMULCPH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCPH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMULCPH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCPH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMULCPH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCPH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCPH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMULCPH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMULCPH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCPH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFMULCPH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCPH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMULCPH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCPH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCPH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFMULCPH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMULCSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCSH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcsh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMULCSHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMULCSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCSH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcsh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMULCSHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMULCSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFMULCSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFMULCSH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfmulcsh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFMULCSHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD132PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD132PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD132PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD132PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD132PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD132PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD132PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD132PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD132PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD132PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD132SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD132SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd132ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD132SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD213PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD213PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD213PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD213PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD213PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD213PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD213PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD213PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD213PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD213PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD213SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD213SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd213ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD213SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD231PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD231PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD231PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD231PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD231PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD231PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD231PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD231PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMADD231PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMADD231PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMADD231SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMADD231SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmadd231ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMADD231SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB132PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB132PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB132PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB132PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB132PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB132PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB132PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB132PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB132PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB132PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB132SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB132SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub132ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB132SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB213PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB213PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB213PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB213PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB213PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB213PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB213PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB213PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB213PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB213PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB213SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB213SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub213ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB213SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB231PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231pd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB231PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231pd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB231PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231pd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231PH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB231PH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231PH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB231PH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231PH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB231PH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB231PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB231PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VFNMSUB231PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231PS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VFNMSUB231PS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231SHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231SHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231SHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231sh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VFNMSUB231SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFNMSUB231SS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfnmsub231ss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VFNMSUB231SSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclasspd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPD128KRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPD128KMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPD256KRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPD512KRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclasspd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPD128KRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPD128KMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPD256KRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPD512KRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclassph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPH128KRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPH128KMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPH256KRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPH512KRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclassph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPH128KRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPH128KMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPH256KRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPH512KRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclassps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPS128KRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPS128KMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPS256KRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPS512KRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclassps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPS128KRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPS128KMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPS256KRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSPS512KRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclasssd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSDKRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSDKMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclasssd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSDKRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSDKMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclasssh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSHKRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSHKMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclasssh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSHKRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSHKMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclassss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSSKRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSSKMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VFPCLASSSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vfpclassss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSSKRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VFPCLASSSSKMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGATHERDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgatherdpd_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGATHERDPD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGATHERDPD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGATHERDPD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGATHERDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgatherdpd_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() && op2.is_vec128() {
            return Ok(Self { opcode: VGATHERDPD128RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_vec256() {
            return Ok(Self { opcode: VGATHERDPD256RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGATHERDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgatherdps_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGATHERDPS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGATHERDPS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGATHERDPS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGATHERDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgatherdps_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() && op2.is_vec128() {
            return Ok(Self { opcode: VGATHERDPS128RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_vec256() {
            return Ok(Self { opcode: VGATHERDPS256RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGATHERQPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgatherqpd_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGATHERQPD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGATHERQPD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGATHERQPD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGATHERQPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgatherqpd_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() && op2.is_vec128() {
            return Ok(Self { opcode: VGATHERQPD128RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_vec256() {
            return Ok(Self { opcode: VGATHERQPD256RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGATHERQPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgatherqps_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGATHERQPS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGATHERQPS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGATHERQPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgatherqps_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() && op2.is_vec128() {
            return Ok(Self { opcode: VGATHERQPS128RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexppd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VGETEXPPD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VGETEXPPD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexppd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VGETEXPPD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VGETEXPPD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexppd_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPD512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexppd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VGETEXPPD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VGETEXPPD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexppd_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPD512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexppd_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPD512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpph(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VGETEXPPH128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPH128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VGETEXPPH256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPH256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPH512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPH512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpph_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VGETEXPPH128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPH128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VGETEXPPH256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPH256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPH512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPH512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpph_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPH512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpph_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VGETEXPPH128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPH128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VGETEXPPH256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPH256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPH512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPH512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpph_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPH512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpph_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPH512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VGETEXPPS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VGETEXPPS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VGETEXPPS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VGETEXPPS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPS256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpps_mask_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPS512RR_MASK_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VGETEXPPS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VGETEXPPS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPS256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VGETEXPPS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpps_maskz_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPS512RR_MASKZ_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPPS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpps_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VGETEXPPS512RR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGETEXPSDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGETEXPSDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSDRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGETEXPSDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSDRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsd_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSDRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGETEXPSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGETEXPSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsh_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSHRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGETEXPSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsh_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSHRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpsh_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSHRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGETEXPSSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGETEXPSSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpss_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSSRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGETEXPSSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpss_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSSRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETEXPSS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetexpss_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGETEXPSSRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantpd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD512RRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantpd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD512RRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantpd_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPD512RRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantph_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH512RRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantph_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH512RRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantph_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPH512RRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantps_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS512RRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantps_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS512RRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTPS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantps_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VGETMANTPS512RRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSDRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSDRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSDRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSDRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSDRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSDRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSDRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSDRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsd_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSDRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsh(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSHRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSHRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsh_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSHRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSHRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsh_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSHRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSHRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSHRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsh_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSHRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantsh_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSHRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantss(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSSRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSSRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantss_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSSRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSSRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantss_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSSRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantss_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSSRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSSRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantss_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSSRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGETMANTSS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgetmantss_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGETMANTSSRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGF2P8AFFINEINVQB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgf2p8affineinvqb(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGF2P8AFFINEINVQB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgf2p8affineinvqb_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGF2P8AFFINEINVQB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgf2p8affineinvqb_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEINVQB512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGF2P8AFFINEQB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgf2p8affineqb(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGF2P8AFFINEQB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgf2p8affineqb_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGF2P8AFFINEQB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgf2p8affineqb_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VGF2P8AFFINEQB512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGF2P8MULB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgf2p8mulb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGF2P8MULB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGF2P8MULB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VGF2P8MULB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VGF2P8MULB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VGF2P8MULB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VGF2P8MULB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGF2P8MULB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgf2p8mulb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGF2P8MULB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGF2P8MULB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VGF2P8MULB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VGF2P8MULB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VGF2P8MULB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VGF2P8MULB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VGF2P8MULB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vgf2p8mulb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VGF2P8MULB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VGF2P8MULB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VGF2P8MULB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VGF2P8MULB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VGF2P8MULB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VGF2P8MULB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VHADDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vhaddpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VHADDPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VHADDPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VHADDPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VHADDPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VHADDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vhaddps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VHADDPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VHADDPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VHADDPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VHADDPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VHSUBPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vhsubpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VHSUBPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VHSUBPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VHSUBPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VHSUBPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VHSUBPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vhsubps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VHSUBPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VHSUBPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VHSUBPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VHSUBPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF128` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf128(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF32X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf32x4(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF32X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf32x4_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF32X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf32x4_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X4_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF32X8` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf32x8(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X8_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X8_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF32X8_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf32x8_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X8_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X8_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF32X8_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf32x8_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X8_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF32X8_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF64X2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf64x2(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF64X2_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf64x2_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF64X2_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf64x2_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X2_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF64X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf64x4(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X4_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X4_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF64X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf64x4_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X4_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X4_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTF64X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertf64x4_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X4_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTF64X4_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI128` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti128(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI32X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti32x4(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI32X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti32x4_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI32X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti32x4_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X4_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI32X8` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti32x8(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X8_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X8_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI32X8_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti32x8_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X8_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X8_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI32X8_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti32x8_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X8_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI32X8_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI64X2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti64x2(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI64X2_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti64x2_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI64X2_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti64x2_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X2_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI64X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti64x4(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X4_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X4_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI64X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti64x4_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X4_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X4_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTI64X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinserti64x4_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X4_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTI64X4_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VINSERTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vinsertps(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTPSRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VINSERTPSRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VLDDQU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vlddqu(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VLDDQU128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VLDDQU256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VLDMXCSR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vldmxcsr(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: VLDMXCSRM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMASKMOVDQU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaskmovdqu(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMASKMOVDQU128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMASKMOVPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaskmovpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMASKMOVPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMASKMOVPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMASKMOVPD128MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMASKMOVPD256MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMASKMOVPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaskmovps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMASKMOVPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMASKMOVPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMASKMOVPS128MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMASKMOVPS256MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMAXPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMAXPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxpd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPD512RRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMAXPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxpd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPD512RRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxpd_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPD512RRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXPH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMAXPH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXPH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMAXPH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxph_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPH512RRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXPH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMAXPH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxph_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPH512RRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxph_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPH512RRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMAXPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMAXPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxps_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPS512RRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMAXPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMAXPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxps_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPS512RRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXPS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxps_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMAXPS512RRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXSDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXSDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSDRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXSDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSDRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsd_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSDRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsh_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSHRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsh_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSHRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxsh_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSHRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXSSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXSSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxss_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSSRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMAXSSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxss_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSSRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMAXSS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmaxss_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMAXSSRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMCALL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmcall() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VMCALL, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `VMCLEAR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmclear(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: VMCLEARM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMFUNC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmfunc() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VMFUNC, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `VMGEXIT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmgexit() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VMGEXIT, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `VMINPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMINPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMINPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMINPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMINPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMINPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMINPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminpd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPD512RRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMINPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMINPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMINPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminpd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPD512RRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminpd_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPD512RRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINPH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINPH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMINPH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMINPH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMINPH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINPH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINPH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMINPH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMINPH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMINPH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminph_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPH512RRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINPH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINPH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMINPH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMINPH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMINPH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminph_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPH512RRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminph_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPH512RRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMINPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMINPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMINPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMINPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMINPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMINPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminps_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPS512RRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMINPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMINPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMINPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminps_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPS512RRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINPS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminps_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMINPS512RRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINSDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINSDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSDRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINSDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSDRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsd_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSDRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsh_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSHRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsh_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSHRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminsh_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSHRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINSSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINSSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminss_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSSRRR_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMINSSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminss_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSSRRR_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMINSS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vminss_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMINSSRRR_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMLAUNCH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmlaunch() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VMLAUNCH, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `VMLOAD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmload() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VMLOAD, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `VMMCALL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmmcall() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VMMCALL, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `VMOVAPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovapd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVAPD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVAPD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVAPD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVAPD256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVAPD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVAPD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVAPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovapd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVAPD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVAPD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVAPD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVAPD128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVAPD256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVAPD512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVAPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovapd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVAPD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVAPD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVAPD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVAPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovaps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVAPS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVAPS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVAPS128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVAPS256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVAPS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVAPS512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVAPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovaps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVAPS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVAPS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPS256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVAPS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVAPS128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVAPS256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVAPS512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVAPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovaps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVAPS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVAPS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPS256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVAPS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVAPS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDDUP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovddup(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDDUP128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDDUP128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDDUP256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDDUP256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDDUP512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDDUP512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDDUP_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovddup_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDDUP128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDDUP128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDDUP256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDDUP256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDDUP512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDDUP512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDDUP_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovddup_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDDUP128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDDUP128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDDUP256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDDUP256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDDUP512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDDUP512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQA` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqa(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQA32` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqa32(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA32_128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA32_128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA32_256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA32_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQA32_512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA32_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA32_128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA32_256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQA32_512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQA32_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqa32_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA32_128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA32_128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA32_256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA32_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQA32_512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA32_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA32_128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA32_256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQA32_512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQA32_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqa32_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA32_128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA32_128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA32_256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA32_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQA32_512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA32_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQA64` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqa64(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA64_128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA64_128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA64_256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA64_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQA64_512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA64_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA64_128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA64_256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQA64_512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQA64_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqa64_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA64_128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA64_128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA64_256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA64_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQA64_512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA64_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA64_128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA64_256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQA64_512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQA64_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqa64_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQA64_128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA64_128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQA64_256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA64_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQA64_512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQA64_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU16` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu16(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU16_128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU16_128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU16_256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU16_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU16_512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU16_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU16_128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU16_256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU16_512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU16_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu16_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU16_128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU16_128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU16_256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU16_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU16_512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU16_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU16_128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU16_256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU16_512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU16_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu16_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU16_128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU16_128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU16_256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU16_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU16_512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU16_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU32` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu32(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU32_128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU32_128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU32_256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU32_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU32_512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU32_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU32_128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU32_256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU32_512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU32_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu32_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU32_128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU32_128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU32_256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU32_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU32_512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU32_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU32_128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU32_256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU32_512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU32_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu32_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU32_128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU32_128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU32_256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU32_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU32_512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU32_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU64` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu64(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU64_128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU64_128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU64_256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU64_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU64_512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU64_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU64_128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU64_256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU64_512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU64_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu64_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU64_128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU64_128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU64_256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU64_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU64_512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU64_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU64_128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU64_256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU64_512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU64_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu64_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU64_128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU64_128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU64_256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU64_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU64_512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU64_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU8` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu8(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU8_128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU8_128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU8_256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU8_256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU8_512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU8_512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU8_128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU8_256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU8_512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU8_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu8_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU8_128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU8_128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU8_256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU8_256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU8_512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU8_512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU8_128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU8_256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU8_512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVDQU8_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovdqu8_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVDQU8_128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU8_128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVDQU8_256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU8_256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVDQU8_512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVDQU8_512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVD_G2X` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovd_g2x(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VMOVD_G2XRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVD_X2G` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovd_x2g(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVD_X2GRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVHLPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovhlps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMOVHLPSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVHPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovhpd_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVHPDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVHPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovhpd_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMOVHPDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVHPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovhps_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVHPSMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVHPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovhps_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMOVHPSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVLHPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovlhps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMOVLHPSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVLPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovlpd_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVLPDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVLPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovlpd_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMOVLPDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVLPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovlps_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVLPSMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVLPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovlps_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMOVLPSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVMSKPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovmskpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVMSKPD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVMSKPD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVMSKPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovmskps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVMSKPS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVMSKPS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVNTDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovntdq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVNTDQ128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVNTDQ256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVNTDQ512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVNTDQA` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovntdqa(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVNTDQA128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVNTDQA256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVNTDQA512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVNTPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovntpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVNTPD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVNTPD256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVNTPD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVNTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovntps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVNTPS128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVNTPS256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVNTPS512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVQRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVQRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVQMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVQ_G2X` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovq_g2x(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VMOVQ_G2XRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVQ_G2XRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_gp64() {
            return Ok(Self { opcode: VMOVQ_G2XRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVQ_X2G` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovq_x2g(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVQ_X2GRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVQ_X2GMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVQ_X2GRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsd_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSDMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsd_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMOVSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsd_mask_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSDRM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSDMR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsd_mask_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMOVSDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsd_maskz_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSDRM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsd_maskz_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMOVSDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsh_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSHMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsh_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMOVSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSHDUP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovshdup(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSHDUP128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHDUP128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVSHDUP256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHDUP256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVSHDUP512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHDUP512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSHDUP_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovshdup_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSHDUP128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHDUP128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVSHDUP256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHDUP256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVSHDUP512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHDUP512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSHDUP_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovshdup_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSHDUP128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHDUP128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVSHDUP256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHDUP256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVSHDUP512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHDUP512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsh_mask_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHRM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSHMR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsh_mask_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMOVSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsh_maskz_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSHRM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsh_maskz_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMOVSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSLDUP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsldup(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSLDUP128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSLDUP128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVSLDUP256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSLDUP256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVSLDUP512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSLDUP512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSLDUP_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsldup_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSLDUP128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSLDUP128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVSLDUP256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSLDUP256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVSLDUP512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSLDUP512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSLDUP_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovsldup_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSLDUP128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSLDUP128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVSLDUP256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSLDUP256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVSLDUP512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSLDUP512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovss_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSSMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovss_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMOVSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovss_mask_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSSRM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVSSMR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovss_mask_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMOVSSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovss_maskz_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVSSRM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovss_maskz_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMOVSSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVUPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovupd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVUPD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVUPD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVUPD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVUPD256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVUPD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVUPD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVUPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovupd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVUPD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVUPD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVUPD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVUPD128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVUPD256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVUPD512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVUPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovupd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVUPD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVUPD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVUPD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVUPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovups(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVUPS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVUPS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVUPS128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVUPS256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVUPS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVUPS512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVUPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovups_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVUPS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVUPS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPS256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVUPS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVUPS128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVUPS256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVUPS512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVUPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovups_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVUPS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VMOVUPS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPS256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VMOVUPS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VMOVUPS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVW_G2X` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovw_g2x(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VMOVW_G2XRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VMOVW_G2XRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMOVW_X2G` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmovw_x2g(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVW_X2GRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VMOVW_X2GMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMPSADBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmpsadbw(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VMPSADBW128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VMPSADBW128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VMPSADBW256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VMPSADBW256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMPTRLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmptrld(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: VMPTRLDM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMPTRST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmptrst(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: VMPTRSTM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMREAD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmread(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: VMREADRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: VMREADMR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMRESUME` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmresume() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VMRESUME, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `VMRUN` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmrun() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VMRUN, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `VMSAVE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmsave() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VMSAVE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `VMULPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMULPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMULPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMULPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulpd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMULPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMULPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMULPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulpd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMULPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMULPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMULPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulpd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULPH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULPH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMULPH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMULPH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMULPH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULPH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULPH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMULPH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMULPH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMULPH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULPH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULPH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMULPH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMULPH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMULPH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMULPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMULPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMULPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMULPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMULPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMULPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VMULPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VMULPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VMULPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULPS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VMULPS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULSDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULSDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULSDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulsh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULSSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULSSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VMULSSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMULSS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmulss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VMULSSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMWRITE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmwrite(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: VMWRITERR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: VMWRITERM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VMXOFF` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmxoff() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VMXOFF, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `VMXON` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vmxon(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: VMXONM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VORPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vorpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VORPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VORPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VORPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VORPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VORPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VORPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VORPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vorpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VORPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VORPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VORPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VORPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VORPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VORPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VORPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vorpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VORPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VORPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VORPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VORPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VORPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VORPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VORPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vorps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VORPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VORPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VORPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VORPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VORPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VORPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VORPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vorps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VORPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VORPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VORPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VORPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VORPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VORPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VORPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vorps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VORPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VORPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VORPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VORPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VORPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VORPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VP2INTERSECTD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vp2intersectd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VP2INTERSECTD128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VP2INTERSECTD128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VP2INTERSECTD256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VP2INTERSECTD256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VP2INTERSECTD512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VP2INTERSECTD512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VP2INTERSECTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vp2intersectq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VP2INTERSECTQ128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VP2INTERSECTQ128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VP2INTERSECTQ256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VP2INTERSECTQ256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VP2INTERSECTQ512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VP2INTERSECTQ512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSB128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSB256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSB512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSB128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSB256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSB512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSB128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSB256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSB512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSW128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSW256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSW512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSW128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSW256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSW512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPABSW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpabsw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPABSW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPABSW128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPABSW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPABSW256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPABSW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPABSW512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKSSDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpackssdw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKSSDW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSDW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKSSDW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSDW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKSSDW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSDW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKSSDW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpackssdw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKSSDW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSDW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKSSDW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSDW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKSSDW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSDW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKSSDW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpackssdw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKSSDW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSDW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKSSDW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSDW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKSSDW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSDW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKSSWB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpacksswb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKSSWB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSWB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKSSWB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSWB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKSSWB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSWB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKSSWB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpacksswb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKSSWB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSWB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKSSWB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSWB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKSSWB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSWB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKSSWB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpacksswb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKSSWB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSWB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKSSWB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSWB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKSSWB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKSSWB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKUSDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpackusdw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKUSDW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSDW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKUSDW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSDW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKUSDW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSDW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKUSDW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpackusdw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKUSDW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSDW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKUSDW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSDW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKUSDW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSDW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKUSDW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpackusdw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKUSDW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSDW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKUSDW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSDW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKUSDW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSDW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKUSWB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpackuswb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKUSWB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSWB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKUSWB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSWB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKUSWB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSWB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKUSWB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpackuswb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKUSWB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSWB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKUSWB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSWB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKUSWB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSWB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPACKUSWB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpackuswb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPACKUSWB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSWB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPACKUSWB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSWB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPACKUSWB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPACKUSWB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddsb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDSB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDSB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDSB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDSB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddsb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDSB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDSB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDSB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDSB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddsb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDSB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDSB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDSB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddsw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDSW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDSW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDSW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDSW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddsw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDSW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDSW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDSW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDSW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddsw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDSW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDSW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDSW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDSW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDUSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddusb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDUSB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDUSB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDUSB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDUSB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddusb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDUSB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDUSB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDUSB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDUSB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddusb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDUSB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDUSB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDUSB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDUSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddusw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDUSW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDUSW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDUSW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDUSW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddusw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDUSW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDUSW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDUSW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDUSW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddusw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDUSW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDUSW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDUSW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDUSW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPADDW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpaddw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPADDW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPADDW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPADDW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPADDW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPADDW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPADDW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPALIGNR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpalignr(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPALIGNR_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpalignr_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPALIGNR_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpalignr_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPALIGNR512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPAND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpand(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPAND128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPAND128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPAND256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPAND256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDN` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandn(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDN128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDN128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDN256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDN256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandnd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDND128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDND128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDND256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDND256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDND512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDND512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDND_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandnd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDND128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDND128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDND256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDND256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDND512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDND512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDND_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandnd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDND128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDND128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDND256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDND256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDND512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDND512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDNQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandnq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDNQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDNQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDNQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDNQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDNQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDNQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDNQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandnq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDNQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDNQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDNQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDNQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDNQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDNQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDNQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandnq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDNQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDNQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDNQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDNQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDNQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDNQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPANDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpandq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPANDQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPANDQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPANDQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPANDQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPANDQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPANDQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPAVGB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpavgb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPAVGB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPAVGB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPAVGB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPAVGB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpavgb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPAVGB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPAVGB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPAVGB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPAVGB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpavgb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPAVGB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPAVGB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPAVGB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPAVGW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpavgw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPAVGW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPAVGW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPAVGW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPAVGW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpavgw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPAVGW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPAVGW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPAVGW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPAVGW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpavgw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPAVGW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPAVGW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPAVGW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPAVGW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPBLENDD128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPBLENDD128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPBLENDD256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPBLENDD256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDMW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendmw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPBLENDMW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPBLENDMW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPBLENDMW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPBLENDMW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDVB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendvb(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_vec128() {
            return Ok(Self { opcode: VPBLENDVB128RRRR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_vec128() {
            return Ok(Self { opcode: VPBLENDVB128RRMR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_vec256() {
            return Ok(Self { opcode: VPBLENDVB256RRRR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_vec256() {
            return Ok(Self { opcode: VPBLENDVB256RRMR, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBLENDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpblendw(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPBLENDW128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPBLENDW128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPBLENDW256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPBLENDW256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTB128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTB256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTB512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTB_GP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastb_gp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTB_GP128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTB_GP256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTB_GP512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTB_GP_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastb_gp_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTB_GP128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTB_GP256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTB_GP512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTB_GP_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastb_gp_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTB_GP128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTB_GP256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTB_GP512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTB128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTB256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTB512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTB128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTB256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTB512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTD_GP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastd_gp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTD_GP128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTD_GP256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTD_GP512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTD_GP_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastd_gp_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTD_GP128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTD_GP256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTD_GP512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTD_GP_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastd_gp_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTD_GP128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTD_GP256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTD_GP512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTMB2Q` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastmb2q(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mask() {
            return Ok(Self { opcode: VPBROADCASTMB2Q128RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mask() {
            return Ok(Self { opcode: VPBROADCASTMB2Q256RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mask() {
            return Ok(Self { opcode: VPBROADCASTMB2Q512RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTMW2D` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastmw2d(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mask() {
            return Ok(Self { opcode: VPBROADCASTMW2D128RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mask() {
            return Ok(Self { opcode: VPBROADCASTMW2D256RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mask() {
            return Ok(Self { opcode: VPBROADCASTMW2D512RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTQ_GP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastq_gp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTQ_GP128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTQ_GP256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTQ_GP512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTQ_GP_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastq_gp_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTQ_GP128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTQ_GP256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTQ_GP512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTQ_GP_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastq_gp_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTQ_GP128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTQ_GP256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTQ_GP512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTW128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTW256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTW512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTW_GP` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastw_gp(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTW_GP128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTW_GP256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTW_GP512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTW_GP_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastw_gp_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTW_GP128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTW_GP256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTW_GP512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTW_GP_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastw_gp_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTW_GP128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTW_GP256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_gp32() {
            return Ok(Self { opcode: VPBROADCASTW_GP512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTW128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTW256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTW512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPBROADCASTW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpbroadcastw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTW128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTW256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPBROADCASTW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPBROADCASTW512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCLMULQDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpclmulqdq(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCLMULQDQ128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCLMULQDQ128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCLMULQDQ256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCLMULQDQ256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCLMULQDQ512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCLMULQDQ512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpb(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB128KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB128KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB256KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB256KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB512KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB512KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpb_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB128KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB128KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB256KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB256KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB512KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPB512KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD128KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD128KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD256KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD256KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD512KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD512KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD128KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD128KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD256KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD256KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD512KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPD512KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPEQB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpeqb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQB128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQB128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQB256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQB256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPEQB512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQB512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPEQB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpeqb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQB128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQB128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQB256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQB256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPEQB512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQB512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPEQD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpeqd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQD128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQD128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQD256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQD256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPEQD512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQD512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPEQD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpeqd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQD128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQD128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQD256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQD256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPEQD512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQD512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPEQQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpeqq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQQ128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQQ128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQQ256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQQ256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPEQQ512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQQ512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPEQQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpeqq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQQ128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQQ128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQQ256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQQ256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPEQQ512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQQ512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPEQW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpeqw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQW128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQW128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQW256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQW256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPEQW512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQW512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPEQW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpeqw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPEQW128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQW128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPEQW256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQW256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPEQW512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPEQW512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPESTRI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpestri(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPCMPESTRIRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPCMPESTRIRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPESTRM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpestrm(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPCMPESTRMRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPCMPESTRMRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPGTB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpgtb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTB128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTB128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTB256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTB256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPGTB512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTB512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPGTB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpgtb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTB128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTB128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTB256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTB256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPGTB512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTB512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPGTD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpgtd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTD128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTD128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTD256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTD256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPGTD512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTD512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPGTD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpgtd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTD128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTD128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTD256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTD256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPGTD512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTD512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPGTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpgtq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTQ128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTQ128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTQ256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTQ256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPGTQ512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTQ512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPGTQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpgtq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTQ128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTQ128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTQ256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTQ256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPGTQ512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTQ512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPGTW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpgtw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTW128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTW128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTW256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTW256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPGTW512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTW512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPGTW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpgtw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPCMPGTW128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTW128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPCMPGTW256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTW256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPCMPGTW512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPCMPGTW512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPISTRI` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpistri(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPCMPISTRIRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPCMPISTRIRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPISTRM` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpistrm(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPCMPISTRMRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPCMPISTRMRMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpq(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ128KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ128KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ256KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ256KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ512KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ512KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpq_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ128KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ128KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ256KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ256KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ512KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPQ512KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPUB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpub(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB128KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB128KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB256KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB256KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB512KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB512KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPUB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpub_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB128KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB128KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB256KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB256KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB512KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUB512KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPUD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpud(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD128KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD128KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD256KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD256KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD512KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD512KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPUD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpud_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD128KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD128KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD256KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD256KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD512KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUD512KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPUQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpuq(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ128KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ128KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ256KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ256KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ512KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ512KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPUQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpuq_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ128KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ128KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ256KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ256KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ512KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUQ512KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPUW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpuw(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW128KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW128KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW256KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW256KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW512KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW512KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPUW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpuw_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW128KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW128KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW256KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW256KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW512KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPUW512KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpw(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW128KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW128KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW256KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW256KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW512KRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW512KRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCMPW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcmpw_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW128KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW128KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW256KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW256KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW512KRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPCMPW512KRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSB128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSB256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSB512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSB128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSB256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSB512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSD256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSD128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSD256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSD512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSQ128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSQ256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSQ512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSQ128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSQ256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSQ512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSW128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSW256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSW512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSW128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSW256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSW512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCOMPRESSW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpcompressw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCOMPRESSW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCOMPRESSW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCOMPRESSW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCONFLICTD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpconflictd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCONFLICTD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCONFLICTD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCONFLICTD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCONFLICTD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpconflictd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCONFLICTD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCONFLICTD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCONFLICTD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCONFLICTD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpconflictd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCONFLICTD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCONFLICTD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCONFLICTD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCONFLICTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpconflictq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCONFLICTQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCONFLICTQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCONFLICTQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCONFLICTQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpconflictq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCONFLICTQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCONFLICTQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCONFLICTQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPCONFLICTQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpconflictq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPCONFLICTQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPCONFLICTQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPCONFLICTQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPCONFLICTQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBSSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbssd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBSSD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBSSD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBSSD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBSSD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBSSDS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbssds(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBSSDS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBSSDS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBSSDS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBSSDS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBSUD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbsud(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBSUD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBSUD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBSUD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBSUD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBSUDS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbsuds(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBSUDS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBSUDS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBSUDS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBSUDS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBUSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbusd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBUSD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBUSD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPBUSD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBUSDS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbusds(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBUSDS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSDS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBUSDS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSDS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPBUSDS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSDS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBUSDS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbusds_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBUSDS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSDS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBUSDS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSDS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPBUSDS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSDS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBUSDS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbusds_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBUSDS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSDS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBUSDS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSDS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPBUSDS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSDS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBUSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbusd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBUSD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBUSD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPBUSD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBUSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbusd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBUSD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBUSD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPBUSD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUSD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBUUD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbuud(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBUUD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUUD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBUUD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUUD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPBUUDS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpbuuds(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPBUUDS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUUDS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPBUUDS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPBUUDS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPWSSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpwssd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPWSSD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPWSSD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPWSSD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPWSSDS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpwssds(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPWSSDS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSDS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPWSSDS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSDS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPWSSDS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSDS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPWSSDS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpwssds_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPWSSDS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSDS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPWSSDS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSDS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPWSSDS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSDS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPWSSDS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpwssds_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPWSSDS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSDS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPWSSDS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSDS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPWSSDS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSDS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPWSSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpwssd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPWSSD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPWSSD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPWSSD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPDPWSSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpdpwssd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPDPWSSD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPDPWSSD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPDPWSSD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPDPWSSD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERM2F128` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vperm2f128(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPERM2F128_256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPERM2F128_256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERM2I128` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vperm2i128(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPERM2I128_256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPERM2I128_256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2B` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2b(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2B128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2B128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2B256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2B256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2B512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2B512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2B_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2b_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2B128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2B128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2B256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2B256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2B512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2B512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2B_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2b_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2B128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2B128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2B256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2B256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2B512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2B512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2D` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2d(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2D128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2D128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2D256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2D256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2D512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2D512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2D_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2d_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2D128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2D128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2D256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2D256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2D512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2D512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2D_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2d_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2D128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2D128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2D256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2D256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2D512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2D512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2Q` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2q(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2Q128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2Q128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2Q256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2Q256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2Q512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2Q512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2Q_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2q_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2Q128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2Q128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2Q256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2Q256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2Q512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2Q512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2Q_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2q_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2Q128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2Q128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2Q256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2Q256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2Q512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2Q512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2W` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2w(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2W128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2W128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2W256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2W256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2W512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2W512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2W_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2w_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2W128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2W128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2W256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2W256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2W512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2W512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMI2W_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermi2w_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMI2W128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2W128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMI2W256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2W256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMI2W512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMI2W512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMILPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermilpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMILPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMILPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMILPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMILPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermilpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMILPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMILPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMILPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMILPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermilpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMILPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMILPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMILPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPD512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMILPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermilps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMILPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMILPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMILPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMILPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermilps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMILPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMILPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMILPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMILPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermilps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMILPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMILPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMILPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMILPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMILPS512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMPD512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPERMQ512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2B` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2b(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2B128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2B128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2B256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2B256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2B512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2B512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2B_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2b_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2B128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2B128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2B256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2B256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2B512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2B512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2B_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2b_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2B128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2B128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2B256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2B256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2B512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2B512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2D` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2d(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2D128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2D128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2D256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2D256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2D512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2D512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2D_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2d_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2D128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2D128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2D256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2D256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2D512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2D512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2D_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2d_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2D128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2D128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2D256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2D256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2D512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2D512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2pd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2PD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2PD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2PD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2pd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2PD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2PD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2PD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2pd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2PD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2PD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2PD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2ps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2PS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2PS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2PS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2ps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2PS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2PS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2PS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2ps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2PS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2PS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2PS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2PS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2Q` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2q(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2Q128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2Q128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2Q256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2Q256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2Q512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2Q512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2Q_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2q_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2Q128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2Q128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2Q256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2Q256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2Q512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2Q512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2Q_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2q_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2Q128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2Q128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2Q256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2Q256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2Q512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2Q512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2W` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2w(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2W128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2W128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2W256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2W256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2W512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2W512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2W_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2w_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2W128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2W128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2W256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2W256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2W512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2W512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMT2W_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermt2w_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMT2W128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2W128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMT2W256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2W256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMT2W512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMT2W512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPERMW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpermw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPERMW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPERMW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPERMW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPERMW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPERMW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPERMW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDB128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDB256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDB512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDB128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDB256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDB512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDB128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDB256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDB512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDW128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDW256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDW512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDW128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDW256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDW512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXPANDW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpexpandw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDW128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDW256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPEXPANDW512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPEXPANDW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPEXPANDW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPEXPANDW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXTRB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpextrb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPEXTRBMRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPEXTRBRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXTRD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpextrd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPEXTRDRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPEXTRDMRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXTRQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpextrq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPEXTRQRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPEXTRQMRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPEXTRQRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPEXTRW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpextrw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPEXTRWRRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPEXTRWMRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPGATHERDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpgatherdd_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPGATHERDD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPGATHERDD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPGATHERDD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPGATHERDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpgatherdd_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() && op2.is_vec128() {
            return Ok(Self { opcode: VPGATHERDD128RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_vec256() {
            return Ok(Self { opcode: VPGATHERDD256RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPGATHERDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpgatherdq_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPGATHERDQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPGATHERDQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPGATHERDQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPGATHERDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpgatherdq_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() && op2.is_vec128() {
            return Ok(Self { opcode: VPGATHERDQ128RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_vec256() {
            return Ok(Self { opcode: VPGATHERDQ256RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPGATHERQD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpgatherqd_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPGATHERQD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPGATHERQD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPGATHERQD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpgatherqd_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() && op2.is_vec128() {
            return Ok(Self { opcode: VPGATHERQD128RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPGATHERQQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpgatherqq_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPGATHERQQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPGATHERQQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPGATHERQQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPGATHERQQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpgatherqq_3(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mem() && op2.is_vec128() {
            return Ok(Self { opcode: VPGATHERQQ128RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_vec256() {
            return Ok(Self { opcode: VPGATHERQQ256RMR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPHADDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vphaddd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPHADDD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPHADDD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPHADDD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPHADDD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPHADDSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vphaddsw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPHADDSW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPHADDSW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPHADDSW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPHADDSW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPHADDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vphaddw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPHADDW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPHADDW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPHADDW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPHADDW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPHMINPOSUW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vphminposuw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPHMINPOSUW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPHMINPOSUW128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPHSUBD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vphsubd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPHSUBD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPHSUBD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPHSUBD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPHSUBD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPHSUBSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vphsubsw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPHSUBSW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPHSUBSW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPHSUBSW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPHSUBSW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPHSUBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vphsubw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPHSUBW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPHSUBW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPHSUBW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPHSUBW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPINSRB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpinsrb(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() && op3.is_imm() {
            return Ok(Self { opcode: VPINSRBRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPINSRBRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPINSRD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpinsrd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() && op3.is_imm() {
            return Ok(Self { opcode: VPINSRDRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPINSRDRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPINSRQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpinsrq(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() && op3.is_imm() {
            return Ok(Self { opcode: VPINSRQRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPINSRQRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp64() && op3.is_imm() {
            return Ok(Self { opcode: VPINSRQRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPINSRW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpinsrw(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_gp32() && op3.is_imm() {
            return Ok(Self { opcode: VPINSRWRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPINSRWRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPLZCNTD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vplzcntd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPLZCNTD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPLZCNTD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPLZCNTD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPLZCNTD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vplzcntd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPLZCNTD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPLZCNTD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPLZCNTD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPLZCNTD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vplzcntd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPLZCNTD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPLZCNTD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPLZCNTD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPLZCNTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vplzcntq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPLZCNTQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPLZCNTQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPLZCNTQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPLZCNTQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vplzcntq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPLZCNTQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPLZCNTQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPLZCNTQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPLZCNTQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vplzcntq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPLZCNTQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPLZCNTQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPLZCNTQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPLZCNTQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADD52HUQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmadd52huq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADD52HUQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52HUQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADD52HUQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52HUQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADD52HUQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52HUQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADD52HUQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmadd52huq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADD52HUQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52HUQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADD52HUQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52HUQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADD52HUQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52HUQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADD52HUQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmadd52huq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADD52HUQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52HUQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADD52HUQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52HUQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADD52HUQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52HUQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADD52LUQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmadd52luq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADD52LUQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52LUQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADD52LUQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52LUQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADD52LUQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52LUQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADD52LUQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmadd52luq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADD52LUQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52LUQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADD52LUQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52LUQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADD52LUQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52LUQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADD52LUQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmadd52luq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADD52LUQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52LUQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADD52LUQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52LUQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADD52LUQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADD52LUQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADDUBSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaddubsw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADDUBSW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDUBSW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADDUBSW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDUBSW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADDUBSW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDUBSW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADDUBSW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaddubsw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADDUBSW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDUBSW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADDUBSW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDUBSW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADDUBSW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDUBSW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADDUBSW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaddubsw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADDUBSW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDUBSW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADDUBSW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDUBSW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADDUBSW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDUBSW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADDWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaddwd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADDWD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDWD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADDWD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDWD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADDWD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDWD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADDWD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaddwd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADDWD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDWD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADDWD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDWD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADDWD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDWD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMADDWD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaddwd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMADDWD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDWD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMADDWD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDWD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMADDWD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMADDWD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMASKMOVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaskmovd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMASKMOVD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMASKMOVD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMASKMOVD128MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMASKMOVD256MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMASKMOVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaskmovq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMASKMOVQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMASKMOVQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMASKMOVQ128MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMASKMOVQ256MRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXSW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxsw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXSW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXSW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXSW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXSW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxub(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxub_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxub_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxud(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxud_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxud_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxuq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxuq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxuq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxuw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxuw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMAXUW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmaxuw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMAXUW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMAXUW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMAXUW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMAXUW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINSW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminsw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINSW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINSW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINSW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINSW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminub(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminub_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminub_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminud(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminud_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminud_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminuq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminuq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminuq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminuw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminuw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMINUW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpminuw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMINUW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMINUW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMINUW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMINUW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVB2M` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovb2m(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVB2M128KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVB2M256KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVB2M512KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVD2M` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovd2m(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVD2M128KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVD2M256KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVD2M512KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVDB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovdb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVDB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVDB128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVDB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVDB256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVDB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVDB512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVDB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovdb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVDB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVDB128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVDB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVDB256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVDB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVDB512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVDB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovdb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVDB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVDB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVDB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovdw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVDW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVDW128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVDW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVDW256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVDW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVDW512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVDW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovdw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVDW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVDW128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVDW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVDW256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVDW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVDW512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVDW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovdw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVDW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVDW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVDW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVM2B` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovm2b(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2B128RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2B256RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2B512RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVM2D` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovm2d(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2D128RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2D256RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2D512RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVM2Q` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovm2q(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2Q128RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2Q256RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2Q512RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVM2W` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovm2w(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2W128RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2W256RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mask() {
            return Ok(Self { opcode: VPMOVM2W512RK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVMSKB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovmskb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVMSKB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVMSKB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVQ2M` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovq2m(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQ2M128KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQ2M256KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQ2M512KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVQB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovqb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQB128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQB256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQB512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVQB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovqb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQB128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQB256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQB512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVQB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovqb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVQD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovqd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQD256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVQD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovqd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQD128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQD256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQD512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVQD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovqd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVQW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovqw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQW128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQW256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQW512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVQW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovqw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQW128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQW256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQW512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVQW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovqw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVQW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVQW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVQW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSDB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsdb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSDB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSDB128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSDB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSDB256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSDB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSDB512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSDB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsdb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSDB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSDB128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSDB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSDB256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSDB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSDB512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSDB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsdb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSDB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSDB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSDB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsdw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSDW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSDW128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSDW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSDW256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSDW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSDW512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSDW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsdw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSDW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSDW128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSDW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSDW256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSDW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSDW512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSDW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsdw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSDW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSDW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSDW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSQB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsqb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQB128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQB256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQB512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSQB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsqb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQB128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQB256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQB512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSQB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsqb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSQD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsqd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQD256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSQD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsqd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQD128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQD256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQD512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSQD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsqd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSQW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsqw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQW128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQW256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQW512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSQW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsqw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQW128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQW256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQW512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSQW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsqw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSQW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSQW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSQW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSWB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovswb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSWB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSWB128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSWB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSWB256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSWB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSWB512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSWB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovswb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSWB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSWB128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSWB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSWB256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSWB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSWB512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSWB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovswb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSWB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSWB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVSWB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXBD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxbd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXBD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxbd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXBD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxbd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXBQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxbq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXBQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxbq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXBQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxbq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxbw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBW128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBW256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSXBW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBW512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXBW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxbw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBW128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBW256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSXBW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBW512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXBW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxbw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBW128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXBW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBW256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSXBW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXBW512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxdq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXDQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXDQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXDQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXDQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSXDQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXDQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxdq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXDQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXDQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXDQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXDQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSXDQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXDQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxdq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXDQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXDQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXDQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXDQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSXDQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXDQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxwd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSXWD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXWD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxwd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSXWD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXWD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxwd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVSXWD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXWQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxwq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXWQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxwq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVSXWQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovsxwq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVSXWQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVSXWQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSDB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusdb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSDB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSDB128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSDB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSDB256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSDB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSDB512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSDB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusdb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSDB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSDB128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSDB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSDB256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSDB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSDB512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSDB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusdb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSDB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSDB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSDB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusdw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSDW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSDW128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSDW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSDW256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSDW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSDW512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSDW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusdw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSDW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSDW128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSDW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSDW256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSDW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSDW512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSDW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusdw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSDW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSDW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSDW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSQB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusqb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQB128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQB256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQB512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSQB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusqb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQB128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQB256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQB512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSQB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusqb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSQD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusqd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQD256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSQD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusqd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQD128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQD256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQD512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSQD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusqd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSQW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusqw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQW128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQW256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQW512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSQW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusqw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQW128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQW256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQW512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSQW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovusqw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSQW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSQW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSQW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSWB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovuswb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSWB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSWB128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSWB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSWB256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSWB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSWB512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSWB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovuswb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSWB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSWB128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSWB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSWB256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSWB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSWB512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVUSWB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovuswb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVUSWB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVUSWB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVUSWB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVW2M` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovw2m(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVW2M128KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVW2M256KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVW2M512KR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVWB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovwb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVWB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVWB128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVWB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVWB256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVWB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVWB512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVWB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovwb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVWB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVWB128MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVWB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVWB256MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVWB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVWB512MR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVWB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovwb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVWB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVWB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec512() {
            return Ok(Self { opcode: VPMOVWB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXBD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxbd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXBD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxbd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXBD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxbd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXBQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxbq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXBQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxbq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXBQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxbq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxbw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBW128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBW256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVZXBW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBW512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXBW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxbw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBW128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBW256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVZXBW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBW512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXBW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxbw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBW128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXBW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBW256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVZXBW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXBW512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxdq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXDQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXDQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXDQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXDQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVZXDQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXDQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxdq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXDQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXDQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXDQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXDQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVZXDQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXDQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxdq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXDQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXDQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXDQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXDQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVZXDQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXDQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxwd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVZXWD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXWD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxwd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVZXWD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXWD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxwd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec256() {
            return Ok(Self { opcode: VPMOVZXWD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXWQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxwq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXWQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxwq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMOVZXWQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmovzxwq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec128() {
            return Ok(Self { opcode: VPMOVZXWQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPMOVZXWQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmuldq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULDQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULDQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULDQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULDQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULDQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULDQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmuldq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULDQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULDQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULDQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULDQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULDQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULDQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmuldq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULDQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULDQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULDQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULDQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULDQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULDQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULHRSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulhrsw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULHRSW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHRSW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULHRSW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHRSW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULHRSW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHRSW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULHRSW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulhrsw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULHRSW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHRSW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULHRSW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHRSW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULHRSW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHRSW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULHRSW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulhrsw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULHRSW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHRSW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULHRSW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHRSW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULHRSW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHRSW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULHUW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulhuw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULHUW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHUW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULHUW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHUW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULHUW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHUW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULHUW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulhuw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULHUW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHUW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULHUW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHUW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULHUW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHUW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULHUW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulhuw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULHUW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHUW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULHUW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHUW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULHUW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHUW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULHW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulhw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULHW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULHW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULHW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULHW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulhw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULHW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULHW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULHW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULHW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulhw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULHW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULHW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULHW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULHW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulld(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULLD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULLD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULLD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULLD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulld_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULLD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULLD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULLD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULLD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmulld_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULLD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULLD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULLD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULLQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmullq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULLQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULLQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULLQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULLQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmullq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULLQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULLQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULLQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULLQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmullq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULLQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULLQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULLQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmullw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULLW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULLW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULLW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULLW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmullw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULLW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULLW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULLW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULLW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmullw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULLW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULLW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULLW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULLW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULTISHIFTQB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmultishiftqb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULTISHIFTQB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULTISHIFTQB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULTISHIFTQB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULTISHIFTQB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULTISHIFTQB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULTISHIFTQB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULTISHIFTQB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmultishiftqb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULTISHIFTQB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULTISHIFTQB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULTISHIFTQB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULTISHIFTQB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULTISHIFTQB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULTISHIFTQB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULTISHIFTQB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmultishiftqb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULTISHIFTQB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULTISHIFTQB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULTISHIFTQB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULTISHIFTQB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULTISHIFTQB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULTISHIFTQB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULUDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmuludq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULUDQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULUDQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULUDQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULUDQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULUDQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULUDQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULUDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmuludq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULUDQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULUDQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULUDQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULUDQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULUDQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULUDQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPMULUDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpmuludq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPMULUDQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPMULUDQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPMULUDQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPMULUDQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPMULUDQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPMULUDQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntb(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTB128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTB128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTB256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTB256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTB512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTB512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntb_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTB128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTB128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTB256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTB256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTB512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTB512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntb_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTB128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTB128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTB256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTB256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTB512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTB512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTQ128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTQ128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTQ256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTQ256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTQ512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTQ512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntq_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTQ128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTQ128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTQ256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTQ256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTQ512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTQ512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntq_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTQ128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTQ128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTQ256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTQ256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTQ512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTQ512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntw(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTW128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTW128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTW256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTW256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTW512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTW512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntw_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTW128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTW128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTW256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTW256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTW512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTW512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOPCNTW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpopcntw_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPOPCNTW128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTW128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPOPCNTW256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTW256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VPOPCNTW512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VPOPCNTW512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpor(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPOR128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPOR128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPOR256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPOR256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPORD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpord(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPORD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPORD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPORD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPORD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPORD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPORD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPORD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpord_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPORD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPORD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPORD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPORD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPORD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPORD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPORD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpord_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPORD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPORD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPORD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPORD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPORD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPORD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPORQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vporq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPORQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPORQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPORQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPORQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPORQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPORQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPORQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vporq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPORQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPORQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPORQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPORQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPORQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPORQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPORQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vporq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPORQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPORQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPORQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPORQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPORQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPORQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprold(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprold_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprold_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLD512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprolq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprolq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprolq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPROLQ512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprolvd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPROLVD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPROLVD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPROLVD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLVD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprolvd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPROLVD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPROLVD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPROLVD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLVD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprolvd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPROLVD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPROLVD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPROLVD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprolvq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPROLVQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPROLVQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPROLVQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLVQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprolvq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPROLVQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPROLVQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPROLVQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPROLVQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprolvq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPROLVQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPROLVQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPROLVQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPROLVQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprord(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprord_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprord_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORD512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprorq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprorq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprorq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPRORQ512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprorvd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPRORVD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPRORVD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPRORVD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORVD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprorvd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPRORVD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPRORVD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPRORVD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORVD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprorvd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPRORVD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPRORVD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPRORVD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprorvq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPRORVQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPRORVQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPRORVQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORVQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprorvq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPRORVQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPRORVQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPRORVQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPRORVQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vprorvq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPRORVQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPRORVQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPRORVQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPRORVQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSADBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsadbw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSADBW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSADBW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSADBW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSADBW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSADBW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSADBW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSCATTERDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpscatterdd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPSCATTERDD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPSCATTERDD256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPSCATTERDD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSCATTERDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpscatterdq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPSCATTERDQ128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPSCATTERDQ256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPSCATTERDQ512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSCATTERQD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpscatterqd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPSCATTERQD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPSCATTERQD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSCATTERQQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpscatterqq(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VPSCATTERQQ128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VPSCATTERQQ256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VPSCATTERQQ512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDD512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldq(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldq_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldq_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDQ512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldvd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHLDVD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHLDVD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHLDVD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDVD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldvd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHLDVD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHLDVD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHLDVD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDVD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldvd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHLDVD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHLDVD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHLDVD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldvq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHLDVQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHLDVQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHLDVQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDVQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldvq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHLDVQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHLDVQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHLDVQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDVQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldvq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHLDVQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHLDVQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHLDVQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDVW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldvw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHLDVW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHLDVW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHLDVW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDVW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldvw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHLDVW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHLDVW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHLDVW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDVW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldvw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHLDVW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHLDVW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHLDVW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHLDVW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldw(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldw_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHLDW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshldw_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHLDW512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDD512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdq(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdq_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdq_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDQ512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdvd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHRDVD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHRDVD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHRDVD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDVD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdvd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHRDVD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHRDVD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHRDVD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDVD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdvd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHRDVD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHRDVD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHRDVD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdvq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHRDVQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHRDVQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHRDVQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDVQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdvq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHRDVQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHRDVQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHRDVQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDVQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdvq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHRDVQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHRDVQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHRDVQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDVW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdvw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHRDVW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHRDVW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHRDVW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDVW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdvw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHRDVW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHRDVW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHRDVW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDVW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdvw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHRDVW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHRDVW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHRDVW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHRDVW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdw(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdw_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHRDW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshrdw_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPSHRDW512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshufb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHUFB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHUFB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHUFB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFBITQMB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshufbitqmb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHUFBITQMB128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFBITQMB128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHUFBITQMB256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFBITQMB256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHUFBITQMB512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFBITQMB512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFBITQMB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshufbitqmb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHUFBITQMB128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFBITQMB128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHUFBITQMB256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFBITQMB256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHUFBITQMB512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFBITQMB512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshufb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHUFB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHUFB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHUFB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshufb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSHUFB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSHUFB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSHUFB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSHUFB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshufd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshufd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshufd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFD512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFHW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshufhw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFHW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshufhw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFHW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshufhw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFHW512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshuflw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFLW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshuflw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSHUFLW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpshuflw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSHUFLW512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSIGNB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsignb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSIGNB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSIGNB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSIGNB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSIGNB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSIGND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsignd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSIGND128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSIGND128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSIGND256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSIGND256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSIGNW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsignw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSIGNW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSIGNW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSIGNW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSIGNW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpslld(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpslldq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLDQ128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLDQ256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLDQ128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLDQ256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLDQ512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLDQ512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpslld_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpslld_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLD512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLQ512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllvd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLVD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSLLVD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSLLVD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLVD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllvd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLVD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSLLVD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSLLVD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLVD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllvd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLVD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSLLVD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSLLVD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllvq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLVQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSLLVQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSLLVQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLVQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllvq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLVQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSLLVQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSLLVQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLVQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllvq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLVQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSLLVQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSLLVQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLVW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllvw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLVW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSLLVW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSLLVW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLVW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllvw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLVW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSLLVW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSLLVW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLVW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllvw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLVW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSLLVW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSLLVW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLVW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSLLW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsllw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSLLW512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSLLW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSLLW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrad(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrad_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrad_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAD512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsraq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsraq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsraq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAQ512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsravd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAVD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRAVD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRAVD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAVD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsravd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAVD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRAVD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRAVD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAVD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsravd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAVD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRAVD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRAVD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsravq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAVQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRAVQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRAVQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAVQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsravq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAVQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRAVQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRAVQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAVQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsravq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAVQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRAVQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRAVQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAVW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsravw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAVW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRAVW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRAVW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAVW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsravw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAVW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRAVW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRAVW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAVW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsravw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAVW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRAVW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRAVW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAVW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsraw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsraw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRAW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsraw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRAW512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRAW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRAW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrld(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrldq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLDQ128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLDQ256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLDQ128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLDQ256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLDQ512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLDQ512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrld_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrld_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLD512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLQ512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlvd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLVD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRLVD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRLVD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLVD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlvd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLVD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRLVD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRLVD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLVD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlvd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLVD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRLVD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRLVD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLVQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlvq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLVQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRLVQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRLVQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLVQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlvq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLVQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRLVQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRLVQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLVQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlvq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLVQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRLVQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRLVQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLVW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlvw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLVW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRLVW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRLVW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLVW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlvw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLVW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRLVW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRLVW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLVW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlvw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLVW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSRLVW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSRLVW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLVW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSRLW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsrlw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VPSRLW512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec128() {
            return Ok(Self { opcode: VPSRLW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSRLW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubsb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBSB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBSB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBSB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBSB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubsb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBSB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBSB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBSB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBSB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubsb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBSB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBSB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBSB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubsw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBSW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBSW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBSW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBSW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubsw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBSW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBSW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBSW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBSW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubsw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBSW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBSW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBSW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBSW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBUSB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubusb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBUSB128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSB128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBUSB256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSB256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBUSB512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSB512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBUSB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubusb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBUSB128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSB128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBUSB256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSB256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBUSB512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSB512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBUSB_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubusb_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBUSB128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSB128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBUSB256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSB256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBUSB512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSB512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBUSW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubusw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBUSW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBUSW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBUSW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBUSW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubusw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBUSW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBUSW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBUSW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBUSW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubusw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBUSW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBUSW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBUSW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBUSW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPSUBW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpsubw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPSUBW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPSUBW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPSUBW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPSUBW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTERNLOGD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpternlogd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTERNLOGD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpternlogd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTERNLOGD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpternlogd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGD512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTERNLOGQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpternlogq(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTERNLOGQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpternlogq_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTERNLOGQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpternlogq_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VPTERNLOGQ512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTEST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptest(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VPTEST128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VPTEST128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VPTEST256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VPTEST256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTMB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestmb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTMB128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMB128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTMB256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMB256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTMB512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMB512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTMB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestmb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTMB128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMB128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTMB256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMB256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTMB512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMB512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTMD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestmd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTMD128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMD128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTMD256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMD256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTMD512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMD512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTMD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestmd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTMD128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMD128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTMD256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMD256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTMD512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMD512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTMQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestmq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTMQ128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMQ128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTMQ256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMQ256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTMQ512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMQ512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTMQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestmq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTMQ128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMQ128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTMQ256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMQ256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTMQ512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMQ512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTMW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestmw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTMW128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMW128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTMW256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMW256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTMW512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMW512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTMW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestmw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTMW128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMW128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTMW256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMW256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTMW512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTMW512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTNMB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestnmb(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTNMB128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMB128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTNMB256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMB256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTNMB512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMB512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTNMB_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestnmb_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTNMB128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMB128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTNMB256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMB256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTNMB512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMB512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTNMD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestnmd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTNMD128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMD128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTNMD256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMD256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTNMD512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMD512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTNMD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestnmd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTNMD128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMD128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTNMD256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMD256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTNMD512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMD512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTNMQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestnmq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTNMQ128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMQ128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTNMQ256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMQ256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTNMQ512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMQ512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTNMQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestnmq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTNMQ128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMQ128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTNMQ256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMQ256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTNMQ512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMQ512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTNMW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestnmw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTNMW128KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMW128KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTNMW256KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMW256KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTNMW512KRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMW512KRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPTESTNMW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vptestnmw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_mask() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPTESTNMW128KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMW128KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPTESTNMW256KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMW256KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPTESTNMW512KRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_mask() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPTESTNMW512KRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhbw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHBW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHBW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHBW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHBW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHBW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHBW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHBW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhbw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHBW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHBW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHBW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHBW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHBW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHBW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHBW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhbw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHBW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHBW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHBW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHBW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHBW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHBW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhdq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHDQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHDQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHDQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHDQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHDQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHDQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhdq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHDQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHDQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHDQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHDQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHDQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHDQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhdq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHDQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHDQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHDQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHDQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHDQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHDQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHQDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhqdq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHQDQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHQDQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHQDQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHQDQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHQDQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHQDQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHQDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhqdq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHQDQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHQDQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHQDQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHQDQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHQDQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHQDQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHQDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhqdq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHQDQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHQDQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHQDQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHQDQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHQDQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHQDQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhwd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHWD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHWD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHWD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHWD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHWD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHWD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHWD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhwd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHWD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHWD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHWD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHWD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHWD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHWD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKHWD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckhwd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKHWD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHWD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKHWD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHWD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKHWD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKHWD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLBW` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpcklbw(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLBW128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLBW128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLBW256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLBW256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLBW512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLBW512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLBW_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpcklbw_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLBW128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLBW128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLBW256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLBW256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLBW512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLBW512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLBW_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpcklbw_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLBW128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLBW128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLBW256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLBW256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLBW512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLBW512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckldq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLDQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLDQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLDQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLDQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLDQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLDQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckldq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLDQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLDQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLDQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLDQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLDQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLDQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpckldq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLDQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLDQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLDQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLDQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLDQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLDQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLQDQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpcklqdq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLQDQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLQDQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLQDQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLQDQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLQDQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLQDQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLQDQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpcklqdq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLQDQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLQDQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLQDQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLQDQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLQDQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLQDQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLQDQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpcklqdq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLQDQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLQDQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLQDQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLQDQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLQDQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLQDQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLWD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpcklwd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLWD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLWD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLWD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLWD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLWD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLWD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLWD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpcklwd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLWD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLWD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLWD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLWD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLWD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLWD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPUNPCKLWD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpunpcklwd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPUNPCKLWD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLWD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPUNPCKLWD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLWD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPUNPCKLWD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPUNPCKLWD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPXOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpxor(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPXOR128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPXOR128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPXOR256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPXOR256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPXORD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpxord(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPXORD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPXORD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPXORD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPXORD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPXORD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPXORD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPXORD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpxord_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPXORD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPXORD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPXORD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPXORD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPXORD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPXORD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPXORD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpxord_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPXORD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPXORD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPXORD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPXORD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPXORD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPXORD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPXORQ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpxorq(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPXORQ128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPXORQ128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPXORQ256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPXORQ256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPXORQ512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPXORQ512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPXORQ_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpxorq_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPXORQ128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPXORQ128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPXORQ256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPXORQ256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPXORQ512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPXORQ512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VPXORQ_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vpxorq_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VPXORQ128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VPXORQ128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VPXORQ256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VPXORQ256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VPXORQ512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VPXORQ512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangepd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangepd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangepd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD512RRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangepd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangepd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD512RRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangepd_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPD512RRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangeps(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangeps_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangeps_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS512RRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangeps_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangeps_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS512RRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGEPS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangeps_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VRANGEPS512RRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangesd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESDRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESDRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangesd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESDRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESDRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangesd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESDRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangesd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESDRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESDRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangesd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESDRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangesd_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESDRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangess(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESSRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESSRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangess_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESSRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESSRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangess_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESSRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangess_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESSRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESSRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangess_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESSRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRANGESS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrangess_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRANGESSRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14pd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRCP14PD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRCP14PD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRCP14PD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14pd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRCP14PD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRCP14PD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRCP14PD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14pd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRCP14PD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRCP14PD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRCP14PD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRCP14PS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRCP14PS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRCP14PS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14ps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRCP14PS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRCP14PS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PS256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRCP14PS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14ps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRCP14PS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRCP14PS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PS256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRCP14PS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRCP14PS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRCP14SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRCP14SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRCP14SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRCP14SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRCP14SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRCP14SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRCP14SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRCP14SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRCP14SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRCP14SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCP14SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcp14ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRCP14SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRCP14SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCPPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcpph(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRCPPH128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRCPPH128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRCPPH256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRCPPH256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRCPPH512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRCPPH512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCPPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcpph_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRCPPH128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRCPPH128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRCPPH256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRCPPH256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRCPPH512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRCPPH512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCPPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcpph_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRCPPH128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRCPPH128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRCPPH256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRCPPH256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRCPPH512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRCPPH512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCPPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcpps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRCPPS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRCPPS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRCPPS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRCPPS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCPSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcpsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRCPSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRCPSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCPSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcpsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRCPSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRCPSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCPSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcpsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRCPSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRCPSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRCPSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrcpss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRCPSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRCPSSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducepd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducepd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducepd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD512RRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducepd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducepd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD512RRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducepd_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPD512RRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceph_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH512RRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceph_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH512RRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceph_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPH512RRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceps_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS512RRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceps_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS512RRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCEPS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreduceps_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VREDUCEPS512RRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESDRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESDRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESDRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESDRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESDRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESDRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESDRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESDRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesd_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESDRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesh(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESHRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESHRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesh_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESHRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESHRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesh_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESHRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesh_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESHRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESHRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesh_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESHRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducesh_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESHRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducess(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESSRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESSRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducess_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESSRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESSRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducess_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESSRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducess_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESSRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESSRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducess_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESSRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VREDUCESS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vreducess_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VREDUCESSRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalepd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalepd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalepd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD512RRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalepd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalepd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD512RRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalepd_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPD512RRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleph_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH512RRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleph_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH512RRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleph_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPH512RRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS512RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS512RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS128RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS128RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS256RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS256RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS512RRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS512RMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleps_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS512RRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS128RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS128RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS256RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS256RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS512RRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS512RMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleps_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS512RRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALEPS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaleps_sae(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_imm() {
            return Ok(Self { opcode: VRNDSCALEPS512RRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESDRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESDRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESDRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESDRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESD_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesd_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESDRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESDRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESDRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESD_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesd_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESDRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesd_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESDRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesh(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESHRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESHRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesh_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESHRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESHRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESH_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesh_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESHRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesh_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESHRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESHRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESH_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesh_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESHRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscalesh_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESHRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaless(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESSRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESSRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaless_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESSRRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESSRRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESS_MASK_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaless_mask_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESSRRRI_MASK_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaless_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESSRRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESSRRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESS_MASKZ_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaless_maskz_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESSRRRI_MASKZ_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRNDSCALESS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrndscaless_sae(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VRNDSCALESSRRRI_SAE, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VROUNDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vroundpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VROUNDPD128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VROUNDPD128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VROUNDPD256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VROUNDPD256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VROUNDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vroundps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_imm() {
            return Ok(Self { opcode: VROUNDPS128RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VROUNDPS128RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_imm() {
            return Ok(Self { opcode: VROUNDPS256RRI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() && op2.is_imm() {
            return Ok(Self { opcode: VROUNDPS256RMI, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VROUNDSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vroundsd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VROUNDSDRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VROUNDSDRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VROUNDSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vroundss(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VROUNDSSRRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VROUNDSSRRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14PD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14pd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRSQRT14PD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRSQRT14PD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRSQRT14PD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14PD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14pd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRSQRT14PD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRSQRT14PD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRSQRT14PD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14PD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14pd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRSQRT14PD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRSQRT14PD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRSQRT14PD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14PS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14ps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRSQRT14PS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRSQRT14PS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRSQRT14PS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14PS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14ps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRSQRT14PS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRSQRT14PS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PS256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRSQRT14PS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14PS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14ps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRSQRT14PS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRSQRT14PS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PS256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRSQRT14PS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRT14PS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14SD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14sd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRSQRT14SDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRSQRT14SDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14SD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14sd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRSQRT14SDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRSQRT14SDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14SD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14sd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRSQRT14SDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRSQRT14SDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14SS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14ss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRSQRT14SSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRSQRT14SSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14SS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14ss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRSQRT14SSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRSQRT14SSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRT14SS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrt14ss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRSQRT14SSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRSQRT14SSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRTPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrtph(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRSQRTPH128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRTPH128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRSQRTPH256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRTPH256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRSQRTPH512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRTPH512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRTPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrtph_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRSQRTPH128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRTPH128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRSQRTPH256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRTPH256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRSQRTPH512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRTPH512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRTPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrtph_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRSQRTPH128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRTPH128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRSQRTPH256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRTPH256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VRSQRTPH512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRTPH512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrtps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VRSQRTPS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRTPS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VRSQRTPS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VRSQRTPS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRTSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrtsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRSQRTSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRSQRTSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRTSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrtsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRSQRTSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRSQRTSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRTSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrtsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRSQRTSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRSQRTSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VRSQRTSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vrsqrtss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VRSQRTSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VRSQRTSSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSCALEFPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefpd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSCALEFPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefpd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSCALEFPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefpd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFPH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSCALEFPH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFPH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSCALEFPH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFPH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSCALEFPH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSCALEFPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSCALEFPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSCALEFPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFPS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSCALEFPS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFSDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFSDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFSDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefsh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFSSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFSSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSCALEFSSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCALEFSS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscalefss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSCALEFSSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCATTERDPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscatterdpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VSCATTERDPD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VSCATTERDPD256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VSCATTERDPD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCATTERDPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscatterdps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VSCATTERDPS128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VSCATTERDPS256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VSCATTERDPS512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCATTERQPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscatterqpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VSCATTERQPD128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VSCATTERQPD256MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec512() {
            return Ok(Self { opcode: VSCATTERQPD512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSCATTERQPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vscatterqps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_vec128() {
            return Ok(Self { opcode: VSCATTERQPS128MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_vec256() {
            return Ok(Self { opcode: VSCATTERQPS512MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFF32X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshuff32x4(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFF32X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshuff32x4_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFF32X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshuff32x4_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF32X4_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFF64X2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshuff64x2(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFF64X2_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshuff64x2_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFF64X2_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshuff64x2_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFF64X2_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFI32X4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufi32x4(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFI32X4_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufi32x4_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFI32X4_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufi32x4_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI32X4_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFI64X2` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufi64x2(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFI64X2_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufi64x2_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFI64X2_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufi64x2_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFI64X2_512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufpd(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufpd_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPD512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufps(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS128RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS128RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS256RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS256RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS512RRRI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS512RRMI, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufps_mask(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS128RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS128RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS256RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS256RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS512RRRI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS512RRMI_MASK, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSHUFPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vshufps_maskz(op0: &Operand, op1: &Operand, op2: &Operand, op3: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS128RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS128RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS256RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS256RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS512RRRI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() && op3.is_imm() {
            return Ok(Self { opcode: VSHUFPS512RRMI_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: *op3 });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSM4KEY4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsm4key4(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSM4KEY4_128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSM4KEY4_128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSM4KEY4_256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSM4KEY4_256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSM4KEY4_512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSM4KEY4_512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSM4RNDS4` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsm4rnds4(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSM4RNDS4_128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSM4RNDS4_128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSM4RNDS4_256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSM4RNDS4_256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSM4RNDS4_512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSM4RNDS4_512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VSQRTPD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VSQRTPD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPD512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPD512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtpd_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPD512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtpd_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VSQRTPD128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPD128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VSQRTPD256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPD256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPD512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPD512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtpd_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPD512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtpd_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VSQRTPD128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPD128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VSQRTPD256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPD256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPD512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPD512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtpd_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPD512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtph(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VSQRTPH128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPH128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VSQRTPH256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPH256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPH512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPH512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtph_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPH512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtph_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VSQRTPH128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPH128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VSQRTPH256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPH256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPH512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPH512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtph_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPH512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtph_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VSQRTPH128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPH128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VSQRTPH256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPH256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPH512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPH512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtph_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPH512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VSQRTPS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VSQRTPS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPS512RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPS512RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtps_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPS512RR_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtps_mask(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VSQRTPS128RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPS128RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VSQRTPS256RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPS256RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPS512RR_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPS512RM_MASK, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtps_mask_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPS512RR_MASK_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtps_maskz(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VSQRTPS128RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPS128RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VSQRTPS256RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPS256RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPS512RR_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_mem() {
            return Ok(Self { opcode: VSQRTPS512RM_MASKZ, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTPS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtps_maskz_er(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() {
            return Ok(Self { opcode: VSQRTPS512RR_MASKZ_ER, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSQRTSDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSQRTSDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSQRTSDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSQRTSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSQRTSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSQRTSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtsh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSQRTSSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSQRTSSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSQRTSSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSQRTSS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsqrtss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSQRTSSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSTMXCSR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vstmxcsr(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: VSTMXCSRM, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSUBPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubpd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPD512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSUBPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubpd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPD512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSUBPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubpd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPD512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubph(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBPH128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPH128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSUBPH256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPH256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPH512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPH512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubph_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPH512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubph_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBPH128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPH128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSUBPH256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPH256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPH512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPH512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubph_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPH512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubph_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBPH128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPH128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSUBPH256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPH256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPH512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPH512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubph_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPH512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSUBPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubps_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPS512RRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSUBPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubps_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPS512RRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VSUBPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VSUBPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBPS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubps_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VSUBPS512RRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSDRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBSDRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSD_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsd_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSDRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSDRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBSDRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSD_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsd_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSDRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSDRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBSDRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSD_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsd_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSDRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsh(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSHRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBSHRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSH_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsh_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSHRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSH_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsh_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSHRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBSHRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSH_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsh_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSHRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSH_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsh_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSHRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBSHRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSH_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubsh_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSHRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubss(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSSRRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBSSRRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSS_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubss_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSSRRR_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubss_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSSRRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBSSRRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSS_MASK_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubss_mask_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSSRRR_MASK_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubss_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSSRRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VSUBSSRRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VSUBSS_MASKZ_ER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vsubss_maskz_er(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VSUBSSRRR_MASKZ_ER, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VTESTPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vtestpd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VTESTPD128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VTESTPD128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VTESTPD256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VTESTPD256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VTESTPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vtestps(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VTESTPS128RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VTESTPS128RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() {
            return Ok(Self { opcode: VTESTPS256RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_mem() {
            return Ok(Self { opcode: VTESTPS256RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUCOMISD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vucomisd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VUCOMISDRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VUCOMISDRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUCOMISD_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vucomisd_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VUCOMISDRR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUCOMISH` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vucomish(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VUCOMISHRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VUCOMISHRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUCOMISH_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vucomish_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VUCOMISHRR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUCOMISS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vucomiss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VUCOMISSRR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_mem() {
            return Ok(Self { opcode: VUCOMISSRM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUCOMISS_SAE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vucomiss_sae(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() {
            return Ok(Self { opcode: VUCOMISSRR_SAE, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKHPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpckhpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKHPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKHPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKHPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKHPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpckhpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKHPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKHPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKHPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKHPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpckhpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKHPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKHPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKHPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKHPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpckhps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKHPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKHPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKHPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKHPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpckhps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKHPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKHPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKHPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKHPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpckhps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKHPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKHPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKHPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKHPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKLPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpcklpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKLPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKLPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKLPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKLPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpcklpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKLPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKLPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKLPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKLPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpcklpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKLPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKLPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKLPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKLPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpcklps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKLPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKLPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKLPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKLPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpcklps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKLPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKLPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKLPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VUNPCKLPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vunpcklps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VUNPCKLPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VUNPCKLPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VUNPCKLPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VUNPCKLPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VXORPD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vxorpd(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VXORPD128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VXORPD128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VXORPD256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VXORPD256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VXORPD512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VXORPD512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VXORPD_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vxorpd_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VXORPD128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VXORPD128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VXORPD256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VXORPD256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VXORPD512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VXORPD512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VXORPD_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vxorpd_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VXORPD128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VXORPD128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VXORPD256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VXORPD256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VXORPD512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VXORPD512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VXORPS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vxorps(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VXORPS128RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VXORPS128RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VXORPS256RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VXORPS256RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VXORPS512RRR, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VXORPS512RRM, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VXORPS_MASK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vxorps_mask(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VXORPS128RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VXORPS128RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VXORPS256RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VXORPS256RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VXORPS512RRR_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VXORPS512RRM_MASK, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VXORPS_MASKZ` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vxorps_maskz(op0: &Operand, op1: &Operand, op2: &Operand) -> Result<Self, AsmError> {
        if op0.is_vec128() && op1.is_vec128() && op2.is_vec128() {
            return Ok(Self { opcode: VXORPS128RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec128() && op1.is_vec128() && op2.is_mem() {
            return Ok(Self { opcode: VXORPS128RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_vec256() {
            return Ok(Self { opcode: VXORPS256RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec256() && op1.is_vec256() && op2.is_mem() {
            return Ok(Self { opcode: VXORPS256RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_vec512() {
            return Ok(Self { opcode: VXORPS512RRR_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        if op0.is_vec512() && op1.is_vec512() && op2.is_mem() {
            return Ok(Self { opcode: VXORPS512RRM_MASKZ, op0: *op0, op1: *op1, op2: *op2, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `VZEROALL` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vzeroall() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VZEROALL, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `VZEROUPPER` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn vzeroupper() -> Result<Self, AsmError> {
        return Ok(Self { opcode: VZEROUPPER, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `WBINVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn wbinvd() -> Result<Self, AsmError> {
        return Ok(Self { opcode: WBINVD, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `WBNOINVD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn wbnoinvd() -> Result<Self, AsmError> {
        return Ok(Self { opcode: WBNOINVD, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `WRFSBASE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn wrfsbase(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: WRFSBASE32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: WRFSBASE64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `WRGSBASE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn wrgsbase(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_gp32() {
            return Ok(Self { opcode: WRGSBASE32R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() {
            return Ok(Self { opcode: WRGSBASE64R, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `WRMSR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn wrmsr() -> Result<Self, AsmError> {
        return Ok(Self { opcode: WRMSR, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `WRMSRLIST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn wrmsrlist() -> Result<Self, AsmError> {
        return Ok(Self { opcode: WRMSRLIST, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `WRMSRNS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn wrmsrns() -> Result<Self, AsmError> {
        return Ok(Self { opcode: WRMSRNS, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `WRMSRNS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn wrmsrns_2(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() && op1.is_gp32() {
            return Ok(Self { opcode: WRMSRNSIR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `WRPKRU` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn wrpkru() -> Result<Self, AsmError> {
        return Ok(Self { opcode: WRPKRU, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `WRSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn wrss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: WRSS32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: WRSS64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `WRUSS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn wruss(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: WRUSS32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: WRUSS64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XABORT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xabort(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: XABORTI, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XADD` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xadd(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: XADD8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: XADD8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: XADD16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: XADD16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: XADD32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: XADD32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: XADD64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: XADD64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XBEGIN` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xbegin(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_imm() {
            return Ok(Self { opcode: XBEGIN, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_sym() {
            return Ok(Self { opcode: XBEGIN, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        if op0.is_label() {
            return Ok(Self { opcode: XBEGIN, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XCHG` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xchg(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: XCHG8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: XCHG8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: XCHG16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: XCHG16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: XCHG32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: XCHG32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: XCHG64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: XCHG64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XEND` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xend() -> Result<Self, AsmError> {
        return Ok(Self { opcode: XEND, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `XGETBV` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xgetbv() -> Result<Self, AsmError> {
        return Ok(Self { opcode: XGETBV, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `XLATB` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xlatb() -> Result<Self, AsmError> {
        return Ok(Self { opcode: XLATB, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `XOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xor(op0: &Operand, op1: &Operand) -> Result<Self, AsmError> {
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: XOR8RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp8Lo) {
            return Ok(Self { opcode: XOR8MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: XOR16RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_reg_type_of(RegType::Gp16) {
            return Ok(Self { opcode: XOR16MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_gp32() {
            return Ok(Self { opcode: XOR32RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp32() {
            return Ok(Self { opcode: XOR32MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_gp64() {
            return Ok(Self { opcode: XOR64RR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_gp64() {
            return Ok(Self { opcode: XOR64MR, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_mem() {
            return Ok(Self { opcode: XOR8RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_mem() {
            return Ok(Self { opcode: XOR16RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_mem() {
            return Ok(Self { opcode: XOR32RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_mem() {
            return Ok(Self { opcode: XOR64RM, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp8Lo) && op1.is_imm() {
            return Ok(Self { opcode: XOR8RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_reg_type_of(RegType::Gp16) && op1.is_imm() {
            return Ok(Self { opcode: XOR16RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp32() && op1.is_imm() {
            return Ok(Self { opcode: XOR32RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_gp64() && op1.is_imm() {
            return Ok(Self { opcode: XOR64RI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        if op0.is_mem() && op1.is_imm() {
            return Ok(Self { opcode: XOR8MI, op0: *op0, op1: *op1, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XRESLDTRK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xresldtrk() -> Result<Self, AsmError> {
        return Ok(Self { opcode: XRESLDTRK, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `XRSTOR` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xrstor(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: XRSTOR32M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XRSTORS` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xrstors(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: XRSTORS32M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XSAVE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xsave(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: XSAVE32M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XSAVEC` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xsavec(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: XSAVEC32M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XSAVEOPT` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xsaveopt(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: XSAVEOPT32M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XSAVES` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xsaves(op0: &Operand) -> Result<Self, AsmError> {
        if op0.is_mem() {
            return Ok(Self { opcode: XSAVES32M, op0: *op0, op1: NOREG, op2: NOREG, op3: NOREG });
        }
        Err(AsmError::InvalidOperand)
    }

    /// Construct a dynamically typed `XSETBV` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xsetbv() -> Result<Self, AsmError> {
        return Ok(Self { opcode: XSETBV, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `XSTORE` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xstore() -> Result<Self, AsmError> {
        return Ok(Self { opcode: XSTORE, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `XSUSLDTRK` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xsusldtrk() -> Result<Self, AsmError> {
        return Ok(Self { opcode: XSUSLDTRK, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }

    /// Construct a dynamically typed `XTEST` instruction.
    /// Checks operand types at runtime; returns `Err` if types do not match.
    pub fn xtest() -> Result<Self, AsmError> {
        return Ok(Self { opcode: XTEST, op0: NOREG, op1: NOREG, op2: NOREG, op3: NOREG });
    }


    /// Build an instruction from a mnemonic string and a slice of operands,
    /// performing runtime operand-type checking.
    ///
    /// # Errors
    /// - [`AsmError::InvalidInstruction`] — unknown mnemonic.
    /// - [`AsmError::InvalidOperand`] — operand count or types do not match.
    pub fn from_mnem(mnem: &str, ops: &[Operand]) -> Result<Self, AsmError> {
        let mnem_l = mnem.to_ascii_lowercase();
        match mnem_l.as_str() {
            "_3dnow" => {
                if ops.len() == 3 {
                    Self::_3dnow(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aadd" => {
                if ops.len() == 2 {
                    Self::aadd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aand" => {
                if ops.len() == 2 {
                    Self::aand(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "adc" => {
                if ops.len() == 2 {
                    Self::adc(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "adcx" => {
                if ops.len() == 2 {
                    Self::adcx(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "add" => {
                if ops.len() == 2 {
                    Self::add(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "adox" => {
                if ops.len() == 2 {
                    Self::adox(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesdec" => {
                if ops.len() == 2 {
                    Self::aesdec(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesdec128kl" => {
                if ops.len() == 2 {
                    Self::aesdec128kl(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesdec256kl" => {
                if ops.len() == 2 {
                    Self::aesdec256kl(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesdeclast" => {
                if ops.len() == 2 {
                    Self::aesdeclast(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesdecwide128kl" => {
                if ops.len() == 1 {
                    Self::aesdecwide128kl(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesdecwide256kl" => {
                if ops.len() == 1 {
                    Self::aesdecwide256kl(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesenc" => {
                if ops.len() == 2 {
                    Self::aesenc(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesenc128kl" => {
                if ops.len() == 2 {
                    Self::aesenc128kl(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesenc256kl" => {
                if ops.len() == 2 {
                    Self::aesenc256kl(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesenclast" => {
                if ops.len() == 2 {
                    Self::aesenclast(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesencwide128kl" => {
                if ops.len() == 1 {
                    Self::aesencwide128kl(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesencwide256kl" => {
                if ops.len() == 1 {
                    Self::aesencwide256kl(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aesimc" => {
                if ops.len() == 2 {
                    Self::aesimc(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aeskeygenassist" => {
                if ops.len() == 3 {
                    Self::aeskeygenassist(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "and" => {
                if ops.len() == 2 {
                    Self::and(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "andn" => {
                if ops.len() == 3 {
                    Self::andn(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "aor" => {
                if ops.len() == 2 {
                    Self::aor(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "axor" => {
                if ops.len() == 2 {
                    Self::axor(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "bextr" => {
                if ops.len() == 3 {
                    Self::bextr(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "blsi" => {
                if ops.len() == 2 {
                    Self::blsi(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "blsmsk" => {
                if ops.len() == 2 {
                    Self::blsmsk(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "blsr" => {
                if ops.len() == 2 {
                    Self::blsr(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "bsf" => {
                if ops.len() == 2 {
                    Self::bsf(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "bsr" => {
                if ops.len() == 2 {
                    Self::bsr(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "bswap" => {
                if ops.len() == 1 {
                    Self::bswap(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "bt" => {
                if ops.len() == 2 {
                    Self::bt(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "btc" => {
                if ops.len() == 2 {
                    Self::btc(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "btr" => {
                if ops.len() == 2 {
                    Self::btr(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "bts" => {
                if ops.len() == 2 {
                    Self::bts(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "bzhi" => {
                if ops.len() == 3 {
                    Self::bzhi(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "call" => {
                if ops.len() == 1 {
                    Self::call(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "callf" => {
                if ops.len() == 1 {
                    Self::callf(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cbw" => {
                if ops.is_empty() {
                    Self::cbw()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cdq" => {
                if ops.is_empty() {
                    Self::cdq()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cdqe" => {
                if ops.is_empty() {
                    Self::cdqe()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "clac" => {
                if ops.is_empty() {
                    Self::clac()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "clc" => {
                if ops.is_empty() {
                    Self::clc()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cld" => {
                if ops.is_empty() {
                    Self::cld()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cldemote" => {
                if ops.len() == 1 {
                    Self::cldemote(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "clflush" => {
                if ops.len() == 1 {
                    Self::clflush(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "clflushopt" => {
                if ops.len() == 1 {
                    Self::clflushopt(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "clgi" => {
                if ops.is_empty() {
                    Self::clgi()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cli" => {
                if ops.is_empty() {
                    Self::cli()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "clrssbsy" => {
                if ops.len() == 1 {
                    Self::clrssbsy(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "clts" => {
                if ops.is_empty() {
                    Self::clts()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "clui" => {
                if ops.is_empty() {
                    Self::clui()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "clwb" => {
                if ops.len() == 1 {
                    Self::clwb(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "clzero" => {
                if ops.len() == 1 {
                    Self::clzero(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmc" => {
                if ops.is_empty() {
                    Self::cmc()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmova" => {
                if ops.len() == 2 {
                    Self::cmova(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovbe" => {
                if ops.len() == 2 {
                    Self::cmovbe(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovc" => {
                if ops.len() == 2 {
                    Self::cmovc(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovg" => {
                if ops.len() == 2 {
                    Self::cmovg(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovge" => {
                if ops.len() == 2 {
                    Self::cmovge(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovl" => {
                if ops.len() == 2 {
                    Self::cmovl(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovle" => {
                if ops.len() == 2 {
                    Self::cmovle(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovnc" => {
                if ops.len() == 2 {
                    Self::cmovnc(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovno" => {
                if ops.len() == 2 {
                    Self::cmovno(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovnp" => {
                if ops.len() == 2 {
                    Self::cmovnp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovns" => {
                if ops.len() == 2 {
                    Self::cmovns(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovnz" => {
                if ops.len() == 2 {
                    Self::cmovnz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovo" => {
                if ops.len() == 2 {
                    Self::cmovo(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovp" => {
                if ops.len() == 2 {
                    Self::cmovp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovs" => {
                if ops.len() == 2 {
                    Self::cmovs(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovz" => {
                if ops.len() == 2 {
                    Self::cmovz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmovcc" => {
                if ops.len() == 2 {
                    Self::cmovcc(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmp" => {
                if ops.len() == 2 {
                    Self::cmp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpbexadd" => {
                if ops.len() == 3 {
                    Self::cmpbexadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpbxadd" => {
                if ops.len() == 3 {
                    Self::cmpbxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmplexadd" => {
                if ops.len() == 3 {
                    Self::cmplexadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmplxadd" => {
                if ops.len() == 3 {
                    Self::cmplxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpnbexadd" => {
                if ops.len() == 3 {
                    Self::cmpnbexadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpnbxadd" => {
                if ops.len() == 3 {
                    Self::cmpnbxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpnlexadd" => {
                if ops.len() == 3 {
                    Self::cmpnlexadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpnlxadd" => {
                if ops.len() == 3 {
                    Self::cmpnlxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpnoxadd" => {
                if ops.len() == 3 {
                    Self::cmpnoxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpnpxadd" => {
                if ops.len() == 3 {
                    Self::cmpnpxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpnsxadd" => {
                if ops.len() == 3 {
                    Self::cmpnsxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpnzxadd" => {
                if ops.len() == 3 {
                    Self::cmpnzxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpoxadd" => {
                if ops.len() == 3 {
                    Self::cmpoxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmppxadd" => {
                if ops.len() == 3 {
                    Self::cmppxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmps" => {
                if ops.is_empty() {
                    Self::cmps()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpsxadd" => {
                if ops.len() == 3 {
                    Self::cmpsxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpxchg" => {
                if ops.len() == 2 {
                    Self::cmpxchg(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpxchg16bm" => {
                if ops.len() == 1 {
                    Self::cmpxchg16bm(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpxchg8bm" => {
                if ops.len() == 1 {
                    Self::cmpxchg8bm(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpxchgd" => {
                if ops.len() == 1 {
                    Self::cmpxchgd(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpzxadd" => {
                if ops.len() == 3 {
                    Self::cmpzxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cmpccxadd" => {
                if ops.len() == 3 {
                    Self::cmpccxadd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cpuid" => {
                if ops.is_empty() {
                    Self::cpuid()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cqo" => {
                if ops.is_empty() {
                    Self::cqo()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "crc32" => {
                if ops.len() == 2 {
                    Self::crc32(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cwd" => {
                if ops.is_empty() {
                    Self::cwd()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "cwde" => {
                if ops.is_empty() {
                    Self::cwde()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "c_ex" => {
                if ops.is_empty() {
                    Self::c_ex()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "c_sep" => {
                if ops.is_empty() {
                    Self::c_sep()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "dec" => {
                if ops.len() == 1 {
                    Self::dec(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "div" => {
                if ops.len() == 1 {
                    Self::div(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "encls" => {
                if ops.is_empty() {
                    Self::encls()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "enclu" => {
                if ops.is_empty() {
                    Self::enclu()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "enclv" => {
                if ops.is_empty() {
                    Self::enclv()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "encodekey128" => {
                if ops.len() == 2 {
                    Self::encodekey128(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "encodekey256" => {
                if ops.len() == 2 {
                    Self::encodekey256(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "endbr32" => {
                if ops.is_empty() {
                    Self::endbr32()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "endbr64" => {
                if ops.is_empty() {
                    Self::endbr64()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "enqcmd" => {
                if ops.len() == 2 {
                    Self::enqcmd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "enqcmds" => {
                if ops.len() == 2 {
                    Self::enqcmds(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "enter" => {
                if ops.len() == 1 {
                    Self::enter(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "erets" => {
                if ops.is_empty() {
                    Self::erets()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "eretu" => {
                if ops.is_empty() {
                    Self::eretu()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "f2xm1" => {
                if ops.is_empty() {
                    Self::f2xm1()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fabs" => {
                if ops.is_empty() {
                    Self::fabs()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fadd" => {
                if ops.len() == 1 {
                    Self::fadd_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fadd" => {
                if ops.len() == 2 {
                    Self::fadd_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "faddp" => {
                if ops.len() == 2 {
                    Self::faddp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fbld" => {
                if ops.len() == 1 {
                    Self::fbld(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fbstp" => {
                if ops.len() == 1 {
                    Self::fbstp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fchs" => {
                if ops.is_empty() {
                    Self::fchs()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fclex" => {
                if ops.is_empty() {
                    Self::fclex()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcmovb" => {
                if ops.len() == 1 {
                    Self::fcmovb(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcmovbe" => {
                if ops.len() == 1 {
                    Self::fcmovbe(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcmove" => {
                if ops.len() == 1 {
                    Self::fcmove(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcmovnb" => {
                if ops.len() == 1 {
                    Self::fcmovnb(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcmovnbe" => {
                if ops.len() == 1 {
                    Self::fcmovnbe(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcmovne" => {
                if ops.len() == 1 {
                    Self::fcmovne(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcmovnu" => {
                if ops.len() == 1 {
                    Self::fcmovnu(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcmovu" => {
                if ops.len() == 1 {
                    Self::fcmovu(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcom" => {
                if ops.len() == 1 {
                    Self::fcom_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcom" => {
                if ops.len() == 2 {
                    Self::fcom_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcomi" => {
                if ops.len() == 1 {
                    Self::fcomi(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcomip" => {
                if ops.len() == 2 {
                    Self::fcomip(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcomp" => {
                if ops.len() == 1 {
                    Self::fcomp_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcomp" => {
                if ops.len() == 2 {
                    Self::fcomp_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcompp" => {
                if ops.is_empty() {
                    Self::fcompp()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fcos" => {
                if ops.is_empty() {
                    Self::fcos()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fdecstp" => {
                if ops.is_empty() {
                    Self::fdecstp()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fdiv" => {
                if ops.len() == 1 {
                    Self::fdiv_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fdiv" => {
                if ops.len() == 2 {
                    Self::fdiv_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fdivp" => {
                if ops.len() == 2 {
                    Self::fdivp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fdivr" => {
                if ops.len() == 1 {
                    Self::fdivr_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fdivr" => {
                if ops.len() == 2 {
                    Self::fdivr_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fdivrp" => {
                if ops.len() == 2 {
                    Self::fdivrp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "femms" => {
                if ops.is_empty() {
                    Self::femms()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ffree" => {
                if ops.len() == 1 {
                    Self::ffree(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fiadd" => {
                if ops.len() == 1 {
                    Self::fiadd(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ficom" => {
                if ops.len() == 1 {
                    Self::ficom(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ficomp" => {
                if ops.len() == 1 {
                    Self::ficomp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fidiv" => {
                if ops.len() == 1 {
                    Self::fidiv(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fidivr" => {
                if ops.len() == 1 {
                    Self::fidivr(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fild" => {
                if ops.len() == 1 {
                    Self::fild(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fimul" => {
                if ops.len() == 1 {
                    Self::fimul(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fincstp" => {
                if ops.is_empty() {
                    Self::fincstp()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "finit" => {
                if ops.is_empty() {
                    Self::finit()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fist" => {
                if ops.len() == 1 {
                    Self::fist(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fistp" => {
                if ops.len() == 1 {
                    Self::fistp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fisttp" => {
                if ops.len() == 1 {
                    Self::fisttp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fisub" => {
                if ops.len() == 1 {
                    Self::fisub(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fisubr" => {
                if ops.len() == 1 {
                    Self::fisubr(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fld" => {
                if ops.len() == 1 {
                    Self::fld(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fld1" => {
                if ops.is_empty() {
                    Self::fld1()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fldcw" => {
                if ops.len() == 1 {
                    Self::fldcw(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fldenv" => {
                if ops.len() == 1 {
                    Self::fldenv(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fldl2e" => {
                if ops.is_empty() {
                    Self::fldl2e()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fldl2t" => {
                if ops.is_empty() {
                    Self::fldl2t()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fldlg2" => {
                if ops.is_empty() {
                    Self::fldlg2()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fldln2" => {
                if ops.is_empty() {
                    Self::fldln2()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fldpi" => {
                if ops.is_empty() {
                    Self::fldpi()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fldz" => {
                if ops.is_empty() {
                    Self::fldz()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fmul" => {
                if ops.len() == 1 {
                    Self::fmul_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fmul" => {
                if ops.len() == 2 {
                    Self::fmul_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fmulp" => {
                if ops.len() == 2 {
                    Self::fmulp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fnop" => {
                if ops.is_empty() {
                    Self::fnop()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fpatan" => {
                if ops.is_empty() {
                    Self::fpatan()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fprem" => {
                if ops.is_empty() {
                    Self::fprem()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fprem1" => {
                if ops.is_empty() {
                    Self::fprem1()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fptan" => {
                if ops.is_empty() {
                    Self::fptan()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "frndint" => {
                if ops.is_empty() {
                    Self::frndint()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "frstor" => {
                if ops.len() == 1 {
                    Self::frstor(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fsave" => {
                if ops.len() == 1 {
                    Self::fsave(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fscale" => {
                if ops.is_empty() {
                    Self::fscale()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fsin" => {
                if ops.is_empty() {
                    Self::fsin()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fsincos" => {
                if ops.is_empty() {
                    Self::fsincos()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fsqrt" => {
                if ops.is_empty() {
                    Self::fsqrt()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fst" => {
                if ops.len() == 1 {
                    Self::fst(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fstcw" => {
                if ops.len() == 1 {
                    Self::fstcw(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fstenv" => {
                if ops.len() == 1 {
                    Self::fstenv(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fstp" => {
                if ops.len() == 1 {
                    Self::fstp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fstsw" => {
                if ops.len() == 1 {
                    Self::fstsw(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fsub" => {
                if ops.len() == 1 {
                    Self::fsub_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fsub" => {
                if ops.len() == 2 {
                    Self::fsub_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fsubp" => {
                if ops.len() == 2 {
                    Self::fsubp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fsubr" => {
                if ops.len() == 1 {
                    Self::fsubr_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fsubr" => {
                if ops.len() == 2 {
                    Self::fsubr_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fsubrp" => {
                if ops.len() == 2 {
                    Self::fsubrp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ftst" => {
                if ops.is_empty() {
                    Self::ftst()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fucom" => {
                if ops.len() == 1 {
                    Self::fucom(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fucomi" => {
                if ops.len() == 1 {
                    Self::fucomi(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fucomip" => {
                if ops.len() == 2 {
                    Self::fucomip(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fucomp" => {
                if ops.len() == 1 {
                    Self::fucomp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fucompp" => {
                if ops.is_empty() {
                    Self::fucompp()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fwait" => {
                if ops.is_empty() {
                    Self::fwait()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fxam" => {
                if ops.is_empty() {
                    Self::fxam()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fxch" => {
                if ops.len() == 1 {
                    Self::fxch(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fxrstor" => {
                if ops.len() == 1 {
                    Self::fxrstor(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fxsave" => {
                if ops.len() == 1 {
                    Self::fxsave(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fxtract" => {
                if ops.is_empty() {
                    Self::fxtract()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fyl2x" => {
                if ops.is_empty() {
                    Self::fyl2x()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "fyl2xp1" => {
                if ops.is_empty() {
                    Self::fyl2xp1()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "getsec" => {
                if ops.is_empty() {
                    Self::getsec()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "gf2p8affineinvqb" => {
                if ops.len() == 3 {
                    Self::gf2p8affineinvqb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "gf2p8affineqb" => {
                if ops.len() == 3 {
                    Self::gf2p8affineqb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "gf2p8mulb" => {
                if ops.len() == 2 {
                    Self::gf2p8mulb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "hlt" => {
                if ops.is_empty() {
                    Self::hlt()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "hreset" => {
                if ops.len() == 1 {
                    Self::hreset(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "idiv" => {
                if ops.len() == 1 {
                    Self::idiv(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "imul" => {
                if ops.len() == 1 {
                    Self::imul_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "imul" => {
                if ops.len() == 2 {
                    Self::imul_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "imul" => {
                if ops.len() == 3 {
                    Self::imul_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "in" => {
                if ops.is_empty() {
                    Self::in_instr()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "in" => {
                if ops.len() == 2 {
                    Self::in_instr_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "inc" => {
                if ops.len() == 1 {
                    Self::inc(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "incssp" => {
                if ops.len() == 1 {
                    Self::incssp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ins" => {
                if ops.is_empty() {
                    Self::ins()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "int" => {
                if ops.len() == 1 {
                    Self::int(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "int1" => {
                if ops.is_empty() {
                    Self::int1()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "int3" => {
                if ops.is_empty() {
                    Self::int3()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "invd" => {
                if ops.is_empty() {
                    Self::invd()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "invept" => {
                if ops.len() == 2 {
                    Self::invept(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "invlpg" => {
                if ops.len() == 1 {
                    Self::invlpg(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "invlpga" => {
                if ops.is_empty() {
                    Self::invlpga()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "invlpgb" => {
                if ops.is_empty() {
                    Self::invlpgb()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "invpcid" => {
                if ops.len() == 2 {
                    Self::invpcid(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "invvpid" => {
                if ops.len() == 2 {
                    Self::invvpid(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "iret" => {
                if ops.is_empty() {
                    Self::iret()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ja" => {
                if ops.len() == 1 {
                    Self::ja(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jbe" => {
                if ops.len() == 1 {
                    Self::jbe(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jc" => {
                if ops.len() == 1 {
                    Self::jc(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jcxz" => {
                if ops.len() == 1 {
                    Self::jcxz(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jg" => {
                if ops.len() == 1 {
                    Self::jg(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jge" => {
                if ops.len() == 1 {
                    Self::jge(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jl" => {
                if ops.len() == 1 {
                    Self::jl(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jle" => {
                if ops.len() == 1 {
                    Self::jle(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jmp" => {
                if ops.len() == 1 {
                    Self::jmp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jmpf" => {
                if ops.len() == 1 {
                    Self::jmpf(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jnc" => {
                if ops.len() == 1 {
                    Self::jnc(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jno" => {
                if ops.len() == 1 {
                    Self::jno(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jnp" => {
                if ops.len() == 1 {
                    Self::jnp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jns" => {
                if ops.len() == 1 {
                    Self::jns(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jnz" => {
                if ops.len() == 1 {
                    Self::jnz(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jo" => {
                if ops.len() == 1 {
                    Self::jo(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jp" => {
                if ops.len() == 1 {
                    Self::jp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "js" => {
                if ops.len() == 1 {
                    Self::js(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jz" => {
                if ops.len() == 1 {
                    Self::jz(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "jcc" => {
                if ops.len() == 1 {
                    Self::jcc(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kaddb" => {
                if ops.len() == 3 {
                    Self::kaddb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kaddd" => {
                if ops.len() == 3 {
                    Self::kaddd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kaddq" => {
                if ops.len() == 3 {
                    Self::kaddq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kaddw" => {
                if ops.len() == 3 {
                    Self::kaddw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kandb" => {
                if ops.len() == 3 {
                    Self::kandb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kandd" => {
                if ops.len() == 3 {
                    Self::kandd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kandnb" => {
                if ops.len() == 3 {
                    Self::kandnb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kandnd" => {
                if ops.len() == 3 {
                    Self::kandnd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kandnq" => {
                if ops.len() == 3 {
                    Self::kandnq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kandnw" => {
                if ops.len() == 3 {
                    Self::kandnw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kandq" => {
                if ops.len() == 3 {
                    Self::kandq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kandw" => {
                if ops.len() == 3 {
                    Self::kandw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kmovb" => {
                if ops.len() == 2 {
                    Self::kmovb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kmovd" => {
                if ops.len() == 2 {
                    Self::kmovd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kmovq" => {
                if ops.len() == 2 {
                    Self::kmovq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kmovw" => {
                if ops.len() == 2 {
                    Self::kmovw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "knotb" => {
                if ops.len() == 2 {
                    Self::knotb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "knotd" => {
                if ops.len() == 2 {
                    Self::knotd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "knotq" => {
                if ops.len() == 2 {
                    Self::knotq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "knotw" => {
                if ops.len() == 2 {
                    Self::knotw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "korb" => {
                if ops.len() == 3 {
                    Self::korb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kord" => {
                if ops.len() == 3 {
                    Self::kord(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "korq" => {
                if ops.len() == 3 {
                    Self::korq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kortestb" => {
                if ops.len() == 2 {
                    Self::kortestb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kortestd" => {
                if ops.len() == 2 {
                    Self::kortestd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kortestq" => {
                if ops.len() == 2 {
                    Self::kortestq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kortestw" => {
                if ops.len() == 2 {
                    Self::kortestw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "korw" => {
                if ops.len() == 3 {
                    Self::korw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kshiftlb" => {
                if ops.len() == 3 {
                    Self::kshiftlb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kshiftld" => {
                if ops.len() == 3 {
                    Self::kshiftld(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kshiftlq" => {
                if ops.len() == 3 {
                    Self::kshiftlq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kshiftlw" => {
                if ops.len() == 3 {
                    Self::kshiftlw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kshiftrb" => {
                if ops.len() == 3 {
                    Self::kshiftrb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kshiftrd" => {
                if ops.len() == 3 {
                    Self::kshiftrd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kshiftrq" => {
                if ops.len() == 3 {
                    Self::kshiftrq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kshiftrw" => {
                if ops.len() == 3 {
                    Self::kshiftrw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ktestb" => {
                if ops.len() == 2 {
                    Self::ktestb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ktestd" => {
                if ops.len() == 2 {
                    Self::ktestd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ktestq" => {
                if ops.len() == 2 {
                    Self::ktestq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ktestw" => {
                if ops.len() == 2 {
                    Self::ktestw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kunpckbw" => {
                if ops.len() == 3 {
                    Self::kunpckbw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kunpckdq" => {
                if ops.len() == 3 {
                    Self::kunpckdq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kunpckwd" => {
                if ops.len() == 3 {
                    Self::kunpckwd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kxnorb" => {
                if ops.len() == 3 {
                    Self::kxnorb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kxnord" => {
                if ops.len() == 3 {
                    Self::kxnord(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kxnorq" => {
                if ops.len() == 3 {
                    Self::kxnorq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kxnorw" => {
                if ops.len() == 3 {
                    Self::kxnorw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kxorb" => {
                if ops.len() == 3 {
                    Self::kxorb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kxord" => {
                if ops.len() == 3 {
                    Self::kxord(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kxorq" => {
                if ops.len() == 3 {
                    Self::kxorq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "kxorw" => {
                if ops.len() == 3 {
                    Self::kxorw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lahf" => {
                if ops.is_empty() {
                    Self::lahf()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lar" => {
                if ops.len() == 2 {
                    Self::lar(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ldmxcsr" => {
                if ops.len() == 1 {
                    Self::ldmxcsr(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ldtilecfg" => {
                if ops.len() == 1 {
                    Self::ldtilecfg(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lea" => {
                if ops.len() == 2 {
                    Self::lea(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "leave" => {
                if ops.is_empty() {
                    Self::leave()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lfence" => {
                if ops.is_empty() {
                    Self::lfence()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lfs" => {
                if ops.len() == 2 {
                    Self::lfs(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lgdt" => {
                if ops.len() == 1 {
                    Self::lgdt(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lgs" => {
                if ops.len() == 2 {
                    Self::lgs(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lidt" => {
                if ops.len() == 1 {
                    Self::lidt(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lkgs" => {
                if ops.len() == 1 {
                    Self::lkgs(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lldt" => {
                if ops.len() == 1 {
                    Self::lldt(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lmsw" => {
                if ops.len() == 1 {
                    Self::lmsw(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "loadiwkey" => {
                if ops.len() == 2 {
                    Self::loadiwkey(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lods" => {
                if ops.is_empty() {
                    Self::lods()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "loop" => {
                if ops.len() == 1 {
                    Self::loop_instr(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "loopnz" => {
                if ops.len() == 1 {
                    Self::loopnz(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "loopz" => {
                if ops.len() == 1 {
                    Self::loopz(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lsl" => {
                if ops.len() == 2 {
                    Self::lsl(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lss" => {
                if ops.len() == 2 {
                    Self::lss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ltr" => {
                if ops.len() == 1 {
                    Self::ltr(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "lzcnt" => {
                if ops.len() == 2 {
                    Self::lzcnt(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mcommit" => {
                if ops.is_empty() {
                    Self::mcommit()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mfence" => {
                if ops.is_empty() {
                    Self::mfence()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_cvtpd2pi" => {
                if ops.len() == 2 {
                    Self::mmx_cvtpd2pi(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_cvtpi2pd" => {
                if ops.len() == 2 {
                    Self::mmx_cvtpi2pd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_cvtpi2ps" => {
                if ops.len() == 2 {
                    Self::mmx_cvtpi2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_cvtps2pi" => {
                if ops.len() == 2 {
                    Self::mmx_cvtps2pi(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_cvttpd2pi" => {
                if ops.len() == 2 {
                    Self::mmx_cvttpd2pi(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_cvttps2pi" => {
                if ops.len() == 2 {
                    Self::mmx_cvttps2pi(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_emms" => {
                if ops.is_empty() {
                    Self::mmx_emms()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_maskmovq" => {
                if ops.len() == 2 {
                    Self::mmx_maskmovq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_movdq2q" => {
                if ops.len() == 2 {
                    Self::mmx_movdq2q(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_movd_g2m" => {
                if ops.len() == 2 {
                    Self::mmx_movd_g2m(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_movd_m2g" => {
                if ops.len() == 2 {
                    Self::mmx_movd_m2g(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_movntq" => {
                if ops.len() == 2 {
                    Self::mmx_movntq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_movq" => {
                if ops.len() == 2 {
                    Self::mmx_movq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_movq2dq" => {
                if ops.len() == 2 {
                    Self::mmx_movq2dq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_movq_g2m" => {
                if ops.len() == 2 {
                    Self::mmx_movq_g2m(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_movq_m2g" => {
                if ops.len() == 2 {
                    Self::mmx_movq_m2g(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pabsb" => {
                if ops.len() == 2 {
                    Self::mmx_pabsb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pabsd" => {
                if ops.len() == 2 {
                    Self::mmx_pabsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pabsw" => {
                if ops.len() == 2 {
                    Self::mmx_pabsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_packssdw" => {
                if ops.len() == 2 {
                    Self::mmx_packssdw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_packsswb" => {
                if ops.len() == 2 {
                    Self::mmx_packsswb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_packuswb" => {
                if ops.len() == 2 {
                    Self::mmx_packuswb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_paddb" => {
                if ops.len() == 2 {
                    Self::mmx_paddb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_paddd" => {
                if ops.len() == 2 {
                    Self::mmx_paddd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_paddq" => {
                if ops.len() == 2 {
                    Self::mmx_paddq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_paddsb" => {
                if ops.len() == 2 {
                    Self::mmx_paddsb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_paddsw" => {
                if ops.len() == 2 {
                    Self::mmx_paddsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_paddusb" => {
                if ops.len() == 2 {
                    Self::mmx_paddusb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_paddusw" => {
                if ops.len() == 2 {
                    Self::mmx_paddusw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_paddw" => {
                if ops.len() == 2 {
                    Self::mmx_paddw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_palignr" => {
                if ops.len() == 3 {
                    Self::mmx_palignr(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pand" => {
                if ops.len() == 2 {
                    Self::mmx_pand(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pandn" => {
                if ops.len() == 2 {
                    Self::mmx_pandn(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pavgb" => {
                if ops.len() == 2 {
                    Self::mmx_pavgb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pavgw" => {
                if ops.len() == 2 {
                    Self::mmx_pavgw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pcmpeqb" => {
                if ops.len() == 2 {
                    Self::mmx_pcmpeqb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pcmpeqd" => {
                if ops.len() == 2 {
                    Self::mmx_pcmpeqd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pcmpeqw" => {
                if ops.len() == 2 {
                    Self::mmx_pcmpeqw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pcmpgtb" => {
                if ops.len() == 2 {
                    Self::mmx_pcmpgtb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pcmpgtd" => {
                if ops.len() == 2 {
                    Self::mmx_pcmpgtd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pcmpgtw" => {
                if ops.len() == 2 {
                    Self::mmx_pcmpgtw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pextrw" => {
                if ops.len() == 3 {
                    Self::mmx_pextrw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_phaddd" => {
                if ops.len() == 2 {
                    Self::mmx_phaddd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_phaddsw" => {
                if ops.len() == 2 {
                    Self::mmx_phaddsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_phaddw" => {
                if ops.len() == 2 {
                    Self::mmx_phaddw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_phsubd" => {
                if ops.len() == 2 {
                    Self::mmx_phsubd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_phsubsw" => {
                if ops.len() == 2 {
                    Self::mmx_phsubsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_phsubw" => {
                if ops.len() == 2 {
                    Self::mmx_phsubw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pinsrw" => {
                if ops.len() == 3 {
                    Self::mmx_pinsrw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pmaddubsw" => {
                if ops.len() == 2 {
                    Self::mmx_pmaddubsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pmaddwd" => {
                if ops.len() == 2 {
                    Self::mmx_pmaddwd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pmaxsw" => {
                if ops.len() == 2 {
                    Self::mmx_pmaxsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pmaxub" => {
                if ops.len() == 2 {
                    Self::mmx_pmaxub(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pminsw" => {
                if ops.len() == 2 {
                    Self::mmx_pminsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pminub" => {
                if ops.len() == 2 {
                    Self::mmx_pminub(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pmovmskb" => {
                if ops.len() == 2 {
                    Self::mmx_pmovmskb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pmulhrsw" => {
                if ops.len() == 2 {
                    Self::mmx_pmulhrsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pmulhuw" => {
                if ops.len() == 2 {
                    Self::mmx_pmulhuw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pmulhw" => {
                if ops.len() == 2 {
                    Self::mmx_pmulhw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pmullw" => {
                if ops.len() == 2 {
                    Self::mmx_pmullw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pmuludq" => {
                if ops.len() == 2 {
                    Self::mmx_pmuludq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_por" => {
                if ops.len() == 2 {
                    Self::mmx_por(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psadbw" => {
                if ops.len() == 2 {
                    Self::mmx_psadbw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pshufb" => {
                if ops.len() == 2 {
                    Self::mmx_pshufb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pshufw" => {
                if ops.len() == 3 {
                    Self::mmx_pshufw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psignb" => {
                if ops.len() == 2 {
                    Self::mmx_psignb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psignd" => {
                if ops.len() == 2 {
                    Self::mmx_psignd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psignw" => {
                if ops.len() == 2 {
                    Self::mmx_psignw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pslld" => {
                if ops.len() == 2 {
                    Self::mmx_pslld(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psllq" => {
                if ops.len() == 2 {
                    Self::mmx_psllq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psllw" => {
                if ops.len() == 2 {
                    Self::mmx_psllw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psrad" => {
                if ops.len() == 2 {
                    Self::mmx_psrad(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psraw" => {
                if ops.len() == 2 {
                    Self::mmx_psraw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psrld" => {
                if ops.len() == 2 {
                    Self::mmx_psrld(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psrlq" => {
                if ops.len() == 2 {
                    Self::mmx_psrlq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psrlw" => {
                if ops.len() == 2 {
                    Self::mmx_psrlw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psubb" => {
                if ops.len() == 2 {
                    Self::mmx_psubb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psubd" => {
                if ops.len() == 2 {
                    Self::mmx_psubd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psubq" => {
                if ops.len() == 2 {
                    Self::mmx_psubq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psubsb" => {
                if ops.len() == 2 {
                    Self::mmx_psubsb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psubsw" => {
                if ops.len() == 2 {
                    Self::mmx_psubsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psubusb" => {
                if ops.len() == 2 {
                    Self::mmx_psubusb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psubusw" => {
                if ops.len() == 2 {
                    Self::mmx_psubusw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_psubw" => {
                if ops.len() == 2 {
                    Self::mmx_psubw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_punpckhbw" => {
                if ops.len() == 2 {
                    Self::mmx_punpckhbw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_punpckhdq" => {
                if ops.len() == 2 {
                    Self::mmx_punpckhdq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_punpckhwd" => {
                if ops.len() == 2 {
                    Self::mmx_punpckhwd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_punpcklbw" => {
                if ops.len() == 2 {
                    Self::mmx_punpcklbw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_punpckldq" => {
                if ops.len() == 2 {
                    Self::mmx_punpckldq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_punpcklwd" => {
                if ops.len() == 2 {
                    Self::mmx_punpcklwd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mmx_pxor" => {
                if ops.len() == 2 {
                    Self::mmx_pxor(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "monitor" => {
                if ops.is_empty() {
                    Self::monitor()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "monitorx" => {
                if ops.is_empty() {
                    Self::monitorx()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mov" => {
                if ops.len() == 2 {
                    Self::mov(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "movbe" => {
                if ops.len() == 2 {
                    Self::movbe(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "movdir64b" => {
                if ops.len() == 2 {
                    Self::movdir64b(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "movdiri" => {
                if ops.len() == 2 {
                    Self::movdiri(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "movnti" => {
                if ops.len() == 2 {
                    Self::movnti(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "movs" => {
                if ops.is_empty() {
                    Self::movs()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "movsx" => {
                if ops.len() == 2 {
                    Self::movsx(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "movzx" => {
                if ops.len() == 2 {
                    Self::movzx(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mov_cr2g" => {
                if ops.len() == 2 {
                    Self::mov_cr2g(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mov_dr2g" => {
                if ops.len() == 2 {
                    Self::mov_dr2g(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mov_g2cr" => {
                if ops.len() == 2 {
                    Self::mov_g2cr(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mov_g2dr" => {
                if ops.len() == 2 {
                    Self::mov_g2dr(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mov_g2s" => {
                if ops.len() == 2 {
                    Self::mov_g2s(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mov_s2g" => {
                if ops.len() == 2 {
                    Self::mov_s2g(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mul" => {
                if ops.len() == 1 {
                    Self::mul(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mulx" => {
                if ops.len() == 3 {
                    Self::mulx(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mwait" => {
                if ops.is_empty() {
                    Self::mwait()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "mwaitx" => {
                if ops.is_empty() {
                    Self::mwaitx()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "neg" => {
                if ops.len() == 1 {
                    Self::neg(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "nop" => {
                if ops.is_empty() {
                    Self::nop()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "nop" => {
                if ops.len() == 1 {
                    Self::nop_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "not" => {
                if ops.len() == 1 {
                    Self::not(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "or" => {
                if ops.len() == 2 {
                    Self::or(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "out" => {
                if ops.is_empty() {
                    Self::out_instr()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "out" => {
                if ops.len() == 2 {
                    Self::out_instr_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "outs" => {
                if ops.is_empty() {
                    Self::outs()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "pause" => {
                if ops.is_empty() {
                    Self::pause()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "pbndkb" => {
                if ops.is_empty() {
                    Self::pbndkb()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "pconfig" => {
                if ops.is_empty() {
                    Self::pconfig()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "pdep" => {
                if ops.len() == 3 {
                    Self::pdep(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "pext" => {
                if ops.len() == 3 {
                    Self::pext(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "pop" => {
                if ops.len() == 1 {
                    Self::pop(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "popcnt" => {
                if ops.len() == 2 {
                    Self::popcnt(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "popf" => {
                if ops.is_empty() {
                    Self::popf()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "pop_seg" => {
                if ops.len() == 1 {
                    Self::pop_seg(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "prefetch" => {
                if ops.len() == 1 {
                    Self::prefetch(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "prefetchit0" => {
                if ops.len() == 1 {
                    Self::prefetchit0(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "prefetchit1" => {
                if ops.len() == 1 {
                    Self::prefetchit1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "prefetchnta" => {
                if ops.len() == 1 {
                    Self::prefetchnta(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "prefetcht0" => {
                if ops.len() == 1 {
                    Self::prefetcht0(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "prefetcht1" => {
                if ops.len() == 1 {
                    Self::prefetcht1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "prefetcht2" => {
                if ops.len() == 1 {
                    Self::prefetcht2(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "prefetchw" => {
                if ops.len() == 1 {
                    Self::prefetchw(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "prefetchwt1" => {
                if ops.len() == 1 {
                    Self::prefetchwt1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "psmash" => {
                if ops.is_empty() {
                    Self::psmash()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ptwrite" => {
                if ops.len() == 1 {
                    Self::ptwrite(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "push" => {
                if ops.len() == 1 {
                    Self::push(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "pushf" => {
                if ops.is_empty() {
                    Self::pushf()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "push_seg" => {
                if ops.len() == 1 {
                    Self::push_seg(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "pvalidate" => {
                if ops.is_empty() {
                    Self::pvalidate()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rcl" => {
                if ops.len() == 2 {
                    Self::rcl(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rcr" => {
                if ops.len() == 2 {
                    Self::rcr(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdfsbase" => {
                if ops.len() == 1 {
                    Self::rdfsbase(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdgsbase" => {
                if ops.len() == 1 {
                    Self::rdgsbase(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdmsr" => {
                if ops.is_empty() {
                    Self::rdmsr()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdmsr" => {
                if ops.len() == 2 {
                    Self::rdmsr_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdmsrlist" => {
                if ops.is_empty() {
                    Self::rdmsrlist()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdpid" => {
                if ops.len() == 1 {
                    Self::rdpid(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdpkru" => {
                if ops.is_empty() {
                    Self::rdpkru()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdpmc" => {
                if ops.is_empty() {
                    Self::rdpmc()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdpru" => {
                if ops.is_empty() {
                    Self::rdpru()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdrand" => {
                if ops.len() == 1 {
                    Self::rdrand(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdseed" => {
                if ops.len() == 1 {
                    Self::rdseed(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdssp" => {
                if ops.len() == 1 {
                    Self::rdssp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdtsc" => {
                if ops.is_empty() {
                    Self::rdtsc()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rdtscp" => {
                if ops.is_empty() {
                    Self::rdtscp()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ret" => {
                if ops.is_empty() {
                    Self::ret()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ret" => {
                if ops.len() == 1 {
                    Self::ret_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "retf" => {
                if ops.is_empty() {
                    Self::retf()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "retf" => {
                if ops.len() == 1 {
                    Self::retf_1(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rmpadjust" => {
                if ops.is_empty() {
                    Self::rmpadjust()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rmpquery" => {
                if ops.is_empty() {
                    Self::rmpquery()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rmpread" => {
                if ops.is_empty() {
                    Self::rmpread()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rmpupdate" => {
                if ops.is_empty() {
                    Self::rmpupdate()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rol" => {
                if ops.len() == 2 {
                    Self::rol(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ror" => {
                if ops.len() == 2 {
                    Self::ror(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rorx" => {
                if ops.len() == 3 {
                    Self::rorx(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rsm" => {
                if ops.is_empty() {
                    Self::rsm()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "rstorssp" => {
                if ops.len() == 1 {
                    Self::rstorssp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sahf" => {
                if ops.is_empty() {
                    Self::sahf()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sar" => {
                if ops.len() == 2 {
                    Self::sar(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sarx" => {
                if ops.len() == 3 {
                    Self::sarx(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "saveprevssp" => {
                if ops.is_empty() {
                    Self::saveprevssp()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sbb" => {
                if ops.len() == 2 {
                    Self::sbb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "scas" => {
                if ops.is_empty() {
                    Self::scas()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "seamcall" => {
                if ops.is_empty() {
                    Self::seamcall()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "seamops" => {
                if ops.is_empty() {
                    Self::seamops()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "seamret" => {
                if ops.is_empty() {
                    Self::seamret()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "senduipi" => {
                if ops.len() == 1 {
                    Self::senduipi(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "serialize" => {
                if ops.is_empty() {
                    Self::serialize()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "seta" => {
                if ops.len() == 1 {
                    Self::seta(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setbe" => {
                if ops.len() == 1 {
                    Self::setbe(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setc" => {
                if ops.len() == 1 {
                    Self::setc(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setg" => {
                if ops.len() == 1 {
                    Self::setg(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setge" => {
                if ops.len() == 1 {
                    Self::setge(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setl" => {
                if ops.len() == 1 {
                    Self::setl(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setle" => {
                if ops.len() == 1 {
                    Self::setle(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setnc" => {
                if ops.len() == 1 {
                    Self::setnc(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setno" => {
                if ops.len() == 1 {
                    Self::setno(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setnp" => {
                if ops.len() == 1 {
                    Self::setnp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setns" => {
                if ops.len() == 1 {
                    Self::setns(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setnz" => {
                if ops.len() == 1 {
                    Self::setnz(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "seto" => {
                if ops.len() == 1 {
                    Self::seto(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setp" => {
                if ops.len() == 1 {
                    Self::setp(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sets" => {
                if ops.len() == 1 {
                    Self::sets(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setssbsy" => {
                if ops.is_empty() {
                    Self::setssbsy()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setz" => {
                if ops.len() == 1 {
                    Self::setz(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "setcc" => {
                if ops.len() == 1 {
                    Self::setcc(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sfence" => {
                if ops.is_empty() {
                    Self::sfence()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sgdt" => {
                if ops.len() == 1 {
                    Self::sgdt(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sha1msg1" => {
                if ops.len() == 2 {
                    Self::sha1msg1(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sha1msg2" => {
                if ops.len() == 2 {
                    Self::sha1msg2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sha1nexte" => {
                if ops.len() == 2 {
                    Self::sha1nexte(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sha1rnds4" => {
                if ops.len() == 3 {
                    Self::sha1rnds4(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sha256msg1" => {
                if ops.len() == 2 {
                    Self::sha256msg1(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sha256msg2" => {
                if ops.len() == 2 {
                    Self::sha256msg2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sha256rnds2" => {
                if ops.len() == 3 {
                    Self::sha256rnds2(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "shl" => {
                if ops.len() == 2 {
                    Self::shl(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "shld" => {
                if ops.len() == 3 {
                    Self::shld(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "shlx" => {
                if ops.len() == 3 {
                    Self::shlx(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "shr" => {
                if ops.len() == 2 {
                    Self::shr(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "shrd" => {
                if ops.len() == 3 {
                    Self::shrd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "shrx" => {
                if ops.len() == 3 {
                    Self::shrx(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sidt" => {
                if ops.len() == 1 {
                    Self::sidt(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "skinit" => {
                if ops.is_empty() {
                    Self::skinit()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sldt" => {
                if ops.len() == 1 {
                    Self::sldt(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "smsw" => {
                if ops.len() == 1 {
                    Self::smsw(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_addpd" => {
                if ops.len() == 2 {
                    Self::sse_addpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_addps" => {
                if ops.len() == 2 {
                    Self::sse_addps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_addsd" => {
                if ops.len() == 2 {
                    Self::sse_addsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_addss" => {
                if ops.len() == 2 {
                    Self::sse_addss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_addsubpd" => {
                if ops.len() == 2 {
                    Self::sse_addsubpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_addsubps" => {
                if ops.len() == 2 {
                    Self::sse_addsubps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_andnpd" => {
                if ops.len() == 2 {
                    Self::sse_andnpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_andnps" => {
                if ops.len() == 2 {
                    Self::sse_andnps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_andpd" => {
                if ops.len() == 2 {
                    Self::sse_andpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_andps" => {
                if ops.len() == 2 {
                    Self::sse_andps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_blendpd" => {
                if ops.len() == 3 {
                    Self::sse_blendpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_blendps" => {
                if ops.len() == 3 {
                    Self::sse_blendps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_blendvpd" => {
                if ops.len() == 3 {
                    Self::sse_blendvpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_blendvps" => {
                if ops.len() == 3 {
                    Self::sse_blendvps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cmppd" => {
                if ops.len() == 3 {
                    Self::sse_cmppd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cmpps" => {
                if ops.len() == 3 {
                    Self::sse_cmpps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cmpsd" => {
                if ops.len() == 3 {
                    Self::sse_cmpsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cmpss" => {
                if ops.len() == 3 {
                    Self::sse_cmpss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_comisd" => {
                if ops.len() == 2 {
                    Self::sse_comisd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_comiss" => {
                if ops.len() == 2 {
                    Self::sse_comiss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtdq2pd" => {
                if ops.len() == 2 {
                    Self::sse_cvtdq2pd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtdq2ps" => {
                if ops.len() == 2 {
                    Self::sse_cvtdq2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtpd2dq" => {
                if ops.len() == 2 {
                    Self::sse_cvtpd2dq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtpd2ps" => {
                if ops.len() == 2 {
                    Self::sse_cvtpd2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtps2dq" => {
                if ops.len() == 2 {
                    Self::sse_cvtps2dq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtps2pd" => {
                if ops.len() == 2 {
                    Self::sse_cvtps2pd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtsd2si" => {
                if ops.len() == 2 {
                    Self::sse_cvtsd2si(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtsd2ss" => {
                if ops.len() == 2 {
                    Self::sse_cvtsd2ss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtsi2sd" => {
                if ops.len() == 2 {
                    Self::sse_cvtsi2sd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtsi2ss" => {
                if ops.len() == 2 {
                    Self::sse_cvtsi2ss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtss2sd" => {
                if ops.len() == 2 {
                    Self::sse_cvtss2sd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvtss2si" => {
                if ops.len() == 2 {
                    Self::sse_cvtss2si(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvttpd2dq" => {
                if ops.len() == 2 {
                    Self::sse_cvttpd2dq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvttps2dq" => {
                if ops.len() == 2 {
                    Self::sse_cvttps2dq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvttsd2si" => {
                if ops.len() == 2 {
                    Self::sse_cvttsd2si(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_cvttss2si" => {
                if ops.len() == 2 {
                    Self::sse_cvttss2si(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_divpd" => {
                if ops.len() == 2 {
                    Self::sse_divpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_divps" => {
                if ops.len() == 2 {
                    Self::sse_divps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_divsd" => {
                if ops.len() == 2 {
                    Self::sse_divsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_divss" => {
                if ops.len() == 2 {
                    Self::sse_divss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_dppd" => {
                if ops.len() == 3 {
                    Self::sse_dppd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_dpps" => {
                if ops.len() == 3 {
                    Self::sse_dpps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_extractps" => {
                if ops.len() == 3 {
                    Self::sse_extractps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_extrq" => {
                if ops.len() == 2 {
                    Self::sse_extrq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_haddpd" => {
                if ops.len() == 2 {
                    Self::sse_haddpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_haddps" => {
                if ops.len() == 2 {
                    Self::sse_haddps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_hsubpd" => {
                if ops.len() == 2 {
                    Self::sse_hsubpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_hsubps" => {
                if ops.len() == 2 {
                    Self::sse_hsubps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_insertps" => {
                if ops.len() == 3 {
                    Self::sse_insertps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_insertq" => {
                if ops.len() == 2 {
                    Self::sse_insertq_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_insertq" => {
                if ops.len() == 3 {
                    Self::sse_insertq_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_lddqu" => {
                if ops.len() == 2 {
                    Self::sse_lddqu(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_maskmovdqu" => {
                if ops.len() == 2 {
                    Self::sse_maskmovdqu(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_maxpd" => {
                if ops.len() == 2 {
                    Self::sse_maxpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_maxps" => {
                if ops.len() == 2 {
                    Self::sse_maxps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_maxsd" => {
                if ops.len() == 2 {
                    Self::sse_maxsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_maxss" => {
                if ops.len() == 2 {
                    Self::sse_maxss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_minpd" => {
                if ops.len() == 2 {
                    Self::sse_minpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_minps" => {
                if ops.len() == 2 {
                    Self::sse_minps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_minsd" => {
                if ops.len() == 2 {
                    Self::sse_minsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_minss" => {
                if ops.len() == 2 {
                    Self::sse_minss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movapd" => {
                if ops.len() == 2 {
                    Self::sse_movapd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movaps" => {
                if ops.len() == 2 {
                    Self::sse_movaps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movddup" => {
                if ops.len() == 2 {
                    Self::sse_movddup(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movdqa" => {
                if ops.len() == 2 {
                    Self::sse_movdqa(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movdqu" => {
                if ops.len() == 2 {
                    Self::sse_movdqu(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movd_g2x" => {
                if ops.len() == 2 {
                    Self::sse_movd_g2x(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movd_x2g" => {
                if ops.len() == 2 {
                    Self::sse_movd_x2g(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movhlps" => {
                if ops.len() == 2 {
                    Self::sse_movhlps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movhpd" => {
                if ops.len() == 2 {
                    Self::sse_movhpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movhps" => {
                if ops.len() == 2 {
                    Self::sse_movhps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movlhps" => {
                if ops.len() == 2 {
                    Self::sse_movlhps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movlpd" => {
                if ops.len() == 2 {
                    Self::sse_movlpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movlps" => {
                if ops.len() == 2 {
                    Self::sse_movlps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movmskpd" => {
                if ops.len() == 2 {
                    Self::sse_movmskpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movmskps" => {
                if ops.len() == 2 {
                    Self::sse_movmskps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movntdq" => {
                if ops.len() == 2 {
                    Self::sse_movntdq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movntdqa" => {
                if ops.len() == 2 {
                    Self::sse_movntdqa(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movntpd" => {
                if ops.len() == 2 {
                    Self::sse_movntpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movntps" => {
                if ops.len() == 2 {
                    Self::sse_movntps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movntsd" => {
                if ops.len() == 2 {
                    Self::sse_movntsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movntss" => {
                if ops.len() == 2 {
                    Self::sse_movntss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movq" => {
                if ops.len() == 2 {
                    Self::sse_movq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movq_g2x" => {
                if ops.len() == 2 {
                    Self::sse_movq_g2x(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movq_x2g" => {
                if ops.len() == 2 {
                    Self::sse_movq_x2g(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movsd" => {
                if ops.len() == 2 {
                    Self::sse_movsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movshdup" => {
                if ops.len() == 2 {
                    Self::sse_movshdup(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movsldup" => {
                if ops.len() == 2 {
                    Self::sse_movsldup(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movss" => {
                if ops.len() == 2 {
                    Self::sse_movss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movupd" => {
                if ops.len() == 2 {
                    Self::sse_movupd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_movups" => {
                if ops.len() == 2 {
                    Self::sse_movups(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_mpsadbw" => {
                if ops.len() == 3 {
                    Self::sse_mpsadbw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_mulpd" => {
                if ops.len() == 2 {
                    Self::sse_mulpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_mulps" => {
                if ops.len() == 2 {
                    Self::sse_mulps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_mulsd" => {
                if ops.len() == 2 {
                    Self::sse_mulsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_mulss" => {
                if ops.len() == 2 {
                    Self::sse_mulss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_orpd" => {
                if ops.len() == 2 {
                    Self::sse_orpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_orps" => {
                if ops.len() == 2 {
                    Self::sse_orps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pabsb" => {
                if ops.len() == 2 {
                    Self::sse_pabsb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pabsd" => {
                if ops.len() == 2 {
                    Self::sse_pabsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pabsw" => {
                if ops.len() == 2 {
                    Self::sse_pabsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_packssdw" => {
                if ops.len() == 2 {
                    Self::sse_packssdw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_packsswb" => {
                if ops.len() == 2 {
                    Self::sse_packsswb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_packusdw" => {
                if ops.len() == 2 {
                    Self::sse_packusdw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_packuswb" => {
                if ops.len() == 2 {
                    Self::sse_packuswb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_paddb" => {
                if ops.len() == 2 {
                    Self::sse_paddb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_paddd" => {
                if ops.len() == 2 {
                    Self::sse_paddd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_paddq" => {
                if ops.len() == 2 {
                    Self::sse_paddq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_paddsb" => {
                if ops.len() == 2 {
                    Self::sse_paddsb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_paddsw" => {
                if ops.len() == 2 {
                    Self::sse_paddsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_paddusb" => {
                if ops.len() == 2 {
                    Self::sse_paddusb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_paddusw" => {
                if ops.len() == 2 {
                    Self::sse_paddusw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_paddw" => {
                if ops.len() == 2 {
                    Self::sse_paddw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_palignr" => {
                if ops.len() == 3 {
                    Self::sse_palignr(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pand" => {
                if ops.len() == 2 {
                    Self::sse_pand(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pandn" => {
                if ops.len() == 2 {
                    Self::sse_pandn(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pavgb" => {
                if ops.len() == 2 {
                    Self::sse_pavgb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pavgw" => {
                if ops.len() == 2 {
                    Self::sse_pavgw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pblendvb" => {
                if ops.len() == 2 {
                    Self::sse_pblendvb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pblendw" => {
                if ops.len() == 3 {
                    Self::sse_pblendw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pclmulqdq" => {
                if ops.len() == 3 {
                    Self::sse_pclmulqdq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpeqb" => {
                if ops.len() == 2 {
                    Self::sse_pcmpeqb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpeqd" => {
                if ops.len() == 2 {
                    Self::sse_pcmpeqd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpeqq" => {
                if ops.len() == 2 {
                    Self::sse_pcmpeqq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpeqw" => {
                if ops.len() == 2 {
                    Self::sse_pcmpeqw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpestri" => {
                if ops.len() == 3 {
                    Self::sse_pcmpestri(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpestrm" => {
                if ops.len() == 3 {
                    Self::sse_pcmpestrm(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpgtb" => {
                if ops.len() == 2 {
                    Self::sse_pcmpgtb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpgtd" => {
                if ops.len() == 2 {
                    Self::sse_pcmpgtd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpgtq" => {
                if ops.len() == 2 {
                    Self::sse_pcmpgtq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpgtw" => {
                if ops.len() == 2 {
                    Self::sse_pcmpgtw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpistri" => {
                if ops.len() == 3 {
                    Self::sse_pcmpistri(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pcmpistrm" => {
                if ops.len() == 3 {
                    Self::sse_pcmpistrm(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pextrb" => {
                if ops.len() == 3 {
                    Self::sse_pextrb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pextrd" => {
                if ops.len() == 3 {
                    Self::sse_pextrd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pextrq" => {
                if ops.len() == 3 {
                    Self::sse_pextrq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pextrw" => {
                if ops.len() == 3 {
                    Self::sse_pextrw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_phaddd" => {
                if ops.len() == 2 {
                    Self::sse_phaddd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_phaddsw" => {
                if ops.len() == 2 {
                    Self::sse_phaddsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_phaddw" => {
                if ops.len() == 2 {
                    Self::sse_phaddw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_phminposuw" => {
                if ops.len() == 2 {
                    Self::sse_phminposuw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_phsubd" => {
                if ops.len() == 2 {
                    Self::sse_phsubd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_phsubsw" => {
                if ops.len() == 2 {
                    Self::sse_phsubsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_phsubw" => {
                if ops.len() == 2 {
                    Self::sse_phsubw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pinsrb" => {
                if ops.len() == 3 {
                    Self::sse_pinsrb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pinsrd" => {
                if ops.len() == 3 {
                    Self::sse_pinsrd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pinsrq" => {
                if ops.len() == 3 {
                    Self::sse_pinsrq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pinsrw" => {
                if ops.len() == 3 {
                    Self::sse_pinsrw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmaddubsw" => {
                if ops.len() == 2 {
                    Self::sse_pmaddubsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmaddwd" => {
                if ops.len() == 2 {
                    Self::sse_pmaddwd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmaxsb" => {
                if ops.len() == 2 {
                    Self::sse_pmaxsb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmaxsd" => {
                if ops.len() == 2 {
                    Self::sse_pmaxsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmaxsw" => {
                if ops.len() == 2 {
                    Self::sse_pmaxsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmaxub" => {
                if ops.len() == 2 {
                    Self::sse_pmaxub(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmaxud" => {
                if ops.len() == 2 {
                    Self::sse_pmaxud(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmaxuw" => {
                if ops.len() == 2 {
                    Self::sse_pmaxuw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pminsb" => {
                if ops.len() == 2 {
                    Self::sse_pminsb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pminsd" => {
                if ops.len() == 2 {
                    Self::sse_pminsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pminsw" => {
                if ops.len() == 2 {
                    Self::sse_pminsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pminub" => {
                if ops.len() == 2 {
                    Self::sse_pminub(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pminud" => {
                if ops.len() == 2 {
                    Self::sse_pminud(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pminuw" => {
                if ops.len() == 2 {
                    Self::sse_pminuw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovmskb" => {
                if ops.len() == 2 {
                    Self::sse_pmovmskb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovsxbd" => {
                if ops.len() == 2 {
                    Self::sse_pmovsxbd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovsxbq" => {
                if ops.len() == 2 {
                    Self::sse_pmovsxbq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovsxbw" => {
                if ops.len() == 2 {
                    Self::sse_pmovsxbw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovsxdq" => {
                if ops.len() == 2 {
                    Self::sse_pmovsxdq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovsxwd" => {
                if ops.len() == 2 {
                    Self::sse_pmovsxwd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovsxwq" => {
                if ops.len() == 2 {
                    Self::sse_pmovsxwq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovzxbd" => {
                if ops.len() == 2 {
                    Self::sse_pmovzxbd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovzxbq" => {
                if ops.len() == 2 {
                    Self::sse_pmovzxbq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovzxbw" => {
                if ops.len() == 2 {
                    Self::sse_pmovzxbw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovzxdq" => {
                if ops.len() == 2 {
                    Self::sse_pmovzxdq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovzxwd" => {
                if ops.len() == 2 {
                    Self::sse_pmovzxwd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmovzxwq" => {
                if ops.len() == 2 {
                    Self::sse_pmovzxwq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmuldq" => {
                if ops.len() == 2 {
                    Self::sse_pmuldq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmulhrsw" => {
                if ops.len() == 2 {
                    Self::sse_pmulhrsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmulhuw" => {
                if ops.len() == 2 {
                    Self::sse_pmulhuw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmulhw" => {
                if ops.len() == 2 {
                    Self::sse_pmulhw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmulld" => {
                if ops.len() == 2 {
                    Self::sse_pmulld(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmullw" => {
                if ops.len() == 2 {
                    Self::sse_pmullw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pmuludq" => {
                if ops.len() == 2 {
                    Self::sse_pmuludq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_por" => {
                if ops.len() == 2 {
                    Self::sse_por(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psadbw" => {
                if ops.len() == 2 {
                    Self::sse_psadbw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pshufb" => {
                if ops.len() == 2 {
                    Self::sse_pshufb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pshufd" => {
                if ops.len() == 3 {
                    Self::sse_pshufd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pshufhw" => {
                if ops.len() == 3 {
                    Self::sse_pshufhw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pshuflw" => {
                if ops.len() == 3 {
                    Self::sse_pshuflw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psignb" => {
                if ops.len() == 2 {
                    Self::sse_psignb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psignd" => {
                if ops.len() == 2 {
                    Self::sse_psignd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psignw" => {
                if ops.len() == 2 {
                    Self::sse_psignw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pslld" => {
                if ops.len() == 2 {
                    Self::sse_pslld(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pslldq" => {
                if ops.len() == 2 {
                    Self::sse_pslldq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psllq" => {
                if ops.len() == 2 {
                    Self::sse_psllq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psllw" => {
                if ops.len() == 2 {
                    Self::sse_psllw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psrad" => {
                if ops.len() == 2 {
                    Self::sse_psrad(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psraw" => {
                if ops.len() == 2 {
                    Self::sse_psraw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psrld" => {
                if ops.len() == 2 {
                    Self::sse_psrld(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psrldq" => {
                if ops.len() == 2 {
                    Self::sse_psrldq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psrlq" => {
                if ops.len() == 2 {
                    Self::sse_psrlq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psrlw" => {
                if ops.len() == 2 {
                    Self::sse_psrlw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psubb" => {
                if ops.len() == 2 {
                    Self::sse_psubb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psubd" => {
                if ops.len() == 2 {
                    Self::sse_psubd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psubq" => {
                if ops.len() == 2 {
                    Self::sse_psubq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psubsb" => {
                if ops.len() == 2 {
                    Self::sse_psubsb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psubsw" => {
                if ops.len() == 2 {
                    Self::sse_psubsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psubusb" => {
                if ops.len() == 2 {
                    Self::sse_psubusb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psubusw" => {
                if ops.len() == 2 {
                    Self::sse_psubusw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_psubw" => {
                if ops.len() == 2 {
                    Self::sse_psubw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_ptest" => {
                if ops.len() == 2 {
                    Self::sse_ptest(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_punpckhbw" => {
                if ops.len() == 2 {
                    Self::sse_punpckhbw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_punpckhdq" => {
                if ops.len() == 2 {
                    Self::sse_punpckhdq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_punpckhqdq" => {
                if ops.len() == 2 {
                    Self::sse_punpckhqdq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_punpckhwd" => {
                if ops.len() == 2 {
                    Self::sse_punpckhwd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_punpcklbw" => {
                if ops.len() == 2 {
                    Self::sse_punpcklbw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_punpckldq" => {
                if ops.len() == 2 {
                    Self::sse_punpckldq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_punpcklqdq" => {
                if ops.len() == 2 {
                    Self::sse_punpcklqdq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_punpcklwd" => {
                if ops.len() == 2 {
                    Self::sse_punpcklwd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_pxor" => {
                if ops.len() == 2 {
                    Self::sse_pxor(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_rcpps" => {
                if ops.len() == 2 {
                    Self::sse_rcpps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_rcpss" => {
                if ops.len() == 2 {
                    Self::sse_rcpss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_roundpd" => {
                if ops.len() == 3 {
                    Self::sse_roundpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_roundps" => {
                if ops.len() == 3 {
                    Self::sse_roundps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_roundsd" => {
                if ops.len() == 3 {
                    Self::sse_roundsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_roundss" => {
                if ops.len() == 3 {
                    Self::sse_roundss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_rsqrtps" => {
                if ops.len() == 2 {
                    Self::sse_rsqrtps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_rsqrtss" => {
                if ops.len() == 2 {
                    Self::sse_rsqrtss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_shufpd" => {
                if ops.len() == 3 {
                    Self::sse_shufpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_shufps" => {
                if ops.len() == 3 {
                    Self::sse_shufps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_sqrtpd" => {
                if ops.len() == 2 {
                    Self::sse_sqrtpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_sqrtps" => {
                if ops.len() == 2 {
                    Self::sse_sqrtps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_sqrtsd" => {
                if ops.len() == 2 {
                    Self::sse_sqrtsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_sqrtss" => {
                if ops.len() == 2 {
                    Self::sse_sqrtss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_subpd" => {
                if ops.len() == 2 {
                    Self::sse_subpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_subps" => {
                if ops.len() == 2 {
                    Self::sse_subps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_subsd" => {
                if ops.len() == 2 {
                    Self::sse_subsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_subss" => {
                if ops.len() == 2 {
                    Self::sse_subss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_ucomisd" => {
                if ops.len() == 2 {
                    Self::sse_ucomisd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_ucomiss" => {
                if ops.len() == 2 {
                    Self::sse_ucomiss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_unpckhpd" => {
                if ops.len() == 2 {
                    Self::sse_unpckhpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_unpckhps" => {
                if ops.len() == 2 {
                    Self::sse_unpckhps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_unpcklpd" => {
                if ops.len() == 2 {
                    Self::sse_unpcklpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_unpcklps" => {
                if ops.len() == 2 {
                    Self::sse_unpcklps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_xorpd" => {
                if ops.len() == 2 {
                    Self::sse_xorpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sse_xorps" => {
                if ops.len() == 2 {
                    Self::sse_xorps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "stac" => {
                if ops.is_empty() {
                    Self::stac()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "stc" => {
                if ops.is_empty() {
                    Self::stc()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "std" => {
                if ops.is_empty() {
                    Self::std()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "stgi" => {
                if ops.is_empty() {
                    Self::stgi()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sti" => {
                if ops.is_empty() {
                    Self::sti()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "stmxcsr" => {
                if ops.len() == 1 {
                    Self::stmxcsr(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "stos" => {
                if ops.is_empty() {
                    Self::stos()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "str" => {
                if ops.len() == 1 {
                    Self::str(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sttilecfg" => {
                if ops.len() == 1 {
                    Self::sttilecfg(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "stui" => {
                if ops.is_empty() {
                    Self::stui()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sub" => {
                if ops.len() == 2 {
                    Self::sub(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "swapgs" => {
                if ops.is_empty() {
                    Self::swapgs()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "syscall" => {
                if ops.is_empty() {
                    Self::syscall()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sysenter" => {
                if ops.is_empty() {
                    Self::sysenter()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sysexit" => {
                if ops.is_empty() {
                    Self::sysexit()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "sysret" => {
                if ops.is_empty() {
                    Self::sysret()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tcmmimfp16ps" => {
                if ops.len() == 3 {
                    Self::tcmmimfp16ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tcmmrlfp16ps" => {
                if ops.len() == 3 {
                    Self::tcmmrlfp16ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tdcall" => {
                if ops.is_empty() {
                    Self::tdcall()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tdpbf16ps" => {
                if ops.len() == 3 {
                    Self::tdpbf16ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tdpbssd" => {
                if ops.len() == 3 {
                    Self::tdpbssd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tdpbsud" => {
                if ops.len() == 3 {
                    Self::tdpbsud(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tdpbusd" => {
                if ops.len() == 3 {
                    Self::tdpbusd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tdpbuud" => {
                if ops.len() == 3 {
                    Self::tdpbuud(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tdpfp16ps" => {
                if ops.len() == 3 {
                    Self::tdpfp16ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "test" => {
                if ops.len() == 2 {
                    Self::test(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "testui" => {
                if ops.is_empty() {
                    Self::testui()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tileloadd" => {
                if ops.len() == 2 {
                    Self::tileloadd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tileloaddt1" => {
                if ops.len() == 2 {
                    Self::tileloaddt1(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tilerelease" => {
                if ops.is_empty() {
                    Self::tilerelease()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tilestored" => {
                if ops.len() == 2 {
                    Self::tilestored(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tilezero" => {
                if ops.len() == 1 {
                    Self::tilezero(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tlbsync" => {
                if ops.is_empty() {
                    Self::tlbsync()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tpause" => {
                if ops.len() == 1 {
                    Self::tpause(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "tzcnt" => {
                if ops.len() == 2 {
                    Self::tzcnt(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ud0" => {
                if ops.len() == 2 {
                    Self::ud0(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ud1" => {
                if ops.len() == 2 {
                    Self::ud1(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "ud2" => {
                if ops.is_empty() {
                    Self::ud2()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "uiret" => {
                if ops.is_empty() {
                    Self::uiret()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "umonitor" => {
                if ops.len() == 1 {
                    Self::umonitor(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "umwait" => {
                if ops.len() == 1 {
                    Self::umwait(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "urdmsr" => {
                if ops.len() == 2 {
                    Self::urdmsr(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "uwrmsr" => {
                if ops.len() == 2 {
                    Self::uwrmsr(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddpd" => {
                if ops.len() == 3 {
                    Self::vaddpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddpd_er" => {
                if ops.len() == 3 {
                    Self::vaddpd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddpd_mask" => {
                if ops.len() == 3 {
                    Self::vaddpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddpd_mask_er" => {
                if ops.len() == 3 {
                    Self::vaddpd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddpd_maskz" => {
                if ops.len() == 3 {
                    Self::vaddpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddpd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vaddpd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddph" => {
                if ops.len() == 3 {
                    Self::vaddph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddph_er" => {
                if ops.len() == 3 {
                    Self::vaddph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddph_mask" => {
                if ops.len() == 3 {
                    Self::vaddph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddph_mask_er" => {
                if ops.len() == 3 {
                    Self::vaddph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddph_maskz" => {
                if ops.len() == 3 {
                    Self::vaddph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vaddph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddps" => {
                if ops.len() == 3 {
                    Self::vaddps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddps_er" => {
                if ops.len() == 3 {
                    Self::vaddps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddps_mask" => {
                if ops.len() == 3 {
                    Self::vaddps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddps_mask_er" => {
                if ops.len() == 3 {
                    Self::vaddps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddps_maskz" => {
                if ops.len() == 3 {
                    Self::vaddps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vaddps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsd" => {
                if ops.len() == 3 {
                    Self::vaddsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsd_er" => {
                if ops.len() == 3 {
                    Self::vaddsd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsd_mask" => {
                if ops.len() == 3 {
                    Self::vaddsd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsd_mask_er" => {
                if ops.len() == 3 {
                    Self::vaddsd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsd_maskz" => {
                if ops.len() == 3 {
                    Self::vaddsd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vaddsd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsh" => {
                if ops.len() == 3 {
                    Self::vaddsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsh_er" => {
                if ops.len() == 3 {
                    Self::vaddsh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsh_mask" => {
                if ops.len() == 3 {
                    Self::vaddsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsh_mask_er" => {
                if ops.len() == 3 {
                    Self::vaddsh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsh_maskz" => {
                if ops.len() == 3 {
                    Self::vaddsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vaddsh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddss" => {
                if ops.len() == 3 {
                    Self::vaddss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddss_er" => {
                if ops.len() == 3 {
                    Self::vaddss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddss_mask" => {
                if ops.len() == 3 {
                    Self::vaddss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddss_mask_er" => {
                if ops.len() == 3 {
                    Self::vaddss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddss_maskz" => {
                if ops.len() == 3 {
                    Self::vaddss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vaddss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsubpd" => {
                if ops.len() == 3 {
                    Self::vaddsubpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaddsubps" => {
                if ops.len() == 3 {
                    Self::vaddsubps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaesdec" => {
                if ops.len() == 3 {
                    Self::vaesdec(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaesdeclast" => {
                if ops.len() == 3 {
                    Self::vaesdeclast(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaesenc" => {
                if ops.len() == 3 {
                    Self::vaesenc(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaesenclast" => {
                if ops.len() == 3 {
                    Self::vaesenclast(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaesimc" => {
                if ops.len() == 2 {
                    Self::vaesimc(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vaeskeygenassist" => {
                if ops.len() == 3 {
                    Self::vaeskeygenassist(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "valignd" => {
                if ops.len() == 4 {
                    Self::valignd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "valignd_mask" => {
                if ops.len() == 4 {
                    Self::valignd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "valignd_maskz" => {
                if ops.len() == 4 {
                    Self::valignd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "valignq" => {
                if ops.len() == 4 {
                    Self::valignq(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "valignq_mask" => {
                if ops.len() == 4 {
                    Self::valignq_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "valignq_maskz" => {
                if ops.len() == 4 {
                    Self::valignq_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandnpd" => {
                if ops.len() == 3 {
                    Self::vandnpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandnpd_mask" => {
                if ops.len() == 3 {
                    Self::vandnpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandnpd_maskz" => {
                if ops.len() == 3 {
                    Self::vandnpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandnps" => {
                if ops.len() == 3 {
                    Self::vandnps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandnps_mask" => {
                if ops.len() == 3 {
                    Self::vandnps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandnps_maskz" => {
                if ops.len() == 3 {
                    Self::vandnps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandpd" => {
                if ops.len() == 3 {
                    Self::vandpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandpd_mask" => {
                if ops.len() == 3 {
                    Self::vandpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandpd_maskz" => {
                if ops.len() == 3 {
                    Self::vandpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandps" => {
                if ops.len() == 3 {
                    Self::vandps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandps_mask" => {
                if ops.len() == 3 {
                    Self::vandps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vandps_maskz" => {
                if ops.len() == 3 {
                    Self::vandps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbcstnebf162ps" => {
                if ops.len() == 2 {
                    Self::vbcstnebf162ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbcstnesh2ps" => {
                if ops.len() == 2 {
                    Self::vbcstnesh2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vblendmpd" => {
                if ops.len() == 3 {
                    Self::vblendmpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vblendmpd_mask" => {
                if ops.len() == 3 {
                    Self::vblendmpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vblendmpd_maskz" => {
                if ops.len() == 3 {
                    Self::vblendmpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vblendmps" => {
                if ops.len() == 3 {
                    Self::vblendmps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vblendmps_mask" => {
                if ops.len() == 3 {
                    Self::vblendmps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vblendmps_maskz" => {
                if ops.len() == 3 {
                    Self::vblendmps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vblendpd" => {
                if ops.len() == 4 {
                    Self::vblendpd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vblendps" => {
                if ops.len() == 4 {
                    Self::vblendps(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vblendvpd" => {
                if ops.len() == 4 {
                    Self::vblendvpd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vblendvps" => {
                if ops.len() == 4 {
                    Self::vblendvps(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf128" => {
                if ops.len() == 2 {
                    Self::vbroadcastf128(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf32x2" => {
                if ops.len() == 2 {
                    Self::vbroadcastf32x2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf32x2_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcastf32x2_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf32x2_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcastf32x2_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf32x4" => {
                if ops.len() == 2 {
                    Self::vbroadcastf32x4(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf32x4_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcastf32x4_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf32x4_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcastf32x4_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf32x8" => {
                if ops.len() == 2 {
                    Self::vbroadcastf32x8(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf32x8_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcastf32x8_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf32x8_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcastf32x8_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf64x2" => {
                if ops.len() == 2 {
                    Self::vbroadcastf64x2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf64x2_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcastf64x2_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf64x2_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcastf64x2_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf64x4" => {
                if ops.len() == 2 {
                    Self::vbroadcastf64x4(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf64x4_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcastf64x4_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastf64x4_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcastf64x4_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti128" => {
                if ops.len() == 2 {
                    Self::vbroadcasti128(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti32x2" => {
                if ops.len() == 2 {
                    Self::vbroadcasti32x2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti32x2_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcasti32x2_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti32x2_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcasti32x2_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti32x4" => {
                if ops.len() == 2 {
                    Self::vbroadcasti32x4(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti32x4_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcasti32x4_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti32x4_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcasti32x4_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti32x8" => {
                if ops.len() == 2 {
                    Self::vbroadcasti32x8(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti32x8_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcasti32x8_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti32x8_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcasti32x8_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti64x2" => {
                if ops.len() == 2 {
                    Self::vbroadcasti64x2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti64x2_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcasti64x2_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti64x2_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcasti64x2_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti64x4" => {
                if ops.len() == 2 {
                    Self::vbroadcasti64x4(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti64x4_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcasti64x4_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcasti64x4_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcasti64x4_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastsd" => {
                if ops.len() == 2 {
                    Self::vbroadcastsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastsd_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcastsd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastsd_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcastsd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastss" => {
                if ops.len() == 2 {
                    Self::vbroadcastss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastss_mask" => {
                if ops.len() == 2 {
                    Self::vbroadcastss_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vbroadcastss_maskz" => {
                if ops.len() == 2 {
                    Self::vbroadcastss_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmppd" => {
                if ops.len() == 4 {
                    Self::vcmppd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmppd_mask" => {
                if ops.len() == 4 {
                    Self::vcmppd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmppd_mask_sae" => {
                if ops.len() == 4 {
                    Self::vcmppd_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmppd_sae" => {
                if ops.len() == 4 {
                    Self::vcmppd_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpph" => {
                if ops.len() == 4 {
                    Self::vcmpph(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpph_mask" => {
                if ops.len() == 4 {
                    Self::vcmpph_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpph_mask_sae" => {
                if ops.len() == 4 {
                    Self::vcmpph_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpph_sae" => {
                if ops.len() == 4 {
                    Self::vcmpph_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpps" => {
                if ops.len() == 4 {
                    Self::vcmpps(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpps_mask" => {
                if ops.len() == 4 {
                    Self::vcmpps_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpps_mask_sae" => {
                if ops.len() == 4 {
                    Self::vcmpps_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpps_sae" => {
                if ops.len() == 4 {
                    Self::vcmpps_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpsd" => {
                if ops.len() == 4 {
                    Self::vcmpsd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpsd_mask" => {
                if ops.len() == 4 {
                    Self::vcmpsd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpsd_mask_sae" => {
                if ops.len() == 4 {
                    Self::vcmpsd_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpsd_sae" => {
                if ops.len() == 4 {
                    Self::vcmpsd_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpsh" => {
                if ops.len() == 4 {
                    Self::vcmpsh(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpsh_mask" => {
                if ops.len() == 4 {
                    Self::vcmpsh_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpsh_mask_sae" => {
                if ops.len() == 4 {
                    Self::vcmpsh_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpsh_sae" => {
                if ops.len() == 4 {
                    Self::vcmpsh_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpss" => {
                if ops.len() == 4 {
                    Self::vcmpss(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpss_mask" => {
                if ops.len() == 4 {
                    Self::vcmpss_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpss_mask_sae" => {
                if ops.len() == 4 {
                    Self::vcmpss_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcmpss_sae" => {
                if ops.len() == 4 {
                    Self::vcmpss_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcomisd" => {
                if ops.len() == 2 {
                    Self::vcomisd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcomisd_sae" => {
                if ops.len() == 2 {
                    Self::vcomisd_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcomish" => {
                if ops.len() == 2 {
                    Self::vcomish(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcomish_sae" => {
                if ops.len() == 2 {
                    Self::vcomish_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcomiss" => {
                if ops.len() == 2 {
                    Self::vcomiss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcomiss_sae" => {
                if ops.len() == 2 {
                    Self::vcomiss_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcompresspd" => {
                if ops.len() == 2 {
                    Self::vcompresspd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcompresspd_mask" => {
                if ops.len() == 2 {
                    Self::vcompresspd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcompresspd_maskz" => {
                if ops.len() == 2 {
                    Self::vcompresspd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcompressps" => {
                if ops.len() == 2 {
                    Self::vcompressps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcompressps_mask" => {
                if ops.len() == 2 {
                    Self::vcompressps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcompressps_maskz" => {
                if ops.len() == 2 {
                    Self::vcompressps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2pd" => {
                if ops.len() == 2 {
                    Self::vcvtdq2pd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2pd_mask" => {
                if ops.len() == 2 {
                    Self::vcvtdq2pd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2pd_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvtdq2pd_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2pd_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtdq2pd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2pd_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvtdq2pd_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2pd_sae" => {
                if ops.len() == 2 {
                    Self::vcvtdq2pd_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ph" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ph(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ph_er" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ph_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ph_mask" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ph_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ph_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ph_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ph_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ph_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ph_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ph_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ps" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ps_er" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ps_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ps_mask" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ps_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ps_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ps_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtdq2ps_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtdq2ps_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtne2ps2bf16" => {
                if ops.len() == 3 {
                    Self::vcvtne2ps2bf16(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtne2ps2bf16_mask" => {
                if ops.len() == 3 {
                    Self::vcvtne2ps2bf16_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtne2ps2bf16_maskz" => {
                if ops.len() == 3 {
                    Self::vcvtne2ps2bf16_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtneebf162ps" => {
                if ops.len() == 2 {
                    Self::vcvtneebf162ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtneeph2ps" => {
                if ops.len() == 2 {
                    Self::vcvtneeph2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtneobf162ps" => {
                if ops.len() == 2 {
                    Self::vcvtneobf162ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtneoph2ps" => {
                if ops.len() == 2 {
                    Self::vcvtneoph2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtneps2bf16" => {
                if ops.len() == 2 {
                    Self::vcvtneps2bf16(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtneps2bf16_mask" => {
                if ops.len() == 2 {
                    Self::vcvtneps2bf16_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtneps2bf16_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtneps2bf16_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2dq" => {
                if ops.len() == 2 {
                    Self::vcvtpd2dq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2dq_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2dq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2dq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtpd2dq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2dq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2dq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2dq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtpd2dq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2dq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2dq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ph" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ph(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ph_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ph_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ph_mask" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ph_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ph_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ph_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ph_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ph_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ph_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ph_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ps" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ps_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ps_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ps_mask" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ps_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ps_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ps_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2ps_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2ps_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2qq" => {
                if ops.len() == 2 {
                    Self::vcvtpd2qq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2qq_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2qq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2qq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtpd2qq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2qq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2qq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2qq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtpd2qq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2qq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2qq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2udq" => {
                if ops.len() == 2 {
                    Self::vcvtpd2udq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2udq_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2udq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2udq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtpd2udq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2udq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2udq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2udq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtpd2udq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2udq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2udq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2uqq" => {
                if ops.len() == 2 {
                    Self::vcvtpd2uqq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2uqq_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2uqq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2uqq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtpd2uqq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2uqq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2uqq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2uqq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtpd2uqq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtpd2uqq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtpd2uqq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2dq" => {
                if ops.len() == 2 {
                    Self::vcvtph2dq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2dq_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2dq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2dq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtph2dq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2dq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2dq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2dq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtph2dq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2dq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2dq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2pd" => {
                if ops.len() == 2 {
                    Self::vcvtph2pd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2pd_mask" => {
                if ops.len() == 2 {
                    Self::vcvtph2pd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2pd_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvtph2pd_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2pd_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtph2pd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2pd_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvtph2pd_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2pd_sae" => {
                if ops.len() == 2 {
                    Self::vcvtph2pd_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2ps" => {
                if ops.len() == 2 {
                    Self::vcvtph2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2psx" => {
                if ops.len() == 2 {
                    Self::vcvtph2psx(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2psx_mask" => {
                if ops.len() == 2 {
                    Self::vcvtph2psx_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2psx_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvtph2psx_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2psx_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtph2psx_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2psx_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvtph2psx_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2psx_sae" => {
                if ops.len() == 2 {
                    Self::vcvtph2psx_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2ps_mask" => {
                if ops.len() == 2 {
                    Self::vcvtph2ps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2ps_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvtph2ps_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2ps_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtph2ps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2ps_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvtph2ps_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2ps_sae" => {
                if ops.len() == 2 {
                    Self::vcvtph2ps_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2qq" => {
                if ops.len() == 2 {
                    Self::vcvtph2qq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2qq_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2qq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2qq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtph2qq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2qq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2qq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2qq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtph2qq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2qq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2qq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2udq" => {
                if ops.len() == 2 {
                    Self::vcvtph2udq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2udq_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2udq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2udq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtph2udq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2udq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2udq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2udq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtph2udq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2udq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2udq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uqq" => {
                if ops.len() == 2 {
                    Self::vcvtph2uqq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uqq_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2uqq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uqq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtph2uqq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uqq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2uqq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uqq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtph2uqq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uqq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2uqq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uw" => {
                if ops.len() == 2 {
                    Self::vcvtph2uw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uw_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2uw_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uw_mask" => {
                if ops.len() == 2 {
                    Self::vcvtph2uw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uw_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2uw_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uw_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtph2uw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2uw_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2uw_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2w" => {
                if ops.len() == 2 {
                    Self::vcvtph2w(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2w_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2w_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2w_mask" => {
                if ops.len() == 2 {
                    Self::vcvtph2w_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2w_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2w_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2w_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtph2w_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtph2w_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtph2w_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2dq" => {
                if ops.len() == 2 {
                    Self::vcvtps2dq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2dq_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2dq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2dq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtps2dq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2dq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2dq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2dq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtps2dq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2dq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2dq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2pd" => {
                if ops.len() == 2 {
                    Self::vcvtps2pd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2pd_mask" => {
                if ops.len() == 2 {
                    Self::vcvtps2pd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2pd_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvtps2pd_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2pd_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtps2pd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2pd_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvtps2pd_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2pd_sae" => {
                if ops.len() == 2 {
                    Self::vcvtps2pd_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2ph" => {
                if ops.len() == 3 {
                    Self::vcvtps2ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2phx" => {
                if ops.len() == 2 {
                    Self::vcvtps2phx(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2phx_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2phx_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2phx_mask" => {
                if ops.len() == 2 {
                    Self::vcvtps2phx_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2phx_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2phx_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2phx_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtps2phx_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2phx_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2phx_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2ph_mask" => {
                if ops.len() == 3 {
                    Self::vcvtps2ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2ph_mask_sae" => {
                if ops.len() == 3 {
                    Self::vcvtps2ph_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2ph_maskz" => {
                if ops.len() == 3 {
                    Self::vcvtps2ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2ph_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vcvtps2ph_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2ph_sae" => {
                if ops.len() == 3 {
                    Self::vcvtps2ph_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2qq" => {
                if ops.len() == 2 {
                    Self::vcvtps2qq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2qq_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2qq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2qq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtps2qq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2qq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2qq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2qq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtps2qq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2qq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2qq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2udq" => {
                if ops.len() == 2 {
                    Self::vcvtps2udq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2udq_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2udq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2udq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtps2udq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2udq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2udq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2udq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtps2udq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2udq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2udq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2uqq" => {
                if ops.len() == 2 {
                    Self::vcvtps2uqq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2uqq_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2uqq_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2uqq_mask" => {
                if ops.len() == 2 {
                    Self::vcvtps2uqq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2uqq_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2uqq_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2uqq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtps2uqq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtps2uqq_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtps2uqq_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2pd" => {
                if ops.len() == 2 {
                    Self::vcvtqq2pd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2pd_er" => {
                if ops.len() == 2 {
                    Self::vcvtqq2pd_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2pd_mask" => {
                if ops.len() == 2 {
                    Self::vcvtqq2pd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2pd_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtqq2pd_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2pd_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtqq2pd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2pd_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtqq2pd_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ph" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ph(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ph_er" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ph_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ph_mask" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ph_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ph_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ph_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ph_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ph_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ph_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ph_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ps" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ps_er" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ps_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ps_mask" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ps_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ps_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ps_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtqq2ps_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtqq2ps_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2sh" => {
                if ops.len() == 3 {
                    Self::vcvtsd2sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2sh_er" => {
                if ops.len() == 3 {
                    Self::vcvtsd2sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2sh_mask" => {
                if ops.len() == 3 {
                    Self::vcvtsd2sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vcvtsd2sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2sh_maskz" => {
                if ops.len() == 3 {
                    Self::vcvtsd2sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vcvtsd2sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2si" => {
                if ops.len() == 2 {
                    Self::vcvtsd2si(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2si_er" => {
                if ops.len() == 2 {
                    Self::vcvtsd2si_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2ss" => {
                if ops.len() == 3 {
                    Self::vcvtsd2ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2ss_er" => {
                if ops.len() == 3 {
                    Self::vcvtsd2ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2ss_mask" => {
                if ops.len() == 3 {
                    Self::vcvtsd2ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vcvtsd2ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2ss_maskz" => {
                if ops.len() == 3 {
                    Self::vcvtsd2ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vcvtsd2ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2usi" => {
                if ops.len() == 2 {
                    Self::vcvtsd2usi(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsd2usi_er" => {
                if ops.len() == 2 {
                    Self::vcvtsd2usi_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2sd" => {
                if ops.len() == 3 {
                    Self::vcvtsh2sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2sd_mask" => {
                if ops.len() == 3 {
                    Self::vcvtsh2sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2sd_mask_sae" => {
                if ops.len() == 3 {
                    Self::vcvtsh2sd_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2sd_maskz" => {
                if ops.len() == 3 {
                    Self::vcvtsh2sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2sd_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vcvtsh2sd_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2sd_sae" => {
                if ops.len() == 3 {
                    Self::vcvtsh2sd_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2si" => {
                if ops.len() == 2 {
                    Self::vcvtsh2si(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2si_er" => {
                if ops.len() == 2 {
                    Self::vcvtsh2si_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2ss" => {
                if ops.len() == 3 {
                    Self::vcvtsh2ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2ss_mask" => {
                if ops.len() == 3 {
                    Self::vcvtsh2ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2ss_mask_sae" => {
                if ops.len() == 3 {
                    Self::vcvtsh2ss_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2ss_maskz" => {
                if ops.len() == 3 {
                    Self::vcvtsh2ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2ss_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vcvtsh2ss_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2ss_sae" => {
                if ops.len() == 3 {
                    Self::vcvtsh2ss_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2usi" => {
                if ops.len() == 2 {
                    Self::vcvtsh2usi(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsh2usi_er" => {
                if ops.len() == 2 {
                    Self::vcvtsh2usi_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsi2sd" => {
                if ops.len() == 3 {
                    Self::vcvtsi2sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsi2sd_er" => {
                if ops.len() == 3 {
                    Self::vcvtsi2sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsi2sh" => {
                if ops.len() == 3 {
                    Self::vcvtsi2sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsi2sh_er" => {
                if ops.len() == 3 {
                    Self::vcvtsi2sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsi2ss" => {
                if ops.len() == 3 {
                    Self::vcvtsi2ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtsi2ss_er" => {
                if ops.len() == 3 {
                    Self::vcvtsi2ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sd" => {
                if ops.len() == 3 {
                    Self::vcvtss2sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sd_mask" => {
                if ops.len() == 3 {
                    Self::vcvtss2sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sd_mask_sae" => {
                if ops.len() == 3 {
                    Self::vcvtss2sd_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sd_maskz" => {
                if ops.len() == 3 {
                    Self::vcvtss2sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sd_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vcvtss2sd_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sd_sae" => {
                if ops.len() == 3 {
                    Self::vcvtss2sd_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sh" => {
                if ops.len() == 3 {
                    Self::vcvtss2sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sh_er" => {
                if ops.len() == 3 {
                    Self::vcvtss2sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sh_mask" => {
                if ops.len() == 3 {
                    Self::vcvtss2sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vcvtss2sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sh_maskz" => {
                if ops.len() == 3 {
                    Self::vcvtss2sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vcvtss2sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2si" => {
                if ops.len() == 2 {
                    Self::vcvtss2si(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2si_er" => {
                if ops.len() == 2 {
                    Self::vcvtss2si_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2usi" => {
                if ops.len() == 2 {
                    Self::vcvtss2usi(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtss2usi_er" => {
                if ops.len() == 2 {
                    Self::vcvtss2usi_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2dq" => {
                if ops.len() == 2 {
                    Self::vcvttpd2dq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2dq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttpd2dq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2dq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2dq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2dq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttpd2dq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2dq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2dq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2dq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2dq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2qq" => {
                if ops.len() == 2 {
                    Self::vcvttpd2qq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2qq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttpd2qq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2qq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2qq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2qq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttpd2qq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2qq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2qq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2qq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2qq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2udq" => {
                if ops.len() == 2 {
                    Self::vcvttpd2udq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2udq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttpd2udq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2udq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2udq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2udq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttpd2udq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2udq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2udq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2udq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2udq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2uqq" => {
                if ops.len() == 2 {
                    Self::vcvttpd2uqq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2uqq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttpd2uqq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2uqq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2uqq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2uqq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttpd2uqq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2uqq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2uqq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttpd2uqq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttpd2uqq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2dq" => {
                if ops.len() == 2 {
                    Self::vcvttph2dq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2dq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttph2dq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2dq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2dq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2dq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttph2dq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2dq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2dq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2dq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2dq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2qq" => {
                if ops.len() == 2 {
                    Self::vcvttph2qq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2qq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttph2qq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2qq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2qq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2qq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttph2qq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2qq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2qq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2qq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2qq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2udq" => {
                if ops.len() == 2 {
                    Self::vcvttph2udq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2udq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttph2udq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2udq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2udq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2udq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttph2udq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2udq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2udq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2udq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2udq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uqq" => {
                if ops.len() == 2 {
                    Self::vcvttph2uqq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uqq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttph2uqq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uqq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2uqq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uqq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttph2uqq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uqq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2uqq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uqq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2uqq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uw" => {
                if ops.len() == 2 {
                    Self::vcvttph2uw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uw_mask" => {
                if ops.len() == 2 {
                    Self::vcvttph2uw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uw_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2uw_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uw_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttph2uw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uw_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2uw_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2uw_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2uw_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2w" => {
                if ops.len() == 2 {
                    Self::vcvttph2w(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2w_mask" => {
                if ops.len() == 2 {
                    Self::vcvttph2w_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2w_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2w_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2w_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttph2w_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2w_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2w_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttph2w_sae" => {
                if ops.len() == 2 {
                    Self::vcvttph2w_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2dq" => {
                if ops.len() == 2 {
                    Self::vcvttps2dq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2dq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttps2dq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2dq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2dq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2dq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttps2dq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2dq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2dq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2dq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2dq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2qq" => {
                if ops.len() == 2 {
                    Self::vcvttps2qq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2qq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttps2qq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2qq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2qq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2qq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttps2qq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2qq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2qq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2qq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2qq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2udq" => {
                if ops.len() == 2 {
                    Self::vcvttps2udq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2udq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttps2udq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2udq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2udq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2udq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttps2udq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2udq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2udq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2udq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2udq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2uqq" => {
                if ops.len() == 2 {
                    Self::vcvttps2uqq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2uqq_mask" => {
                if ops.len() == 2 {
                    Self::vcvttps2uqq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2uqq_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2uqq_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2uqq_maskz" => {
                if ops.len() == 2 {
                    Self::vcvttps2uqq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2uqq_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2uqq_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttps2uqq_sae" => {
                if ops.len() == 2 {
                    Self::vcvttps2uqq_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttsd2si" => {
                if ops.len() == 2 {
                    Self::vcvttsd2si(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttsd2si_sae" => {
                if ops.len() == 2 {
                    Self::vcvttsd2si_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttsd2usi" => {
                if ops.len() == 2 {
                    Self::vcvttsd2usi(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttsd2usi_sae" => {
                if ops.len() == 2 {
                    Self::vcvttsd2usi_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttsh2si" => {
                if ops.len() == 2 {
                    Self::vcvttsh2si(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttsh2si_sae" => {
                if ops.len() == 2 {
                    Self::vcvttsh2si_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttsh2usi" => {
                if ops.len() == 2 {
                    Self::vcvttsh2usi(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttsh2usi_sae" => {
                if ops.len() == 2 {
                    Self::vcvttsh2usi_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttss2si" => {
                if ops.len() == 2 {
                    Self::vcvttss2si(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttss2si_sae" => {
                if ops.len() == 2 {
                    Self::vcvttss2si_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttss2usi" => {
                if ops.len() == 2 {
                    Self::vcvttss2usi(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvttss2usi_sae" => {
                if ops.len() == 2 {
                    Self::vcvttss2usi_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2pd" => {
                if ops.len() == 2 {
                    Self::vcvtudq2pd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2pd_mask" => {
                if ops.len() == 2 {
                    Self::vcvtudq2pd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2pd_mask_sae" => {
                if ops.len() == 2 {
                    Self::vcvtudq2pd_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2pd_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtudq2pd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2pd_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vcvtudq2pd_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2pd_sae" => {
                if ops.len() == 2 {
                    Self::vcvtudq2pd_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ph" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ph(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ph_er" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ph_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ph_mask" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ph_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ph_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ph_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ph_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ph_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ph_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ph_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ps" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ps_er" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ps_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ps_mask" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ps_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ps_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ps_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtudq2ps_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtudq2ps_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2pd" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2pd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2pd_er" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2pd_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2pd_mask" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2pd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2pd_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2pd_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2pd_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2pd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2pd_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2pd_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ph" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ph(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ph_er" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ph_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ph_mask" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ph_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ph_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ph_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ph_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ph_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ph_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ph_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ps" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ps_er" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ps_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ps_mask" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ps_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ps_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ps_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuqq2ps_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtuqq2ps_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtusi2sd" => {
                if ops.len() == 3 {
                    Self::vcvtusi2sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtusi2sd_er" => {
                if ops.len() == 3 {
                    Self::vcvtusi2sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtusi2sh" => {
                if ops.len() == 3 {
                    Self::vcvtusi2sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtusi2sh_er" => {
                if ops.len() == 3 {
                    Self::vcvtusi2sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtusi2ss" => {
                if ops.len() == 3 {
                    Self::vcvtusi2ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtusi2ss_er" => {
                if ops.len() == 3 {
                    Self::vcvtusi2ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuw2ph" => {
                if ops.len() == 2 {
                    Self::vcvtuw2ph(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuw2ph_er" => {
                if ops.len() == 2 {
                    Self::vcvtuw2ph_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuw2ph_mask" => {
                if ops.len() == 2 {
                    Self::vcvtuw2ph_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuw2ph_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtuw2ph_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuw2ph_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtuw2ph_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtuw2ph_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtuw2ph_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtw2ph" => {
                if ops.len() == 2 {
                    Self::vcvtw2ph(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtw2ph_er" => {
                if ops.len() == 2 {
                    Self::vcvtw2ph_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtw2ph_mask" => {
                if ops.len() == 2 {
                    Self::vcvtw2ph_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtw2ph_mask_er" => {
                if ops.len() == 2 {
                    Self::vcvtw2ph_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtw2ph_maskz" => {
                if ops.len() == 2 {
                    Self::vcvtw2ph_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vcvtw2ph_maskz_er" => {
                if ops.len() == 2 {
                    Self::vcvtw2ph_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdbpsadbw" => {
                if ops.len() == 4 {
                    Self::vdbpsadbw(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdbpsadbw_mask" => {
                if ops.len() == 4 {
                    Self::vdbpsadbw_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdbpsadbw_maskz" => {
                if ops.len() == 4 {
                    Self::vdbpsadbw_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivpd" => {
                if ops.len() == 3 {
                    Self::vdivpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivpd_er" => {
                if ops.len() == 3 {
                    Self::vdivpd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivpd_mask" => {
                if ops.len() == 3 {
                    Self::vdivpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivpd_mask_er" => {
                if ops.len() == 3 {
                    Self::vdivpd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivpd_maskz" => {
                if ops.len() == 3 {
                    Self::vdivpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivpd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vdivpd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivph" => {
                if ops.len() == 3 {
                    Self::vdivph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivph_er" => {
                if ops.len() == 3 {
                    Self::vdivph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivph_mask" => {
                if ops.len() == 3 {
                    Self::vdivph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivph_mask_er" => {
                if ops.len() == 3 {
                    Self::vdivph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivph_maskz" => {
                if ops.len() == 3 {
                    Self::vdivph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vdivph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivps" => {
                if ops.len() == 3 {
                    Self::vdivps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivps_er" => {
                if ops.len() == 3 {
                    Self::vdivps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivps_mask" => {
                if ops.len() == 3 {
                    Self::vdivps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivps_mask_er" => {
                if ops.len() == 3 {
                    Self::vdivps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivps_maskz" => {
                if ops.len() == 3 {
                    Self::vdivps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vdivps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsd" => {
                if ops.len() == 3 {
                    Self::vdivsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsd_er" => {
                if ops.len() == 3 {
                    Self::vdivsd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsd_mask" => {
                if ops.len() == 3 {
                    Self::vdivsd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsd_mask_er" => {
                if ops.len() == 3 {
                    Self::vdivsd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsd_maskz" => {
                if ops.len() == 3 {
                    Self::vdivsd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vdivsd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsh" => {
                if ops.len() == 3 {
                    Self::vdivsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsh_er" => {
                if ops.len() == 3 {
                    Self::vdivsh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsh_mask" => {
                if ops.len() == 3 {
                    Self::vdivsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsh_mask_er" => {
                if ops.len() == 3 {
                    Self::vdivsh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsh_maskz" => {
                if ops.len() == 3 {
                    Self::vdivsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivsh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vdivsh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivss" => {
                if ops.len() == 3 {
                    Self::vdivss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivss_er" => {
                if ops.len() == 3 {
                    Self::vdivss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivss_mask" => {
                if ops.len() == 3 {
                    Self::vdivss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivss_mask_er" => {
                if ops.len() == 3 {
                    Self::vdivss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivss_maskz" => {
                if ops.len() == 3 {
                    Self::vdivss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdivss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vdivss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdpbf16ps" => {
                if ops.len() == 3 {
                    Self::vdpbf16ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdpbf16ps_mask" => {
                if ops.len() == 3 {
                    Self::vdpbf16ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdpbf16ps_maskz" => {
                if ops.len() == 3 {
                    Self::vdpbf16ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdppd" => {
                if ops.len() == 4 {
                    Self::vdppd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vdpps" => {
                if ops.len() == 4 {
                    Self::vdpps(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "verr" => {
                if ops.len() == 1 {
                    Self::verr(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "verw" => {
                if ops.len() == 1 {
                    Self::verw(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vexpandpd" => {
                if ops.len() == 2 {
                    Self::vexpandpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vexpandpd_mask" => {
                if ops.len() == 2 {
                    Self::vexpandpd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vexpandpd_maskz" => {
                if ops.len() == 2 {
                    Self::vexpandpd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vexpandps" => {
                if ops.len() == 2 {
                    Self::vexpandps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vexpandps_mask" => {
                if ops.len() == 2 {
                    Self::vexpandps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vexpandps_maskz" => {
                if ops.len() == 2 {
                    Self::vexpandps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf128" => {
                if ops.len() == 3 {
                    Self::vextractf128(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf32x4" => {
                if ops.len() == 3 {
                    Self::vextractf32x4(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf32x4_mask" => {
                if ops.len() == 3 {
                    Self::vextractf32x4_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf32x4_maskz" => {
                if ops.len() == 3 {
                    Self::vextractf32x4_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf32x8" => {
                if ops.len() == 3 {
                    Self::vextractf32x8(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf32x8_mask" => {
                if ops.len() == 3 {
                    Self::vextractf32x8_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf32x8_maskz" => {
                if ops.len() == 3 {
                    Self::vextractf32x8_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf64x2" => {
                if ops.len() == 3 {
                    Self::vextractf64x2(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf64x2_mask" => {
                if ops.len() == 3 {
                    Self::vextractf64x2_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf64x2_maskz" => {
                if ops.len() == 3 {
                    Self::vextractf64x2_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf64x4" => {
                if ops.len() == 3 {
                    Self::vextractf64x4(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf64x4_mask" => {
                if ops.len() == 3 {
                    Self::vextractf64x4_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractf64x4_maskz" => {
                if ops.len() == 3 {
                    Self::vextractf64x4_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti128" => {
                if ops.len() == 3 {
                    Self::vextracti128(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti32x4" => {
                if ops.len() == 3 {
                    Self::vextracti32x4(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti32x4_mask" => {
                if ops.len() == 3 {
                    Self::vextracti32x4_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti32x4_maskz" => {
                if ops.len() == 3 {
                    Self::vextracti32x4_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti32x8" => {
                if ops.len() == 3 {
                    Self::vextracti32x8(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti32x8_mask" => {
                if ops.len() == 3 {
                    Self::vextracti32x8_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti32x8_maskz" => {
                if ops.len() == 3 {
                    Self::vextracti32x8_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti64x2" => {
                if ops.len() == 3 {
                    Self::vextracti64x2(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti64x2_mask" => {
                if ops.len() == 3 {
                    Self::vextracti64x2_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti64x2_maskz" => {
                if ops.len() == 3 {
                    Self::vextracti64x2_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti64x4" => {
                if ops.len() == 3 {
                    Self::vextracti64x4(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti64x4_mask" => {
                if ops.len() == 3 {
                    Self::vextracti64x4_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextracti64x4_maskz" => {
                if ops.len() == 3 {
                    Self::vextracti64x4_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vextractps" => {
                if ops.len() == 3 {
                    Self::vextractps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcph" => {
                if ops.len() == 3 {
                    Self::vfcmaddcph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcph_er" => {
                if ops.len() == 3 {
                    Self::vfcmaddcph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcph_mask" => {
                if ops.len() == 3 {
                    Self::vfcmaddcph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfcmaddcph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcph_maskz" => {
                if ops.len() == 3 {
                    Self::vfcmaddcph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfcmaddcph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcsh" => {
                if ops.len() == 3 {
                    Self::vfcmaddcsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcsh_er" => {
                if ops.len() == 3 {
                    Self::vfcmaddcsh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcsh_mask" => {
                if ops.len() == 3 {
                    Self::vfcmaddcsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcsh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfcmaddcsh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcsh_maskz" => {
                if ops.len() == 3 {
                    Self::vfcmaddcsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmaddcsh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfcmaddcsh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcph" => {
                if ops.len() == 3 {
                    Self::vfcmulcph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcph_er" => {
                if ops.len() == 3 {
                    Self::vfcmulcph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcph_mask" => {
                if ops.len() == 3 {
                    Self::vfcmulcph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfcmulcph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcph_maskz" => {
                if ops.len() == 3 {
                    Self::vfcmulcph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfcmulcph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcsh" => {
                if ops.len() == 3 {
                    Self::vfcmulcsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcsh_er" => {
                if ops.len() == 3 {
                    Self::vfcmulcsh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcsh_mask" => {
                if ops.len() == 3 {
                    Self::vfcmulcsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcsh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfcmulcsh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcsh_maskz" => {
                if ops.len() == 3 {
                    Self::vfcmulcsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfcmulcsh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfcmulcsh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmpd" => {
                if ops.len() == 4 {
                    Self::vfixupimmpd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmpd_mask" => {
                if ops.len() == 4 {
                    Self::vfixupimmpd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmpd_mask_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmpd_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmpd_maskz" => {
                if ops.len() == 4 {
                    Self::vfixupimmpd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmpd_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmpd_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmpd_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmpd_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmps" => {
                if ops.len() == 4 {
                    Self::vfixupimmps(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmps_mask" => {
                if ops.len() == 4 {
                    Self::vfixupimmps_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmps_mask_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmps_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmps_maskz" => {
                if ops.len() == 4 {
                    Self::vfixupimmps_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmps_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmps_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmps_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmps_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmsd" => {
                if ops.len() == 4 {
                    Self::vfixupimmsd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmsd_mask" => {
                if ops.len() == 4 {
                    Self::vfixupimmsd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmsd_mask_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmsd_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmsd_maskz" => {
                if ops.len() == 4 {
                    Self::vfixupimmsd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmsd_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmsd_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmsd_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmsd_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmss" => {
                if ops.len() == 4 {
                    Self::vfixupimmss(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmss_mask" => {
                if ops.len() == 4 {
                    Self::vfixupimmss_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmss_mask_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmss_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmss_maskz" => {
                if ops.len() == 4 {
                    Self::vfixupimmss_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmss_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmss_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfixupimmss_sae" => {
                if ops.len() == 4 {
                    Self::vfixupimmss_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132pd" => {
                if ops.len() == 3 {
                    Self::vfmadd132pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132pd_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd132pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd132pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ph" => {
                if ops.len() == 3 {
                    Self::vfmadd132ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ph_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd132ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd132ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ps" => {
                if ops.len() == 3 {
                    Self::vfmadd132ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ps_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd132ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd132ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sd" => {
                if ops.len() == 3 {
                    Self::vfmadd132sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sd_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sd_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd132sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd132sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sh" => {
                if ops.len() == 3 {
                    Self::vfmadd132sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sh_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sh_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd132sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd132sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ss" => {
                if ops.len() == 3 {
                    Self::vfmadd132ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ss_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ss_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd132ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd132ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd132ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd132ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213pd" => {
                if ops.len() == 3 {
                    Self::vfmadd213pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213pd_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd213pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd213pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ph" => {
                if ops.len() == 3 {
                    Self::vfmadd213ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ph_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd213ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd213ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ps" => {
                if ops.len() == 3 {
                    Self::vfmadd213ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ps_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd213ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd213ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sd" => {
                if ops.len() == 3 {
                    Self::vfmadd213sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sd_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sd_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd213sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd213sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sh" => {
                if ops.len() == 3 {
                    Self::vfmadd213sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sh_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sh_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd213sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd213sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ss" => {
                if ops.len() == 3 {
                    Self::vfmadd213ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ss_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ss_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd213ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd213ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd213ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd213ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231pd" => {
                if ops.len() == 3 {
                    Self::vfmadd231pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231pd_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd231pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd231pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ph" => {
                if ops.len() == 3 {
                    Self::vfmadd231ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ph_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd231ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd231ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ps" => {
                if ops.len() == 3 {
                    Self::vfmadd231ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ps_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd231ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd231ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sd" => {
                if ops.len() == 3 {
                    Self::vfmadd231sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sd_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sd_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd231sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd231sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sh" => {
                if ops.len() == 3 {
                    Self::vfmadd231sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sh_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sh_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd231sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd231sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ss" => {
                if ops.len() == 3 {
                    Self::vfmadd231ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ss_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ss_mask" => {
                if ops.len() == 3 {
                    Self::vfmadd231ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfmadd231ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmadd231ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmadd231ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcph" => {
                if ops.len() == 3 {
                    Self::vfmaddcph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcph_er" => {
                if ops.len() == 3 {
                    Self::vfmaddcph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcph_mask" => {
                if ops.len() == 3 {
                    Self::vfmaddcph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmaddcph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmaddcph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmaddcph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcsh" => {
                if ops.len() == 3 {
                    Self::vfmaddcsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcsh_er" => {
                if ops.len() == 3 {
                    Self::vfmaddcsh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcsh_mask" => {
                if ops.len() == 3 {
                    Self::vfmaddcsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcsh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmaddcsh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcsh_maskz" => {
                if ops.len() == 3 {
                    Self::vfmaddcsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddcsh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmaddcsh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132pd" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132pd_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ph" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ph_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ps" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ps_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub132ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub132ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213pd" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213pd_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ph" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ph_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ps" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ps_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub213ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub213ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231pd" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231pd_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ph" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ph_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ps" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ps_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmaddsub231ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmaddsub231ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132pd" => {
                if ops.len() == 3 {
                    Self::vfmsub132pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132pd_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub132pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub132pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ph" => {
                if ops.len() == 3 {
                    Self::vfmsub132ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ph_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub132ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub132ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ps" => {
                if ops.len() == 3 {
                    Self::vfmsub132ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ps_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub132ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub132ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sd" => {
                if ops.len() == 3 {
                    Self::vfmsub132sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sd_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sd_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub132sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub132sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sh" => {
                if ops.len() == 3 {
                    Self::vfmsub132sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sh_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sh_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub132sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub132sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ss" => {
                if ops.len() == 3 {
                    Self::vfmsub132ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ss_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ss_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub132ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub132ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub132ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub132ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213pd" => {
                if ops.len() == 3 {
                    Self::vfmsub213pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213pd_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub213pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub213pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ph" => {
                if ops.len() == 3 {
                    Self::vfmsub213ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ph_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub213ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub213ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ps" => {
                if ops.len() == 3 {
                    Self::vfmsub213ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ps_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub213ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub213ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sd" => {
                if ops.len() == 3 {
                    Self::vfmsub213sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sd_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sd_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub213sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub213sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sh" => {
                if ops.len() == 3 {
                    Self::vfmsub213sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sh_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sh_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub213sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub213sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ss" => {
                if ops.len() == 3 {
                    Self::vfmsub213ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ss_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ss_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub213ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub213ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub213ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub213ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231pd" => {
                if ops.len() == 3 {
                    Self::vfmsub231pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231pd_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub231pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub231pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ph" => {
                if ops.len() == 3 {
                    Self::vfmsub231ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ph_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub231ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub231ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ps" => {
                if ops.len() == 3 {
                    Self::vfmsub231ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ps_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub231ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub231ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sd" => {
                if ops.len() == 3 {
                    Self::vfmsub231sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sd_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sd_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub231sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub231sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sh" => {
                if ops.len() == 3 {
                    Self::vfmsub231sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sh_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sh_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub231sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub231sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ss" => {
                if ops.len() == 3 {
                    Self::vfmsub231ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ss_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ss_mask" => {
                if ops.len() == 3 {
                    Self::vfmsub231ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsub231ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsub231ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsub231ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132pd" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132pd_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ph" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ph_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ps" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ps_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd132ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd132ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213pd" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213pd_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ph" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ph_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ps" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ps_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd213ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd213ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231pd" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231pd_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231pd_mask" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ph" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ph_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ph_mask" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ps" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ps_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ps_mask" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmsubadd231ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmsubadd231ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcph" => {
                if ops.len() == 3 {
                    Self::vfmulcph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcph_er" => {
                if ops.len() == 3 {
                    Self::vfmulcph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcph_mask" => {
                if ops.len() == 3 {
                    Self::vfmulcph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmulcph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcph_maskz" => {
                if ops.len() == 3 {
                    Self::vfmulcph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmulcph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcsh" => {
                if ops.len() == 3 {
                    Self::vfmulcsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcsh_er" => {
                if ops.len() == 3 {
                    Self::vfmulcsh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcsh_mask" => {
                if ops.len() == 3 {
                    Self::vfmulcsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcsh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfmulcsh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcsh_maskz" => {
                if ops.len() == 3 {
                    Self::vfmulcsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfmulcsh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfmulcsh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132pd" => {
                if ops.len() == 3 {
                    Self::vfnmadd132pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132pd_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132pd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd132pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd132pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ph" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ph_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ph_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ps" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ps_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ps_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sd" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sd_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sh" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sh_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sh_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ss" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ss_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ss_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd132ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd132ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213pd" => {
                if ops.len() == 3 {
                    Self::vfnmadd213pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213pd_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213pd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd213pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd213pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ph" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ph_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ph_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ps" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ps_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ps_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sd" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sd_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sh" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sh_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sh_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ss" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ss_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ss_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd213ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd213ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231pd" => {
                if ops.len() == 3 {
                    Self::vfnmadd231pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231pd_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231pd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd231pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd231pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ph" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ph_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ph_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ps" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ps_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ps_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sd" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sd_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sh" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sh_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sh_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ss" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ss_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ss_mask" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmadd231ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmadd231ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132pd" => {
                if ops.len() == 3 {
                    Self::vfnmsub132pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132pd_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132pd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub132pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub132pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ph" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ph_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ph_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ps" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ps_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ps_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sd" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sd_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sh" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sh_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sh_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ss" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ss_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ss_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub132ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub132ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213pd" => {
                if ops.len() == 3 {
                    Self::vfnmsub213pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213pd_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213pd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub213pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub213pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ph" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ph_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ph_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ps" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ps_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ps_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sd" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sd_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sh" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sh_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sh_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ss" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ss_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ss_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub213ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub213ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231pd" => {
                if ops.len() == 3 {
                    Self::vfnmsub231pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231pd_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231pd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231pd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub231pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231pd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231pd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231pd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub231pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231pd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231pd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ph" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ph_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ph_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ph_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ph_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ps" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ps_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ps_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ps_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ps_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sd" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sd_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sd_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sd_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sd_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sh" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sh_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sh_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sh_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sh_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231sh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231sh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ss" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ss_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ss_mask" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ss_mask_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ss_maskz" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfnmsub231ss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vfnmsub231ss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclasspd" => {
                if ops.len() == 3 {
                    Self::vfpclasspd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclasspd_mask" => {
                if ops.len() == 3 {
                    Self::vfpclasspd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclassph" => {
                if ops.len() == 3 {
                    Self::vfpclassph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclassph_mask" => {
                if ops.len() == 3 {
                    Self::vfpclassph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclassps" => {
                if ops.len() == 3 {
                    Self::vfpclassps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclassps_mask" => {
                if ops.len() == 3 {
                    Self::vfpclassps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclasssd" => {
                if ops.len() == 3 {
                    Self::vfpclasssd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclasssd_mask" => {
                if ops.len() == 3 {
                    Self::vfpclasssd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclasssh" => {
                if ops.len() == 3 {
                    Self::vfpclasssh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclasssh_mask" => {
                if ops.len() == 3 {
                    Self::vfpclasssh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclassss" => {
                if ops.len() == 3 {
                    Self::vfpclassss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vfpclassss_mask" => {
                if ops.len() == 3 {
                    Self::vfpclassss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgatherdpd" => {
                if ops.len() == 2 {
                    Self::vgatherdpd_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgatherdpd" => {
                if ops.len() == 3 {
                    Self::vgatherdpd_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgatherdps" => {
                if ops.len() == 2 {
                    Self::vgatherdps_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgatherdps" => {
                if ops.len() == 3 {
                    Self::vgatherdps_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgatherqpd" => {
                if ops.len() == 2 {
                    Self::vgatherqpd_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgatherqpd" => {
                if ops.len() == 3 {
                    Self::vgatherqpd_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgatherqps" => {
                if ops.len() == 2 {
                    Self::vgatherqps_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgatherqps" => {
                if ops.len() == 3 {
                    Self::vgatherqps_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexppd" => {
                if ops.len() == 2 {
                    Self::vgetexppd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexppd_mask" => {
                if ops.len() == 2 {
                    Self::vgetexppd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexppd_mask_sae" => {
                if ops.len() == 2 {
                    Self::vgetexppd_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexppd_maskz" => {
                if ops.len() == 2 {
                    Self::vgetexppd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexppd_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vgetexppd_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexppd_sae" => {
                if ops.len() == 2 {
                    Self::vgetexppd_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpph" => {
                if ops.len() == 2 {
                    Self::vgetexpph(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpph_mask" => {
                if ops.len() == 2 {
                    Self::vgetexpph_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpph_mask_sae" => {
                if ops.len() == 2 {
                    Self::vgetexpph_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpph_maskz" => {
                if ops.len() == 2 {
                    Self::vgetexpph_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpph_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vgetexpph_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpph_sae" => {
                if ops.len() == 2 {
                    Self::vgetexpph_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpps" => {
                if ops.len() == 2 {
                    Self::vgetexpps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpps_mask" => {
                if ops.len() == 2 {
                    Self::vgetexpps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpps_mask_sae" => {
                if ops.len() == 2 {
                    Self::vgetexpps_mask_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpps_maskz" => {
                if ops.len() == 2 {
                    Self::vgetexpps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpps_maskz_sae" => {
                if ops.len() == 2 {
                    Self::vgetexpps_maskz_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpps_sae" => {
                if ops.len() == 2 {
                    Self::vgetexpps_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsd" => {
                if ops.len() == 3 {
                    Self::vgetexpsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsd_mask" => {
                if ops.len() == 3 {
                    Self::vgetexpsd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsd_mask_sae" => {
                if ops.len() == 3 {
                    Self::vgetexpsd_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsd_maskz" => {
                if ops.len() == 3 {
                    Self::vgetexpsd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsd_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vgetexpsd_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsd_sae" => {
                if ops.len() == 3 {
                    Self::vgetexpsd_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsh" => {
                if ops.len() == 3 {
                    Self::vgetexpsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsh_mask" => {
                if ops.len() == 3 {
                    Self::vgetexpsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsh_mask_sae" => {
                if ops.len() == 3 {
                    Self::vgetexpsh_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsh_maskz" => {
                if ops.len() == 3 {
                    Self::vgetexpsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsh_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vgetexpsh_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpsh_sae" => {
                if ops.len() == 3 {
                    Self::vgetexpsh_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpss" => {
                if ops.len() == 3 {
                    Self::vgetexpss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpss_mask" => {
                if ops.len() == 3 {
                    Self::vgetexpss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpss_mask_sae" => {
                if ops.len() == 3 {
                    Self::vgetexpss_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpss_maskz" => {
                if ops.len() == 3 {
                    Self::vgetexpss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpss_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vgetexpss_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetexpss_sae" => {
                if ops.len() == 3 {
                    Self::vgetexpss_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantpd" => {
                if ops.len() == 3 {
                    Self::vgetmantpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantpd_mask" => {
                if ops.len() == 3 {
                    Self::vgetmantpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantpd_mask_sae" => {
                if ops.len() == 3 {
                    Self::vgetmantpd_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantpd_maskz" => {
                if ops.len() == 3 {
                    Self::vgetmantpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantpd_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vgetmantpd_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantpd_sae" => {
                if ops.len() == 3 {
                    Self::vgetmantpd_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantph" => {
                if ops.len() == 3 {
                    Self::vgetmantph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantph_mask" => {
                if ops.len() == 3 {
                    Self::vgetmantph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantph_mask_sae" => {
                if ops.len() == 3 {
                    Self::vgetmantph_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantph_maskz" => {
                if ops.len() == 3 {
                    Self::vgetmantph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantph_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vgetmantph_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantph_sae" => {
                if ops.len() == 3 {
                    Self::vgetmantph_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantps" => {
                if ops.len() == 3 {
                    Self::vgetmantps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantps_mask" => {
                if ops.len() == 3 {
                    Self::vgetmantps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantps_mask_sae" => {
                if ops.len() == 3 {
                    Self::vgetmantps_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantps_maskz" => {
                if ops.len() == 3 {
                    Self::vgetmantps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantps_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vgetmantps_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantps_sae" => {
                if ops.len() == 3 {
                    Self::vgetmantps_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsd" => {
                if ops.len() == 4 {
                    Self::vgetmantsd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsd_mask" => {
                if ops.len() == 4 {
                    Self::vgetmantsd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsd_mask_sae" => {
                if ops.len() == 4 {
                    Self::vgetmantsd_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsd_maskz" => {
                if ops.len() == 4 {
                    Self::vgetmantsd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsd_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vgetmantsd_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsd_sae" => {
                if ops.len() == 4 {
                    Self::vgetmantsd_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsh" => {
                if ops.len() == 4 {
                    Self::vgetmantsh(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsh_mask" => {
                if ops.len() == 4 {
                    Self::vgetmantsh_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsh_mask_sae" => {
                if ops.len() == 4 {
                    Self::vgetmantsh_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsh_maskz" => {
                if ops.len() == 4 {
                    Self::vgetmantsh_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsh_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vgetmantsh_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantsh_sae" => {
                if ops.len() == 4 {
                    Self::vgetmantsh_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantss" => {
                if ops.len() == 4 {
                    Self::vgetmantss(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantss_mask" => {
                if ops.len() == 4 {
                    Self::vgetmantss_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantss_mask_sae" => {
                if ops.len() == 4 {
                    Self::vgetmantss_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantss_maskz" => {
                if ops.len() == 4 {
                    Self::vgetmantss_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantss_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vgetmantss_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgetmantss_sae" => {
                if ops.len() == 4 {
                    Self::vgetmantss_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgf2p8affineinvqb" => {
                if ops.len() == 4 {
                    Self::vgf2p8affineinvqb(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgf2p8affineinvqb_mask" => {
                if ops.len() == 4 {
                    Self::vgf2p8affineinvqb_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgf2p8affineinvqb_maskz" => {
                if ops.len() == 4 {
                    Self::vgf2p8affineinvqb_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgf2p8affineqb" => {
                if ops.len() == 4 {
                    Self::vgf2p8affineqb(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgf2p8affineqb_mask" => {
                if ops.len() == 4 {
                    Self::vgf2p8affineqb_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgf2p8affineqb_maskz" => {
                if ops.len() == 4 {
                    Self::vgf2p8affineqb_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgf2p8mulb" => {
                if ops.len() == 3 {
                    Self::vgf2p8mulb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgf2p8mulb_mask" => {
                if ops.len() == 3 {
                    Self::vgf2p8mulb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vgf2p8mulb_maskz" => {
                if ops.len() == 3 {
                    Self::vgf2p8mulb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vhaddpd" => {
                if ops.len() == 3 {
                    Self::vhaddpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vhaddps" => {
                if ops.len() == 3 {
                    Self::vhaddps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vhsubpd" => {
                if ops.len() == 3 {
                    Self::vhsubpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vhsubps" => {
                if ops.len() == 3 {
                    Self::vhsubps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf128" => {
                if ops.len() == 4 {
                    Self::vinsertf128(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf32x4" => {
                if ops.len() == 4 {
                    Self::vinsertf32x4(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf32x4_mask" => {
                if ops.len() == 4 {
                    Self::vinsertf32x4_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf32x4_maskz" => {
                if ops.len() == 4 {
                    Self::vinsertf32x4_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf32x8" => {
                if ops.len() == 4 {
                    Self::vinsertf32x8(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf32x8_mask" => {
                if ops.len() == 4 {
                    Self::vinsertf32x8_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf32x8_maskz" => {
                if ops.len() == 4 {
                    Self::vinsertf32x8_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf64x2" => {
                if ops.len() == 4 {
                    Self::vinsertf64x2(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf64x2_mask" => {
                if ops.len() == 4 {
                    Self::vinsertf64x2_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf64x2_maskz" => {
                if ops.len() == 4 {
                    Self::vinsertf64x2_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf64x4" => {
                if ops.len() == 4 {
                    Self::vinsertf64x4(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf64x4_mask" => {
                if ops.len() == 4 {
                    Self::vinsertf64x4_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertf64x4_maskz" => {
                if ops.len() == 4 {
                    Self::vinsertf64x4_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti128" => {
                if ops.len() == 4 {
                    Self::vinserti128(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti32x4" => {
                if ops.len() == 4 {
                    Self::vinserti32x4(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti32x4_mask" => {
                if ops.len() == 4 {
                    Self::vinserti32x4_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti32x4_maskz" => {
                if ops.len() == 4 {
                    Self::vinserti32x4_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti32x8" => {
                if ops.len() == 4 {
                    Self::vinserti32x8(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti32x8_mask" => {
                if ops.len() == 4 {
                    Self::vinserti32x8_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti32x8_maskz" => {
                if ops.len() == 4 {
                    Self::vinserti32x8_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti64x2" => {
                if ops.len() == 4 {
                    Self::vinserti64x2(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti64x2_mask" => {
                if ops.len() == 4 {
                    Self::vinserti64x2_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti64x2_maskz" => {
                if ops.len() == 4 {
                    Self::vinserti64x2_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti64x4" => {
                if ops.len() == 4 {
                    Self::vinserti64x4(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti64x4_mask" => {
                if ops.len() == 4 {
                    Self::vinserti64x4_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinserti64x4_maskz" => {
                if ops.len() == 4 {
                    Self::vinserti64x4_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vinsertps" => {
                if ops.len() == 4 {
                    Self::vinsertps(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vlddqu" => {
                if ops.len() == 2 {
                    Self::vlddqu(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vldmxcsr" => {
                if ops.len() == 1 {
                    Self::vldmxcsr(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaskmovdqu" => {
                if ops.len() == 2 {
                    Self::vmaskmovdqu(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaskmovpd" => {
                if ops.len() == 3 {
                    Self::vmaskmovpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaskmovps" => {
                if ops.len() == 3 {
                    Self::vmaskmovps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxpd" => {
                if ops.len() == 3 {
                    Self::vmaxpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxpd_mask" => {
                if ops.len() == 3 {
                    Self::vmaxpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxpd_mask_sae" => {
                if ops.len() == 3 {
                    Self::vmaxpd_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxpd_maskz" => {
                if ops.len() == 3 {
                    Self::vmaxpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxpd_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vmaxpd_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxpd_sae" => {
                if ops.len() == 3 {
                    Self::vmaxpd_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxph" => {
                if ops.len() == 3 {
                    Self::vmaxph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxph_mask" => {
                if ops.len() == 3 {
                    Self::vmaxph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxph_mask_sae" => {
                if ops.len() == 3 {
                    Self::vmaxph_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxph_maskz" => {
                if ops.len() == 3 {
                    Self::vmaxph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxph_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vmaxph_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxph_sae" => {
                if ops.len() == 3 {
                    Self::vmaxph_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxps" => {
                if ops.len() == 3 {
                    Self::vmaxps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxps_mask" => {
                if ops.len() == 3 {
                    Self::vmaxps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxps_mask_sae" => {
                if ops.len() == 3 {
                    Self::vmaxps_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxps_maskz" => {
                if ops.len() == 3 {
                    Self::vmaxps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxps_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vmaxps_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxps_sae" => {
                if ops.len() == 3 {
                    Self::vmaxps_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsd" => {
                if ops.len() == 3 {
                    Self::vmaxsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsd_mask" => {
                if ops.len() == 3 {
                    Self::vmaxsd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsd_mask_sae" => {
                if ops.len() == 3 {
                    Self::vmaxsd_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsd_maskz" => {
                if ops.len() == 3 {
                    Self::vmaxsd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsd_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vmaxsd_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsd_sae" => {
                if ops.len() == 3 {
                    Self::vmaxsd_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsh" => {
                if ops.len() == 3 {
                    Self::vmaxsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsh_mask" => {
                if ops.len() == 3 {
                    Self::vmaxsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsh_mask_sae" => {
                if ops.len() == 3 {
                    Self::vmaxsh_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsh_maskz" => {
                if ops.len() == 3 {
                    Self::vmaxsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsh_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vmaxsh_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxsh_sae" => {
                if ops.len() == 3 {
                    Self::vmaxsh_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxss" => {
                if ops.len() == 3 {
                    Self::vmaxss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxss_mask" => {
                if ops.len() == 3 {
                    Self::vmaxss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxss_mask_sae" => {
                if ops.len() == 3 {
                    Self::vmaxss_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxss_maskz" => {
                if ops.len() == 3 {
                    Self::vmaxss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxss_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vmaxss_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmaxss_sae" => {
                if ops.len() == 3 {
                    Self::vmaxss_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmcall" => {
                if ops.is_empty() {
                    Self::vmcall()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmclear" => {
                if ops.len() == 1 {
                    Self::vmclear(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmfunc" => {
                if ops.is_empty() {
                    Self::vmfunc()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmgexit" => {
                if ops.is_empty() {
                    Self::vmgexit()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminpd" => {
                if ops.len() == 3 {
                    Self::vminpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminpd_mask" => {
                if ops.len() == 3 {
                    Self::vminpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminpd_mask_sae" => {
                if ops.len() == 3 {
                    Self::vminpd_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminpd_maskz" => {
                if ops.len() == 3 {
                    Self::vminpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminpd_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vminpd_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminpd_sae" => {
                if ops.len() == 3 {
                    Self::vminpd_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminph" => {
                if ops.len() == 3 {
                    Self::vminph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminph_mask" => {
                if ops.len() == 3 {
                    Self::vminph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminph_mask_sae" => {
                if ops.len() == 3 {
                    Self::vminph_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminph_maskz" => {
                if ops.len() == 3 {
                    Self::vminph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminph_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vminph_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminph_sae" => {
                if ops.len() == 3 {
                    Self::vminph_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminps" => {
                if ops.len() == 3 {
                    Self::vminps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminps_mask" => {
                if ops.len() == 3 {
                    Self::vminps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminps_mask_sae" => {
                if ops.len() == 3 {
                    Self::vminps_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminps_maskz" => {
                if ops.len() == 3 {
                    Self::vminps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminps_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vminps_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminps_sae" => {
                if ops.len() == 3 {
                    Self::vminps_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsd" => {
                if ops.len() == 3 {
                    Self::vminsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsd_mask" => {
                if ops.len() == 3 {
                    Self::vminsd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsd_mask_sae" => {
                if ops.len() == 3 {
                    Self::vminsd_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsd_maskz" => {
                if ops.len() == 3 {
                    Self::vminsd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsd_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vminsd_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsd_sae" => {
                if ops.len() == 3 {
                    Self::vminsd_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsh" => {
                if ops.len() == 3 {
                    Self::vminsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsh_mask" => {
                if ops.len() == 3 {
                    Self::vminsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsh_mask_sae" => {
                if ops.len() == 3 {
                    Self::vminsh_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsh_maskz" => {
                if ops.len() == 3 {
                    Self::vminsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsh_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vminsh_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminsh_sae" => {
                if ops.len() == 3 {
                    Self::vminsh_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminss" => {
                if ops.len() == 3 {
                    Self::vminss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminss_mask" => {
                if ops.len() == 3 {
                    Self::vminss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminss_mask_sae" => {
                if ops.len() == 3 {
                    Self::vminss_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminss_maskz" => {
                if ops.len() == 3 {
                    Self::vminss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminss_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vminss_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vminss_sae" => {
                if ops.len() == 3 {
                    Self::vminss_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmlaunch" => {
                if ops.is_empty() {
                    Self::vmlaunch()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmload" => {
                if ops.is_empty() {
                    Self::vmload()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmmcall" => {
                if ops.is_empty() {
                    Self::vmmcall()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovapd" => {
                if ops.len() == 2 {
                    Self::vmovapd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovapd_mask" => {
                if ops.len() == 2 {
                    Self::vmovapd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovapd_maskz" => {
                if ops.len() == 2 {
                    Self::vmovapd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovaps" => {
                if ops.len() == 2 {
                    Self::vmovaps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovaps_mask" => {
                if ops.len() == 2 {
                    Self::vmovaps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovaps_maskz" => {
                if ops.len() == 2 {
                    Self::vmovaps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovd" => {
                if ops.len() == 2 {
                    Self::vmovd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovddup" => {
                if ops.len() == 2 {
                    Self::vmovddup(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovddup_mask" => {
                if ops.len() == 2 {
                    Self::vmovddup_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovddup_maskz" => {
                if ops.len() == 2 {
                    Self::vmovddup_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqa" => {
                if ops.len() == 2 {
                    Self::vmovdqa(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqa32" => {
                if ops.len() == 2 {
                    Self::vmovdqa32(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqa32_mask" => {
                if ops.len() == 2 {
                    Self::vmovdqa32_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqa32_maskz" => {
                if ops.len() == 2 {
                    Self::vmovdqa32_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqa64" => {
                if ops.len() == 2 {
                    Self::vmovdqa64(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqa64_mask" => {
                if ops.len() == 2 {
                    Self::vmovdqa64_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqa64_maskz" => {
                if ops.len() == 2 {
                    Self::vmovdqa64_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu" => {
                if ops.len() == 2 {
                    Self::vmovdqu(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu16" => {
                if ops.len() == 2 {
                    Self::vmovdqu16(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu16_mask" => {
                if ops.len() == 2 {
                    Self::vmovdqu16_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu16_maskz" => {
                if ops.len() == 2 {
                    Self::vmovdqu16_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu32" => {
                if ops.len() == 2 {
                    Self::vmovdqu32(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu32_mask" => {
                if ops.len() == 2 {
                    Self::vmovdqu32_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu32_maskz" => {
                if ops.len() == 2 {
                    Self::vmovdqu32_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu64" => {
                if ops.len() == 2 {
                    Self::vmovdqu64(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu64_mask" => {
                if ops.len() == 2 {
                    Self::vmovdqu64_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu64_maskz" => {
                if ops.len() == 2 {
                    Self::vmovdqu64_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu8" => {
                if ops.len() == 2 {
                    Self::vmovdqu8(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu8_mask" => {
                if ops.len() == 2 {
                    Self::vmovdqu8_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovdqu8_maskz" => {
                if ops.len() == 2 {
                    Self::vmovdqu8_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovd_g2x" => {
                if ops.len() == 2 {
                    Self::vmovd_g2x(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovd_x2g" => {
                if ops.len() == 2 {
                    Self::vmovd_x2g(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovhlps" => {
                if ops.len() == 3 {
                    Self::vmovhlps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovhpd" => {
                if ops.len() == 2 {
                    Self::vmovhpd_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovhpd" => {
                if ops.len() == 3 {
                    Self::vmovhpd_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovhps" => {
                if ops.len() == 2 {
                    Self::vmovhps_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovhps" => {
                if ops.len() == 3 {
                    Self::vmovhps_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovlhps" => {
                if ops.len() == 3 {
                    Self::vmovlhps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovlpd" => {
                if ops.len() == 2 {
                    Self::vmovlpd_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovlpd" => {
                if ops.len() == 3 {
                    Self::vmovlpd_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovlps" => {
                if ops.len() == 2 {
                    Self::vmovlps_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovlps" => {
                if ops.len() == 3 {
                    Self::vmovlps_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovmskpd" => {
                if ops.len() == 2 {
                    Self::vmovmskpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovmskps" => {
                if ops.len() == 2 {
                    Self::vmovmskps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovntdq" => {
                if ops.len() == 2 {
                    Self::vmovntdq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovntdqa" => {
                if ops.len() == 2 {
                    Self::vmovntdqa(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovntpd" => {
                if ops.len() == 2 {
                    Self::vmovntpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovntps" => {
                if ops.len() == 2 {
                    Self::vmovntps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovq" => {
                if ops.len() == 2 {
                    Self::vmovq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovq_g2x" => {
                if ops.len() == 2 {
                    Self::vmovq_g2x(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovq_x2g" => {
                if ops.len() == 2 {
                    Self::vmovq_x2g(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsd" => {
                if ops.len() == 2 {
                    Self::vmovsd_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsd" => {
                if ops.len() == 3 {
                    Self::vmovsd_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsd_mask" => {
                if ops.len() == 2 {
                    Self::vmovsd_mask_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsd_mask" => {
                if ops.len() == 3 {
                    Self::vmovsd_mask_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsd_maskz" => {
                if ops.len() == 2 {
                    Self::vmovsd_maskz_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsd_maskz" => {
                if ops.len() == 3 {
                    Self::vmovsd_maskz_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsh" => {
                if ops.len() == 2 {
                    Self::vmovsh_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsh" => {
                if ops.len() == 3 {
                    Self::vmovsh_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovshdup" => {
                if ops.len() == 2 {
                    Self::vmovshdup(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovshdup_mask" => {
                if ops.len() == 2 {
                    Self::vmovshdup_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovshdup_maskz" => {
                if ops.len() == 2 {
                    Self::vmovshdup_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsh_mask" => {
                if ops.len() == 2 {
                    Self::vmovsh_mask_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsh_mask" => {
                if ops.len() == 3 {
                    Self::vmovsh_mask_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsh_maskz" => {
                if ops.len() == 2 {
                    Self::vmovsh_maskz_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsh_maskz" => {
                if ops.len() == 3 {
                    Self::vmovsh_maskz_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsldup" => {
                if ops.len() == 2 {
                    Self::vmovsldup(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsldup_mask" => {
                if ops.len() == 2 {
                    Self::vmovsldup_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovsldup_maskz" => {
                if ops.len() == 2 {
                    Self::vmovsldup_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovss" => {
                if ops.len() == 2 {
                    Self::vmovss_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovss" => {
                if ops.len() == 3 {
                    Self::vmovss_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovss_mask" => {
                if ops.len() == 2 {
                    Self::vmovss_mask_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovss_mask" => {
                if ops.len() == 3 {
                    Self::vmovss_mask_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovss_maskz" => {
                if ops.len() == 2 {
                    Self::vmovss_maskz_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovss_maskz" => {
                if ops.len() == 3 {
                    Self::vmovss_maskz_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovupd" => {
                if ops.len() == 2 {
                    Self::vmovupd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovupd_mask" => {
                if ops.len() == 2 {
                    Self::vmovupd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovupd_maskz" => {
                if ops.len() == 2 {
                    Self::vmovupd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovups" => {
                if ops.len() == 2 {
                    Self::vmovups(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovups_mask" => {
                if ops.len() == 2 {
                    Self::vmovups_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovups_maskz" => {
                if ops.len() == 2 {
                    Self::vmovups_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovw_g2x" => {
                if ops.len() == 2 {
                    Self::vmovw_g2x(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmovw_x2g" => {
                if ops.len() == 2 {
                    Self::vmovw_x2g(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmpsadbw" => {
                if ops.len() == 4 {
                    Self::vmpsadbw(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmptrld" => {
                if ops.len() == 1 {
                    Self::vmptrld(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmptrst" => {
                if ops.len() == 1 {
                    Self::vmptrst(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmread" => {
                if ops.len() == 2 {
                    Self::vmread(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmresume" => {
                if ops.is_empty() {
                    Self::vmresume()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmrun" => {
                if ops.is_empty() {
                    Self::vmrun()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmsave" => {
                if ops.is_empty() {
                    Self::vmsave()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulpd" => {
                if ops.len() == 3 {
                    Self::vmulpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulpd_er" => {
                if ops.len() == 3 {
                    Self::vmulpd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulpd_mask" => {
                if ops.len() == 3 {
                    Self::vmulpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulpd_mask_er" => {
                if ops.len() == 3 {
                    Self::vmulpd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulpd_maskz" => {
                if ops.len() == 3 {
                    Self::vmulpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulpd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vmulpd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulph" => {
                if ops.len() == 3 {
                    Self::vmulph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulph_er" => {
                if ops.len() == 3 {
                    Self::vmulph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulph_mask" => {
                if ops.len() == 3 {
                    Self::vmulph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulph_mask_er" => {
                if ops.len() == 3 {
                    Self::vmulph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulph_maskz" => {
                if ops.len() == 3 {
                    Self::vmulph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vmulph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulps" => {
                if ops.len() == 3 {
                    Self::vmulps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulps_er" => {
                if ops.len() == 3 {
                    Self::vmulps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulps_mask" => {
                if ops.len() == 3 {
                    Self::vmulps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulps_mask_er" => {
                if ops.len() == 3 {
                    Self::vmulps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulps_maskz" => {
                if ops.len() == 3 {
                    Self::vmulps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vmulps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsd" => {
                if ops.len() == 3 {
                    Self::vmulsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsd_er" => {
                if ops.len() == 3 {
                    Self::vmulsd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsd_mask" => {
                if ops.len() == 3 {
                    Self::vmulsd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsd_mask_er" => {
                if ops.len() == 3 {
                    Self::vmulsd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsd_maskz" => {
                if ops.len() == 3 {
                    Self::vmulsd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vmulsd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsh" => {
                if ops.len() == 3 {
                    Self::vmulsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsh_er" => {
                if ops.len() == 3 {
                    Self::vmulsh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsh_mask" => {
                if ops.len() == 3 {
                    Self::vmulsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsh_mask_er" => {
                if ops.len() == 3 {
                    Self::vmulsh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsh_maskz" => {
                if ops.len() == 3 {
                    Self::vmulsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulsh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vmulsh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulss" => {
                if ops.len() == 3 {
                    Self::vmulss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulss_er" => {
                if ops.len() == 3 {
                    Self::vmulss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulss_mask" => {
                if ops.len() == 3 {
                    Self::vmulss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulss_mask_er" => {
                if ops.len() == 3 {
                    Self::vmulss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulss_maskz" => {
                if ops.len() == 3 {
                    Self::vmulss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmulss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vmulss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmwrite" => {
                if ops.len() == 2 {
                    Self::vmwrite(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmxoff" => {
                if ops.is_empty() {
                    Self::vmxoff()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vmxon" => {
                if ops.len() == 1 {
                    Self::vmxon(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vorpd" => {
                if ops.len() == 3 {
                    Self::vorpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vorpd_mask" => {
                if ops.len() == 3 {
                    Self::vorpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vorpd_maskz" => {
                if ops.len() == 3 {
                    Self::vorpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vorps" => {
                if ops.len() == 3 {
                    Self::vorps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vorps_mask" => {
                if ops.len() == 3 {
                    Self::vorps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vorps_maskz" => {
                if ops.len() == 3 {
                    Self::vorps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vp2intersectd" => {
                if ops.len() == 3 {
                    Self::vp2intersectd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vp2intersectq" => {
                if ops.len() == 3 {
                    Self::vp2intersectq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsb" => {
                if ops.len() == 2 {
                    Self::vpabsb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsb_mask" => {
                if ops.len() == 2 {
                    Self::vpabsb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsb_maskz" => {
                if ops.len() == 2 {
                    Self::vpabsb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsd" => {
                if ops.len() == 2 {
                    Self::vpabsd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsd_mask" => {
                if ops.len() == 2 {
                    Self::vpabsd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsd_maskz" => {
                if ops.len() == 2 {
                    Self::vpabsd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsq" => {
                if ops.len() == 2 {
                    Self::vpabsq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsq_mask" => {
                if ops.len() == 2 {
                    Self::vpabsq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsq_maskz" => {
                if ops.len() == 2 {
                    Self::vpabsq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsw" => {
                if ops.len() == 2 {
                    Self::vpabsw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsw_mask" => {
                if ops.len() == 2 {
                    Self::vpabsw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpabsw_maskz" => {
                if ops.len() == 2 {
                    Self::vpabsw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpackssdw" => {
                if ops.len() == 3 {
                    Self::vpackssdw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpackssdw_mask" => {
                if ops.len() == 3 {
                    Self::vpackssdw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpackssdw_maskz" => {
                if ops.len() == 3 {
                    Self::vpackssdw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpacksswb" => {
                if ops.len() == 3 {
                    Self::vpacksswb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpacksswb_mask" => {
                if ops.len() == 3 {
                    Self::vpacksswb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpacksswb_maskz" => {
                if ops.len() == 3 {
                    Self::vpacksswb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpackusdw" => {
                if ops.len() == 3 {
                    Self::vpackusdw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpackusdw_mask" => {
                if ops.len() == 3 {
                    Self::vpackusdw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpackusdw_maskz" => {
                if ops.len() == 3 {
                    Self::vpackusdw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpackuswb" => {
                if ops.len() == 3 {
                    Self::vpackuswb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpackuswb_mask" => {
                if ops.len() == 3 {
                    Self::vpackuswb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpackuswb_maskz" => {
                if ops.len() == 3 {
                    Self::vpackuswb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddb" => {
                if ops.len() == 3 {
                    Self::vpaddb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddb_mask" => {
                if ops.len() == 3 {
                    Self::vpaddb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddb_maskz" => {
                if ops.len() == 3 {
                    Self::vpaddb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddd" => {
                if ops.len() == 3 {
                    Self::vpaddd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddd_mask" => {
                if ops.len() == 3 {
                    Self::vpaddd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddd_maskz" => {
                if ops.len() == 3 {
                    Self::vpaddd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddq" => {
                if ops.len() == 3 {
                    Self::vpaddq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddq_mask" => {
                if ops.len() == 3 {
                    Self::vpaddq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddq_maskz" => {
                if ops.len() == 3 {
                    Self::vpaddq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddsb" => {
                if ops.len() == 3 {
                    Self::vpaddsb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddsb_mask" => {
                if ops.len() == 3 {
                    Self::vpaddsb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddsb_maskz" => {
                if ops.len() == 3 {
                    Self::vpaddsb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddsw" => {
                if ops.len() == 3 {
                    Self::vpaddsw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddsw_mask" => {
                if ops.len() == 3 {
                    Self::vpaddsw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddsw_maskz" => {
                if ops.len() == 3 {
                    Self::vpaddsw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddusb" => {
                if ops.len() == 3 {
                    Self::vpaddusb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddusb_mask" => {
                if ops.len() == 3 {
                    Self::vpaddusb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddusb_maskz" => {
                if ops.len() == 3 {
                    Self::vpaddusb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddusw" => {
                if ops.len() == 3 {
                    Self::vpaddusw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddusw_mask" => {
                if ops.len() == 3 {
                    Self::vpaddusw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddusw_maskz" => {
                if ops.len() == 3 {
                    Self::vpaddusw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddw" => {
                if ops.len() == 3 {
                    Self::vpaddw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddw_mask" => {
                if ops.len() == 3 {
                    Self::vpaddw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpaddw_maskz" => {
                if ops.len() == 3 {
                    Self::vpaddw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpalignr" => {
                if ops.len() == 4 {
                    Self::vpalignr(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpalignr_mask" => {
                if ops.len() == 4 {
                    Self::vpalignr_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpalignr_maskz" => {
                if ops.len() == 4 {
                    Self::vpalignr_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpand" => {
                if ops.len() == 3 {
                    Self::vpand(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandd" => {
                if ops.len() == 3 {
                    Self::vpandd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandd_mask" => {
                if ops.len() == 3 {
                    Self::vpandd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandd_maskz" => {
                if ops.len() == 3 {
                    Self::vpandd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandn" => {
                if ops.len() == 3 {
                    Self::vpandn(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandnd" => {
                if ops.len() == 3 {
                    Self::vpandnd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandnd_mask" => {
                if ops.len() == 3 {
                    Self::vpandnd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandnd_maskz" => {
                if ops.len() == 3 {
                    Self::vpandnd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandnq" => {
                if ops.len() == 3 {
                    Self::vpandnq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandnq_mask" => {
                if ops.len() == 3 {
                    Self::vpandnq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandnq_maskz" => {
                if ops.len() == 3 {
                    Self::vpandnq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandq" => {
                if ops.len() == 3 {
                    Self::vpandq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandq_mask" => {
                if ops.len() == 3 {
                    Self::vpandq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpandq_maskz" => {
                if ops.len() == 3 {
                    Self::vpandq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpavgb" => {
                if ops.len() == 3 {
                    Self::vpavgb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpavgb_mask" => {
                if ops.len() == 3 {
                    Self::vpavgb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpavgb_maskz" => {
                if ops.len() == 3 {
                    Self::vpavgb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpavgw" => {
                if ops.len() == 3 {
                    Self::vpavgw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpavgw_mask" => {
                if ops.len() == 3 {
                    Self::vpavgw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpavgw_maskz" => {
                if ops.len() == 3 {
                    Self::vpavgw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendd" => {
                if ops.len() == 4 {
                    Self::vpblendd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmb" => {
                if ops.len() == 3 {
                    Self::vpblendmb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmb_mask" => {
                if ops.len() == 3 {
                    Self::vpblendmb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmb_maskz" => {
                if ops.len() == 3 {
                    Self::vpblendmb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmd" => {
                if ops.len() == 3 {
                    Self::vpblendmd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmd_mask" => {
                if ops.len() == 3 {
                    Self::vpblendmd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmd_maskz" => {
                if ops.len() == 3 {
                    Self::vpblendmd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmq" => {
                if ops.len() == 3 {
                    Self::vpblendmq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmq_mask" => {
                if ops.len() == 3 {
                    Self::vpblendmq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmq_maskz" => {
                if ops.len() == 3 {
                    Self::vpblendmq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmw" => {
                if ops.len() == 3 {
                    Self::vpblendmw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmw_mask" => {
                if ops.len() == 3 {
                    Self::vpblendmw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendmw_maskz" => {
                if ops.len() == 3 {
                    Self::vpblendmw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendvb" => {
                if ops.len() == 4 {
                    Self::vpblendvb(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpblendw" => {
                if ops.len() == 4 {
                    Self::vpblendw(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastb" => {
                if ops.len() == 2 {
                    Self::vpbroadcastb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastb_gp" => {
                if ops.len() == 2 {
                    Self::vpbroadcastb_gp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastb_gp_mask" => {
                if ops.len() == 2 {
                    Self::vpbroadcastb_gp_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastb_gp_maskz" => {
                if ops.len() == 2 {
                    Self::vpbroadcastb_gp_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastb_mask" => {
                if ops.len() == 2 {
                    Self::vpbroadcastb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastb_maskz" => {
                if ops.len() == 2 {
                    Self::vpbroadcastb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastd" => {
                if ops.len() == 2 {
                    Self::vpbroadcastd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastd_gp" => {
                if ops.len() == 2 {
                    Self::vpbroadcastd_gp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastd_gp_mask" => {
                if ops.len() == 2 {
                    Self::vpbroadcastd_gp_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastd_gp_maskz" => {
                if ops.len() == 2 {
                    Self::vpbroadcastd_gp_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastd_mask" => {
                if ops.len() == 2 {
                    Self::vpbroadcastd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastd_maskz" => {
                if ops.len() == 2 {
                    Self::vpbroadcastd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastmb2q" => {
                if ops.len() == 2 {
                    Self::vpbroadcastmb2q(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastmw2d" => {
                if ops.len() == 2 {
                    Self::vpbroadcastmw2d(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastq" => {
                if ops.len() == 2 {
                    Self::vpbroadcastq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastq_gp" => {
                if ops.len() == 2 {
                    Self::vpbroadcastq_gp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastq_gp_mask" => {
                if ops.len() == 2 {
                    Self::vpbroadcastq_gp_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastq_gp_maskz" => {
                if ops.len() == 2 {
                    Self::vpbroadcastq_gp_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastq_mask" => {
                if ops.len() == 2 {
                    Self::vpbroadcastq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastq_maskz" => {
                if ops.len() == 2 {
                    Self::vpbroadcastq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastw" => {
                if ops.len() == 2 {
                    Self::vpbroadcastw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastw_gp" => {
                if ops.len() == 2 {
                    Self::vpbroadcastw_gp(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastw_gp_mask" => {
                if ops.len() == 2 {
                    Self::vpbroadcastw_gp_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastw_gp_maskz" => {
                if ops.len() == 2 {
                    Self::vpbroadcastw_gp_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastw_mask" => {
                if ops.len() == 2 {
                    Self::vpbroadcastw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpbroadcastw_maskz" => {
                if ops.len() == 2 {
                    Self::vpbroadcastw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpclmulqdq" => {
                if ops.len() == 4 {
                    Self::vpclmulqdq(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpb" => {
                if ops.len() == 4 {
                    Self::vpcmpb(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpb_mask" => {
                if ops.len() == 4 {
                    Self::vpcmpb_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpd" => {
                if ops.len() == 4 {
                    Self::vpcmpd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpd_mask" => {
                if ops.len() == 4 {
                    Self::vpcmpd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpeqb" => {
                if ops.len() == 3 {
                    Self::vpcmpeqb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpeqb_mask" => {
                if ops.len() == 3 {
                    Self::vpcmpeqb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpeqd" => {
                if ops.len() == 3 {
                    Self::vpcmpeqd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpeqd_mask" => {
                if ops.len() == 3 {
                    Self::vpcmpeqd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpeqq" => {
                if ops.len() == 3 {
                    Self::vpcmpeqq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpeqq_mask" => {
                if ops.len() == 3 {
                    Self::vpcmpeqq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpeqw" => {
                if ops.len() == 3 {
                    Self::vpcmpeqw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpeqw_mask" => {
                if ops.len() == 3 {
                    Self::vpcmpeqw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpestri" => {
                if ops.len() == 3 {
                    Self::vpcmpestri(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpestrm" => {
                if ops.len() == 3 {
                    Self::vpcmpestrm(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpgtb" => {
                if ops.len() == 3 {
                    Self::vpcmpgtb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpgtb_mask" => {
                if ops.len() == 3 {
                    Self::vpcmpgtb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpgtd" => {
                if ops.len() == 3 {
                    Self::vpcmpgtd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpgtd_mask" => {
                if ops.len() == 3 {
                    Self::vpcmpgtd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpgtq" => {
                if ops.len() == 3 {
                    Self::vpcmpgtq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpgtq_mask" => {
                if ops.len() == 3 {
                    Self::vpcmpgtq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpgtw" => {
                if ops.len() == 3 {
                    Self::vpcmpgtw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpgtw_mask" => {
                if ops.len() == 3 {
                    Self::vpcmpgtw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpistri" => {
                if ops.len() == 3 {
                    Self::vpcmpistri(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpistrm" => {
                if ops.len() == 3 {
                    Self::vpcmpistrm(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpq" => {
                if ops.len() == 4 {
                    Self::vpcmpq(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpq_mask" => {
                if ops.len() == 4 {
                    Self::vpcmpq_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpub" => {
                if ops.len() == 4 {
                    Self::vpcmpub(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpub_mask" => {
                if ops.len() == 4 {
                    Self::vpcmpub_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpud" => {
                if ops.len() == 4 {
                    Self::vpcmpud(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpud_mask" => {
                if ops.len() == 4 {
                    Self::vpcmpud_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpuq" => {
                if ops.len() == 4 {
                    Self::vpcmpuq(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpuq_mask" => {
                if ops.len() == 4 {
                    Self::vpcmpuq_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpuw" => {
                if ops.len() == 4 {
                    Self::vpcmpuw(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpuw_mask" => {
                if ops.len() == 4 {
                    Self::vpcmpuw_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpw" => {
                if ops.len() == 4 {
                    Self::vpcmpw(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcmpw_mask" => {
                if ops.len() == 4 {
                    Self::vpcmpw_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressb" => {
                if ops.len() == 2 {
                    Self::vpcompressb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressb_mask" => {
                if ops.len() == 2 {
                    Self::vpcompressb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressb_maskz" => {
                if ops.len() == 2 {
                    Self::vpcompressb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressd" => {
                if ops.len() == 2 {
                    Self::vpcompressd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressd_mask" => {
                if ops.len() == 2 {
                    Self::vpcompressd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressd_maskz" => {
                if ops.len() == 2 {
                    Self::vpcompressd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressq" => {
                if ops.len() == 2 {
                    Self::vpcompressq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressq_mask" => {
                if ops.len() == 2 {
                    Self::vpcompressq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressq_maskz" => {
                if ops.len() == 2 {
                    Self::vpcompressq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressw" => {
                if ops.len() == 2 {
                    Self::vpcompressw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressw_mask" => {
                if ops.len() == 2 {
                    Self::vpcompressw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpcompressw_maskz" => {
                if ops.len() == 2 {
                    Self::vpcompressw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpconflictd" => {
                if ops.len() == 2 {
                    Self::vpconflictd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpconflictd_mask" => {
                if ops.len() == 2 {
                    Self::vpconflictd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpconflictd_maskz" => {
                if ops.len() == 2 {
                    Self::vpconflictd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpconflictq" => {
                if ops.len() == 2 {
                    Self::vpconflictq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpconflictq_mask" => {
                if ops.len() == 2 {
                    Self::vpconflictq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpconflictq_maskz" => {
                if ops.len() == 2 {
                    Self::vpconflictq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbssd" => {
                if ops.len() == 3 {
                    Self::vpdpbssd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbssds" => {
                if ops.len() == 3 {
                    Self::vpdpbssds(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbsud" => {
                if ops.len() == 3 {
                    Self::vpdpbsud(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbsuds" => {
                if ops.len() == 3 {
                    Self::vpdpbsuds(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbusd" => {
                if ops.len() == 3 {
                    Self::vpdpbusd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbusds" => {
                if ops.len() == 3 {
                    Self::vpdpbusds(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbusds_mask" => {
                if ops.len() == 3 {
                    Self::vpdpbusds_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbusds_maskz" => {
                if ops.len() == 3 {
                    Self::vpdpbusds_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbusd_mask" => {
                if ops.len() == 3 {
                    Self::vpdpbusd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbusd_maskz" => {
                if ops.len() == 3 {
                    Self::vpdpbusd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbuud" => {
                if ops.len() == 3 {
                    Self::vpdpbuud(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpbuuds" => {
                if ops.len() == 3 {
                    Self::vpdpbuuds(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpwssd" => {
                if ops.len() == 3 {
                    Self::vpdpwssd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpwssds" => {
                if ops.len() == 3 {
                    Self::vpdpwssds(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpwssds_mask" => {
                if ops.len() == 3 {
                    Self::vpdpwssds_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpwssds_maskz" => {
                if ops.len() == 3 {
                    Self::vpdpwssds_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpwssd_mask" => {
                if ops.len() == 3 {
                    Self::vpdpwssd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpdpwssd_maskz" => {
                if ops.len() == 3 {
                    Self::vpdpwssd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vperm2f128" => {
                if ops.len() == 4 {
                    Self::vperm2f128(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vperm2i128" => {
                if ops.len() == 4 {
                    Self::vperm2i128(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermb" => {
                if ops.len() == 3 {
                    Self::vpermb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermb_mask" => {
                if ops.len() == 3 {
                    Self::vpermb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermb_maskz" => {
                if ops.len() == 3 {
                    Self::vpermb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermd" => {
                if ops.len() == 3 {
                    Self::vpermd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermd_mask" => {
                if ops.len() == 3 {
                    Self::vpermd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermd_maskz" => {
                if ops.len() == 3 {
                    Self::vpermd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2b" => {
                if ops.len() == 3 {
                    Self::vpermi2b(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2b_mask" => {
                if ops.len() == 3 {
                    Self::vpermi2b_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2b_maskz" => {
                if ops.len() == 3 {
                    Self::vpermi2b_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2d" => {
                if ops.len() == 3 {
                    Self::vpermi2d(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2d_mask" => {
                if ops.len() == 3 {
                    Self::vpermi2d_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2d_maskz" => {
                if ops.len() == 3 {
                    Self::vpermi2d_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2pd" => {
                if ops.len() == 3 {
                    Self::vpermi2pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2pd_mask" => {
                if ops.len() == 3 {
                    Self::vpermi2pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2pd_maskz" => {
                if ops.len() == 3 {
                    Self::vpermi2pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2ps" => {
                if ops.len() == 3 {
                    Self::vpermi2ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2ps_mask" => {
                if ops.len() == 3 {
                    Self::vpermi2ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2ps_maskz" => {
                if ops.len() == 3 {
                    Self::vpermi2ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2q" => {
                if ops.len() == 3 {
                    Self::vpermi2q(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2q_mask" => {
                if ops.len() == 3 {
                    Self::vpermi2q_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2q_maskz" => {
                if ops.len() == 3 {
                    Self::vpermi2q_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2w" => {
                if ops.len() == 3 {
                    Self::vpermi2w(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2w_mask" => {
                if ops.len() == 3 {
                    Self::vpermi2w_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermi2w_maskz" => {
                if ops.len() == 3 {
                    Self::vpermi2w_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermilpd" => {
                if ops.len() == 3 {
                    Self::vpermilpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermilpd_mask" => {
                if ops.len() == 3 {
                    Self::vpermilpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermilpd_maskz" => {
                if ops.len() == 3 {
                    Self::vpermilpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermilps" => {
                if ops.len() == 3 {
                    Self::vpermilps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermilps_mask" => {
                if ops.len() == 3 {
                    Self::vpermilps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermilps_maskz" => {
                if ops.len() == 3 {
                    Self::vpermilps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermpd" => {
                if ops.len() == 3 {
                    Self::vpermpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermpd_mask" => {
                if ops.len() == 3 {
                    Self::vpermpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermpd_maskz" => {
                if ops.len() == 3 {
                    Self::vpermpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermps" => {
                if ops.len() == 3 {
                    Self::vpermps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermps_mask" => {
                if ops.len() == 3 {
                    Self::vpermps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermps_maskz" => {
                if ops.len() == 3 {
                    Self::vpermps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermq" => {
                if ops.len() == 3 {
                    Self::vpermq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermq_mask" => {
                if ops.len() == 3 {
                    Self::vpermq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermq_maskz" => {
                if ops.len() == 3 {
                    Self::vpermq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2b" => {
                if ops.len() == 3 {
                    Self::vpermt2b(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2b_mask" => {
                if ops.len() == 3 {
                    Self::vpermt2b_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2b_maskz" => {
                if ops.len() == 3 {
                    Self::vpermt2b_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2d" => {
                if ops.len() == 3 {
                    Self::vpermt2d(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2d_mask" => {
                if ops.len() == 3 {
                    Self::vpermt2d_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2d_maskz" => {
                if ops.len() == 3 {
                    Self::vpermt2d_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2pd" => {
                if ops.len() == 3 {
                    Self::vpermt2pd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2pd_mask" => {
                if ops.len() == 3 {
                    Self::vpermt2pd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2pd_maskz" => {
                if ops.len() == 3 {
                    Self::vpermt2pd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2ps" => {
                if ops.len() == 3 {
                    Self::vpermt2ps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2ps_mask" => {
                if ops.len() == 3 {
                    Self::vpermt2ps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2ps_maskz" => {
                if ops.len() == 3 {
                    Self::vpermt2ps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2q" => {
                if ops.len() == 3 {
                    Self::vpermt2q(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2q_mask" => {
                if ops.len() == 3 {
                    Self::vpermt2q_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2q_maskz" => {
                if ops.len() == 3 {
                    Self::vpermt2q_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2w" => {
                if ops.len() == 3 {
                    Self::vpermt2w(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2w_mask" => {
                if ops.len() == 3 {
                    Self::vpermt2w_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermt2w_maskz" => {
                if ops.len() == 3 {
                    Self::vpermt2w_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermw" => {
                if ops.len() == 3 {
                    Self::vpermw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermw_mask" => {
                if ops.len() == 3 {
                    Self::vpermw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpermw_maskz" => {
                if ops.len() == 3 {
                    Self::vpermw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandb" => {
                if ops.len() == 2 {
                    Self::vpexpandb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandb_mask" => {
                if ops.len() == 2 {
                    Self::vpexpandb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandb_maskz" => {
                if ops.len() == 2 {
                    Self::vpexpandb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandd" => {
                if ops.len() == 2 {
                    Self::vpexpandd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandd_mask" => {
                if ops.len() == 2 {
                    Self::vpexpandd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandd_maskz" => {
                if ops.len() == 2 {
                    Self::vpexpandd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandq" => {
                if ops.len() == 2 {
                    Self::vpexpandq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandq_mask" => {
                if ops.len() == 2 {
                    Self::vpexpandq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandq_maskz" => {
                if ops.len() == 2 {
                    Self::vpexpandq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandw" => {
                if ops.len() == 2 {
                    Self::vpexpandw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandw_mask" => {
                if ops.len() == 2 {
                    Self::vpexpandw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpexpandw_maskz" => {
                if ops.len() == 2 {
                    Self::vpexpandw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpextrb" => {
                if ops.len() == 3 {
                    Self::vpextrb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpextrd" => {
                if ops.len() == 3 {
                    Self::vpextrd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpextrq" => {
                if ops.len() == 3 {
                    Self::vpextrq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpextrw" => {
                if ops.len() == 3 {
                    Self::vpextrw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpgatherdd" => {
                if ops.len() == 2 {
                    Self::vpgatherdd_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpgatherdd" => {
                if ops.len() == 3 {
                    Self::vpgatherdd_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpgatherdq" => {
                if ops.len() == 2 {
                    Self::vpgatherdq_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpgatherdq" => {
                if ops.len() == 3 {
                    Self::vpgatherdq_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpgatherqd" => {
                if ops.len() == 2 {
                    Self::vpgatherqd_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpgatherqd" => {
                if ops.len() == 3 {
                    Self::vpgatherqd_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpgatherqq" => {
                if ops.len() == 2 {
                    Self::vpgatherqq_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpgatherqq" => {
                if ops.len() == 3 {
                    Self::vpgatherqq_3(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vphaddd" => {
                if ops.len() == 3 {
                    Self::vphaddd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vphaddsw" => {
                if ops.len() == 3 {
                    Self::vphaddsw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vphaddw" => {
                if ops.len() == 3 {
                    Self::vphaddw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vphminposuw" => {
                if ops.len() == 2 {
                    Self::vphminposuw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vphsubd" => {
                if ops.len() == 3 {
                    Self::vphsubd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vphsubsw" => {
                if ops.len() == 3 {
                    Self::vphsubsw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vphsubw" => {
                if ops.len() == 3 {
                    Self::vphsubw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpinsrb" => {
                if ops.len() == 4 {
                    Self::vpinsrb(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpinsrd" => {
                if ops.len() == 4 {
                    Self::vpinsrd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpinsrq" => {
                if ops.len() == 4 {
                    Self::vpinsrq(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpinsrw" => {
                if ops.len() == 4 {
                    Self::vpinsrw(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vplzcntd" => {
                if ops.len() == 2 {
                    Self::vplzcntd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vplzcntd_mask" => {
                if ops.len() == 2 {
                    Self::vplzcntd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vplzcntd_maskz" => {
                if ops.len() == 2 {
                    Self::vplzcntd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vplzcntq" => {
                if ops.len() == 2 {
                    Self::vplzcntq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vplzcntq_mask" => {
                if ops.len() == 2 {
                    Self::vplzcntq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vplzcntq_maskz" => {
                if ops.len() == 2 {
                    Self::vplzcntq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmadd52huq" => {
                if ops.len() == 3 {
                    Self::vpmadd52huq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmadd52huq_mask" => {
                if ops.len() == 3 {
                    Self::vpmadd52huq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmadd52huq_maskz" => {
                if ops.len() == 3 {
                    Self::vpmadd52huq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmadd52luq" => {
                if ops.len() == 3 {
                    Self::vpmadd52luq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmadd52luq_mask" => {
                if ops.len() == 3 {
                    Self::vpmadd52luq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmadd52luq_maskz" => {
                if ops.len() == 3 {
                    Self::vpmadd52luq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaddubsw" => {
                if ops.len() == 3 {
                    Self::vpmaddubsw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaddubsw_mask" => {
                if ops.len() == 3 {
                    Self::vpmaddubsw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaddubsw_maskz" => {
                if ops.len() == 3 {
                    Self::vpmaddubsw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaddwd" => {
                if ops.len() == 3 {
                    Self::vpmaddwd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaddwd_mask" => {
                if ops.len() == 3 {
                    Self::vpmaddwd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaddwd_maskz" => {
                if ops.len() == 3 {
                    Self::vpmaddwd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaskmovd" => {
                if ops.len() == 3 {
                    Self::vpmaskmovd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaskmovq" => {
                if ops.len() == 3 {
                    Self::vpmaskmovq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsb" => {
                if ops.len() == 3 {
                    Self::vpmaxsb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsb_mask" => {
                if ops.len() == 3 {
                    Self::vpmaxsb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsb_maskz" => {
                if ops.len() == 3 {
                    Self::vpmaxsb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsd" => {
                if ops.len() == 3 {
                    Self::vpmaxsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsd_mask" => {
                if ops.len() == 3 {
                    Self::vpmaxsd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsd_maskz" => {
                if ops.len() == 3 {
                    Self::vpmaxsd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsq" => {
                if ops.len() == 3 {
                    Self::vpmaxsq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsq_mask" => {
                if ops.len() == 3 {
                    Self::vpmaxsq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsq_maskz" => {
                if ops.len() == 3 {
                    Self::vpmaxsq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsw" => {
                if ops.len() == 3 {
                    Self::vpmaxsw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsw_mask" => {
                if ops.len() == 3 {
                    Self::vpmaxsw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxsw_maskz" => {
                if ops.len() == 3 {
                    Self::vpmaxsw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxub" => {
                if ops.len() == 3 {
                    Self::vpmaxub(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxub_mask" => {
                if ops.len() == 3 {
                    Self::vpmaxub_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxub_maskz" => {
                if ops.len() == 3 {
                    Self::vpmaxub_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxud" => {
                if ops.len() == 3 {
                    Self::vpmaxud(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxud_mask" => {
                if ops.len() == 3 {
                    Self::vpmaxud_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxud_maskz" => {
                if ops.len() == 3 {
                    Self::vpmaxud_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxuq" => {
                if ops.len() == 3 {
                    Self::vpmaxuq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxuq_mask" => {
                if ops.len() == 3 {
                    Self::vpmaxuq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxuq_maskz" => {
                if ops.len() == 3 {
                    Self::vpmaxuq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxuw" => {
                if ops.len() == 3 {
                    Self::vpmaxuw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxuw_mask" => {
                if ops.len() == 3 {
                    Self::vpmaxuw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmaxuw_maskz" => {
                if ops.len() == 3 {
                    Self::vpmaxuw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsb" => {
                if ops.len() == 3 {
                    Self::vpminsb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsb_mask" => {
                if ops.len() == 3 {
                    Self::vpminsb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsb_maskz" => {
                if ops.len() == 3 {
                    Self::vpminsb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsd" => {
                if ops.len() == 3 {
                    Self::vpminsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsd_mask" => {
                if ops.len() == 3 {
                    Self::vpminsd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsd_maskz" => {
                if ops.len() == 3 {
                    Self::vpminsd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsq" => {
                if ops.len() == 3 {
                    Self::vpminsq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsq_mask" => {
                if ops.len() == 3 {
                    Self::vpminsq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsq_maskz" => {
                if ops.len() == 3 {
                    Self::vpminsq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsw" => {
                if ops.len() == 3 {
                    Self::vpminsw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsw_mask" => {
                if ops.len() == 3 {
                    Self::vpminsw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminsw_maskz" => {
                if ops.len() == 3 {
                    Self::vpminsw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminub" => {
                if ops.len() == 3 {
                    Self::vpminub(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminub_mask" => {
                if ops.len() == 3 {
                    Self::vpminub_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminub_maskz" => {
                if ops.len() == 3 {
                    Self::vpminub_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminud" => {
                if ops.len() == 3 {
                    Self::vpminud(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminud_mask" => {
                if ops.len() == 3 {
                    Self::vpminud_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminud_maskz" => {
                if ops.len() == 3 {
                    Self::vpminud_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminuq" => {
                if ops.len() == 3 {
                    Self::vpminuq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminuq_mask" => {
                if ops.len() == 3 {
                    Self::vpminuq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminuq_maskz" => {
                if ops.len() == 3 {
                    Self::vpminuq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminuw" => {
                if ops.len() == 3 {
                    Self::vpminuw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminuw_mask" => {
                if ops.len() == 3 {
                    Self::vpminuw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpminuw_maskz" => {
                if ops.len() == 3 {
                    Self::vpminuw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovb2m" => {
                if ops.len() == 2 {
                    Self::vpmovb2m(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovd2m" => {
                if ops.len() == 2 {
                    Self::vpmovd2m(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovdb" => {
                if ops.len() == 2 {
                    Self::vpmovdb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovdb_mask" => {
                if ops.len() == 2 {
                    Self::vpmovdb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovdb_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovdb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovdw" => {
                if ops.len() == 2 {
                    Self::vpmovdw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovdw_mask" => {
                if ops.len() == 2 {
                    Self::vpmovdw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovdw_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovdw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovm2b" => {
                if ops.len() == 2 {
                    Self::vpmovm2b(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovm2d" => {
                if ops.len() == 2 {
                    Self::vpmovm2d(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovm2q" => {
                if ops.len() == 2 {
                    Self::vpmovm2q(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovm2w" => {
                if ops.len() == 2 {
                    Self::vpmovm2w(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovmskb" => {
                if ops.len() == 2 {
                    Self::vpmovmskb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovq2m" => {
                if ops.len() == 2 {
                    Self::vpmovq2m(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovqb" => {
                if ops.len() == 2 {
                    Self::vpmovqb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovqb_mask" => {
                if ops.len() == 2 {
                    Self::vpmovqb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovqb_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovqb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovqd" => {
                if ops.len() == 2 {
                    Self::vpmovqd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovqd_mask" => {
                if ops.len() == 2 {
                    Self::vpmovqd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovqd_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovqd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovqw" => {
                if ops.len() == 2 {
                    Self::vpmovqw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovqw_mask" => {
                if ops.len() == 2 {
                    Self::vpmovqw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovqw_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovqw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsdb" => {
                if ops.len() == 2 {
                    Self::vpmovsdb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsdb_mask" => {
                if ops.len() == 2 {
                    Self::vpmovsdb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsdb_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovsdb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsdw" => {
                if ops.len() == 2 {
                    Self::vpmovsdw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsdw_mask" => {
                if ops.len() == 2 {
                    Self::vpmovsdw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsdw_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovsdw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsqb" => {
                if ops.len() == 2 {
                    Self::vpmovsqb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsqb_mask" => {
                if ops.len() == 2 {
                    Self::vpmovsqb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsqb_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovsqb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsqd" => {
                if ops.len() == 2 {
                    Self::vpmovsqd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsqd_mask" => {
                if ops.len() == 2 {
                    Self::vpmovsqd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsqd_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovsqd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsqw" => {
                if ops.len() == 2 {
                    Self::vpmovsqw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsqw_mask" => {
                if ops.len() == 2 {
                    Self::vpmovsqw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsqw_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovsqw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovswb" => {
                if ops.len() == 2 {
                    Self::vpmovswb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovswb_mask" => {
                if ops.len() == 2 {
                    Self::vpmovswb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovswb_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovswb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxbd" => {
                if ops.len() == 2 {
                    Self::vpmovsxbd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxbd_mask" => {
                if ops.len() == 2 {
                    Self::vpmovsxbd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxbd_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovsxbd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxbq" => {
                if ops.len() == 2 {
                    Self::vpmovsxbq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxbq_mask" => {
                if ops.len() == 2 {
                    Self::vpmovsxbq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxbq_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovsxbq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxbw" => {
                if ops.len() == 2 {
                    Self::vpmovsxbw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxbw_mask" => {
                if ops.len() == 2 {
                    Self::vpmovsxbw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxbw_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovsxbw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxdq" => {
                if ops.len() == 2 {
                    Self::vpmovsxdq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxdq_mask" => {
                if ops.len() == 2 {
                    Self::vpmovsxdq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxdq_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovsxdq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxwd" => {
                if ops.len() == 2 {
                    Self::vpmovsxwd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxwd_mask" => {
                if ops.len() == 2 {
                    Self::vpmovsxwd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxwd_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovsxwd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxwq" => {
                if ops.len() == 2 {
                    Self::vpmovsxwq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxwq_mask" => {
                if ops.len() == 2 {
                    Self::vpmovsxwq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovsxwq_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovsxwq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusdb" => {
                if ops.len() == 2 {
                    Self::vpmovusdb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusdb_mask" => {
                if ops.len() == 2 {
                    Self::vpmovusdb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusdb_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovusdb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusdw" => {
                if ops.len() == 2 {
                    Self::vpmovusdw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusdw_mask" => {
                if ops.len() == 2 {
                    Self::vpmovusdw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusdw_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovusdw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusqb" => {
                if ops.len() == 2 {
                    Self::vpmovusqb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusqb_mask" => {
                if ops.len() == 2 {
                    Self::vpmovusqb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusqb_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovusqb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusqd" => {
                if ops.len() == 2 {
                    Self::vpmovusqd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusqd_mask" => {
                if ops.len() == 2 {
                    Self::vpmovusqd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusqd_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovusqd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusqw" => {
                if ops.len() == 2 {
                    Self::vpmovusqw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusqw_mask" => {
                if ops.len() == 2 {
                    Self::vpmovusqw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovusqw_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovusqw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovuswb" => {
                if ops.len() == 2 {
                    Self::vpmovuswb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovuswb_mask" => {
                if ops.len() == 2 {
                    Self::vpmovuswb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovuswb_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovuswb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovw2m" => {
                if ops.len() == 2 {
                    Self::vpmovw2m(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovwb" => {
                if ops.len() == 2 {
                    Self::vpmovwb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovwb_mask" => {
                if ops.len() == 2 {
                    Self::vpmovwb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovwb_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovwb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxbd" => {
                if ops.len() == 2 {
                    Self::vpmovzxbd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxbd_mask" => {
                if ops.len() == 2 {
                    Self::vpmovzxbd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxbd_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovzxbd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxbq" => {
                if ops.len() == 2 {
                    Self::vpmovzxbq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxbq_mask" => {
                if ops.len() == 2 {
                    Self::vpmovzxbq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxbq_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovzxbq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxbw" => {
                if ops.len() == 2 {
                    Self::vpmovzxbw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxbw_mask" => {
                if ops.len() == 2 {
                    Self::vpmovzxbw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxbw_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovzxbw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxdq" => {
                if ops.len() == 2 {
                    Self::vpmovzxdq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxdq_mask" => {
                if ops.len() == 2 {
                    Self::vpmovzxdq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxdq_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovzxdq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxwd" => {
                if ops.len() == 2 {
                    Self::vpmovzxwd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxwd_mask" => {
                if ops.len() == 2 {
                    Self::vpmovzxwd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxwd_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovzxwd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxwq" => {
                if ops.len() == 2 {
                    Self::vpmovzxwq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxwq_mask" => {
                if ops.len() == 2 {
                    Self::vpmovzxwq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmovzxwq_maskz" => {
                if ops.len() == 2 {
                    Self::vpmovzxwq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmuldq" => {
                if ops.len() == 3 {
                    Self::vpmuldq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmuldq_mask" => {
                if ops.len() == 3 {
                    Self::vpmuldq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmuldq_maskz" => {
                if ops.len() == 3 {
                    Self::vpmuldq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulhrsw" => {
                if ops.len() == 3 {
                    Self::vpmulhrsw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulhrsw_mask" => {
                if ops.len() == 3 {
                    Self::vpmulhrsw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulhrsw_maskz" => {
                if ops.len() == 3 {
                    Self::vpmulhrsw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulhuw" => {
                if ops.len() == 3 {
                    Self::vpmulhuw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulhuw_mask" => {
                if ops.len() == 3 {
                    Self::vpmulhuw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulhuw_maskz" => {
                if ops.len() == 3 {
                    Self::vpmulhuw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulhw" => {
                if ops.len() == 3 {
                    Self::vpmulhw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulhw_mask" => {
                if ops.len() == 3 {
                    Self::vpmulhw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulhw_maskz" => {
                if ops.len() == 3 {
                    Self::vpmulhw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulld" => {
                if ops.len() == 3 {
                    Self::vpmulld(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulld_mask" => {
                if ops.len() == 3 {
                    Self::vpmulld_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmulld_maskz" => {
                if ops.len() == 3 {
                    Self::vpmulld_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmullq" => {
                if ops.len() == 3 {
                    Self::vpmullq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmullq_mask" => {
                if ops.len() == 3 {
                    Self::vpmullq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmullq_maskz" => {
                if ops.len() == 3 {
                    Self::vpmullq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmullw" => {
                if ops.len() == 3 {
                    Self::vpmullw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmullw_mask" => {
                if ops.len() == 3 {
                    Self::vpmullw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmullw_maskz" => {
                if ops.len() == 3 {
                    Self::vpmullw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmultishiftqb" => {
                if ops.len() == 3 {
                    Self::vpmultishiftqb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmultishiftqb_mask" => {
                if ops.len() == 3 {
                    Self::vpmultishiftqb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmultishiftqb_maskz" => {
                if ops.len() == 3 {
                    Self::vpmultishiftqb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmuludq" => {
                if ops.len() == 3 {
                    Self::vpmuludq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmuludq_mask" => {
                if ops.len() == 3 {
                    Self::vpmuludq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpmuludq_maskz" => {
                if ops.len() == 3 {
                    Self::vpmuludq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntb" => {
                if ops.len() == 2 {
                    Self::vpopcntb(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntb_mask" => {
                if ops.len() == 2 {
                    Self::vpopcntb_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntb_maskz" => {
                if ops.len() == 2 {
                    Self::vpopcntb_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntd" => {
                if ops.len() == 2 {
                    Self::vpopcntd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntd_mask" => {
                if ops.len() == 2 {
                    Self::vpopcntd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntd_maskz" => {
                if ops.len() == 2 {
                    Self::vpopcntd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntq" => {
                if ops.len() == 2 {
                    Self::vpopcntq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntq_mask" => {
                if ops.len() == 2 {
                    Self::vpopcntq_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntq_maskz" => {
                if ops.len() == 2 {
                    Self::vpopcntq_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntw" => {
                if ops.len() == 2 {
                    Self::vpopcntw(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntw_mask" => {
                if ops.len() == 2 {
                    Self::vpopcntw_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpopcntw_maskz" => {
                if ops.len() == 2 {
                    Self::vpopcntw_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpor" => {
                if ops.len() == 3 {
                    Self::vpor(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpord" => {
                if ops.len() == 3 {
                    Self::vpord(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpord_mask" => {
                if ops.len() == 3 {
                    Self::vpord_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpord_maskz" => {
                if ops.len() == 3 {
                    Self::vpord_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vporq" => {
                if ops.len() == 3 {
                    Self::vporq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vporq_mask" => {
                if ops.len() == 3 {
                    Self::vporq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vporq_maskz" => {
                if ops.len() == 3 {
                    Self::vporq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprold" => {
                if ops.len() == 3 {
                    Self::vprold(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprold_mask" => {
                if ops.len() == 3 {
                    Self::vprold_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprold_maskz" => {
                if ops.len() == 3 {
                    Self::vprold_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprolq" => {
                if ops.len() == 3 {
                    Self::vprolq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprolq_mask" => {
                if ops.len() == 3 {
                    Self::vprolq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprolq_maskz" => {
                if ops.len() == 3 {
                    Self::vprolq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprolvd" => {
                if ops.len() == 3 {
                    Self::vprolvd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprolvd_mask" => {
                if ops.len() == 3 {
                    Self::vprolvd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprolvd_maskz" => {
                if ops.len() == 3 {
                    Self::vprolvd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprolvq" => {
                if ops.len() == 3 {
                    Self::vprolvq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprolvq_mask" => {
                if ops.len() == 3 {
                    Self::vprolvq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprolvq_maskz" => {
                if ops.len() == 3 {
                    Self::vprolvq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprord" => {
                if ops.len() == 3 {
                    Self::vprord(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprord_mask" => {
                if ops.len() == 3 {
                    Self::vprord_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprord_maskz" => {
                if ops.len() == 3 {
                    Self::vprord_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprorq" => {
                if ops.len() == 3 {
                    Self::vprorq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprorq_mask" => {
                if ops.len() == 3 {
                    Self::vprorq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprorq_maskz" => {
                if ops.len() == 3 {
                    Self::vprorq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprorvd" => {
                if ops.len() == 3 {
                    Self::vprorvd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprorvd_mask" => {
                if ops.len() == 3 {
                    Self::vprorvd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprorvd_maskz" => {
                if ops.len() == 3 {
                    Self::vprorvd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprorvq" => {
                if ops.len() == 3 {
                    Self::vprorvq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprorvq_mask" => {
                if ops.len() == 3 {
                    Self::vprorvq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vprorvq_maskz" => {
                if ops.len() == 3 {
                    Self::vprorvq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsadbw" => {
                if ops.len() == 3 {
                    Self::vpsadbw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpscatterdd" => {
                if ops.len() == 2 {
                    Self::vpscatterdd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpscatterdq" => {
                if ops.len() == 2 {
                    Self::vpscatterdq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpscatterqd" => {
                if ops.len() == 2 {
                    Self::vpscatterqd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpscatterqq" => {
                if ops.len() == 2 {
                    Self::vpscatterqq(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldd" => {
                if ops.len() == 4 {
                    Self::vpshldd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldd_mask" => {
                if ops.len() == 4 {
                    Self::vpshldd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldd_maskz" => {
                if ops.len() == 4 {
                    Self::vpshldd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldq" => {
                if ops.len() == 4 {
                    Self::vpshldq(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldq_mask" => {
                if ops.len() == 4 {
                    Self::vpshldq_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldq_maskz" => {
                if ops.len() == 4 {
                    Self::vpshldq_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldvd" => {
                if ops.len() == 3 {
                    Self::vpshldvd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldvd_mask" => {
                if ops.len() == 3 {
                    Self::vpshldvd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldvd_maskz" => {
                if ops.len() == 3 {
                    Self::vpshldvd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldvq" => {
                if ops.len() == 3 {
                    Self::vpshldvq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldvq_mask" => {
                if ops.len() == 3 {
                    Self::vpshldvq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldvq_maskz" => {
                if ops.len() == 3 {
                    Self::vpshldvq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldvw" => {
                if ops.len() == 3 {
                    Self::vpshldvw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldvw_mask" => {
                if ops.len() == 3 {
                    Self::vpshldvw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldvw_maskz" => {
                if ops.len() == 3 {
                    Self::vpshldvw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldw" => {
                if ops.len() == 4 {
                    Self::vpshldw(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldw_mask" => {
                if ops.len() == 4 {
                    Self::vpshldw_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshldw_maskz" => {
                if ops.len() == 4 {
                    Self::vpshldw_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdd" => {
                if ops.len() == 4 {
                    Self::vpshrdd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdd_mask" => {
                if ops.len() == 4 {
                    Self::vpshrdd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdd_maskz" => {
                if ops.len() == 4 {
                    Self::vpshrdd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdq" => {
                if ops.len() == 4 {
                    Self::vpshrdq(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdq_mask" => {
                if ops.len() == 4 {
                    Self::vpshrdq_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdq_maskz" => {
                if ops.len() == 4 {
                    Self::vpshrdq_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdvd" => {
                if ops.len() == 3 {
                    Self::vpshrdvd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdvd_mask" => {
                if ops.len() == 3 {
                    Self::vpshrdvd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdvd_maskz" => {
                if ops.len() == 3 {
                    Self::vpshrdvd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdvq" => {
                if ops.len() == 3 {
                    Self::vpshrdvq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdvq_mask" => {
                if ops.len() == 3 {
                    Self::vpshrdvq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdvq_maskz" => {
                if ops.len() == 3 {
                    Self::vpshrdvq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdvw" => {
                if ops.len() == 3 {
                    Self::vpshrdvw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdvw_mask" => {
                if ops.len() == 3 {
                    Self::vpshrdvw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdvw_maskz" => {
                if ops.len() == 3 {
                    Self::vpshrdvw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdw" => {
                if ops.len() == 4 {
                    Self::vpshrdw(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdw_mask" => {
                if ops.len() == 4 {
                    Self::vpshrdw_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshrdw_maskz" => {
                if ops.len() == 4 {
                    Self::vpshrdw_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshufb" => {
                if ops.len() == 3 {
                    Self::vpshufb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshufbitqmb" => {
                if ops.len() == 3 {
                    Self::vpshufbitqmb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshufbitqmb_mask" => {
                if ops.len() == 3 {
                    Self::vpshufbitqmb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshufb_mask" => {
                if ops.len() == 3 {
                    Self::vpshufb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshufb_maskz" => {
                if ops.len() == 3 {
                    Self::vpshufb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshufd" => {
                if ops.len() == 3 {
                    Self::vpshufd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshufd_mask" => {
                if ops.len() == 3 {
                    Self::vpshufd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshufd_maskz" => {
                if ops.len() == 3 {
                    Self::vpshufd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshufhw" => {
                if ops.len() == 3 {
                    Self::vpshufhw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshufhw_mask" => {
                if ops.len() == 3 {
                    Self::vpshufhw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshufhw_maskz" => {
                if ops.len() == 3 {
                    Self::vpshufhw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshuflw" => {
                if ops.len() == 3 {
                    Self::vpshuflw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshuflw_mask" => {
                if ops.len() == 3 {
                    Self::vpshuflw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpshuflw_maskz" => {
                if ops.len() == 3 {
                    Self::vpshuflw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsignb" => {
                if ops.len() == 3 {
                    Self::vpsignb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsignd" => {
                if ops.len() == 3 {
                    Self::vpsignd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsignw" => {
                if ops.len() == 3 {
                    Self::vpsignw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpslld" => {
                if ops.len() == 3 {
                    Self::vpslld(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpslldq" => {
                if ops.len() == 3 {
                    Self::vpslldq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpslld_mask" => {
                if ops.len() == 3 {
                    Self::vpslld_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpslld_maskz" => {
                if ops.len() == 3 {
                    Self::vpslld_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllq" => {
                if ops.len() == 3 {
                    Self::vpsllq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllq_mask" => {
                if ops.len() == 3 {
                    Self::vpsllq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllq_maskz" => {
                if ops.len() == 3 {
                    Self::vpsllq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllvd" => {
                if ops.len() == 3 {
                    Self::vpsllvd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllvd_mask" => {
                if ops.len() == 3 {
                    Self::vpsllvd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllvd_maskz" => {
                if ops.len() == 3 {
                    Self::vpsllvd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllvq" => {
                if ops.len() == 3 {
                    Self::vpsllvq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllvq_mask" => {
                if ops.len() == 3 {
                    Self::vpsllvq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllvq_maskz" => {
                if ops.len() == 3 {
                    Self::vpsllvq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllvw" => {
                if ops.len() == 3 {
                    Self::vpsllvw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllvw_mask" => {
                if ops.len() == 3 {
                    Self::vpsllvw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllvw_maskz" => {
                if ops.len() == 3 {
                    Self::vpsllvw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllw" => {
                if ops.len() == 3 {
                    Self::vpsllw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllw_mask" => {
                if ops.len() == 3 {
                    Self::vpsllw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsllw_maskz" => {
                if ops.len() == 3 {
                    Self::vpsllw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrad" => {
                if ops.len() == 3 {
                    Self::vpsrad(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrad_mask" => {
                if ops.len() == 3 {
                    Self::vpsrad_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrad_maskz" => {
                if ops.len() == 3 {
                    Self::vpsrad_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsraq" => {
                if ops.len() == 3 {
                    Self::vpsraq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsraq_mask" => {
                if ops.len() == 3 {
                    Self::vpsraq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsraq_maskz" => {
                if ops.len() == 3 {
                    Self::vpsraq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsravd" => {
                if ops.len() == 3 {
                    Self::vpsravd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsravd_mask" => {
                if ops.len() == 3 {
                    Self::vpsravd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsravd_maskz" => {
                if ops.len() == 3 {
                    Self::vpsravd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsravq" => {
                if ops.len() == 3 {
                    Self::vpsravq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsravq_mask" => {
                if ops.len() == 3 {
                    Self::vpsravq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsravq_maskz" => {
                if ops.len() == 3 {
                    Self::vpsravq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsravw" => {
                if ops.len() == 3 {
                    Self::vpsravw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsravw_mask" => {
                if ops.len() == 3 {
                    Self::vpsravw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsravw_maskz" => {
                if ops.len() == 3 {
                    Self::vpsravw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsraw" => {
                if ops.len() == 3 {
                    Self::vpsraw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsraw_mask" => {
                if ops.len() == 3 {
                    Self::vpsraw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsraw_maskz" => {
                if ops.len() == 3 {
                    Self::vpsraw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrld" => {
                if ops.len() == 3 {
                    Self::vpsrld(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrldq" => {
                if ops.len() == 3 {
                    Self::vpsrldq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrld_mask" => {
                if ops.len() == 3 {
                    Self::vpsrld_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrld_maskz" => {
                if ops.len() == 3 {
                    Self::vpsrld_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlq" => {
                if ops.len() == 3 {
                    Self::vpsrlq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlq_mask" => {
                if ops.len() == 3 {
                    Self::vpsrlq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlq_maskz" => {
                if ops.len() == 3 {
                    Self::vpsrlq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlvd" => {
                if ops.len() == 3 {
                    Self::vpsrlvd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlvd_mask" => {
                if ops.len() == 3 {
                    Self::vpsrlvd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlvd_maskz" => {
                if ops.len() == 3 {
                    Self::vpsrlvd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlvq" => {
                if ops.len() == 3 {
                    Self::vpsrlvq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlvq_mask" => {
                if ops.len() == 3 {
                    Self::vpsrlvq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlvq_maskz" => {
                if ops.len() == 3 {
                    Self::vpsrlvq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlvw" => {
                if ops.len() == 3 {
                    Self::vpsrlvw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlvw_mask" => {
                if ops.len() == 3 {
                    Self::vpsrlvw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlvw_maskz" => {
                if ops.len() == 3 {
                    Self::vpsrlvw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlw" => {
                if ops.len() == 3 {
                    Self::vpsrlw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlw_mask" => {
                if ops.len() == 3 {
                    Self::vpsrlw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsrlw_maskz" => {
                if ops.len() == 3 {
                    Self::vpsrlw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubb" => {
                if ops.len() == 3 {
                    Self::vpsubb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubb_mask" => {
                if ops.len() == 3 {
                    Self::vpsubb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubb_maskz" => {
                if ops.len() == 3 {
                    Self::vpsubb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubd" => {
                if ops.len() == 3 {
                    Self::vpsubd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubd_mask" => {
                if ops.len() == 3 {
                    Self::vpsubd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubd_maskz" => {
                if ops.len() == 3 {
                    Self::vpsubd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubq" => {
                if ops.len() == 3 {
                    Self::vpsubq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubq_mask" => {
                if ops.len() == 3 {
                    Self::vpsubq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubq_maskz" => {
                if ops.len() == 3 {
                    Self::vpsubq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubsb" => {
                if ops.len() == 3 {
                    Self::vpsubsb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubsb_mask" => {
                if ops.len() == 3 {
                    Self::vpsubsb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubsb_maskz" => {
                if ops.len() == 3 {
                    Self::vpsubsb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubsw" => {
                if ops.len() == 3 {
                    Self::vpsubsw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubsw_mask" => {
                if ops.len() == 3 {
                    Self::vpsubsw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubsw_maskz" => {
                if ops.len() == 3 {
                    Self::vpsubsw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubusb" => {
                if ops.len() == 3 {
                    Self::vpsubusb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubusb_mask" => {
                if ops.len() == 3 {
                    Self::vpsubusb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubusb_maskz" => {
                if ops.len() == 3 {
                    Self::vpsubusb_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubusw" => {
                if ops.len() == 3 {
                    Self::vpsubusw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubusw_mask" => {
                if ops.len() == 3 {
                    Self::vpsubusw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubusw_maskz" => {
                if ops.len() == 3 {
                    Self::vpsubusw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubw" => {
                if ops.len() == 3 {
                    Self::vpsubw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubw_mask" => {
                if ops.len() == 3 {
                    Self::vpsubw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpsubw_maskz" => {
                if ops.len() == 3 {
                    Self::vpsubw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpternlogd" => {
                if ops.len() == 4 {
                    Self::vpternlogd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpternlogd_mask" => {
                if ops.len() == 4 {
                    Self::vpternlogd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpternlogd_maskz" => {
                if ops.len() == 4 {
                    Self::vpternlogd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpternlogq" => {
                if ops.len() == 4 {
                    Self::vpternlogq(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpternlogq_mask" => {
                if ops.len() == 4 {
                    Self::vpternlogq_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpternlogq_maskz" => {
                if ops.len() == 4 {
                    Self::vpternlogq_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptest" => {
                if ops.len() == 2 {
                    Self::vptest(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestmb" => {
                if ops.len() == 3 {
                    Self::vptestmb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestmb_mask" => {
                if ops.len() == 3 {
                    Self::vptestmb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestmd" => {
                if ops.len() == 3 {
                    Self::vptestmd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestmd_mask" => {
                if ops.len() == 3 {
                    Self::vptestmd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestmq" => {
                if ops.len() == 3 {
                    Self::vptestmq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestmq_mask" => {
                if ops.len() == 3 {
                    Self::vptestmq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestmw" => {
                if ops.len() == 3 {
                    Self::vptestmw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestmw_mask" => {
                if ops.len() == 3 {
                    Self::vptestmw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestnmb" => {
                if ops.len() == 3 {
                    Self::vptestnmb(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestnmb_mask" => {
                if ops.len() == 3 {
                    Self::vptestnmb_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestnmd" => {
                if ops.len() == 3 {
                    Self::vptestnmd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestnmd_mask" => {
                if ops.len() == 3 {
                    Self::vptestnmd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestnmq" => {
                if ops.len() == 3 {
                    Self::vptestnmq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestnmq_mask" => {
                if ops.len() == 3 {
                    Self::vptestnmq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestnmw" => {
                if ops.len() == 3 {
                    Self::vptestnmw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vptestnmw_mask" => {
                if ops.len() == 3 {
                    Self::vptestnmw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhbw" => {
                if ops.len() == 3 {
                    Self::vpunpckhbw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhbw_mask" => {
                if ops.len() == 3 {
                    Self::vpunpckhbw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhbw_maskz" => {
                if ops.len() == 3 {
                    Self::vpunpckhbw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhdq" => {
                if ops.len() == 3 {
                    Self::vpunpckhdq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhdq_mask" => {
                if ops.len() == 3 {
                    Self::vpunpckhdq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhdq_maskz" => {
                if ops.len() == 3 {
                    Self::vpunpckhdq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhqdq" => {
                if ops.len() == 3 {
                    Self::vpunpckhqdq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhqdq_mask" => {
                if ops.len() == 3 {
                    Self::vpunpckhqdq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhqdq_maskz" => {
                if ops.len() == 3 {
                    Self::vpunpckhqdq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhwd" => {
                if ops.len() == 3 {
                    Self::vpunpckhwd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhwd_mask" => {
                if ops.len() == 3 {
                    Self::vpunpckhwd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckhwd_maskz" => {
                if ops.len() == 3 {
                    Self::vpunpckhwd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpcklbw" => {
                if ops.len() == 3 {
                    Self::vpunpcklbw(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpcklbw_mask" => {
                if ops.len() == 3 {
                    Self::vpunpcklbw_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpcklbw_maskz" => {
                if ops.len() == 3 {
                    Self::vpunpcklbw_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckldq" => {
                if ops.len() == 3 {
                    Self::vpunpckldq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckldq_mask" => {
                if ops.len() == 3 {
                    Self::vpunpckldq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpckldq_maskz" => {
                if ops.len() == 3 {
                    Self::vpunpckldq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpcklqdq" => {
                if ops.len() == 3 {
                    Self::vpunpcklqdq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpcklqdq_mask" => {
                if ops.len() == 3 {
                    Self::vpunpcklqdq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpcklqdq_maskz" => {
                if ops.len() == 3 {
                    Self::vpunpcklqdq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpcklwd" => {
                if ops.len() == 3 {
                    Self::vpunpcklwd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpcklwd_mask" => {
                if ops.len() == 3 {
                    Self::vpunpcklwd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpunpcklwd_maskz" => {
                if ops.len() == 3 {
                    Self::vpunpcklwd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpxor" => {
                if ops.len() == 3 {
                    Self::vpxor(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpxord" => {
                if ops.len() == 3 {
                    Self::vpxord(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpxord_mask" => {
                if ops.len() == 3 {
                    Self::vpxord_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpxord_maskz" => {
                if ops.len() == 3 {
                    Self::vpxord_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpxorq" => {
                if ops.len() == 3 {
                    Self::vpxorq(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpxorq_mask" => {
                if ops.len() == 3 {
                    Self::vpxorq_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vpxorq_maskz" => {
                if ops.len() == 3 {
                    Self::vpxorq_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangepd" => {
                if ops.len() == 4 {
                    Self::vrangepd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangepd_mask" => {
                if ops.len() == 4 {
                    Self::vrangepd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangepd_mask_sae" => {
                if ops.len() == 4 {
                    Self::vrangepd_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangepd_maskz" => {
                if ops.len() == 4 {
                    Self::vrangepd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangepd_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vrangepd_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangepd_sae" => {
                if ops.len() == 4 {
                    Self::vrangepd_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangeps" => {
                if ops.len() == 4 {
                    Self::vrangeps(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangeps_mask" => {
                if ops.len() == 4 {
                    Self::vrangeps_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangeps_mask_sae" => {
                if ops.len() == 4 {
                    Self::vrangeps_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangeps_maskz" => {
                if ops.len() == 4 {
                    Self::vrangeps_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangeps_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vrangeps_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangeps_sae" => {
                if ops.len() == 4 {
                    Self::vrangeps_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangesd" => {
                if ops.len() == 4 {
                    Self::vrangesd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangesd_mask" => {
                if ops.len() == 4 {
                    Self::vrangesd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangesd_mask_sae" => {
                if ops.len() == 4 {
                    Self::vrangesd_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangesd_maskz" => {
                if ops.len() == 4 {
                    Self::vrangesd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangesd_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vrangesd_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangesd_sae" => {
                if ops.len() == 4 {
                    Self::vrangesd_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangess" => {
                if ops.len() == 4 {
                    Self::vrangess(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangess_mask" => {
                if ops.len() == 4 {
                    Self::vrangess_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangess_mask_sae" => {
                if ops.len() == 4 {
                    Self::vrangess_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangess_maskz" => {
                if ops.len() == 4 {
                    Self::vrangess_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangess_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vrangess_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrangess_sae" => {
                if ops.len() == 4 {
                    Self::vrangess_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14pd" => {
                if ops.len() == 2 {
                    Self::vrcp14pd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14pd_mask" => {
                if ops.len() == 2 {
                    Self::vrcp14pd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14pd_maskz" => {
                if ops.len() == 2 {
                    Self::vrcp14pd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14ps" => {
                if ops.len() == 2 {
                    Self::vrcp14ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14ps_mask" => {
                if ops.len() == 2 {
                    Self::vrcp14ps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14ps_maskz" => {
                if ops.len() == 2 {
                    Self::vrcp14ps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14sd" => {
                if ops.len() == 3 {
                    Self::vrcp14sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14sd_mask" => {
                if ops.len() == 3 {
                    Self::vrcp14sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14sd_maskz" => {
                if ops.len() == 3 {
                    Self::vrcp14sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14ss" => {
                if ops.len() == 3 {
                    Self::vrcp14ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14ss_mask" => {
                if ops.len() == 3 {
                    Self::vrcp14ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcp14ss_maskz" => {
                if ops.len() == 3 {
                    Self::vrcp14ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcpph" => {
                if ops.len() == 2 {
                    Self::vrcpph(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcpph_mask" => {
                if ops.len() == 2 {
                    Self::vrcpph_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcpph_maskz" => {
                if ops.len() == 2 {
                    Self::vrcpph_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcpps" => {
                if ops.len() == 2 {
                    Self::vrcpps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcpsh" => {
                if ops.len() == 3 {
                    Self::vrcpsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcpsh_mask" => {
                if ops.len() == 3 {
                    Self::vrcpsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcpsh_maskz" => {
                if ops.len() == 3 {
                    Self::vrcpsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrcpss" => {
                if ops.len() == 3 {
                    Self::vrcpss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducepd" => {
                if ops.len() == 3 {
                    Self::vreducepd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducepd_mask" => {
                if ops.len() == 3 {
                    Self::vreducepd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducepd_mask_sae" => {
                if ops.len() == 3 {
                    Self::vreducepd_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducepd_maskz" => {
                if ops.len() == 3 {
                    Self::vreducepd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducepd_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vreducepd_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducepd_sae" => {
                if ops.len() == 3 {
                    Self::vreducepd_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceph" => {
                if ops.len() == 3 {
                    Self::vreduceph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceph_mask" => {
                if ops.len() == 3 {
                    Self::vreduceph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceph_mask_sae" => {
                if ops.len() == 3 {
                    Self::vreduceph_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceph_maskz" => {
                if ops.len() == 3 {
                    Self::vreduceph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceph_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vreduceph_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceph_sae" => {
                if ops.len() == 3 {
                    Self::vreduceph_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceps" => {
                if ops.len() == 3 {
                    Self::vreduceps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceps_mask" => {
                if ops.len() == 3 {
                    Self::vreduceps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceps_mask_sae" => {
                if ops.len() == 3 {
                    Self::vreduceps_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceps_maskz" => {
                if ops.len() == 3 {
                    Self::vreduceps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceps_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vreduceps_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreduceps_sae" => {
                if ops.len() == 3 {
                    Self::vreduceps_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesd" => {
                if ops.len() == 4 {
                    Self::vreducesd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesd_mask" => {
                if ops.len() == 4 {
                    Self::vreducesd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesd_mask_sae" => {
                if ops.len() == 4 {
                    Self::vreducesd_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesd_maskz" => {
                if ops.len() == 4 {
                    Self::vreducesd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesd_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vreducesd_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesd_sae" => {
                if ops.len() == 4 {
                    Self::vreducesd_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesh" => {
                if ops.len() == 4 {
                    Self::vreducesh(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesh_mask" => {
                if ops.len() == 4 {
                    Self::vreducesh_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesh_mask_sae" => {
                if ops.len() == 4 {
                    Self::vreducesh_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesh_maskz" => {
                if ops.len() == 4 {
                    Self::vreducesh_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesh_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vreducesh_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducesh_sae" => {
                if ops.len() == 4 {
                    Self::vreducesh_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducess" => {
                if ops.len() == 4 {
                    Self::vreducess(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducess_mask" => {
                if ops.len() == 4 {
                    Self::vreducess_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducess_mask_sae" => {
                if ops.len() == 4 {
                    Self::vreducess_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducess_maskz" => {
                if ops.len() == 4 {
                    Self::vreducess_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducess_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vreducess_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vreducess_sae" => {
                if ops.len() == 4 {
                    Self::vreducess_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalepd" => {
                if ops.len() == 3 {
                    Self::vrndscalepd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalepd_mask" => {
                if ops.len() == 3 {
                    Self::vrndscalepd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalepd_mask_sae" => {
                if ops.len() == 3 {
                    Self::vrndscalepd_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalepd_maskz" => {
                if ops.len() == 3 {
                    Self::vrndscalepd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalepd_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vrndscalepd_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalepd_sae" => {
                if ops.len() == 3 {
                    Self::vrndscalepd_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleph" => {
                if ops.len() == 3 {
                    Self::vrndscaleph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleph_mask" => {
                if ops.len() == 3 {
                    Self::vrndscaleph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleph_mask_sae" => {
                if ops.len() == 3 {
                    Self::vrndscaleph_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleph_maskz" => {
                if ops.len() == 3 {
                    Self::vrndscaleph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleph_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vrndscaleph_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleph_sae" => {
                if ops.len() == 3 {
                    Self::vrndscaleph_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleps" => {
                if ops.len() == 3 {
                    Self::vrndscaleps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleps_mask" => {
                if ops.len() == 3 {
                    Self::vrndscaleps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleps_mask_sae" => {
                if ops.len() == 3 {
                    Self::vrndscaleps_mask_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleps_maskz" => {
                if ops.len() == 3 {
                    Self::vrndscaleps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleps_maskz_sae" => {
                if ops.len() == 3 {
                    Self::vrndscaleps_maskz_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaleps_sae" => {
                if ops.len() == 3 {
                    Self::vrndscaleps_sae(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesd" => {
                if ops.len() == 4 {
                    Self::vrndscalesd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesd_mask" => {
                if ops.len() == 4 {
                    Self::vrndscalesd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesd_mask_sae" => {
                if ops.len() == 4 {
                    Self::vrndscalesd_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesd_maskz" => {
                if ops.len() == 4 {
                    Self::vrndscalesd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesd_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vrndscalesd_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesd_sae" => {
                if ops.len() == 4 {
                    Self::vrndscalesd_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesh" => {
                if ops.len() == 4 {
                    Self::vrndscalesh(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesh_mask" => {
                if ops.len() == 4 {
                    Self::vrndscalesh_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesh_mask_sae" => {
                if ops.len() == 4 {
                    Self::vrndscalesh_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesh_maskz" => {
                if ops.len() == 4 {
                    Self::vrndscalesh_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesh_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vrndscalesh_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscalesh_sae" => {
                if ops.len() == 4 {
                    Self::vrndscalesh_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaless" => {
                if ops.len() == 4 {
                    Self::vrndscaless(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaless_mask" => {
                if ops.len() == 4 {
                    Self::vrndscaless_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaless_mask_sae" => {
                if ops.len() == 4 {
                    Self::vrndscaless_mask_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaless_maskz" => {
                if ops.len() == 4 {
                    Self::vrndscaless_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaless_maskz_sae" => {
                if ops.len() == 4 {
                    Self::vrndscaless_maskz_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrndscaless_sae" => {
                if ops.len() == 4 {
                    Self::vrndscaless_sae(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vroundpd" => {
                if ops.len() == 3 {
                    Self::vroundpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vroundps" => {
                if ops.len() == 3 {
                    Self::vroundps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vroundsd" => {
                if ops.len() == 4 {
                    Self::vroundsd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vroundss" => {
                if ops.len() == 4 {
                    Self::vroundss(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14pd" => {
                if ops.len() == 2 {
                    Self::vrsqrt14pd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14pd_mask" => {
                if ops.len() == 2 {
                    Self::vrsqrt14pd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14pd_maskz" => {
                if ops.len() == 2 {
                    Self::vrsqrt14pd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14ps" => {
                if ops.len() == 2 {
                    Self::vrsqrt14ps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14ps_mask" => {
                if ops.len() == 2 {
                    Self::vrsqrt14ps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14ps_maskz" => {
                if ops.len() == 2 {
                    Self::vrsqrt14ps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14sd" => {
                if ops.len() == 3 {
                    Self::vrsqrt14sd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14sd_mask" => {
                if ops.len() == 3 {
                    Self::vrsqrt14sd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14sd_maskz" => {
                if ops.len() == 3 {
                    Self::vrsqrt14sd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14ss" => {
                if ops.len() == 3 {
                    Self::vrsqrt14ss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14ss_mask" => {
                if ops.len() == 3 {
                    Self::vrsqrt14ss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrt14ss_maskz" => {
                if ops.len() == 3 {
                    Self::vrsqrt14ss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrtph" => {
                if ops.len() == 2 {
                    Self::vrsqrtph(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrtph_mask" => {
                if ops.len() == 2 {
                    Self::vrsqrtph_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrtph_maskz" => {
                if ops.len() == 2 {
                    Self::vrsqrtph_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrtps" => {
                if ops.len() == 2 {
                    Self::vrsqrtps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrtsh" => {
                if ops.len() == 3 {
                    Self::vrsqrtsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrtsh_mask" => {
                if ops.len() == 3 {
                    Self::vrsqrtsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrtsh_maskz" => {
                if ops.len() == 3 {
                    Self::vrsqrtsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vrsqrtss" => {
                if ops.len() == 3 {
                    Self::vrsqrtss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefpd" => {
                if ops.len() == 3 {
                    Self::vscalefpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefpd_er" => {
                if ops.len() == 3 {
                    Self::vscalefpd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefpd_mask" => {
                if ops.len() == 3 {
                    Self::vscalefpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefpd_mask_er" => {
                if ops.len() == 3 {
                    Self::vscalefpd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefpd_maskz" => {
                if ops.len() == 3 {
                    Self::vscalefpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefpd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vscalefpd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefph" => {
                if ops.len() == 3 {
                    Self::vscalefph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefph_er" => {
                if ops.len() == 3 {
                    Self::vscalefph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefph_mask" => {
                if ops.len() == 3 {
                    Self::vscalefph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefph_mask_er" => {
                if ops.len() == 3 {
                    Self::vscalefph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefph_maskz" => {
                if ops.len() == 3 {
                    Self::vscalefph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vscalefph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefps" => {
                if ops.len() == 3 {
                    Self::vscalefps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefps_er" => {
                if ops.len() == 3 {
                    Self::vscalefps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefps_mask" => {
                if ops.len() == 3 {
                    Self::vscalefps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefps_mask_er" => {
                if ops.len() == 3 {
                    Self::vscalefps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefps_maskz" => {
                if ops.len() == 3 {
                    Self::vscalefps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vscalefps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsd" => {
                if ops.len() == 3 {
                    Self::vscalefsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsd_er" => {
                if ops.len() == 3 {
                    Self::vscalefsd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsd_mask" => {
                if ops.len() == 3 {
                    Self::vscalefsd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsd_mask_er" => {
                if ops.len() == 3 {
                    Self::vscalefsd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsd_maskz" => {
                if ops.len() == 3 {
                    Self::vscalefsd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vscalefsd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsh" => {
                if ops.len() == 3 {
                    Self::vscalefsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsh_er" => {
                if ops.len() == 3 {
                    Self::vscalefsh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsh_mask" => {
                if ops.len() == 3 {
                    Self::vscalefsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsh_mask_er" => {
                if ops.len() == 3 {
                    Self::vscalefsh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsh_maskz" => {
                if ops.len() == 3 {
                    Self::vscalefsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefsh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vscalefsh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefss" => {
                if ops.len() == 3 {
                    Self::vscalefss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefss_er" => {
                if ops.len() == 3 {
                    Self::vscalefss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefss_mask" => {
                if ops.len() == 3 {
                    Self::vscalefss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefss_mask_er" => {
                if ops.len() == 3 {
                    Self::vscalefss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefss_maskz" => {
                if ops.len() == 3 {
                    Self::vscalefss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscalefss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vscalefss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscatterdpd" => {
                if ops.len() == 2 {
                    Self::vscatterdpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscatterdps" => {
                if ops.len() == 2 {
                    Self::vscatterdps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscatterqpd" => {
                if ops.len() == 2 {
                    Self::vscatterqpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vscatterqps" => {
                if ops.len() == 2 {
                    Self::vscatterqps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshuff32x4" => {
                if ops.len() == 4 {
                    Self::vshuff32x4(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshuff32x4_mask" => {
                if ops.len() == 4 {
                    Self::vshuff32x4_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshuff32x4_maskz" => {
                if ops.len() == 4 {
                    Self::vshuff32x4_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshuff64x2" => {
                if ops.len() == 4 {
                    Self::vshuff64x2(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshuff64x2_mask" => {
                if ops.len() == 4 {
                    Self::vshuff64x2_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshuff64x2_maskz" => {
                if ops.len() == 4 {
                    Self::vshuff64x2_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufi32x4" => {
                if ops.len() == 4 {
                    Self::vshufi32x4(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufi32x4_mask" => {
                if ops.len() == 4 {
                    Self::vshufi32x4_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufi32x4_maskz" => {
                if ops.len() == 4 {
                    Self::vshufi32x4_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufi64x2" => {
                if ops.len() == 4 {
                    Self::vshufi64x2(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufi64x2_mask" => {
                if ops.len() == 4 {
                    Self::vshufi64x2_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufi64x2_maskz" => {
                if ops.len() == 4 {
                    Self::vshufi64x2_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufpd" => {
                if ops.len() == 4 {
                    Self::vshufpd(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufpd_mask" => {
                if ops.len() == 4 {
                    Self::vshufpd_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufpd_maskz" => {
                if ops.len() == 4 {
                    Self::vshufpd_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufps" => {
                if ops.len() == 4 {
                    Self::vshufps(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufps_mask" => {
                if ops.len() == 4 {
                    Self::vshufps_mask(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vshufps_maskz" => {
                if ops.len() == 4 {
                    Self::vshufps_maskz(&ops[0], &ops[1], &ops[2], &ops[3])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsm4key4" => {
                if ops.len() == 3 {
                    Self::vsm4key4(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsm4rnds4" => {
                if ops.len() == 3 {
                    Self::vsm4rnds4(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtpd" => {
                if ops.len() == 2 {
                    Self::vsqrtpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtpd_er" => {
                if ops.len() == 2 {
                    Self::vsqrtpd_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtpd_mask" => {
                if ops.len() == 2 {
                    Self::vsqrtpd_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtpd_mask_er" => {
                if ops.len() == 2 {
                    Self::vsqrtpd_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtpd_maskz" => {
                if ops.len() == 2 {
                    Self::vsqrtpd_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtpd_maskz_er" => {
                if ops.len() == 2 {
                    Self::vsqrtpd_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtph" => {
                if ops.len() == 2 {
                    Self::vsqrtph(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtph_er" => {
                if ops.len() == 2 {
                    Self::vsqrtph_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtph_mask" => {
                if ops.len() == 2 {
                    Self::vsqrtph_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtph_mask_er" => {
                if ops.len() == 2 {
                    Self::vsqrtph_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtph_maskz" => {
                if ops.len() == 2 {
                    Self::vsqrtph_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtph_maskz_er" => {
                if ops.len() == 2 {
                    Self::vsqrtph_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtps" => {
                if ops.len() == 2 {
                    Self::vsqrtps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtps_er" => {
                if ops.len() == 2 {
                    Self::vsqrtps_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtps_mask" => {
                if ops.len() == 2 {
                    Self::vsqrtps_mask(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtps_mask_er" => {
                if ops.len() == 2 {
                    Self::vsqrtps_mask_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtps_maskz" => {
                if ops.len() == 2 {
                    Self::vsqrtps_maskz(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtps_maskz_er" => {
                if ops.len() == 2 {
                    Self::vsqrtps_maskz_er(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsd" => {
                if ops.len() == 3 {
                    Self::vsqrtsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsd_er" => {
                if ops.len() == 3 {
                    Self::vsqrtsd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsd_mask" => {
                if ops.len() == 3 {
                    Self::vsqrtsd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsd_mask_er" => {
                if ops.len() == 3 {
                    Self::vsqrtsd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsd_maskz" => {
                if ops.len() == 3 {
                    Self::vsqrtsd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vsqrtsd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsh" => {
                if ops.len() == 3 {
                    Self::vsqrtsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsh_er" => {
                if ops.len() == 3 {
                    Self::vsqrtsh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsh_mask" => {
                if ops.len() == 3 {
                    Self::vsqrtsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsh_mask_er" => {
                if ops.len() == 3 {
                    Self::vsqrtsh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsh_maskz" => {
                if ops.len() == 3 {
                    Self::vsqrtsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtsh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vsqrtsh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtss" => {
                if ops.len() == 3 {
                    Self::vsqrtss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtss_er" => {
                if ops.len() == 3 {
                    Self::vsqrtss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtss_mask" => {
                if ops.len() == 3 {
                    Self::vsqrtss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtss_mask_er" => {
                if ops.len() == 3 {
                    Self::vsqrtss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtss_maskz" => {
                if ops.len() == 3 {
                    Self::vsqrtss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsqrtss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vsqrtss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vstmxcsr" => {
                if ops.len() == 1 {
                    Self::vstmxcsr(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubpd" => {
                if ops.len() == 3 {
                    Self::vsubpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubpd_er" => {
                if ops.len() == 3 {
                    Self::vsubpd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubpd_mask" => {
                if ops.len() == 3 {
                    Self::vsubpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubpd_mask_er" => {
                if ops.len() == 3 {
                    Self::vsubpd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubpd_maskz" => {
                if ops.len() == 3 {
                    Self::vsubpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubpd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vsubpd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubph" => {
                if ops.len() == 3 {
                    Self::vsubph(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubph_er" => {
                if ops.len() == 3 {
                    Self::vsubph_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubph_mask" => {
                if ops.len() == 3 {
                    Self::vsubph_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubph_mask_er" => {
                if ops.len() == 3 {
                    Self::vsubph_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubph_maskz" => {
                if ops.len() == 3 {
                    Self::vsubph_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubph_maskz_er" => {
                if ops.len() == 3 {
                    Self::vsubph_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubps" => {
                if ops.len() == 3 {
                    Self::vsubps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubps_er" => {
                if ops.len() == 3 {
                    Self::vsubps_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubps_mask" => {
                if ops.len() == 3 {
                    Self::vsubps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubps_mask_er" => {
                if ops.len() == 3 {
                    Self::vsubps_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubps_maskz" => {
                if ops.len() == 3 {
                    Self::vsubps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubps_maskz_er" => {
                if ops.len() == 3 {
                    Self::vsubps_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsd" => {
                if ops.len() == 3 {
                    Self::vsubsd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsd_er" => {
                if ops.len() == 3 {
                    Self::vsubsd_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsd_mask" => {
                if ops.len() == 3 {
                    Self::vsubsd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsd_mask_er" => {
                if ops.len() == 3 {
                    Self::vsubsd_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsd_maskz" => {
                if ops.len() == 3 {
                    Self::vsubsd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsd_maskz_er" => {
                if ops.len() == 3 {
                    Self::vsubsd_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsh" => {
                if ops.len() == 3 {
                    Self::vsubsh(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsh_er" => {
                if ops.len() == 3 {
                    Self::vsubsh_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsh_mask" => {
                if ops.len() == 3 {
                    Self::vsubsh_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsh_mask_er" => {
                if ops.len() == 3 {
                    Self::vsubsh_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsh_maskz" => {
                if ops.len() == 3 {
                    Self::vsubsh_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubsh_maskz_er" => {
                if ops.len() == 3 {
                    Self::vsubsh_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubss" => {
                if ops.len() == 3 {
                    Self::vsubss(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubss_er" => {
                if ops.len() == 3 {
                    Self::vsubss_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubss_mask" => {
                if ops.len() == 3 {
                    Self::vsubss_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubss_mask_er" => {
                if ops.len() == 3 {
                    Self::vsubss_mask_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubss_maskz" => {
                if ops.len() == 3 {
                    Self::vsubss_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vsubss_maskz_er" => {
                if ops.len() == 3 {
                    Self::vsubss_maskz_er(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vtestpd" => {
                if ops.len() == 2 {
                    Self::vtestpd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vtestps" => {
                if ops.len() == 2 {
                    Self::vtestps(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vucomisd" => {
                if ops.len() == 2 {
                    Self::vucomisd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vucomisd_sae" => {
                if ops.len() == 2 {
                    Self::vucomisd_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vucomish" => {
                if ops.len() == 2 {
                    Self::vucomish(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vucomish_sae" => {
                if ops.len() == 2 {
                    Self::vucomish_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vucomiss" => {
                if ops.len() == 2 {
                    Self::vucomiss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vucomiss_sae" => {
                if ops.len() == 2 {
                    Self::vucomiss_sae(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpckhpd" => {
                if ops.len() == 3 {
                    Self::vunpckhpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpckhpd_mask" => {
                if ops.len() == 3 {
                    Self::vunpckhpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpckhpd_maskz" => {
                if ops.len() == 3 {
                    Self::vunpckhpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpckhps" => {
                if ops.len() == 3 {
                    Self::vunpckhps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpckhps_mask" => {
                if ops.len() == 3 {
                    Self::vunpckhps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpckhps_maskz" => {
                if ops.len() == 3 {
                    Self::vunpckhps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpcklpd" => {
                if ops.len() == 3 {
                    Self::vunpcklpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpcklpd_mask" => {
                if ops.len() == 3 {
                    Self::vunpcklpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpcklpd_maskz" => {
                if ops.len() == 3 {
                    Self::vunpcklpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpcklps" => {
                if ops.len() == 3 {
                    Self::vunpcklps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpcklps_mask" => {
                if ops.len() == 3 {
                    Self::vunpcklps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vunpcklps_maskz" => {
                if ops.len() == 3 {
                    Self::vunpcklps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vxorpd" => {
                if ops.len() == 3 {
                    Self::vxorpd(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vxorpd_mask" => {
                if ops.len() == 3 {
                    Self::vxorpd_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vxorpd_maskz" => {
                if ops.len() == 3 {
                    Self::vxorpd_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vxorps" => {
                if ops.len() == 3 {
                    Self::vxorps(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vxorps_mask" => {
                if ops.len() == 3 {
                    Self::vxorps_mask(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vxorps_maskz" => {
                if ops.len() == 3 {
                    Self::vxorps_maskz(&ops[0], &ops[1], &ops[2])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vzeroall" => {
                if ops.is_empty() {
                    Self::vzeroall()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "vzeroupper" => {
                if ops.is_empty() {
                    Self::vzeroupper()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "wbinvd" => {
                if ops.is_empty() {
                    Self::wbinvd()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "wbnoinvd" => {
                if ops.is_empty() {
                    Self::wbnoinvd()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "wrfsbase" => {
                if ops.len() == 1 {
                    Self::wrfsbase(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "wrgsbase" => {
                if ops.len() == 1 {
                    Self::wrgsbase(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "wrmsr" => {
                if ops.is_empty() {
                    Self::wrmsr()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "wrmsrlist" => {
                if ops.is_empty() {
                    Self::wrmsrlist()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "wrmsrns" => {
                if ops.is_empty() {
                    Self::wrmsrns()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "wrmsrns" => {
                if ops.len() == 2 {
                    Self::wrmsrns_2(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "wrpkru" => {
                if ops.is_empty() {
                    Self::wrpkru()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "wrss" => {
                if ops.len() == 2 {
                    Self::wrss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "wruss" => {
                if ops.len() == 2 {
                    Self::wruss(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xabort" => {
                if ops.len() == 1 {
                    Self::xabort(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xadd" => {
                if ops.len() == 2 {
                    Self::xadd(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xbegin" => {
                if ops.len() == 1 {
                    Self::xbegin(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xchg" => {
                if ops.len() == 2 {
                    Self::xchg(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xend" => {
                if ops.is_empty() {
                    Self::xend()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xgetbv" => {
                if ops.is_empty() {
                    Self::xgetbv()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xlatb" => {
                if ops.is_empty() {
                    Self::xlatb()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xor" => {
                if ops.len() == 2 {
                    Self::xor(&ops[0], &ops[1])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xresldtrk" => {
                if ops.is_empty() {
                    Self::xresldtrk()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xrstor" => {
                if ops.len() == 1 {
                    Self::xrstor(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xrstors" => {
                if ops.len() == 1 {
                    Self::xrstors(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xsave" => {
                if ops.len() == 1 {
                    Self::xsave(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xsavec" => {
                if ops.len() == 1 {
                    Self::xsavec(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xsaveopt" => {
                if ops.len() == 1 {
                    Self::xsaveopt(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xsaves" => {
                if ops.len() == 1 {
                    Self::xsaves(&ops[0])
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xsetbv" => {
                if ops.is_empty() {
                    Self::xsetbv()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xstore" => {
                if ops.is_empty() {
                    Self::xstore()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xsusldtrk" => {
                if ops.is_empty() {
                    Self::xsusldtrk()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            "xtest" => {
                if ops.is_empty() {
                    Self::xtest()
                } else {
                    Err(AsmError::InvalidOperand)
                }
            },
            _ => Err(AsmError::InvalidInstruction),
        }
    }
}

impl<'a> Assembler<'a> {
    /// Emit an instruction identified by mnemonic string and operand slice.
    ///
    /// This performs runtime operand-type checking to select the correct encoding.
    /// Requires the `x86-dyn` Cargo feature.
    pub fn emit_dyn(&mut self, mnem: &str, ops: &[Operand]) -> Result<(), AsmError> {
        Instruction::from_mnem(mnem, ops)?.emit(self);
        Ok(())
    }
}