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#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! Basic timers
//!
//! Used by: stm32h753
use crate::{RWRegister, WORegister};
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;
/// control register 1
pub mod CR1 {
/// UIF status bit remapping
pub mod UIFREMAP {
/// Offset (11 bits)
pub const offset: u32 = 11;
/// Mask (1 bit: 1 << 11)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Auto-reload preload enable
pub mod ARPE {
/// Offset (7 bits)
pub const offset: u32 = 7;
/// Mask (1 bit: 1 << 7)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: TIMx_APRR register is not buffered
pub const Disabled: u32 = 0b0;
/// 0b1: TIMx_APRR register is buffered
pub const Enabled: u32 = 0b1;
}
}
/// One-pulse mode
pub mod OPM {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Counter is not stopped at update event
pub const Disabled: u32 = 0b0;
/// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
pub const Enabled: u32 = 0b1;
}
}
/// Update request source
pub mod URS {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
pub const AnyEvent: u32 = 0b0;
/// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
pub const CounterOnly: u32 = 0b1;
}
}
/// Update disable
pub mod UDIS {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Update event enabled
pub const Enabled: u32 = 0b0;
/// 0b1: Update event disabled
pub const Disabled: u32 = 0b1;
}
}
/// Counter enable
pub mod CEN {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Counter disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Counter enabled
pub const Enabled: u32 = 0b1;
}
}
}
/// control register 2
pub mod CR2 {
/// Master mode selection
pub mod MMS {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (3 bits: 0b111 << 4)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// DMA/Interrupt enable register
pub mod DIER {
/// Update DMA request enable
pub mod UDE {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (1 bit: 1 << 8)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Update interrupt enable
pub mod UIE {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Update interrupt disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Update interrupt enabled
pub const Enabled: u32 = 0b1;
}
}
}
/// status register
pub mod SR {
/// Update interrupt flag
pub mod UIF {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: No update occurred
pub const Clear: u32 = 0b0;
/// 0b1: Update interrupt pending.
pub const UpdatePending: u32 = 0b1;
}
}
}
/// event generation register
pub mod EGR {
/// Update generation
pub mod UG {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b1: Re-initializes the timer counter and generates an update of the registers.
pub const Update: u32 = 0b1;
}
}
}
/// counter
pub mod CNT {
/// Low counter value
pub mod CNT {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// UIF Copy
pub mod UIFCPY {
/// Offset (31 bits)
pub const offset: u32 = 31;
/// Mask (1 bit: 1 << 31)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// prescaler
pub mod PSC {
/// Prescaler value
pub mod PSC {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// auto-reload register
pub mod ARR {
/// Low Auto-reload value
pub mod ARR {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
#[repr(C)]
pub struct RegisterBlock {
/// control register 1
pub CR1: RWRegister<u32>,
/// control register 2
pub CR2: RWRegister<u32>,
_reserved1: [u32; 1],
/// DMA/Interrupt enable register
pub DIER: RWRegister<u32>,
/// status register
pub SR: RWRegister<u32>,
/// event generation register
pub EGR: WORegister<u32>,
_reserved2: [u32; 3],
/// counter
pub CNT: RWRegister<u32>,
/// prescaler
pub PSC: RWRegister<u32>,
/// auto-reload register
pub ARR: RWRegister<u32>,
}
pub struct ResetValues {
pub CR1: u32,
pub CR2: u32,
pub DIER: u32,
pub SR: u32,
pub EGR: u32,
pub CNT: u32,
pub PSC: u32,
pub ARR: u32,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
pub(crate) addr: u32,
pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
type Target = RegisterBlock;
#[inline(always)]
fn deref(&self) -> &RegisterBlock {
unsafe { &*(self.addr as *const _) }
}
}
#[cfg(feature = "rtic")]
unsafe impl Send for Instance {}