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#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! Processor features
//!
//! Used by: stm32h743, stm32h743v, stm32h747cm4, stm32h747cm7, stm32h753, stm32h753v, stm32h7b3
use crate::RORegister;
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;
/// Cache Level ID register
pub mod CLIDR {
/// CL1
pub mod CL1 {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (3 bits: 0b111 << 0)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CL2
pub mod CL2 {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (3 bits: 0b111 << 3)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CL3
pub mod CL3 {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (3 bits: 0b111 << 6)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CL4
pub mod CL4 {
/// Offset (9 bits)
pub const offset: u32 = 9;
/// Mask (3 bits: 0b111 << 9)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CL5
pub mod CL5 {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (3 bits: 0b111 << 12)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CL6
pub mod CL6 {
/// Offset (15 bits)
pub const offset: u32 = 15;
/// Mask (3 bits: 0b111 << 15)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CL7
pub mod CL7 {
/// Offset (18 bits)
pub const offset: u32 = 18;
/// Mask (3 bits: 0b111 << 18)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// LoUIS
pub mod LoUIS {
/// Offset (21 bits)
pub const offset: u32 = 21;
/// Mask (3 bits: 0b111 << 21)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// LoC
pub mod LoC {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (3 bits: 0b111 << 24)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// LoU
pub mod LoU {
/// Offset (27 bits)
pub const offset: u32 = 27;
/// Mask (3 bits: 0b111 << 27)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Cache Type register
pub mod CTR {
/// IminLine
pub mod _IminLine {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// DMinLine
pub mod DMinLine {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (4 bits: 0b1111 << 16)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// ERG
pub mod ERG {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (4 bits: 0b1111 << 20)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// CWG
pub mod CWG {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (4 bits: 0b1111 << 24)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Format
pub mod Format {
/// Offset (29 bits)
pub const offset: u32 = 29;
/// Mask (3 bits: 0b111 << 29)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Cache Size ID register
pub mod CCSIDR {
/// LineSize
pub mod LineSize {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (3 bits: 0b111 << 0)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Associativity
pub mod Associativity {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (10 bits: 0x3ff << 3)
pub const mask: u32 = 0x3ff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// NumSets
pub mod NumSets {
/// Offset (13 bits)
pub const offset: u32 = 13;
/// Mask (15 bits: 0x7fff << 13)
pub const mask: u32 = 0x7fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WA
pub mod WA {
/// Offset (28 bits)
pub const offset: u32 = 28;
/// Mask (1 bit: 1 << 28)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RA
pub mod RA {
/// Offset (29 bits)
pub const offset: u32 = 29;
/// Mask (1 bit: 1 << 29)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WB
pub mod WB {
/// Offset (30 bits)
pub const offset: u32 = 30;
/// Mask (1 bit: 1 << 30)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// WT
pub mod WT {
/// Offset (31 bits)
pub const offset: u32 = 31;
/// Mask (1 bit: 1 << 31)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
#[repr(C)]
pub struct RegisterBlock {
/// Cache Level ID register
pub CLIDR: RORegister<u32>,
/// Cache Type register
pub CTR: RORegister<u32>,
/// Cache Size ID register
pub CCSIDR: RORegister<u32>,
}
pub struct ResetValues {
pub CLIDR: u32,
pub CTR: u32,
pub CCSIDR: u32,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
pub(crate) addr: u32,
pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
type Target = RegisterBlock;
#[inline(always)]
fn deref(&self) -> &RegisterBlock {
unsafe { &*(self.addr as *const _) }
}
}
#[cfg(feature = "rtic")]
unsafe impl Send for Instance {}