#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! RTC
//!
//! Used by: stm32h743, stm32h743v, stm32h747cm7, stm32h753, stm32h753v, stm32h7b3
use crate::{RORegister, RWRegister, WORegister};
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;
/// The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub mod TR {
/// Second units in BCD format
pub mod SU {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Second tens in BCD format
pub mod ST {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (3 bits: 0b111 << 4)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Minute units in BCD format
pub mod MNU {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (4 bits: 0b1111 << 8)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Minute tens in BCD format
pub mod MNT {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (3 bits: 0b111 << 12)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Hour units in BCD format
pub mod HU {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (4 bits: 0b1111 << 16)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Hour tens in BCD format
pub mod HT {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (2 bits: 0b11 << 20)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// AM/PM notation
pub mod PM {
/// Offset (22 bits)
pub const offset: u32 = 22;
/// Mask (1 bit: 1 << 22)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: AM or 24-hour format
pub const AM: u32 = 0b0;
/// 0b1: PM
pub const PM: u32 = 0b1;
}
}
}
/// The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub mod DR {
/// Date units in BCD format
pub mod DU {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Date tens in BCD format
pub mod DT {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (2 bits: 0b11 << 4)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Month units in BCD format
pub mod MU {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (4 bits: 0b1111 << 8)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Month tens in BCD format
pub mod MT {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (1 bit: 1 << 12)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Week day units
pub mod WDU {
/// Offset (13 bits)
pub const offset: u32 = 13;
/// Mask (3 bits: 0b111 << 13)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Year units in BCD format
pub mod YU {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (4 bits: 0b1111 << 16)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Year tens in BCD format
pub mod YT {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (4 bits: 0b1111 << 20)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// RTC control register
pub mod CR {
/// Wakeup clock selection
pub mod WUCKSEL {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (3 bits: 0b111 << 0)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b000: RTC/16 clock is selected
pub const Div16: u32 = 0b000;
/// 0b001: RTC/8 clock is selected
pub const Div8: u32 = 0b001;
/// 0b010: RTC/4 clock is selected
pub const Div4: u32 = 0b010;
/// 0b011: RTC/2 clock is selected
pub const Div2: u32 = 0b011;
/// 0b100: ck_spre (usually 1 Hz) clock is selected
pub const ClockSpare: u32 = 0b100;
/// 0b110: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
pub const ClockSpareWithOffset: u32 = 0b110;
}
}
/// Time-stamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
pub mod TSEDGE {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: RTC_TS input rising edge generates a time-stamp event
pub const RisingEdge: u32 = 0b0;
/// 0b1: RTC_TS input falling edge generates a time-stamp event
pub const FallingEdge: u32 = 0b1;
}
}
/// RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF.
pub mod REFCKON {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: RTC_REFIN detection disabled
pub const Disabled: u32 = 0b0;
/// 0b1: RTC_REFIN detection enabled
pub const Enabled: u32 = 0b1;
}
}
/// Bypass the shadow registers Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
pub mod BYPSHAD {
/// Offset (5 bits)
pub const offset: u32 = 5;
/// Mask (1 bit: 1 << 5)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
pub const ShadowReg: u32 = 0b0;
/// 0b1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
pub const BypassShadowReg: u32 = 0b1;
}
}
/// Hour format
pub mod FMT {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (1 bit: 1 << 6)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: 24 hour/day format
pub const Twenty_Four_Hour: u32 = 0b0;
/// 0b1: AM/PM hour format
pub const AM_PM: u32 = 0b1;
}
}
/// Alarm A enable
pub mod ALRAE {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (1 bit: 1 << 8)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Alarm A disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Alarm A enabled
pub const Enabled: u32 = 0b1;
}
}
/// Alarm B enable
pub mod ALRBE {
/// Offset (9 bits)
pub const offset: u32 = 9;
/// Mask (1 bit: 1 << 9)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Alarm B disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Alarm B enabled
pub const Enabled: u32 = 0b1;
}
}
/// Wakeup timer enable
pub mod WUTE {
/// Offset (10 bits)
pub const offset: u32 = 10;
/// Mask (1 bit: 1 << 10)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Wakeup timer disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Wakeup timer enabled
pub const Enabled: u32 = 0b1;
}
}
/// timestamp enable
pub mod TSE {
/// Offset (11 bits)
pub const offset: u32 = 11;
/// Mask (1 bit: 1 << 11)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Timestamp disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Timestamp enabled
pub const Enabled: u32 = 0b1;
}
}
/// Alarm A interrupt enable
pub mod ALRAIE {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (1 bit: 1 << 12)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Alarm A interrupt disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Alarm A interrupt enabled
pub const Enabled: u32 = 0b1;
}
}
/// Alarm B interrupt enable
pub mod ALRBIE {
/// Offset (13 bits)
pub const offset: u32 = 13;
/// Mask (1 bit: 1 << 13)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Alarm B Interrupt disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Alarm B Interrupt enabled
pub const Enabled: u32 = 0b1;
}
}
/// Wakeup timer interrupt enable
pub mod WUTIE {
/// Offset (14 bits)
pub const offset: u32 = 14;
/// Mask (1 bit: 1 << 14)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Wakeup timer interrupt disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Wakeup timer interrupt enabled
pub const Enabled: u32 = 0b1;
}
}
/// Time-stamp interrupt enable
pub mod TSIE {
/// Offset (15 bits)
pub const offset: u32 = 15;
/// Mask (1 bit: 1 << 15)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Time-stamp Interrupt disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Time-stamp Interrupt enabled
pub const Enabled: u32 = 0b1;
}
}
/// Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.
pub mod ADD1H {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (1 bit: 1 << 16)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values
pub mod W {
/// 0b1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
pub const Add1: u32 = 0b1;
}
/// Read-write values (empty)
pub mod RW {}
}
/// Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0.
pub mod SUB1H {
/// Offset (17 bits)
pub const offset: u32 = 17;
/// Mask (1 bit: 1 << 17)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values
pub mod W {
/// 0b1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
pub const Sub1: u32 = 0b1;
}
/// Read-write values (empty)
pub mod RW {}
}
/// Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
pub mod BKP {
/// Offset (18 bits)
pub const offset: u32 = 18;
/// Mask (1 bit: 1 << 18)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Daylight Saving Time change has not been performed
pub const DST_Not_Changed: u32 = 0b0;
/// 0b1: Daylight Saving Time change has been performed
pub const DST_Changed: u32 = 0b1;
}
}
/// Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section24.3.15: Calibration clock output
pub mod COSEL {
/// Offset (19 bits)
pub const offset: u32 = 19;
/// Mask (1 bit: 1 << 19)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Calibration output is 512 Hz (with default prescaler setting)
pub const CalFreq_512Hz: u32 = 0b0;
/// 0b1: Calibration output is 1 Hz (with default prescaler setting)
pub const CalFreq_1Hz: u32 = 0b1;
}
}
/// Output polarity This bit is used to configure the polarity of RTC_ALARM output
pub mod POL {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (1 bit: 1 << 20)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
pub const High: u32 = 0b0;
/// 0b1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
pub const Low: u32 = 0b1;
}
}
/// Output selection These bits are used to select the flag to be routed to RTC_ALARM output
pub mod OSEL {
/// Offset (21 bits)
pub const offset: u32 = 21;
/// Mask (2 bits: 0b11 << 21)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b00: Output disabled
pub const Disabled: u32 = 0b00;
/// 0b01: Alarm A output enabled
pub const AlarmA: u32 = 0b01;
/// 0b10: Alarm B output enabled
pub const AlarmB: u32 = 0b10;
/// 0b11: Wakeup output enabled
pub const Wakeup: u32 = 0b11;
}
}
/// Calibration output enable This bit enables the RTC_CALIB output
pub mod COE {
/// Offset (23 bits)
pub const offset: u32 = 23;
/// Mask (1 bit: 1 << 23)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Calibration output disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Calibration output enabled
pub const Enabled: u32 = 0b1;
}
}
/// timestamp on internal event enable
pub mod ITSE {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (1 bit: 1 << 24)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Internal event timestamp is disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Internal event timestamp is enabled
pub const Enabled: u32 = 0b1;
}
}
}
/// This register is write protected (except for RTC_ISR\[13:8\] bits). The write access procedure is described in RTC register write protection on page9.
pub mod ISR {
/// Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
pub mod ALRAWF {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: Alarm update not allowed
pub const UpdateNotAllowed: u32 = 0b0;
/// 0b1: Alarm update allowed
pub const UpdateAllowed: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Alarm B write flag This bit is set by hardware when Alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
pub mod ALRBWF {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
pub use super::ALRAWF::R;
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Wakeup timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set.
pub mod WUTWF {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: Wakeup timer configuration update not allowed
pub const UpdateNotAllowed: u32 = 0b0;
/// 0b1: Wakeup timer configuration update allowed
pub const UpdateAllowed: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.
pub mod SHPF {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: No shift operation is pending
pub const NoShiftPending: u32 = 0b0;
/// 0b1: A shift operation is pending
pub const ShiftPending: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state).
pub mod INITS {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: Calendar has not been initialized
pub const NotInitalized: u32 = 0b0;
/// 0b1: Calendar has been initialized
pub const Initalized: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
pub mod RSF {
/// Offset (5 bits)
pub const offset: u32 = 5;
/// Mask (1 bit: 1 << 5)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: Calendar shadow registers not yet synchronized
pub const NotSynced: u32 = 0b0;
/// 0b1: Calendar shadow registers synchronized
pub const Synced: u32 = 0b1;
}
/// Write-only values
pub mod W {
/// 0b0: This flag is cleared by software by writing 0
pub const Clear: u32 = 0b0;
}
/// Read-write values (empty)
pub mod RW {}
}
/// Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.
pub mod INITF {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (1 bit: 1 << 6)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: Calendar registers update is not allowed
pub const NotAllowed: u32 = 0b0;
/// 0b1: Calendar registers update is allowed
pub const Allowed: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Initialization mode
pub mod INIT {
/// Offset (7 bits)
pub const offset: u32 = 7;
/// Mask (1 bit: 1 << 7)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Free running mode
pub const FreeRunningMode: u32 = 0b0;
/// 0b1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
pub const InitMode: u32 = 0b1;
}
}
/// Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0.
pub mod ALRAF {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (1 bit: 1 << 8)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b1: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
pub const Match: u32 = 0b1;
}
pub use super::RSF::W;
/// Read-write values (empty)
pub mod RW {}
}
/// Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). This flag is cleared by software by writing 0.
pub mod ALRBF {
/// Offset (9 bits)
pub const offset: u32 = 9;
/// Mask (1 bit: 1 << 9)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b1: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)
pub const Match: u32 = 0b1;
}
pub use super::RSF::W;
/// Read-write values (empty)
pub mod RW {}
}
/// Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.
pub mod WUTF {
/// Offset (10 bits)
pub const offset: u32 = 10;
/// Mask (1 bit: 1 << 10)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b1: This flag is set by hardware when the wakeup auto-reload counter reaches 0
pub const Zero: u32 = 0b1;
}
pub use super::RSF::W;
/// Read-write values (empty)
pub mod RW {}
}
/// Time-stamp flag This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0.
pub mod TSF {
/// Offset (11 bits)
pub const offset: u32 = 11;
/// Mask (1 bit: 1 << 11)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b1: This flag is set by hardware when a time-stamp event occurs
pub const TimestampEvent: u32 = 0b1;
}
pub use super::RSF::W;
/// Read-write values (empty)
pub mod RW {}
}
/// Time-stamp overflow flag This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a time-stamp event occurs immediately before the TSF bit is cleared.
pub mod TSOVF {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (1 bit: 1 << 12)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b1: This flag is set by hardware when a time-stamp event occurs while TSF is already set
pub const Overflow: u32 = 0b1;
}
pub use super::RSF::W;
/// Read-write values (empty)
pub mod RW {}
}
/// RTC_TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0
pub mod TAMP1F {
/// Offset (13 bits)
pub const offset: u32 = 13;
/// Mask (1 bit: 1 << 13)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b1: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
pub const Tampered: u32 = 0b1;
}
/// Write-only values
pub mod W {
/// 0b0: Flag cleared by software writing 0
pub const Clear: u32 = 0b0;
}
/// Read-write values (empty)
pub mod RW {}
}
/// RTC_TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input. It is cleared by software writing 0
pub mod TAMP2F {
/// Offset (14 bits)
pub const offset: u32 = 14;
/// Mask (1 bit: 1 << 14)
pub const mask: u32 = 1 << offset;
pub use super::TAMP1F::R;
pub use super::TAMP1F::W;
/// Read-write values (empty)
pub mod RW {}
}
/// RTC_TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input. It is cleared by software writing 0
pub mod TAMP3F {
/// Offset (15 bits)
pub const offset: u32 = 15;
/// Mask (1 bit: 1 << 15)
pub const mask: u32 = 1 << offset;
pub use super::TAMP1F::R;
pub use super::TAMP1F::W;
/// Read-write values (empty)
pub mod RW {}
}
/// Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly.
pub mod RECALPF {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (1 bit: 1 << 16)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b1: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
pub const Pending: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Internal tTime-stamp flag
pub mod ITSF {
/// Offset (17 bits)
pub const offset: u32 = 17;
/// Mask (1 bit: 1 << 17)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b1: This flag is set by hardware when a time-stamp on the internal event occurs
pub const Match: u32 = 0b1;
}
/// Write-only values
pub mod W {
/// 0b0: This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits
pub const Clear: u32 = 0b0;
}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub mod PRER {
/// Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
pub mod PREDIV_S {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (15 bits: 0x7fff << 0)
pub const mask: u32 = 0x7fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
pub mod PREDIV_A {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (7 bits: 0x7f << 16)
pub const mask: u32 = 0x7f << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub mod WUTR {
/// Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT\[15:0\] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL\[2:0\] bits of the RTC_CR register When WUCKSEL\[2\] = 1, the wakeup timer becomes 17-bits and WUCKSEL\[1\] effectively becomes WUT\[16\] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT\[15:0\] to 0x0000 with WUCKSEL\[2:0\] =011 (RTCCLK/2) is forbidden.
pub mod WUT {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub mod ALRMAR {
/// Second units in BCD format.
pub mod SU {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Second tens in BCD format.
pub mod ST {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (3 bits: 0b111 << 4)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Alarm A seconds mask
pub mod MSK1 {
/// Offset (7 bits)
pub const offset: u32 = 7;
/// Mask (1 bit: 1 << 7)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Alarm set if the date/day match
pub const Mask: u32 = 0b0;
/// 0b1: Date/day don’t care in Alarm comparison
pub const NotMask: u32 = 0b1;
}
}
/// Minute units in BCD format.
pub mod MNU {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (4 bits: 0b1111 << 8)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Minute tens in BCD format.
pub mod MNT {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (3 bits: 0b111 << 12)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Alarm A minutes mask
pub mod MSK2 {
/// Offset (15 bits)
pub const offset: u32 = 15;
/// Mask (1 bit: 1 << 15)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
pub use super::MSK1::RW;
}
/// Hour units in BCD format.
pub mod HU {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (4 bits: 0b1111 << 16)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Hour tens in BCD format.
pub mod HT {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (2 bits: 0b11 << 20)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// AM/PM notation
pub mod PM {
/// Offset (22 bits)
pub const offset: u32 = 22;
/// Mask (1 bit: 1 << 22)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: AM or 24-hour format
pub const AM: u32 = 0b0;
/// 0b1: PM
pub const PM: u32 = 0b1;
}
}
/// Alarm A hours mask
pub mod MSK3 {
/// Offset (23 bits)
pub const offset: u32 = 23;
/// Mask (1 bit: 1 << 23)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
pub use super::MSK1::RW;
}
/// Date units or day in BCD format.
pub mod DU {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (4 bits: 0b1111 << 24)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Date tens in BCD format.
pub mod DT {
/// Offset (28 bits)
pub const offset: u32 = 28;
/// Mask (2 bits: 0b11 << 28)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Week day selection
pub mod WDSEL {
/// Offset (30 bits)
pub const offset: u32 = 30;
/// Mask (1 bit: 1 << 30)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: DU\[3:0\] represents the date units
pub const DateUnits: u32 = 0b0;
/// 0b1: DU\[3:0\] represents the week day. DT\[1:0\] is don’t care.
pub const WeekDay: u32 = 0b1;
}
}
/// Alarm A date mask
pub mod MSK4 {
/// Offset (31 bits)
pub const offset: u32 = 31;
/// Mask (1 bit: 1 << 31)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
pub use super::MSK1::RW;
}
}
/// This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub mod ALRMBR {
pub use super::ALRMAR::DT;
pub use super::ALRMAR::DU;
pub use super::ALRMAR::HT;
pub use super::ALRMAR::HU;
pub use super::ALRMAR::MNT;
pub use super::ALRMAR::MNU;
pub use super::ALRMAR::MSK1;
pub use super::ALRMAR::MSK2;
pub use super::ALRMAR::MSK3;
pub use super::ALRMAR::MSK4;
pub use super::ALRMAR::PM;
pub use super::ALRMAR::ST;
pub use super::ALRMAR::SU;
pub use super::ALRMAR::WDSEL;
}
/// RTC write protection register
pub mod WPR {
/// Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection.
pub mod KEY {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (8 bits: 0xff << 0)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// RTC sub second register
pub mod SSR {
/// Sub second value SS\[15:0\] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR.
pub mod SS {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (16 bits: 0xffff << 0)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub mod SHIFTR {
/// Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time.
pub mod SUBFS {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (15 bits: 0x7fff << 0)
pub const mask: u32 = 0x7fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.
pub mod ADD1S {
/// Offset (31 bits)
pub const offset: u32 = 31;
/// Mask (1 bit: 1 << 31)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values
pub mod W {
/// 0b1: Add one second to the clock/calendar
pub const Add1: u32 = 0b1;
}
/// Read-write values (empty)
pub mod RW {}
}
}
/// The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
pub mod TSTR {
/// Second units in BCD format.
pub mod SU {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Second tens in BCD format.
pub mod ST {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (3 bits: 0b111 << 4)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Minute units in BCD format.
pub mod MNU {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (4 bits: 0b1111 << 8)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Minute tens in BCD format.
pub mod MNT {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (3 bits: 0b111 << 12)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Hour units in BCD format.
pub mod HU {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (4 bits: 0b1111 << 16)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Hour tens in BCD format.
pub mod HT {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (2 bits: 0b11 << 20)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// AM/PM notation
pub mod PM {
/// Offset (22 bits)
pub const offset: u32 = 22;
/// Mask (1 bit: 1 << 22)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
pub mod TSDR {
/// Date units in BCD format
pub mod DU {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Date tens in BCD format
pub mod DT {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (2 bits: 0b11 << 4)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Month units in BCD format
pub mod MU {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (4 bits: 0b1111 << 8)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Month tens in BCD format
pub mod MT {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (1 bit: 1 << 12)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Week day units
pub mod WDU {
/// Offset (13 bits)
pub const offset: u32 = 13;
/// Mask (3 bits: 0b111 << 13)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset.
pub mod TSSSR {
pub use super::SSR::SS;
}
/// This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub mod CALR {
/// Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section24.3.12: RTC smooth digital calibration on page13.
pub mod CALM {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (9 bits: 0x1ff << 0)
pub const mask: u32 = 0x1ff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. Note: CALM\[0\] is stuck at 0 when CALW16= 1. Refer to Section24.3.12: RTC smooth digital calibration.
pub mod CALW16 {
/// Offset (13 bits)
pub const offset: u32 = 13;
/// Mask (1 bit: 1 << 13)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b1: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1
pub const Sixteen_Second: u32 = 0b1;
}
}
/// Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM\[1:0\] are stuck at 00; when CALW8= 1. Refer to Section24.3.12: RTC smooth digital calibration.
pub mod CALW8 {
/// Offset (14 bits)
pub const offset: u32 = 14;
/// Mask (1 bit: 1 << 14)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b1: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected
pub const Eight_Second: u32 = 0b1;
}
}
/// Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. Refer to Section24.3.12: RTC smooth digital calibration.
pub mod CALP {
/// Offset (15 bits)
pub const offset: u32 = 15;
/// Mask (1 bit: 1 << 15)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: No RTCCLK pulses are added
pub const NoChange: u32 = 0b0;
/// 0b1: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
pub const IncreaseFreq: u32 = 0b1;
}
}
}
/// RTC tamper and alternate function configuration register
pub mod TAMPCR {
/// RTC_TAMP1 input detection enable
pub mod TAMP1E {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Active level for RTC_TAMP1 input If TAMPFLT != 00 if TAMPFLT = 00:
pub mod TAMP1TRG {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Tamper interrupt enable
pub mod TAMPIE {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RTC_TAMP2 input detection enable
pub mod TAMP2E {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Active level for RTC_TAMP2 input if TAMPFLT != 00: if TAMPFLT = 00:
pub mod TAMP2TRG {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RTC_TAMP3 detection enable
pub mod TAMP3E {
/// Offset (5 bits)
pub const offset: u32 = 5;
/// Mask (1 bit: 1 << 5)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Active level for RTC_TAMP3 input if TAMPFLT != 00: if TAMPFLT = 00:
pub mod TAMP3TRG {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (1 bit: 1 << 6)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Activate timestamp on tamper detection event TAMPTS is valid even if TSE=0 in the RTC_CR register.
pub mod TAMPTS {
/// Offset (7 bits)
pub const offset: u32 = 7;
/// Mask (1 bit: 1 << 7)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Tamper sampling frequency Determines the frequency at which each of the RTC_TAMPx inputs are sampled.
pub mod TAMPFREQ {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (3 bits: 0b111 << 8)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RTC_TAMPx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs.
pub mod TAMPFLT {
/// Offset (11 bits)
pub const offset: u32 = 11;
/// Mask (2 bits: 0b11 << 11)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs.
pub mod TAMPPRCH {
/// Offset (13 bits)
pub const offset: u32 = 13;
/// Mask (2 bits: 0b11 << 13)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RTC_TAMPx pull-up disable This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample.
pub mod TAMPPUDIS {
/// Offset (15 bits)
pub const offset: u32 = 15;
/// Mask (1 bit: 1 << 15)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Tamper 1 interrupt enable
pub mod TAMP1IE {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (1 bit: 1 << 16)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Tamper 1 no erase
pub mod TAMP1NOERASE {
/// Offset (17 bits)
pub const offset: u32 = 17;
/// Mask (1 bit: 1 << 17)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Tamper 1 mask flag
pub mod TAMP1MF {
/// Offset (18 bits)
pub const offset: u32 = 18;
/// Mask (1 bit: 1 << 18)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Tamper 2 interrupt enable
pub mod TAMP2IE {
/// Offset (19 bits)
pub const offset: u32 = 19;
/// Mask (1 bit: 1 << 19)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Tamper 2 no erase
pub mod TAMP2NOERASE {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (1 bit: 1 << 20)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Tamper 2 mask flag
pub mod TAMP2MF {
/// Offset (21 bits)
pub const offset: u32 = 21;
/// Mask (1 bit: 1 << 21)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Tamper 3 interrupt enable
pub mod TAMP3IE {
/// Offset (22 bits)
pub const offset: u32 = 22;
/// Mask (1 bit: 1 << 22)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Tamper 3 no erase
pub mod TAMP3NOERASE {
/// Offset (23 bits)
pub const offset: u32 = 23;
/// Mask (1 bit: 1 << 23)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Tamper 3 mask flag
pub mod TAMP3MF {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (1 bit: 1 << 24)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9
pub mod ALRMASSR {
/// Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
pub mod SS {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (15 bits: 0x7fff << 0)
pub const mask: u32 = 0x7fff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.
pub mod MASKSS {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (4 bits: 0b1111 << 24)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection.
pub mod ALRMBSSR {
pub use super::ALRMASSR::MASKSS;
pub use super::ALRMASSR::SS;
}
/// RTC backup registers
pub mod BKP0R {
/// The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
pub mod BKP {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (32 bits: 0xffffffff << 0)
pub const mask: u32 = 0xffffffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// RTC backup registers
pub mod BKP1R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP2R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP3R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP4R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP5R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP6R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP7R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP8R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP9R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP10R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP11R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP12R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP13R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP14R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP15R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP16R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP17R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP18R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP19R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP20R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP21R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP22R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP23R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP24R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP25R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP26R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP27R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP28R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP29R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP30R {
pub use super::BKP0R::BKP;
}
/// RTC backup registers
pub mod BKP31R {
pub use super::BKP0R::BKP;
}
/// RTC option register
pub mod OR {
/// RTC_ALARM output type on PC13
pub mod RTC_ALARM_TYPE {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// RTC_OUT remap
pub mod RTC_OUT_RMP {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
#[repr(C)]
pub struct RegisterBlock {
/// The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub TR: RWRegister<u32>,
/// The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub DR: RWRegister<u32>,
/// RTC control register
pub CR: RWRegister<u32>,
/// This register is write protected (except for RTC_ISR\[13:8\] bits). The write access procedure is described in RTC register write protection on page9.
pub ISR: RWRegister<u32>,
/// This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub PRER: RWRegister<u32>,
/// This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub WUTR: RWRegister<u32>,
_reserved1: [u32; 1],
/// This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub ALRMAR: RWRegister<u32>,
/// This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub ALRMBR: RWRegister<u32>,
/// RTC write protection register
pub WPR: WORegister<u32>,
/// RTC sub second register
pub SSR: RORegister<u32>,
/// This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub SHIFTR: WORegister<u32>,
/// The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
pub TSTR: RORegister<u32>,
/// The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
pub TSDR: RORegister<u32>,
/// The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset.
pub TSSSR: RORegister<u32>,
/// This register is write protected. The write access procedure is described in RTC register write protection on page9.
pub CALR: RWRegister<u32>,
/// RTC tamper and alternate function configuration register
pub TAMPCR: RWRegister<u32>,
/// This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9
pub ALRMASSR: RWRegister<u32>,
/// This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection.
pub ALRMBSSR: RWRegister<u32>,
/// RTC option register
pub OR: RWRegister<u32>,
/// RTC backup registers
pub BKP0R: RWRegister<u32>,
/// RTC backup registers
pub BKP1R: RWRegister<u32>,
/// RTC backup registers
pub BKP2R: RWRegister<u32>,
/// RTC backup registers
pub BKP3R: RWRegister<u32>,
/// RTC backup registers
pub BKP4R: RWRegister<u32>,
/// RTC backup registers
pub BKP5R: RWRegister<u32>,
/// RTC backup registers
pub BKP6R: RWRegister<u32>,
/// RTC backup registers
pub BKP7R: RWRegister<u32>,
/// RTC backup registers
pub BKP8R: RWRegister<u32>,
/// RTC backup registers
pub BKP9R: RWRegister<u32>,
/// RTC backup registers
pub BKP10R: RWRegister<u32>,
/// RTC backup registers
pub BKP11R: RWRegister<u32>,
/// RTC backup registers
pub BKP12R: RWRegister<u32>,
/// RTC backup registers
pub BKP13R: RWRegister<u32>,
/// RTC backup registers
pub BKP14R: RWRegister<u32>,
/// RTC backup registers
pub BKP15R: RWRegister<u32>,
/// RTC backup registers
pub BKP16R: RWRegister<u32>,
/// RTC backup registers
pub BKP17R: RWRegister<u32>,
/// RTC backup registers
pub BKP18R: RWRegister<u32>,
/// RTC backup registers
pub BKP19R: RWRegister<u32>,
/// RTC backup registers
pub BKP20R: RWRegister<u32>,
/// RTC backup registers
pub BKP21R: RWRegister<u32>,
/// RTC backup registers
pub BKP22R: RWRegister<u32>,
/// RTC backup registers
pub BKP23R: RWRegister<u32>,
/// RTC backup registers
pub BKP24R: RWRegister<u32>,
/// RTC backup registers
pub BKP25R: RWRegister<u32>,
/// RTC backup registers
pub BKP26R: RWRegister<u32>,
/// RTC backup registers
pub BKP27R: RWRegister<u32>,
/// RTC backup registers
pub BKP28R: RWRegister<u32>,
/// RTC backup registers
pub BKP29R: RWRegister<u32>,
/// RTC backup registers
pub BKP30R: RWRegister<u32>,
/// RTC backup registers
pub BKP31R: RWRegister<u32>,
}
pub struct ResetValues {
pub TR: u32,
pub DR: u32,
pub CR: u32,
pub ISR: u32,
pub PRER: u32,
pub WUTR: u32,
pub ALRMAR: u32,
pub ALRMBR: u32,
pub WPR: u32,
pub SSR: u32,
pub SHIFTR: u32,
pub TSTR: u32,
pub TSDR: u32,
pub TSSSR: u32,
pub CALR: u32,
pub TAMPCR: u32,
pub ALRMASSR: u32,
pub ALRMBSSR: u32,
pub OR: u32,
pub BKP0R: u32,
pub BKP1R: u32,
pub BKP2R: u32,
pub BKP3R: u32,
pub BKP4R: u32,
pub BKP5R: u32,
pub BKP6R: u32,
pub BKP7R: u32,
pub BKP8R: u32,
pub BKP9R: u32,
pub BKP10R: u32,
pub BKP11R: u32,
pub BKP12R: u32,
pub BKP13R: u32,
pub BKP14R: u32,
pub BKP15R: u32,
pub BKP16R: u32,
pub BKP17R: u32,
pub BKP18R: u32,
pub BKP19R: u32,
pub BKP20R: u32,
pub BKP21R: u32,
pub BKP22R: u32,
pub BKP23R: u32,
pub BKP24R: u32,
pub BKP25R: u32,
pub BKP26R: u32,
pub BKP27R: u32,
pub BKP28R: u32,
pub BKP29R: u32,
pub BKP30R: u32,
pub BKP31R: u32,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
pub(crate) addr: u32,
pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
type Target = RegisterBlock;
#[inline(always)]
fn deref(&self) -> &RegisterBlock {
unsafe { &*(self.addr as *const _) }
}
}
#[cfg(feature = "rtic")]
unsafe impl Send for Instance {}