#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! SAI
//!
//! Used by: stm32h743, stm32h743v, stm32h747cm4, stm32h747cm7, stm32h753, stm32h753v, stm32h7b3
use crate::{RORegister, RWRegister, WORegister};
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;
/// Global configuration register
pub mod GCR {
/// Synchronization outputs These bits are set and cleared by software.
pub mod SYNCOUT {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (2 bits: 0b11 << 4)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Synchronization inputs
pub mod SYNCIN {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (2 bits: 0b11 << 0)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// PDM control register
pub mod PDMCR {
/// PDM enable
pub mod PDMEN {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Number of microphones
pub mod MICNBR {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (2 bits: 0b11 << 4)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Clock enable of bitstream clock number 1
pub mod CKEN1 {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (1 bit: 1 << 8)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Clock enable of bitstream clock number 2
pub mod CKEN2 {
/// Offset (9 bits)
pub const offset: u32 = 9;
/// Mask (1 bit: 1 << 9)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Clock enable of bitstream clock number 3
pub mod CKEN3 {
/// Offset (10 bits)
pub const offset: u32 = 10;
/// Mask (1 bit: 1 << 10)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Clock enable of bitstream clock number 4
pub mod CKEN4 {
/// Offset (11 bits)
pub const offset: u32 = 11;
/// Mask (1 bit: 1 << 11)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// PDM delay register
pub mod PDMDLY {
/// Delay line adjust for first microphone of pair 1
pub mod DLYM1L {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (3 bits: 0b111 << 0)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Delay line adjust for second microphone of pair 1
pub mod DLYM1R {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (3 bits: 0b111 << 4)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Delay line for first microphone of pair 2
pub mod DLYM2L {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (3 bits: 0b111 << 8)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Delay line for second microphone of pair 2
pub mod DLYM2R {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (3 bits: 0b111 << 12)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Delay line for first microphone of pair 3
pub mod DLYM3L {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (3 bits: 0b111 << 16)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Delay line for second microphone of pair 3
pub mod DLYM3R {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (3 bits: 0b111 << 20)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Delay line for first microphone of pair 4
pub mod DLYM4L {
/// Offset (24 bits)
pub const offset: u32 = 24;
/// Mask (3 bits: 0b111 << 24)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Delay line for second microphone of pair 4
pub mod DLYM4R {
/// Offset (28 bits)
pub const offset: u32 = 28;
/// Mask (3 bits: 0b111 << 28)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Configuration register 1
pub mod CR1A {
/// SAIx audio block mode immediately
pub mod MODE {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (2 bits: 0b11 << 0)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b00: Master transmitter
pub const MasterTx: u32 = 0b00;
/// 0b01: Master receiver
pub const MasterRx: u32 = 0b01;
/// 0b10: Slave transmitter
pub const SlaveTx: u32 = 0b10;
/// 0b11: Slave receiver
pub const SlaveRx: u32 = 0b11;
}
}
/// Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled.
pub mod PRTCFG {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (2 bits: 0b11 << 2)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b00: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
pub const Free: u32 = 0b00;
/// 0b01: SPDIF protocol
pub const Spdif: u32 = 0b01;
/// 0b10: AC’97 protocol
pub const Ac97: u32 = 0b10;
}
}
/// Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG\[1:0\]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP\[1:0\] bits, DS\[1:0\] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled.
pub mod DS {
/// Offset (5 bits)
pub const offset: u32 = 5;
/// Mask (3 bits: 0b111 << 5)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b010: 8 bits
pub const Bit8: u32 = 0b010;
/// 0b011: 10 bits
pub const Bit10: u32 = 0b011;
/// 0b100: 16 bits
pub const Bit16: u32 = 0b100;
/// 0b101: 20 bits
pub const Bit20: u32 = 0b101;
/// 0b110: 24 bits
pub const Bit24: u32 = 0b110;
/// 0b111: 32 bits
pub const Bit32: u32 = 0b111;
}
}
/// Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first.
pub mod LSBFIRST {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (1 bit: 1 << 8)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Data are transferred with MSB first
pub const MsbFirst: u32 = 0b0;
/// 0b1: Data are transferred with LSB first
pub const LsbFirst: u32 = 0b1;
}
}
/// Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol.
pub mod CKSTR {
/// Offset (9 bits)
pub const offset: u32 = 9;
/// Mask (1 bit: 1 << 9)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Data strobing edge is falling edge of SCK
pub const FallingEdge: u32 = 0b0;
/// 0b1: Data strobing edge is rising edge of SCK
pub const RisingEdge: u32 = 0b1;
}
}
/// Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.
pub mod SYNCEN {
/// Offset (10 bits)
pub const offset: u32 = 10;
/// Mask (2 bits: 0b11 << 10)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b00: audio sub-block in asynchronous mode
pub const Asynchronous: u32 = 0b00;
/// 0b01: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
pub const Internal: u32 = 0b01;
/// 0b10: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
pub const External: u32 = 0b10;
}
}
/// Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details.
pub mod MONO {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (1 bit: 1 << 12)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Stereo mode
pub const Stereo: u32 = 0b0;
/// 0b1: Mono mode
pub const Mono: u32 = 0b1;
}
}
/// Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration.
pub mod OUTDRIV {
/// Offset (13 bits)
pub const offset: u32 = 13;
/// Mask (1 bit: 1 << 13)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Audio block output driven when SAIEN is set
pub const OnStart: u32 = 0b0;
/// 0b1: Audio block output driven immediately after the setting of this bit
pub const Immediately: u32 = 0b1;
}
}
/// Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit.
pub mod SAIEN {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (1 bit: 1 << 16)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: SAI audio block disabled
pub const Disabled: u32 = 0b0;
/// 0b1: SAI audio block enabled
pub const Enabled: u32 = 0b1;
}
}
/// DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE\[1:0\] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode.
pub mod DMAEN {
/// Offset (17 bits)
pub const offset: u32 = 17;
/// Mask (1 bit: 1 << 17)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: DMA disabled
pub const Disabled: u32 = 0b0;
/// 0b1: DMA enabled
pub const Enabled: u32 = 0b1;
}
}
/// No divider
pub mod NODIV {
/// Offset (19 bits)
pub const offset: u32 = 19;
/// Mask (1 bit: 1 << 19)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Master clock generator is enabled
pub const MasterClock: u32 = 0b0;
/// 0b1: No divider used in the clock generator (in this case Master Clock Divider bit has no effect)
pub const NoDiv: u32 = 0b1;
}
}
/// Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:
pub mod MCKDIV {
/// Offset (20 bits)
pub const offset: u32 = 20;
/// Mask (6 bits: 0x3f << 20)
pub const mask: u32 = 0x3f << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Oversampling ratio for master clock
pub mod OSR {
/// Offset (26 bits)
pub const offset: u32 = 26;
/// Mask (1 bit: 1 << 26)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Master clock generation enable
pub mod MCKEN {
/// Offset (27 bits)
pub const offset: u32 = 27;
/// Mask (1 bit: 1 << 27)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Configuration register 2
pub mod CR2A {
/// FIFO threshold. This bit is set and cleared by software.
pub mod FTH {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (3 bits: 0b111 << 0)
pub const mask: u32 = 0b111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b000: FIFO empty
pub const Empty: u32 = 0b000;
/// 0b001: 1⁄4 FIFO
pub const Quarter1: u32 = 0b001;
/// 0b010: 1⁄2 FIFO
pub const Quarter2: u32 = 0b010;
/// 0b011: 3⁄4 FIFO
pub const Quarter3: u32 = 0b011;
/// 0b100: FIFO full
pub const Full: u32 = 0b100;
}
}
/// FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled.
pub mod FFLUSH {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: No FIFO flush
pub const NoFlush: u32 = 0b0;
/// 0b1: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
pub const Flush: u32 = 0b1;
}
}
/// Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details.
pub mod TRIS {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.
pub mod MUTE {
/// Offset (5 bits)
pub const offset: u32 = 5;
/// Mask (1 bit: 1 << 5)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: No mute mode
pub const Disabled: u32 = 0b0;
/// 0b1: Mute mode enabled
pub const Enabled: u32 = 0b1;
}
}
/// Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.
pub mod MUTEVAL {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (1 bit: 1 << 6)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Bit value 0 is sent during the mute mode
pub const SendZero: u32 = 0b0;
/// 0b1: Last values are sent during the mute mode
pub const SendLast: u32 = 0b1;
}
}
/// Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details.
pub mod MUTECNT {
/// Offset (7 bits)
pub const offset: u32 = 7;
/// Mask (6 bits: 0x3f << 7)
pub const mask: u32 = 0x3f << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm.
pub mod CPL {
/// Offset (13 bits)
pub const offset: u32 = 13;
/// Mask (1 bit: 1 << 13)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: 1’s complement representation
pub const OnesComplement: u32 = 0b0;
/// 0b1: 2’s complement representation
pub const TwosComplement: u32 = 0b1;
}
}
/// Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE\[0\]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected.
pub mod COMP {
/// Offset (14 bits)
pub const offset: u32 = 14;
/// Mask (2 bits: 0b11 << 14)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b00: No companding algorithm
pub const NoCompanding: u32 = 0b00;
/// 0b10: μ-Law algorithm
pub const MuLaw: u32 = 0b10;
/// 0b11: A-Law algorithm
pub const ALaw: u32 = 0b11;
}
}
}
/// This register has no meaning in AC97 and SPDIF audio protocol
pub mod FRCRA {
/// Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL\[7:0\] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT\[4:0\] of SAI_xSLOTR register (NBSLOT\[3:0\] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration.
pub mod FRL {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (8 bits: 0xff << 0)
pub const mask: u32 = 0xff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL\[6:0\] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled.
pub mod FSALL {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (7 bits: 0x7f << 8)
pub const mask: u32 = 0x7f << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled.
pub mod FSDEF {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (1 bit: 1 << 16)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.
pub mod FSPOL {
/// Offset (17 bits)
pub const offset: u32 = 17;
/// Mask (1 bit: 1 << 17)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: FS is active low (falling edge)
pub const FallingEdge: u32 = 0b0;
/// 0b1: FS is active high (rising edge)
pub const RisingEdge: u32 = 0b1;
}
}
/// Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.
pub mod FSOFF {
/// Offset (18 bits)
pub const offset: u32 = 18;
/// Mask (1 bit: 1 << 18)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: FS is asserted on the first bit of the slot 0
pub const OnFirst: u32 = 0b0;
/// 0b1: FS is asserted one bit before the first bit of the slot 0
pub const BeforeFirst: u32 = 0b1;
}
}
}
/// This register has no meaning in AC97 and SPDIF audio protocol
pub mod SLOTRA {
/// First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.
pub mod FBOFF {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (5 bits: 0b11111 << 0)
pub const mask: u32 = 0b11111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.
pub mod SLOTSZ {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (2 bits: 0b11 << 6)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b00: The slot size is equivalent to the data size (specified in DS\[3:0\] in the SAI_xCR1 register)
pub const DataSize: u32 = 0b00;
/// 0b01: 16-bit
pub const Bit16: u32 = 0b01;
/// 0b10: 32-bit
pub const Bit32: u32 = 0b10;
}
}
/// Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode.
pub mod NBSLOT {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (4 bits: 0b1111 << 8)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode.
pub mod SLOTEN {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (16 bits: 0xffff << 16)
pub const mask: u32 = 0xffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0000000000000000: Inactive slot
pub const Inactive: u32 = 0b0000000000000000;
/// 0b0000000000000001: Active slot
pub const Active: u32 = 0b0000000000000001;
}
}
}
/// Interrupt mask register 2
pub mod IMA {
/// Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set.
pub mod OVRUDRIE {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Interrupt is disabled
pub const Disabled: u32 = 0b0;
/// 0b1: Interrupt is enabled
pub const Enabled: u32 = 0b1;
}
}
/// Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode.
pub mod MUTEDETIE {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
pub use super::OVRUDRIE::RW;
}
/// Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE\[1\] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes.
pub mod WCKCFGIE {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
pub use super::OVRUDRIE::RW;
}
/// FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,
pub mod FREQIE {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
pub use super::OVRUDRIE::RW;
}
/// Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG\[1:0\] bits and the audio block is operates as a receiver.
pub mod CNRDYIE {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
pub use super::OVRUDRIE::RW;
}
/// Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.
pub mod AFSDETIE {
/// Offset (5 bits)
pub const offset: u32 = 5;
/// Mask (1 bit: 1 << 5)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
pub use super::OVRUDRIE::RW;
}
/// Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.
pub mod LFSDETIE {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (1 bit: 1 << 6)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
pub use super::OVRUDRIE::RW;
}
}
/// Status register
pub mod SRA {
/// Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register.
pub mod OVRUDR {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: No overrun/underrun error
pub const NoError: u32 = 0b0;
/// 0b1: Overrun/underrun error detection
pub const Overrun: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.
pub mod MUTEDET {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: No MUTE detection on the SD input line
pub const NoMute: u32 = 0b0;
/// 0b1: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame
pub const Mute: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE\[1\] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register.
pub mod WCKCFG {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: Clock configuration is correct
pub const Correct: u32 = 0b0;
/// 0b1: Clock configuration does not respect the rule concerning the frame length specification
pub const Wrong: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.
pub mod FREQ {
/// Offset (3 bits)
pub const offset: u32 = 3;
/// Mask (1 bit: 1 << 3)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: No FIFO request
pub const NoRequest: u32 = 0b0;
/// 0b1: FIFO request to read or to write the SAI_xDR
pub const Request: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register.
pub mod CNRDY {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: External AC’97 Codec is ready
pub const Ready: u32 = 0b0;
/// 0b1: External AC’97 Codec is not ready
pub const NotReady: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.
pub mod AFSDET {
/// Offset (5 bits)
pub const offset: u32 = 5;
/// Mask (1 bit: 1 << 5)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: No error
pub const NoError: u32 = 0b0;
/// 0b1: Frame synchronization signal is detected earlier than expected
pub const EarlySync: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register
pub mod LFSDET {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (1 bit: 1 << 6)
pub const mask: u32 = 1 << offset;
/// Read-only values
pub mod R {
/// 0b0: No error
pub const NoError: u32 = 0b0;
/// 0b1: Frame synchronization signal is not present at the right time
pub const NoSync: u32 = 0b1;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:
pub mod FLVL {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (3 bits: 0b111 << 16)
pub const mask: u32 = 0b111 << offset;
/// Read-only values
pub mod R {
/// 0b000: FIFO empty
pub const Empty: u32 = 0b000;
/// 0b001: FIFO <= 1⁄4 but not empty
pub const Quarter1: u32 = 0b001;
/// 0b010: 1⁄4 < FIFO <= 1⁄2
pub const Quarter2: u32 = 0b010;
/// 0b011: 1⁄2 < FIFO <= 3⁄4
pub const Quarter3: u32 = 0b011;
/// 0b100: 3⁄4 < FIFO but not full
pub const Quarter4: u32 = 0b100;
/// 0b101: FIFO full
pub const Full: u32 = 0b101;
}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Clear flag register
pub mod CLRFRA {
/// Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0.
pub mod COVRUDR {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values
pub mod W {
/// 0b1: Clears the OVRUDR flag
pub const Clear: u32 = 0b1;
}
/// Read-write values (empty)
pub mod RW {}
}
/// Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0.
pub mod CMUTEDET {
/// Offset (1 bits)
pub const offset: u32 = 1;
/// Mask (1 bit: 1 << 1)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values
pub mod W {
/// 0b1: Clears the MUTEDET flag
pub const Clear: u32 = 0b1;
}
/// Read-write values (empty)
pub mod RW {}
}
/// Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE\[1\] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0.
pub mod CWCKCFG {
/// Offset (2 bits)
pub const offset: u32 = 2;
/// Mask (1 bit: 1 << 2)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values
pub mod W {
/// 0b1: Clears the WCKCFG flag
pub const Clear: u32 = 0b1;
}
/// Read-write values (empty)
pub mod RW {}
}
/// Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0.
pub mod CCNRDY {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (1 bit: 1 << 4)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values
pub mod W {
/// 0b1: Clears the CNRDY flag
pub const Clear: u32 = 0b1;
}
/// Read-write values (empty)
pub mod RW {}
}
/// Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0.
pub mod CAFSDET {
/// Offset (5 bits)
pub const offset: u32 = 5;
/// Mask (1 bit: 1 << 5)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values
pub mod W {
/// 0b1: Clears the AFSDET flag
pub const Clear: u32 = 0b1;
}
/// Read-write values (empty)
pub mod RW {}
}
/// Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0.
pub mod CLFSDET {
/// Offset (6 bits)
pub const offset: u32 = 6;
/// Mask (1 bit: 1 << 6)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values
pub mod W {
/// 0b1: Clears the LFSDET flag
pub const Clear: u32 = 0b1;
}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Data register
pub mod DRA {
/// Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty.
pub mod DATA {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (32 bits: 0xffffffff << 0)
pub const mask: u32 = 0xffffffff << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Configuration register 1
pub mod CR1B {
pub use super::CR1A::CKSTR;
pub use super::CR1A::DMAEN;
pub use super::CR1A::DS;
pub use super::CR1A::LSBFIRST;
pub use super::CR1A::MCKDIV;
pub use super::CR1A::MCKEN;
pub use super::CR1A::MODE;
pub use super::CR1A::MONO;
pub use super::CR1A::NODIV;
pub use super::CR1A::OSR;
pub use super::CR1A::OUTDRIV;
pub use super::CR1A::PRTCFG;
pub use super::CR1A::SAIEN;
pub use super::CR1A::SYNCEN;
}
/// Configuration register 2
pub mod CR2B {
pub use super::CR2A::COMP;
pub use super::CR2A::CPL;
pub use super::CR2A::FFLUSH;
pub use super::CR2A::FTH;
pub use super::CR2A::MUTE;
pub use super::CR2A::MUTECNT;
pub use super::CR2A::MUTEVAL;
pub use super::CR2A::TRIS;
}
/// This register has no meaning in AC97 and SPDIF audio protocol
pub mod FRCRB {
pub use super::FRCRA::FRL;
pub use super::FRCRA::FSALL;
pub use super::FRCRA::FSDEF;
pub use super::FRCRA::FSOFF;
pub use super::FRCRA::FSPOL;
}
/// This register has no meaning in AC97 and SPDIF audio protocol
pub mod SLOTRB {
pub use super::SLOTRA::FBOFF;
pub use super::SLOTRA::NBSLOT;
pub use super::SLOTRA::SLOTEN;
pub use super::SLOTRA::SLOTSZ;
}
/// Interrupt mask register 2
pub mod IMB {
pub use super::IMA::AFSDETIE;
pub use super::IMA::CNRDYIE;
pub use super::IMA::FREQIE;
pub use super::IMA::LFSDETIE;
pub use super::IMA::MUTEDETIE;
pub use super::IMA::OVRUDRIE;
pub use super::IMA::WCKCFGIE;
}
/// Status register
pub mod SRB {
pub use super::SRA::AFSDET;
pub use super::SRA::CNRDY;
pub use super::SRA::FLVL;
pub use super::SRA::FREQ;
pub use super::SRA::LFSDET;
pub use super::SRA::MUTEDET;
pub use super::SRA::OVRUDR;
pub use super::SRA::WCKCFG;
}
/// Clear flag register
pub mod CLRFRB {
pub use super::CLRFRA::CAFSDET;
pub use super::CLRFRA::CCNRDY;
pub use super::CLRFRA::CLFSDET;
pub use super::CLRFRA::CMUTEDET;
pub use super::CLRFRA::COVRUDR;
pub use super::CLRFRA::CWCKCFG;
}
/// Data register
pub mod DRB {
pub use super::DRA::DATA;
}
#[repr(C)]
pub struct RegisterBlock {
/// Global configuration register
pub GCR: RWRegister<u32>,
/// Configuration register 1
pub CR1A: RWRegister<u32>,
/// Configuration register 2
pub CR2A: RWRegister<u32>,
/// This register has no meaning in AC97 and SPDIF audio protocol
pub FRCRA: RWRegister<u32>,
/// This register has no meaning in AC97 and SPDIF audio protocol
pub SLOTRA: RWRegister<u32>,
/// Interrupt mask register 2
pub IMA: RWRegister<u32>,
/// Status register
pub SRA: RORegister<u32>,
/// Clear flag register
pub CLRFRA: WORegister<u32>,
/// Data register
pub DRA: RWRegister<u32>,
/// Configuration register 1
pub CR1B: RWRegister<u32>,
/// Configuration register 2
pub CR2B: RWRegister<u32>,
/// This register has no meaning in AC97 and SPDIF audio protocol
pub FRCRB: RWRegister<u32>,
/// This register has no meaning in AC97 and SPDIF audio protocol
pub SLOTRB: RWRegister<u32>,
/// Interrupt mask register 2
pub IMB: RWRegister<u32>,
/// Status register
pub SRB: RORegister<u32>,
/// Clear flag register
pub CLRFRB: WORegister<u32>,
/// Data register
pub DRB: RWRegister<u32>,
/// PDM control register
pub PDMCR: RWRegister<u32>,
/// PDM delay register
pub PDMDLY: RWRegister<u32>,
}
pub struct ResetValues {
pub GCR: u32,
pub CR1A: u32,
pub CR2A: u32,
pub FRCRA: u32,
pub SLOTRA: u32,
pub IMA: u32,
pub SRA: u32,
pub CLRFRA: u32,
pub DRA: u32,
pub CR1B: u32,
pub CR2B: u32,
pub FRCRB: u32,
pub SLOTRB: u32,
pub IMB: u32,
pub SRB: u32,
pub CLRFRB: u32,
pub DRB: u32,
pub PDMCR: u32,
pub PDMDLY: u32,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
pub(crate) addr: u32,
pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
type Target = RegisterBlock;
#[inline(always)]
fn deref(&self) -> &RegisterBlock {
unsafe { &*(self.addr as *const _) }
}
}
#[cfg(feature = "rtic")]
unsafe impl Send for Instance {}