stm32mp1 0.16.0

Device support crates for STM32MP1 devices
Documentation 
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///Register `WISR` reader
pub type R = crate::R<WISRrs>;
///Field `TEIF` reader - TEIF
pub type TEIF_R = crate::BitReader;
///Field `ERIF` reader - ERIF
pub type ERIF_R = crate::BitReader;
///Field `BUSY` reader - BUSY
pub type BUSY_R = crate::BitReader;
///Field `PLLLS` reader - PLLLS
pub type PLLLS_R = crate::BitReader;
///Field `PLLLIF` reader - PLLLIF
pub type PLLLIF_R = crate::BitReader;
///Field `PLLUIF` reader - PLLUIF
pub type PLLUIF_R = crate::BitReader;
///Field `RRS` reader - RRS
pub type RRS_R = crate::BitReader;
///Field `RRIF` reader - RRIF
pub type RRIF_R = crate::BitReader;
impl R {
    ///Bit 0 - TEIF
    #[inline(always)]
    pub fn teif(&self) -> TEIF_R {
        TEIF_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - ERIF
    #[inline(always)]
    pub fn erif(&self) -> ERIF_R {
        ERIF_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - BUSY
    #[inline(always)]
    pub fn busy(&self) -> BUSY_R {
        BUSY_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 8 - PLLLS
    #[inline(always)]
    pub fn pllls(&self) -> PLLLS_R {
        PLLLS_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - PLLLIF
    #[inline(always)]
    pub fn plllif(&self) -> PLLLIF_R {
        PLLLIF_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - PLLUIF
    #[inline(always)]
    pub fn plluif(&self) -> PLLUIF_R {
        PLLUIF_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bit 12 - RRS
    #[inline(always)]
    pub fn rrs(&self) -> RRS_R {
        RRS_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - RRIF
    #[inline(always)]
    pub fn rrif(&self) -> RRIF_R {
        RRIF_R::new(((self.bits >> 13) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WISR")
            .field("teif", &self.teif())
            .field("erif", &self.erif())
            .field("busy", &self.busy())
            .field("pllls", &self.pllls())
            .field("plllif", &self.plllif())
            .field("plluif", &self.plluif())
            .field("rrs", &self.rrs())
            .field("rrif", &self.rrif())
            .finish()
    }
}
/**DSI wrapper interrupt and status register

You can [`read`](crate::Reg::read) this register and get [`wisr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DSI:WISR)*/
pub struct WISRrs;
impl crate::RegisterSpec for WISRrs {
    type Ux = u32;
}
///`read()` method returns [`wisr::R`](R) reader structure
impl crate::Readable for WISRrs {}
///`reset()` method sets WISR to value 0
impl crate::Resettable for WISRrs {}