1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
///Register `LCVCIDR` reader
pub type R = crate::R<LCVCIDRrs>;
///Register `LCVCIDR` writer
pub type W = crate::W<LCVCIDRrs>;
///Field `VCID` reader - VCID
pub type VCID_R = crate::FieldReader;
///Field `VCID` writer - VCID
pub type VCID_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
///Bits 0:1 - VCID
#[inline(always)]
pub fn vcid(&self) -> VCID_R {
VCID_R::new((self.bits & 3) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LCVCIDR")
.field("vcid", &self.vcid())
.finish()
}
}
impl W {
///Bits 0:1 - VCID
#[inline(always)]
pub fn vcid(&mut self) -> VCID_W<LCVCIDRrs> {
VCID_W::new(self, 0)
}
}
/**DSI Host LTDC current VCID register
You can [`read`](crate::Reg::read) this register and get [`lcvcidr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcvcidr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DSI:LCVCIDR)*/
pub struct LCVCIDRrs;
impl crate::RegisterSpec for LCVCIDRrs {
type Ux = u32;
}
///`read()` method returns [`lcvcidr::R`](R) reader structure
impl crate::Readable for LCVCIDRrs {}
///`write(|w| ..)` method takes [`lcvcidr::W`](W) writer structure
impl crate::Writable for LCVCIDRrs {
type Safety = crate::Unsafe;
}
///`reset()` method sets LCVCIDR to value 0
impl crate::Resettable for LCVCIDRrs {}