stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

///Register `MACPPSIR` reader
pub type R = crate::R<MACPPSIRrs>;
///Register `MACPPSIR` writer
pub type W = crate::W<MACPPSIRrs>;
///Field `PPSINT0` reader - PPS Output Signal Interval These bits store the interval between the rising edges of PPS signal output. The interval is stored in terms of number of units of subsecond increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20 ns), and desired interval between the rising edges of PPS signal output is 100 ns (that is, 5 units of subsecond increment value), you should program value 4 (5-1) in this register.
pub type PPSINT0_R = crate::FieldReader<u32>;
///Field `PPSINT0` writer - PPS Output Signal Interval These bits store the interval between the rising edges of PPS signal output. The interval is stored in terms of number of units of subsecond increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20 ns), and desired interval between the rising edges of PPS signal output is 100 ns (that is, 5 units of subsecond increment value), you should program value 4 (5-1) in this register.
pub type PPSINT0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
    ///Bits 0:31 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS signal output. The interval is stored in terms of number of units of subsecond increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20 ns), and desired interval between the rising edges of PPS signal output is 100 ns (that is, 5 units of subsecond increment value), you should program value 4 (5-1) in this register.
    #[inline(always)]
    pub fn ppsint0(&self) -> PPSINT0_R {
        PPSINT0_R::new(self.bits)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MACPPSIR").field("ppsint0", &self.ppsint0()).finish()
    }
}
impl W {
    ///Bits 0:31 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS signal output. The interval is stored in terms of number of units of subsecond increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20 ns), and desired interval between the rising edges of PPS signal output is 100 ns (that is, 5 units of subsecond increment value), you should program value 4 (5-1) in this register.
    #[inline(always)]
    pub fn ppsint0(&mut self) -> PPSINT0_W<MACPPSIRrs> {
        PPSINT0_W::new(self, 0)
    }
}
/**PPS interval register

You can [`read`](crate::Reg::read) this register and get [`macppsir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`macppsir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct MACPPSIRrs;
impl crate::RegisterSpec for MACPPSIRrs {
    type Ux = u32;
}
///`read()` method returns [`macppsir::R`](R) reader structure
impl crate::Readable for MACPPSIRrs {}
///`write(|w| ..)` method takes [`macppsir::W`](W) writer structure
impl crate::Writable for MACPPSIRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets MACPPSIR to value 0
impl crate::Resettable for MACPPSIRrs {}